FFTtest_nativelink_simulation.rpt

Info: Start Nativelink Simulation process
executing command line: ip-make-simscript --nativelink-mode --output-directory=FFTtest_iputf_input --spd=C:/intelFPGA_lite/17.1/projects/FFTtest/FFT/FFT.spd --spd=C:/intelFPGA_lite/17.1/projects/FFTtest/PLL/PLL.spd 

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cyclonev
Quartus root          :  c:/intelfpga_lite/17.1/quartus/bin64/
Quartus sim root      :  c:/intelfpga_lite/17.1/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/17.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File FFTtest_run_msim_rtl_verilog.do already exists - backing up current file as FFTtest_run_msim_rtl_verilog.do.bak
Info: Spawning ModelSim-Altera Simulation software 
Info: NativeLink simulation flow was successful