Supervisor-level iprio configurability

[evgeniy-paltsev]

The AIA spec says

For a given interrupt number, if the corresponding bit in sie is read-only zero, then the interrupt’s priority number in the supervisor-level iprio array must be read-only zero as well.

Does it include the case when sie[n] is read-only zero because corresponding mideleg[n] & mvien[n] bits are both set to zero?
I'm assuming here that either mideleg[n] or mvien[n] (or both) is writable and can be set to 1.

[jhauser-us]

First, I should add a correction: When the H (hypervisor) extension is implemented, the AIA spec should say, "if the corresponding bit is read-only zero in both sie and hie, then the interrupt’s priority number in the supervisor-level iprio array must be read-only zero as well."

Does it include the case when sie[n] is read-only zero because corresponding mideleg[n] & mvien[n] bits are both set to zero?

Yes, it does.