diff --git a/arches/big_core.yaml b/arches/big_core.yaml index 37566b97..ca79d6d3 100644 --- a/arches/big_core.yaml +++ b/arches/big_core.yaml @@ -40,11 +40,11 @@ top.cpu.core0.extension.core_extensions: # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive # if you want just one execution unit to issue queue you can do: # ["0"] which would result in iq0 -> exe0 - # *note if you change the number of issue queues, + # *note if you change the number of issue queues, # you need to add it to latency matrix below issue_queue_to_pipe_map: - [ + [ ["0", "1"], # iq0 -> exe0, exe1 ["2", "3"], # iq1 -> exe2, exe3 ["4", "5"], # iq2 -> exe4, exe5 @@ -52,6 +52,22 @@ top.cpu.core0.extension.core_extensions: ["8", "9"], # iq4 -> exe8, exe9 ["10"] # iq5 -> exe10 ] + + exe_pipe_rename: + [ + ["exe0", "sys_pipe"], + ["exe1", "alu1_pipe"], + ["exe2", "alu2_pipe"], + ["exe3", "alu3_pipe"], + ["exe4", "alu4_pipe"], + ["exe5", "alu5_pipe"], + ["exe6", "fpu0_pipe"], + ["exe7", "fpu1_pipe"], + ["exe8", "br0_pipe"], + ["exe9", "br1_pipe"], + ["exe10", "vint_pipe"] + ] + top.cpu.core0.rename.scoreboards: # From # | diff --git a/arches/medium_core.yaml b/arches/medium_core.yaml index 661f8e47..cf0d0178 100644 --- a/arches/medium_core.yaml +++ b/arches/medium_core.yaml @@ -29,15 +29,15 @@ top.cpu.core0.extension.core_extensions: ["br"], # exe5 ["vint", "vset", "vdiv", "vmul"] # exe6 ] - + # this is used to set how many units per queue # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive # if you want just one execution unit to issue queue you can do: # ["0"] which would result in iq0 -> exe0 - # *note if you change the number of issue queues, + # *note if you change the number of issue queues, # you need to add it to latency matrix below issue_queue_to_pipe_map: - [ + [ ["0"], # iq0 -> exe0 ["1", "2"], # iq1 -> exe1, exe2 ["3", "4"], # iq2 -> exe3, exe4 @@ -45,6 +45,17 @@ top.cpu.core0.extension.core_extensions: ["6"] ] + exe_pipe_rename: + [ + ["exe0", "alu0_pipe"], + ["exe1", "alu1_pipe"], + ["exe2", "alu2_pipe"], + ["exe3", "fpu0_pipe"], + ["exe4", "fpu1_pipe"], + ["exe5", "br_pipe"], + ["exe6", "vint_pipe"] + ] + top.cpu.core0.rename.scoreboards: # From # | diff --git a/arches/small_core.yaml b/arches/small_core.yaml index 67cb94db..32815268 100644 --- a/arches/small_core.yaml +++ b/arches/small_core.yaml @@ -27,16 +27,25 @@ top.cpu.core0.extension.core_extensions: # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive # if you want just one execution unit to issue queue you can do: # ["0"] which would result in iq0 -> exe0 - # *note if you change the number of issue queues, + # *note if you change the number of issue queues, # you need to add it to latency matrix below issue_queue_to_pipe_map: - [ + [ ["0"], # iq0 -> exe0 ["1"], # iq1 -> exe1 ["2"], # iq2 -> exe2 ["3"], # iq3 -> exe3 ] + exe_pipe_rename: + [ + ["exe0", "alu0_pipe"], + ["exe1", "fpu0_pipe"], + ["exe2", "br_pipe"], + ["exe3", "vint_pipe"] + ] + + top.cpu.core0.rename.scoreboards: # From # | diff --git a/core/DCache.cpp b/core/DCache.cpp index 11b9fa40..1bd811b8 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -272,7 +272,6 @@ namespace olympia void DCache::receiveMemReqFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr) { ILOG("Received memory access request from LSU " << memory_access_info_ptr); - out_lsu_lookup_ack_.send(memory_access_info_ptr); in_l2_cache_resp_receive_event_.schedule(); lsu_mem_access_info_ = memory_access_info_ptr; } diff --git a/core/DCache.hpp b/core/DCache.hpp index 36d0349d..d3d87b4f 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -97,7 +97,7 @@ namespace olympia // Input Ports //////////////////////////////////////////////////////////////////////////////// sparta::DataInPort in_lsu_lookup_req_{&unit_port_set_, - "in_lsu_lookup_req", 1}; + "in_lsu_lookup_req", 0}; sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; diff --git a/core/Dispatch.hpp b/core/Dispatch.hpp index 54c750cf..c8174e2f 100644 --- a/core/Dispatch.hpp +++ b/core/Dispatch.hpp @@ -153,83 +153,89 @@ namespace olympia // Counters -- this is only supported in C++11 -- uses // Counter's move semantics std::array stall_counters_{ - {sparta::CycleCounter(getStatisticSet(), "stall_cmov_busy", "CMOV busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_div_busy", "DIV busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_faddsub_busy", "FADDSUB busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_float_busy", "FLOAT busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_fmac_busy", "FMAC busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_i2f_busy", "I2F busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_f2i_busy", "F2I busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_int_busy", "INT busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_lsu_busy", "LSU busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_mul_busy", "MUL busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy", - sparta::Counter::COUNT_NORMAL, getClock()), + { + sparta::CycleCounter(getStatisticSet(), "stall_br_busy", "BR busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_cmov_busy", "CMOV busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_div_busy", "DIV busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_faddsub_busy", "FADDSUB busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_float_busy", "FLOAT busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_fmac_busy", "FMAC busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_i2f_busy", "I2F busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_f2i_busy", "F2I busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_int_busy", "INT busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_lsu_busy", "LSU busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_mul_busy", "MUL busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vint_busy", "VINT busy", + sparta::Counter::COUNT_NORMAL, getClock()), sparta::CycleCounter(getStatisticSet(), "stall_vfixed_busy", "VFIXED busy", sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_sys_busy", "No credits from ROB", - sparta::Counter::COUNT_NORMAL, getClock()), - sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", - "Dispatch not stalled, all instructions dispatched", - sparta::Counter::COUNT_NORMAL, getClock())}}; + sparta::CycleCounter(getStatisticSet(), "stall_vmask_busy", "VMASK busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vmul_busy", "VMUL busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vdiv_busy", "VDIV busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_vset_busy", "VSET busy", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_rob_full", "No credits from ROB", + sparta::Counter::COUNT_NORMAL, getClock()), + sparta::CycleCounter(getStatisticSet(), "stall_not_stalled", + "Dispatch not stalled, all instructions dispatched", + sparta::Counter::COUNT_NORMAL, getClock()) + } + }; std::array unit_distribution_{ - {sparta::Counter(getStatisticSet(), "count_cmov_insts", "Total CMOV insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_div_insts", "Total DIV insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_faddsub_insts", "Total FADDSUB insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_float_insts", "Total FLOAT insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_fmac_insts", "Total FMAC insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_i2f_insts", "Total I2F insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_f2i_insts", "Total F2I insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_int_insts", "Total INT insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_lsu_insts", "Total LSU insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_mul_insts", "Total MUL insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts", + { + sparta::Counter(getStatisticSet(), "count_br_insts", "Total BR insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_cmov_insts", "Total CMOV insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_div_insts", "Total DIV insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_faddsub_insts", "Total FADDSUB insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_float_insts", "Total FLOAT insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_fmac_insts", "Total FMAC insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_i2f_insts", "Total I2F insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_f2i_insts", "Total F2I insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_int_insts", "Total INT insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_lsu_insts", "Total LSU insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_mul_insts", "Total MUL insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vint_insts", "Total VINT insts", sparta::Counter::COUNT_NORMAL), sparta::Counter(getStatisticSet(), "count_vfixed_insts", "Total VFIXED insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", - sparta::Counter::COUNT_NORMAL), - sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", - sparta::Counter::COUNT_NORMAL)}}; + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmask_insts", "Total VMASK insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vmul_insts", "Total VMUL insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vdiv_insts", "Total VDIV insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_vset_insts", "Total VSET insts", + sparta::Counter::COUNT_NORMAL), + sparta::Counter(getStatisticSet(), "count_sys_insts", "Total SYS insts", + sparta::Counter::COUNT_NORMAL) + } + }; // As an example, this is a context counter that does the same // thing as the unit_distribution counter, albeit a little diff --git a/core/Inst.hpp b/core/Inst.hpp index 6002b0a2..9f62e06c 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -517,9 +517,9 @@ namespace olympia // - any changes here will break EXPECT inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { - os << "uid: " << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " " - << std::hex << inst.getPC() << std::dec << " pid: " << inst.getProgramID() - << " uopid: " << inst.getUOpID() << " '" << inst.getDisasm() << "' "; + os << "uid:" << inst.getUniqueID() << std::setw(10) << inst.getStatus() << " " + << std::hex << inst.getPC() << std::dec << " pid:" << inst.getProgramID() + << " uopid:" << inst.getUOpID() << " '" << inst.getDisasm() << "' "; return os; } diff --git a/core/IssueQueue.cpp b/core/IssueQueue.cpp index afcabcd1..c7ff9cb5 100644 --- a/core/IssueQueue.cpp +++ b/core/IssueQueue.cpp @@ -188,6 +188,7 @@ namespace olympia ready_queue_.erase(delete_iter); popIssueQueue_(inst); ++total_insts_issued_; + issue_event_.collect(*inst); break; } } diff --git a/core/IssueQueue.hpp b/core/IssueQueue.hpp index 0781dfe5..318686a6 100644 --- a/core/IssueQueue.hpp +++ b/core/IssueQueue.hpp @@ -14,6 +14,7 @@ #include "sparta/simulation/ResourceFactory.hpp" #include "sparta/simulation/TreeNode.hpp" #include "sparta/simulation/Unit.hpp" +#include "sparta/pevents/PeventCollector.hpp" #include "sparta/resources/PriorityQueue.hpp" @@ -137,9 +138,13 @@ namespace olympia sparta::Counter::COUNT_NORMAL}; bool rob_stopped_simulation_ = false; friend class IssueQueueTester; + + // For correlation activities + sparta::pevents::PeventCollector issue_event_{"ISSUE", getContainer(), getClock()}; + }; using IssueQueueFactory = sparta::ResourceFactory; class IssueQueueTester; -} // namespace olympia \ No newline at end of file +} // namespace olympia diff --git a/core/LSU.cpp b/core/LSU.cpp index 2324cddd..5be73076 100644 --- a/core/LSU.cpp +++ b/core/LSU.cpp @@ -104,6 +104,12 @@ namespace olympia node->getParent()->registerForNotification( this, "rob_stopped_notif_channel", false /* ROB maybe not be constructed yet */); + + auto & events = ldst_pipeline_.getEventsAtStage(cache_read_stage_); + for (auto & event : events) { + in_cache_lookup_ack_.registerConsumerEvent(event->getScheduleable()); + } + uev_append_ready_ >> uev_issue_inst_; // NOTE: // To resolve the race condition when: @@ -244,7 +250,7 @@ namespace olympia // either a new issue event, or a re-issue event // however, we can ONLY update instruction status as SCHEDULED for a new issue event - ILOG("Another issue event scheduled " << inst_ptr); + ILOG("Inst fully readdy: " << inst_ptr); if (isReadyToIssueInsts_()) { @@ -529,6 +535,7 @@ namespace olympia // Is its a cache miss we dont need to rechedule the instruction if (!mem_access_info_ptr->isCacheHit()) { + ILOG("ma cache miss: " << mem_access_info_ptr); return; } diff --git a/core/LoadStoreInstInfo.hpp b/core/LoadStoreInstInfo.hpp index 3f9151cc..e7fe4264 100644 --- a/core/LoadStoreInstInfo.hpp +++ b/core/LoadStoreInstInfo.hpp @@ -195,8 +195,8 @@ namespace olympia inline std::ostream & operator<<(std::ostream & os, const olympia::LoadStoreInstInfo & ls_info) { os << "lsinfo: " - << "uid: " << ls_info.getInstUniqueID() << " pri:" << ls_info.getPriority() - << " state: " << ls_info.getState(); + << "uid:" << ls_info.getInstUniqueID() << " pri:" << ls_info.getPriority() + << " state:" << ls_info.getState(); return os; } diff --git a/layouts/Makefile b/layouts/Makefile index d6ad8878..3a79b2d6 100644 --- a/layouts/Makefile +++ b/layouts/Makefile @@ -1,9 +1,9 @@ all: small_core.alf medium_core.alf big_core.alf -%_core.alf: ./gen_alf.py +%_core.alf: ./gen_alf.py ../fastdebug/olympia @echo "Generating pipeout for $@" - @(cd ../release; ./olympia -z ../layouts/pipeout -i1 traces/dhry_riscv.zstf > /dev/null) + @(cd ../fastdebug; ./olympia -z ../layouts/pipeout -i1 traces/dhry_riscv.zstf > /dev/null) @./gen_alf.py -d pipeoutlocation.dat -a $*_core.alf @rm pipeout* diff --git a/layouts/big_core.alf b/layouts/big_core.alf index ef63cb58..8c3e20f2 100644 --- a/layouts/big_core.alf +++ b/layouts/big_core.alf @@ -1,7 +1,7 @@ --- - type: schedule color: (192,192,192) - dimensions: (720,1428) + dimensions: (720,1050) position: (159,2) pixel_offset: 80 time_scale: 0.125 @@ -216,1120 +216,769 @@ LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: -10 type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,467) + position: (159,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,472) + position: (159,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,477) + position: (159,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,482) + position: (159,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,487) + position: (159,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,492) + position: (159,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,497) + position: (159,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,512) + position: (159,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,527) + position: (159,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,542) + position: (159,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,557) + position: (159,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: -10 type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: -10 + type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: -10 + type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,572) + position: (159,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,587) + position: (159,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,592) + position: (159,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,597) + position: (159,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,602) + position: (159,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,607) + position: (159,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,612) + position: (159,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,617) + position: (159,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,622) + position: (159,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,627) + position: (159,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,632) + position: (159,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,637) + position: (159,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,642) + position: (159,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,647) + position: (159,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,652) + position: (159,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,657) + position: (159,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,662) + position: (159,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,667) + position: (159,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,672) + position: (159,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,677) + position: (159,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,682) + position: (159,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,687) + position: (159,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,692) + position: (159,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,697) + position: (159,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,702) + position: (159,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,707) + position: (159,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,722) + position: (159,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,737) + position: (159,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,752) + position: (159,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,767) + position: (159,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,782) + position: (159,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: -10 type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,797) + position: (159,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,2) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,7) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,12) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,17) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,22) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,27) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,32) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,37) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,42) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,57) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,72) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,77) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,82) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,87) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,92) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,97) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,102) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,107) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,112) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,127) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,142) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,147) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,152) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,157) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,162) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,167) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,172) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,177) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,182) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,197) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,97) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,102) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,107) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 t_offset: 0 -- Content: auto_color_anno_notext +- Content: auto_color_annotation color: (192,192,192) - dimensions: (150,5) - position: (1049,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 + dimensions: (750,15) + position: (1049,112) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,127) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 t_offset: 0 -- Content: auto_color_annotation +- Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,15) - position: (1049,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 + dimensions: (750,5) + position: (1049,142) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 + dimensions: (750,5) + position: (1049,147) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 + dimensions: (750,5) + position: (1049,152) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,157) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,162) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,167) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 + dimensions: (750,5) + position: (1049,172) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 + t_offset: 0 +- Content: auto_color_anno_notext + color: (192,192,192) + dimensions: (750,5) + position: (1049,177) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,182) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 + dimensions: (750,15) + position: (1049,197) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,467) + dimensions: (750,5) + position: (1049,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,472) + dimensions: (750,5) + position: (1049,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,477) + dimensions: (750,5) + position: (1049,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,482) + dimensions: (750,5) + position: (1049,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,487) + dimensions: (750,5) + position: (1049,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,492) + dimensions: (750,5) + position: (1049,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,497) + dimensions: (750,15) + position: (1049,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,512) + dimensions: (750,15) + position: (1049,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,527) + dimensions: (750,15) + position: (1049,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,542) + dimensions: (750,15) + position: (1049,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,557) + dimensions: (750,15) + position: (1049,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,572) + dimensions: (750,15) + position: (1049,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,587) + dimensions: (750,5) + position: (1049,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,592) + dimensions: (750,5) + position: (1049,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,597) + dimensions: (750,5) + position: (1049,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,602) + dimensions: (750,5) + position: (1049,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,607) + dimensions: (750,5) + position: (1049,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,612) + dimensions: (750,5) + position: (1049,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,617) + dimensions: (750,5) + position: (1049,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,622) + dimensions: (750,5) + position: (1049,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,627) + dimensions: (750,5) + position: (1049,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,632) + dimensions: (750,5) + position: (1049,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,637) + dimensions: (750,5) + position: (1049,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,642) + dimensions: (750,5) + position: (1049,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,647) + dimensions: (750,5) + position: (1049,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,652) + dimensions: (750,5) + position: (1049,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,657) + dimensions: (750,5) + position: (1049,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,662) + dimensions: (750,5) + position: (1049,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,667) + dimensions: (750,5) + position: (1049,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,672) + dimensions: (750,5) + position: (1049,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,677) + dimensions: (750,5) + position: (1049,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,682) + dimensions: (750,5) + position: (1049,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,687) + dimensions: (750,5) + position: (1049,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,692) + dimensions: (750,5) + position: (1049,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,697) + dimensions: (750,5) + position: (1049,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,702) + dimensions: (750,5) + position: (1049,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,707) + dimensions: (750,15) + position: (1049,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,722) + dimensions: (750,15) + position: (1049,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,737) + dimensions: (750,15) + position: (1049,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,752) + dimensions: (750,15) + position: (1049,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,767) + dimensions: (750,15) + position: (1049,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,782) + dimensions: (750,15) + position: (1049,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,797) + dimensions: (750,15) + position: (1049,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: 0 - Content: caption @@ -1424,394 +1073,274 @@ caption: Dispatch0 - Content: caption color: (192,192,192) - dimensions: (150,15) + dimensions: (150,14) position: (10,212) - caption: ALU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,213) - caption: ALU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,227) - caption: FPU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,228) - caption: FPU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,242) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,243) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,257) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,258) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,272) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,273) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) - dimensions: (150,14) + dimensions: (150,15) position: (10,287) - caption: alu0 Sch[7-2] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,288) - caption: alu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,317) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,318) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,332) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,333) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,347) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,348) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,377) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,378) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,392) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,393) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,407) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,408) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,437) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,438) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,452) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,453) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,467) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,468) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,497) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,498) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,512) - caption: LSU IQ[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,513) - caption: LSU IQ[0] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,527) - caption: LSU Pipe0 + position: (10,302) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,528) - caption: LSU Pipe0 + position: (899,303) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,542) - caption: LSU Pipe1 + position: (10,317) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,543) - caption: LSU Pipe1 + position: (899,318) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,557) - caption: LSU Pipe2 + position: (10,332) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,558) - caption: LSU Pipe2 + position: (899,333) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,572) + position: (10,347) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,573) + position: (899,348) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (10,587) + position: (10,362) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,588) + position: (899,363) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,707) + position: (10,482) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,708) + position: (899,483) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,722) + position: (10,497) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,723) + position: (899,498) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,737) + position: (10,512) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,738) + position: (899,513) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,752) + position: (10,527) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,753) + position: (899,528) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,767) + position: (10,542) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,768) + position: (899,543) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,782) + position: (10,557) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,783) + position: (899,558) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,797) + position: (10,572) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,798) + position: (899,573) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,812) + position: (10,587) caption: C=1 Cycle - Content: cycle color: (192,192,192) dimensions: (100,15) - position: (60,812) + position: (60,587) LocationString: .*rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (160,812) + position: (160,587) caption: C=1 -10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (200,812) + position: (200,587) caption: C=1 -5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (240,812) + position: (240,587) caption: C=1 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (280,812) + position: (280,587) caption: C=1 5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (320,812) + position: (320,587) caption: C=1 10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (360,812) + position: (360,587) caption: C=1 15 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (400,812) + position: (400,587) caption: C=1 20 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (440,812) + position: (440,587) caption: C=1 25 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (480,812) + position: (480,587) caption: C=1 30 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (520,812) + position: (520,587) caption: C=1 35 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (560,812) + position: (560,587) caption: C=1 40 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (600,812) + position: (600,587) caption: C=1 45 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (640,812) + position: (640,587) caption: C=1 50 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (680,812) + position: (680,587) caption: C=1 55 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (720,812) + position: (720,587) caption: C=1 60 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (760,812) + position: (760,587) caption: C=1 65 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (800,812) + position: (800,587) caption: C=1 70 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (840,812) + position: (840,587) caption: C=1 75 - Content: caption color: (0,0,0) @@ -1831,31 +1360,16 @@ - Content: caption color: (0,0,0) dimensions: (870,1) - position: (10,287) + position: (10,272) caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,347) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,407) - caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,467) - caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,572) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,797) - caption: ... diff --git a/layouts/gen_alf.py b/layouts/gen_alf.py index 2b8e8457..67a196ab 100755 --- a/layouts/gen_alf.py +++ b/layouts/gen_alf.py @@ -61,6 +61,7 @@ sl_grp = layout.createScheduleLineGroup(default_color=[192,192,192], include_detail_column = True, + content_width=750, margins=ALFLayout.Margin(top = 2, left = 10)) #-------------------------------------------------- Fetch/Decode @@ -72,12 +73,9 @@ #-------------------------------------------------- Dispatch sl_grp.addScheduleLine('.*dispatch.dispatch_queue.dispatch_queue', ["Dispatch"], mini_split=[80,20], space=True) -sl_grp.addScheduleLine('.*dispatch.in_alu([0-9])_credits', [r"ALU[\1] cred"], nomunge=True) -sl_grp.addScheduleLine('.*dispatch.in_fpu([0-9])_credits', [r"FPU[\1] cred"], nomunge=True) - -sl_grp.addScheduleLine('.*dispatch.in_br([0-9])_credits', [r"BR[\1] cred"], nomunge=True) -sl_grp.addScheduleLine('.*dispatch.in_lsu_credits', ["LSU cred"], nomunge=True) -sl_grp.addScheduleLine('.*dispatch.in_reorder_buffer_credits', ["ROB cred"], nomunge=True, space=True) +#sl_grp.addScheduleLine('.*dispatch.in_iq([0-9])_credits', [r"ALU[\1] cred"], nomunge=True) +#sl_grp.addScheduleLine('.*dispatch.in_lsu_credits', ["LSU cred"], nomunge=True) +#sl_grp.addScheduleLine('.*dispatch.in_reorder_buffer_credits', ["ROB cred"], nomunge=True, space=True) #-------------------------------------------------- Exe Blocks for block in ['alu','fpu','br']: @@ -89,10 +87,10 @@ num += 1 #-------------------------------------------------- LSU -sl_grp.addScheduleLine('.*lsu.lsu_inst_queue.lsu_inst_queue([0-9]+)', [r"LSU IQ[\1]"], mini_split=[80,20]) +sl_grp.addScheduleLine('.*lsu.lsu_inst_queue.lsu_inst_queue([0-9]+)', [r"LSU IQ[\1]"], mini_split=[80,20], space=True) #sl_grp.addScheduleLine('.*lsu.replay_buffer.replay_buffer([0-9]+)', ["LSU Replay[\1]"], mini_split=[80,20]) -sl_grp.addScheduleLine('.*lsu.LoadStorePipeline.LoadStorePipeline', ["LSU Pipe"], space=True, reverse=False) +sl_grp.addScheduleLine('.*lsu.LoadStorePipeline.LoadStorePipeline([0-9]+)', ["AGEN", "MMU", "D$L", "D$R", "WB"], space=True, reverse=False) sl_grp.addScheduleLine('.*lsu.dcache_busy', ["DL1 busy"], nomunge=True) #-------------------------------------------------- Retire diff --git a/layouts/medium_core.alf b/layouts/medium_core.alf index ef63cb58..8c3e20f2 100644 --- a/layouts/medium_core.alf +++ b/layouts/medium_core.alf @@ -1,7 +1,7 @@ --- - type: schedule color: (192,192,192) - dimensions: (720,1428) + dimensions: (720,1050) position: (159,2) pixel_offset: 80 time_scale: 0.125 @@ -216,1120 +216,769 @@ LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: -10 type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,467) + position: (159,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,472) + position: (159,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,477) + position: (159,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,482) + position: (159,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,487) + position: (159,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,492) + position: (159,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,497) + position: (159,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,512) + position: (159,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,527) + position: (159,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,542) + position: (159,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,557) + position: (159,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: -10 type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: -10 + type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: -10 + type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,572) + position: (159,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,587) + position: (159,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,592) + position: (159,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,597) + position: (159,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,602) + position: (159,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,607) + position: (159,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,612) + position: (159,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,617) + position: (159,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,622) + position: (159,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,627) + position: (159,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,632) + position: (159,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,637) + position: (159,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,642) + position: (159,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,647) + position: (159,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,652) + position: (159,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,657) + position: (159,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,662) + position: (159,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,667) + position: (159,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,672) + position: (159,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,677) + position: (159,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,682) + position: (159,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,687) + position: (159,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,692) + position: (159,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,697) + position: (159,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,702) + position: (159,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,707) + position: (159,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,722) + position: (159,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,737) + position: (159,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,752) + position: (159,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,767) + position: (159,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,782) + position: (159,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: -10 type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,797) + position: (159,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,2) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,7) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,12) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,17) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,22) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,27) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,32) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,37) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,42) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,57) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,72) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,77) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,82) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,87) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,92) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,97) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,102) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,107) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,112) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,127) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,142) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,147) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,152) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,157) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,162) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,167) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,172) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,177) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,182) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,197) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,97) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,102) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,107) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 t_offset: 0 -- Content: auto_color_anno_notext +- Content: auto_color_annotation color: (192,192,192) - dimensions: (150,5) - position: (1049,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 + dimensions: (750,15) + position: (1049,112) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,127) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 t_offset: 0 -- Content: auto_color_annotation +- Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,15) - position: (1049,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 + dimensions: (750,5) + position: (1049,142) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 + dimensions: (750,5) + position: (1049,147) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 + dimensions: (750,5) + position: (1049,152) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,157) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,162) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,167) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 + dimensions: (750,5) + position: (1049,172) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 + t_offset: 0 +- Content: auto_color_anno_notext + color: (192,192,192) + dimensions: (750,5) + position: (1049,177) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,182) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 + dimensions: (750,15) + position: (1049,197) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,467) + dimensions: (750,5) + position: (1049,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,472) + dimensions: (750,5) + position: (1049,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,477) + dimensions: (750,5) + position: (1049,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,482) + dimensions: (750,5) + position: (1049,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,487) + dimensions: (750,5) + position: (1049,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,492) + dimensions: (750,5) + position: (1049,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,497) + dimensions: (750,15) + position: (1049,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,512) + dimensions: (750,15) + position: (1049,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,527) + dimensions: (750,15) + position: (1049,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,542) + dimensions: (750,15) + position: (1049,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,557) + dimensions: (750,15) + position: (1049,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,572) + dimensions: (750,15) + position: (1049,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,587) + dimensions: (750,5) + position: (1049,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,592) + dimensions: (750,5) + position: (1049,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,597) + dimensions: (750,5) + position: (1049,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,602) + dimensions: (750,5) + position: (1049,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,607) + dimensions: (750,5) + position: (1049,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,612) + dimensions: (750,5) + position: (1049,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,617) + dimensions: (750,5) + position: (1049,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,622) + dimensions: (750,5) + position: (1049,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,627) + dimensions: (750,5) + position: (1049,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,632) + dimensions: (750,5) + position: (1049,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,637) + dimensions: (750,5) + position: (1049,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,642) + dimensions: (750,5) + position: (1049,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,647) + dimensions: (750,5) + position: (1049,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,652) + dimensions: (750,5) + position: (1049,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,657) + dimensions: (750,5) + position: (1049,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,662) + dimensions: (750,5) + position: (1049,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,667) + dimensions: (750,5) + position: (1049,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,672) + dimensions: (750,5) + position: (1049,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,677) + dimensions: (750,5) + position: (1049,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,682) + dimensions: (750,5) + position: (1049,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,687) + dimensions: (750,5) + position: (1049,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,692) + dimensions: (750,5) + position: (1049,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,697) + dimensions: (750,5) + position: (1049,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,702) + dimensions: (750,5) + position: (1049,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,707) + dimensions: (750,15) + position: (1049,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,722) + dimensions: (750,15) + position: (1049,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,737) + dimensions: (750,15) + position: (1049,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,752) + dimensions: (750,15) + position: (1049,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,767) + dimensions: (750,15) + position: (1049,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,782) + dimensions: (750,15) + position: (1049,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,797) + dimensions: (750,15) + position: (1049,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: 0 - Content: caption @@ -1424,394 +1073,274 @@ caption: Dispatch0 - Content: caption color: (192,192,192) - dimensions: (150,15) + dimensions: (150,14) position: (10,212) - caption: ALU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,213) - caption: ALU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,227) - caption: FPU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,228) - caption: FPU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,242) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,243) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,257) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,258) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,272) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,273) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) - dimensions: (150,14) + dimensions: (150,15) position: (10,287) - caption: alu0 Sch[7-2] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,288) - caption: alu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,317) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,318) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,332) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,333) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,347) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,348) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,377) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,378) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,392) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,393) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,407) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,408) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,437) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,438) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,452) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,453) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,467) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,468) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,497) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,498) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,512) - caption: LSU IQ[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,513) - caption: LSU IQ[0] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,527) - caption: LSU Pipe0 + position: (10,302) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,528) - caption: LSU Pipe0 + position: (899,303) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,542) - caption: LSU Pipe1 + position: (10,317) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,543) - caption: LSU Pipe1 + position: (899,318) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,557) - caption: LSU Pipe2 + position: (10,332) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,558) - caption: LSU Pipe2 + position: (899,333) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,572) + position: (10,347) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,573) + position: (899,348) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (10,587) + position: (10,362) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,588) + position: (899,363) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,707) + position: (10,482) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,708) + position: (899,483) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,722) + position: (10,497) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,723) + position: (899,498) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,737) + position: (10,512) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,738) + position: (899,513) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,752) + position: (10,527) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,753) + position: (899,528) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,767) + position: (10,542) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,768) + position: (899,543) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,782) + position: (10,557) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,783) + position: (899,558) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,797) + position: (10,572) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,798) + position: (899,573) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,812) + position: (10,587) caption: C=1 Cycle - Content: cycle color: (192,192,192) dimensions: (100,15) - position: (60,812) + position: (60,587) LocationString: .*rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (160,812) + position: (160,587) caption: C=1 -10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (200,812) + position: (200,587) caption: C=1 -5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (240,812) + position: (240,587) caption: C=1 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (280,812) + position: (280,587) caption: C=1 5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (320,812) + position: (320,587) caption: C=1 10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (360,812) + position: (360,587) caption: C=1 15 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (400,812) + position: (400,587) caption: C=1 20 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (440,812) + position: (440,587) caption: C=1 25 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (480,812) + position: (480,587) caption: C=1 30 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (520,812) + position: (520,587) caption: C=1 35 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (560,812) + position: (560,587) caption: C=1 40 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (600,812) + position: (600,587) caption: C=1 45 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (640,812) + position: (640,587) caption: C=1 50 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (680,812) + position: (680,587) caption: C=1 55 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (720,812) + position: (720,587) caption: C=1 60 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (760,812) + position: (760,587) caption: C=1 65 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (800,812) + position: (800,587) caption: C=1 70 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (840,812) + position: (840,587) caption: C=1 75 - Content: caption color: (0,0,0) @@ -1831,31 +1360,16 @@ - Content: caption color: (0,0,0) dimensions: (870,1) - position: (10,287) + position: (10,272) caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,347) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,407) - caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,467) - caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,572) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,797) - caption: ... diff --git a/layouts/small_core.alf b/layouts/small_core.alf index ef63cb58..8c3e20f2 100644 --- a/layouts/small_core.alf +++ b/layouts/small_core.alf @@ -1,7 +1,7 @@ --- - type: schedule color: (192,192,192) - dimensions: (720,1428) + dimensions: (720,1050) position: (159,2) pixel_offset: 80 time_scale: 0.125 @@ -216,1120 +216,769 @@ LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: -10 type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (720,15) - position: (159,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 - t_offset: -10 - type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 - t_offset: -10 - type: schedule_line - - Content: auto_color_annotation - color: (192,192,192) - dimensions: (720,15) - position: (159,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 - t_offset: -10 - type: schedule_line - - Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (720,5) - position: (159,467) + position: (159,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,472) + position: (159,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,477) + position: (159,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,482) + position: (159,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,487) + position: (159,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,492) + position: (159,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,497) + position: (159,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,512) + position: (159,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,527) + position: (159,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,542) + position: (159,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,557) + position: (159,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: -10 type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: -10 + type: schedule_line + - Content: auto_color_annotation + color: (192,192,192) + dimensions: (720,15) + position: (159,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: -10 + type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,572) + position: (159,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,587) + position: (159,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,592) + position: (159,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,597) + position: (159,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,602) + position: (159,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,607) + position: (159,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,612) + position: (159,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,617) + position: (159,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,622) + position: (159,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,627) + position: (159,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,632) + position: (159,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,637) + position: (159,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,642) + position: (159,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,647) + position: (159,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,652) + position: (159,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,657) + position: (159,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,662) + position: (159,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,667) + position: (159,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,672) + position: (159,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,677) + position: (159,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,682) + position: (159,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,687) + position: (159,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,692) + position: (159,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,697) + position: (159,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) dimensions: (720,5) - position: (159,702) + position: (159,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,707) + position: (159,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,722) + position: (159,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,737) + position: (159,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,752) + position: (159,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,767) + position: (159,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: -10 type: schedule_line - Content: auto_color_annotation color: (192,192,192) dimensions: (720,15) - position: (159,782) + position: (159,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: -10 type: schedule_line - Content: auto_color_anno_nomunge color: (192,192,192) dimensions: (720,15) - position: (159,797) + position: (159,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: -10 type: schedule_line - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,2) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,7) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,12) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,17) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,22) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,27) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,32) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,37) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,42) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) + dimensions: (750,15) position: (1049,57) LocationString: top.cpu.core0.decode.FetchQueue.FetchQueue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,72) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,77) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,82) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,87) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) + dimensions: (750,5) position: (1049,92) LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,97) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,102) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,107) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,112) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,127) - LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,142) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,147) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,152) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,157) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,162) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,167) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,172) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,177) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,182) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,197) - LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,212) - LocationString: top.cpu.core0.dispatch.in_alu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,227) - LocationString: top.cpu.core0.dispatch.in_fpu0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,242) - LocationString: top.cpu.core0.dispatch.in_br0_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,257) - LocationString: top.cpu.core0.dispatch.in_lsu_credits - t_offset: 0 -- Content: auto_color_anno_nomunge - color: (192,192,192) - dimensions: (150,15) - position: (1049,272) - LocationString: top.cpu.core0.dispatch.in_reorder_buffer_credits - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,287) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,292) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,297) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue5 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,302) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue4 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,307) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue3 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,312) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue2 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,317) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue1 - t_offset: 0 -- Content: auto_color_annotation - color: (192,192,192) - dimensions: (150,15) - position: (1049,332) - LocationString: top.cpu.core0.execute.alu0.scheduler_queue.scheduler_queue0 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,347) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue7 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,352) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue6 - t_offset: 0 -- Content: auto_color_anno_notext - color: (192,192,192) - dimensions: (150,5) - position: (1049,357) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,97) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,362) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,102) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,367) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,107) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue2 t_offset: 0 -- Content: auto_color_anno_notext +- Content: auto_color_annotation color: (192,192,192) - dimensions: (150,5) - position: (1049,372) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue2 + dimensions: (750,15) + position: (1049,112) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,377) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,127) + LocationString: top.cpu.core0.rename.rename_uop_queue.rename_uop_queue0 t_offset: 0 -- Content: auto_color_annotation +- Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,15) - position: (1049,392) - LocationString: top.cpu.core0.execute.fpu0.scheduler_queue.scheduler_queue0 + dimensions: (750,5) + position: (1049,142) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,407) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue7 + dimensions: (750,5) + position: (1049,147) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,412) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue6 + dimensions: (750,5) + position: (1049,152) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,417) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue5 + dimensions: (750,5) + position: (1049,157) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,422) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue4 + dimensions: (750,5) + position: (1049,162) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,427) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue3 + dimensions: (750,5) + position: (1049,167) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,432) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue2 + dimensions: (750,5) + position: (1049,172) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue3 + t_offset: 0 +- Content: auto_color_anno_notext + color: (192,192,192) + dimensions: (750,5) + position: (1049,177) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,437) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue1 + dimensions: (750,15) + position: (1049,182) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,452) - LocationString: top.cpu.core0.execute.br0.scheduler_queue.scheduler_queue0 + dimensions: (750,15) + position: (1049,197) + LocationString: top.cpu.core0.dispatch.dispatch_queue.dispatch_queue0 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,467) + dimensions: (750,5) + position: (1049,212) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,472) + dimensions: (750,5) + position: (1049,217) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue6 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,477) + dimensions: (750,5) + position: (1049,222) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue5 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,482) + dimensions: (750,5) + position: (1049,227) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue4 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,487) + dimensions: (750,5) + position: (1049,232) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue3 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,492) + dimensions: (750,5) + position: (1049,237) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,497) + dimensions: (750,15) + position: (1049,242) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,512) + dimensions: (750,15) + position: (1049,257) LocationString: top.cpu.core0.lsu.lsu_inst_queue.lsu_inst_queue0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,527) + dimensions: (750,15) + position: (1049,272) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline0 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,542) + dimensions: (750,15) + position: (1049,287) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,557) + dimensions: (750,15) + position: (1049,302) LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline2 t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,317) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline3 + t_offset: 0 +- Content: auto_color_annotation + color: (192,192,192) + dimensions: (750,15) + position: (1049,332) + LocationString: top.cpu.core0.lsu.LoadStorePipeline.LoadStorePipeline4 + t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,572) + dimensions: (750,15) + position: (1049,347) LocationString: top.cpu.core0.lsu.dcache_busy t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,587) + dimensions: (750,5) + position: (1049,362) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer29 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,592) + dimensions: (750,5) + position: (1049,367) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer28 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,597) + dimensions: (750,5) + position: (1049,372) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer27 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,602) + dimensions: (750,5) + position: (1049,377) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer26 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,607) + dimensions: (750,5) + position: (1049,382) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer25 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,612) + dimensions: (750,5) + position: (1049,387) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer24 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,617) + dimensions: (750,5) + position: (1049,392) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer23 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,622) + dimensions: (750,5) + position: (1049,397) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer22 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,627) + dimensions: (750,5) + position: (1049,402) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer21 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,632) + dimensions: (750,5) + position: (1049,407) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer20 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,637) + dimensions: (750,5) + position: (1049,412) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer19 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,642) + dimensions: (750,5) + position: (1049,417) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer18 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,647) + dimensions: (750,5) + position: (1049,422) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer17 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,652) + dimensions: (750,5) + position: (1049,427) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer16 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,657) + dimensions: (750,5) + position: (1049,432) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer15 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,662) + dimensions: (750,5) + position: (1049,437) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer14 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,667) + dimensions: (750,5) + position: (1049,442) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer13 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,672) + dimensions: (750,5) + position: (1049,447) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer12 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,677) + dimensions: (750,5) + position: (1049,452) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer11 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,682) + dimensions: (750,5) + position: (1049,457) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer10 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,687) + dimensions: (750,5) + position: (1049,462) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer9 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,692) + dimensions: (750,5) + position: (1049,467) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer8 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,697) + dimensions: (750,5) + position: (1049,472) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer7 t_offset: 0 - Content: auto_color_anno_notext color: (192,192,192) - dimensions: (150,5) - position: (1049,702) + dimensions: (750,5) + position: (1049,477) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer6 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,707) + dimensions: (750,15) + position: (1049,482) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer5 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,722) + dimensions: (750,15) + position: (1049,497) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer4 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,737) + dimensions: (750,15) + position: (1049,512) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer3 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,752) + dimensions: (750,15) + position: (1049,527) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer2 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,767) + dimensions: (750,15) + position: (1049,542) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer1 t_offset: 0 - Content: auto_color_annotation color: (192,192,192) - dimensions: (150,15) - position: (1049,782) + dimensions: (750,15) + position: (1049,557) LocationString: top.cpu.core0.rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: auto_color_anno_nomunge color: (192,192,192) - dimensions: (150,15) - position: (1049,797) + dimensions: (750,15) + position: (1049,572) LocationString: top.cpu.core0.dispatch.in_reorder_flush t_offset: 0 - Content: caption @@ -1424,394 +1073,274 @@ caption: Dispatch0 - Content: caption color: (192,192,192) - dimensions: (150,15) + dimensions: (150,14) position: (10,212) - caption: ALU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,213) - caption: ALU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,227) - caption: FPU[0] cred -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,228) - caption: FPU[0] cred + caption: LSU IQ[7-2] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,242) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,243) - caption: BR[0] cred + caption: LSU IQ[1] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,257) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,258) - caption: LSU cred + caption: LSU IQ[0] - Content: caption color: (192,192,192) dimensions: (150,15) position: (10,272) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,273) - caption: ROB cred + caption: AGEN - Content: caption color: (192,192,192) - dimensions: (150,14) + dimensions: (150,15) position: (10,287) - caption: alu0 Sch[7-2] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,14) position: (899,288) - caption: alu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,317) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,318) - caption: alu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,332) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,333) - caption: alu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,347) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,348) - caption: fpu0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,377) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,378) - caption: fpu0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,392) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,393) - caption: fpu0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,407) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,408) - caption: br0 Sch[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,437) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,438) - caption: br0 Sch[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,452) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,453) - caption: br0 Sch[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (10,467) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,468) - caption: LSU IQ[7-2] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,497) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,498) - caption: LSU IQ[1] -- Content: caption - color: (192,192,192) - dimensions: (150,15) - position: (10,512) - caption: LSU IQ[0] -- Content: caption - color: (192,192,192) - dimensions: (150,14) - position: (899,513) - caption: LSU IQ[0] + caption: MMU - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,527) - caption: LSU Pipe0 + position: (10,302) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,528) - caption: LSU Pipe0 + position: (899,303) + caption: D$L - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,542) - caption: LSU Pipe1 + position: (10,317) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,543) - caption: LSU Pipe1 + position: (899,318) + caption: D$R - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,557) - caption: LSU Pipe2 + position: (10,332) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,558) - caption: LSU Pipe2 + position: (899,333) + caption: WB - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,572) + position: (10,347) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,573) + position: (899,348) caption: DL1 busy - Content: caption color: (192,192,192) dimensions: (150,14) - position: (10,587) + position: (10,362) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,588) + position: (899,363) caption: ROB[29-6] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,707) + position: (10,482) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,708) + position: (899,483) caption: ROB[5] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,722) + position: (10,497) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,723) + position: (899,498) caption: ROB[4] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,737) + position: (10,512) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,738) + position: (899,513) caption: ROB[3] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,752) + position: (10,527) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,753) + position: (899,528) caption: ROB[2] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,767) + position: (10,542) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,768) + position: (899,543) caption: ROB[1] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,782) + position: (10,557) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,783) + position: (899,558) caption: ROB[0] - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,797) + position: (10,572) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,14) - position: (899,798) + position: (899,573) caption: ROB flush - Content: caption color: (192,192,192) dimensions: (150,15) - position: (10,812) + position: (10,587) caption: C=1 Cycle - Content: cycle color: (192,192,192) dimensions: (100,15) - position: (60,812) + position: (60,587) LocationString: .*rob.ReorderBuffer.ReorderBuffer0 t_offset: 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (160,812) + position: (160,587) caption: C=1 -10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (200,812) + position: (200,587) caption: C=1 -5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (240,812) + position: (240,587) caption: C=1 0 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (280,812) + position: (280,587) caption: C=1 5 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (320,812) + position: (320,587) caption: C=1 10 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (360,812) + position: (360,587) caption: C=1 15 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (400,812) + position: (400,587) caption: C=1 20 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (440,812) + position: (440,587) caption: C=1 25 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (480,812) + position: (480,587) caption: C=1 30 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (520,812) + position: (520,587) caption: C=1 35 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (560,812) + position: (560,587) caption: C=1 40 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (600,812) + position: (600,587) caption: C=1 45 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (640,812) + position: (640,587) caption: C=1 50 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (680,812) + position: (680,587) caption: C=1 55 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (720,812) + position: (720,587) caption: C=1 60 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (760,812) + position: (760,587) caption: C=1 65 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (800,812) + position: (800,587) caption: C=1 70 - Content: caption color: (192,192,192) dimensions: (40,15) - position: (840,812) + position: (840,587) caption: C=1 75 - Content: caption color: (0,0,0) @@ -1831,31 +1360,16 @@ - Content: caption color: (0,0,0) dimensions: (870,1) - position: (10,287) + position: (10,272) caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,347) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,407) - caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,467) - caption: - Content: caption color: (0,0,0) dimensions: (870,1) position: (10,572) caption: -- Content: caption - color: (0,0,0) - dimensions: (870,1) - position: (10,797) - caption: ... diff --git a/test/core/dcache/expected_output/arbitrate.out.EXPECTED b/test/core/dcache/expected_output/arbitrate.out.EXPECTED index 12179a3c..56419b63 100644 --- a/test/core/dcache/expected_output/arbitrate.out.EXPECTED +++ b/test/core/dcache/expected_output/arbitrate.out.EXPECTED @@ -3,39 +3,70 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Wednesday Wed Jul 31 16:59:06 2024 -#Elapsed: 0.002178s -{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Requested -{0000000001 00000001 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received -{0000000001 00000001 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000002 00000002 top.dcache info} mshrRequest_: Send mshr req -{0000000002 00000002 top.dcache info} handleLookup_: Lookup stage -{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage -{0000000002 00000002 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef -{0000000002 00000002 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' performing lookup 0 -{0000000002 00000002 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000002 00000002 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 -{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received -{0000000003 00000003 top.dcache info} handleDataRead_: Data Read stage -{0000000003 00000003 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in read stage -{0000000003 00000003 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' Received -{0000000004 00000004 top.next_lvl info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' ' sinked -{0000000004 00000004 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000004 00000004 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage -{0000000004 00000004 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' ' Requested -{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000009 00000009 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000009 00000009 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' -{0000000009 00000009 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3' ' Received -{0000000010 00000010 top.dcache info} mshrRequest_: Send mshr req -{0000000010 00000010 top.dcache info} handleLookup_: Lookup stage -{0000000010 00000010 top.dcache info} handleLookup_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in Lookup stage -{0000000010 00000010 top.dcache info} handleLookup_: Incoming cache refill memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' -{0000000011 00000011 top.dcache info} handleDataRead_: Data Read stage -{0000000011 00000011 top.dcache info} handleDataRead_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in read stage -{0000000011 00000011 top.dcache info} reloadCache_: DCache reload complete! -{0000000012 00000012 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000012 00000012 top.dcache info} handleDeallocate_: memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'lw 5,3' in deallocate stage +#Start: Tuesday Tue Oct 8 16:49:19 2024 +#Elapsed: 0.00278s +{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Requested +{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: Lookup stage +{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000001 00000001 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef +{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' performing lookup 0 +{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 +{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000001 00000001 top.dcache info} mshrRequest_: Send mshr req +{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' sinked +{0000000002 00000002 top.dcache info} handleDataRead_: Data Read stage +{0000000002 00000002 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000003 00000003 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000003 00000003 top.dcache info} mshrRequest_: Send mshr req +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} handleLookup_: Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Requested +{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} mshrRequest_: Send mshr req +{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: Lookup stage +{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000009 00000009 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeedbeef +{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' performing lookup 0 +{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeedbee0 +{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000009 00000009 top.dcache info} handleDataRead_: Data Read stage +{0000000009 00000009 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000009 00000009 top.dcache info} reloadCache_: DCache reload complete! +{0000000009 00000009 top.dcache info} mshrRequest_: Send mshr req +{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' sinked +{0000000010 00000010 top.dcache info} handleDataRead_: Data Read stage +{0000000010 00000010 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000011 00000011 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000011 00000011 top.dcache info} mshrRequest_: Send mshr req +{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000016 00000016 top.dcache info} handleLookup_: Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000016 00000016 top.dcache info} mshrRequest_: Send mshr req +{0000000017 00000017 top.dcache info} handleDataRead_: Data Read stage +{0000000017 00000017 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000017 00000017 top.dcache info} reloadCache_: DCache reload complete! +{0000000018 00000018 top.dcache info} handleDeallocate_: Data Dellocate stage +{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index 5f049f20..b54f664a 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.003678s +#Start: Tuesday Tue Oct 8 16:46:24 2024 +#Elapsed: 0.00175s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,18 +51,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -70,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index 837fbfc3..b999934f 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.003807s +#Start: Tuesday Tue Oct 8 16:46:24 2024 +#Elapsed: 0.001696s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,18 +44,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index f1f7560a..c5889fc6 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.003546s +#Start: Tuesday Tue Oct 8 16:46:24 2024 +#Elapsed: 0.002685s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,18 +38,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -57,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 0 uopid: 0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 10 RENAMED 0 pid: 0 uopid: 0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 11 RENAMED 0 pid: 0 uopid: 0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 12 RENAMED 0 pid: 0 uopid: 0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid: 0 COMPLETED 0 pid: 0 uopid: 0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 1 DISPATCHED 0 pid: 0 uopid: 0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid: 3 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid: 13 RENAMED 0 pid: 0 uopid: 0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid: 1 SCHEDULED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid: 4 RENAMED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid: 14 RENAMED 0 pid: 0 uopid: 0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid: 1 COMPLETED 0 pid: 0 uopid: 0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 2 DISPATCHED 0 pid: 0 uopid: 0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid: 5 RENAMED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid: 15 RENAMED 0 pid: 0 uopid: 0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid: 2 SCHEDULED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid: 6 RENAMED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid: 16 RENAMED 0 pid: 0 uopid: 0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid: 2 COMPLETED 0 pid: 0 uopid: 0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 3 DISPATCHED 0 pid: 0 uopid: 0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid: 7 RENAMED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid: 17 RENAMED 0 pid: 0 uopid: 0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid: 3 SCHEDULED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid: 8 RENAMED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid: 18 RENAMED 0 pid: 0 uopid: 0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid: 3 COMPLETED 0 pid: 0 uopid: 0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 4 DISPATCHED 0 pid: 0 uopid: 0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid: 9 RENAMED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid: 19 RENAMED 0 pid: 0 uopid: 0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid: 4 SCHEDULED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid: 4 COMPLETED 0 pid: 0 uopid: 0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 5 DISPATCHED 0 pid: 0 uopid: 0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid: 5 SCHEDULED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid: 5 COMPLETED 0 pid: 0 uopid: 0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 6 DISPATCHED 0 pid: 0 uopid: 0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid: 6 SCHEDULED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid: 6 COMPLETED 0 pid: 0 uopid: 0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 7 DISPATCHED 0 pid: 0 uopid: 0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid: 7 SCHEDULED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid: 7 COMPLETED 0 pid: 0 uopid: 0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 8 DISPATCHED 0 pid: 0 uopid: 0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid: 8 SCHEDULED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid: 8 COMPLETED 0 pid: 0 uopid: 0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 9 DISPATCHED 0 pid: 0 uopid: 0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid: 9 SCHEDULED 0 pid: 0 uopid: 0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid: 9 COMPLETED 0 pid: 0 uopid: 0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index 619d9ce5..94443f92 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu May 30 21:50:32 2024 -#Elapsed: 0.012536s +#Start: Tuesday Tue Oct 8 16:48:48 2024 +#Elapsed: 0.00378s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,21 +48,21 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port @@ -77,15 +77,15 @@ {0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid: 1 FETCHED 0 pid: 2 uopid: 0 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index 5af68b58..9aa80273 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,16 +3,16 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Thursday Thu May 30 21:50:19 2024 -#Elapsed: 0.015993s +#Start: Tuesday Tue Oct 8 16:48:48 2024 +#Elapsed: 0.00446s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 {0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received {0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Requested +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested {0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! @@ -28,16 +28,16 @@ {0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received {0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid: 0 FETCHED 0 pid: 1 uopid: 0 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index f954c737..02c33544 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.003622s +#Start: Tuesday Tue Oct 8 16:47:17 2024 +#Elapsed: 0.002245s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index 395d3a52..f98a7fc0 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.00475s +#Start: Tuesday Tue Oct 8 16:47:54 2024 +#Elapsed: 0.003636s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index 5eb25f2f..710dddf4 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.004244s +#Start: Tuesday Tue Oct 8 16:47:05 2024 +#Elapsed: 0.003742s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,7 +44,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 37d343de..36d8a20b 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Jul 16 09:09:57 2024 -#Elapsed: 0.004802s +#Start: Tuesday Tue Oct 8 16:47:26 2024 +#Elapsed: 0.003386s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,7 +38,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -46,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid: 0 RENAMED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid: 0 DISPATCHED 0 pid: 1 uopid: 0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid: 1 RENAMED 0 pid: 2 uopid: 0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid: 1 DISPATCHED 0 pid: 2 uopid: 0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid: 0 SCHEDULED 0 pid: 1 uopid: 0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid: 2 RENAMED 0 pid: 3 uopid: 0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid: 2 DISPATCHED 0 pid: 3 uopid: 0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid: 3 RENAMED 0 pid: 4 uopid: 0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/sim/CMakeLists.txt b/test/sim/CMakeLists.txt index 1ac20e41..ee44c64d 100644 --- a/test/sim/CMakeLists.txt +++ b/test/sim/CMakeLists.txt @@ -82,7 +82,7 @@ foreach(ARCH_FULL_PATH ${TEST_YAML}) sparta_named_test(olympia_arch_${ARCH_NAME}_random_branch_misprediction_test olympia -i500K --workload traces/dhry_riscv.zstf --arch ${ARCH_NAME} - -p top.cpu.core0.execute.exe*.params.enable_random_misprediction 1) + -p top.cpu.core0.execute.br*.params.enable_random_misprediction 1) endforeach() set(test_params_list) diff --git a/traces/load_to_use.json b/traces/load_to_use.json new file mode 100644 index 00000000..7b68a36d --- /dev/null +++ b/traces/load_to_use.json @@ -0,0 +1,15 @@ +[ + { + "mnemonic": "lw", + "rs1": 4, + "rs2": 3, + "rd": 5, + "vaddr" : "0xdeadbeef" + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 3, + "rd": 6 + } +] diff --git a/traces/many_adds.json b/traces/many_adds.json new file mode 100644 index 00000000..a71ae97e --- /dev/null +++ b/traces/many_adds.json @@ -0,0 +1,956 @@ +[ + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "add", + "rs1": 5, + "rs2": 2, + "rd": 3 + } +] diff --git a/traces/many_loads.json b/traces/many_loads.json new file mode 100644 index 00000000..2e37353f --- /dev/null +++ b/traces/many_loads.json @@ -0,0 +1,464 @@ +[ + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + }, + { + "mnemonic": "lw", + "rs1": 4, + "rd": 5, + "vaddr" : "0xdeadbee0" + } +] diff --git a/traces/many_muls.json b/traces/many_muls.json new file mode 100644 index 00000000..621ac6e9 --- /dev/null +++ b/traces/many_muls.json @@ -0,0 +1,602 @@ +[ + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + }, + { + "mnemonic": "mul", + "rs1": 5, + "rs2": 2, + "rd": 3 + } +]