diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5ae6aa6..926cdae 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,9 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.16.0] - 2022-08-25
+- Added instructions in updated crypto scalar spec.
+
 ## [0.15.0] - 2022-08-25
 - Added support for instruction aliases
 
diff --git a/riscv_isac/coverage.py b/riscv_isac/coverage.py
index 32c6402..6cd10a4 100644
--- a/riscv_isac/coverage.py
+++ b/riscv_isac/coverage.py
@@ -39,14 +39,17 @@
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
-        'bclri','bexti','binvi','bseti','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu']
+        'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci',\
+        'fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu']
+
 unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
         'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
         'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
         'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\
         'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
         'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
-        'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
+        'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw',\
+        'xperm4','xperm8','zip','unzip']
 
 class cross():
 
diff --git a/riscv_isac/data/rvopcodesdecoder.py b/riscv_isac/data/rvopcodesdecoder.py
index 22bf061..0c0d0d9 100644
--- a/riscv_isac/data/rvopcodesdecoder.py
+++ b/riscv_isac/data/rvopcodesdecoder.py
@@ -395,6 +395,10 @@ def decode(self, instrObj_temp):
                     temp_instrobj.rm = int(get_arg_val(arg)(mcode), 2)
                 if arg == 'csr':
                     temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'bs':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
+                if arg == 'rnum':
+                    temp_instrobj.imm = int(get_arg_val(arg)(mcode), 2)
                 if arg.find('imm') != -1:
                     if arg in ['imm12', 'imm20', 'zimm', 'imm2', 'imm3', 'imm4', 'imm5']:
                         imm = get_arg_val(arg)(mcode)
diff --git a/riscv_isac/plugins/internaldecoder.py b/riscv_isac/plugins/internaldecoder.py
index 0e9a4ea..59e3459 100644
--- a/riscv_isac/plugins/internaldecoder.py
+++ b/riscv_isac/plugins/internaldecoder.py
@@ -598,10 +598,10 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b001:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
-                    instrObj.instr_name = 'zip'
-                    instrObj.rs1= rs1
-                    instrObj.rd = rd
+                if self.arch == 'rv32':
+                   instrObj.instr_name = 'zip'
+                   instrObj.rs1= rs1
+                   instrObj.rd = rd
             elif sbi == 0b0100100 or  sbi == 0b010010:
                 instrObj.rs1 = rs1
                 instrObj.rd = rd
@@ -720,7 +720,7 @@ def arithi_ops(self, instrObj):
 
         if funct3 == 0b101:
             if funct7 == 0b0000100:
-                if instrObj.arch == 'rv32':
+                if self.arch == 'rv32':
                     instrObj.instr_name = 'unzip'
                     instrObj.rs1= rs1
                     instrObj.rd = rd
@@ -1210,15 +1210,10 @@ def arith_ops(self, instrObj):
                 instrObj.rs2 = rs2
                 instrObj.rd = rd
             elif funct7 == 0b0000100:
-                if rs2[0] == 0b0:
-                    instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
-                else:
-                    instrObj.instr_name = 'pack'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+                instrObj.instr_name = 'pack'
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0000101:
                 instrObj.instr_name = 'min'
                 instrObj.rs1 = rs1
@@ -1499,15 +1494,14 @@ def rv64i_arith_ops(self, instrObj):
 
         if funct3 == 0b100:
             if funct7 == 0b0000100:
-                if rs2[0] == 0b0:
-                    instrObj.instr_name = 'zext.h'
-                    instrObj.rs1 = rs1
-                    instrObj.rd = rd
-                else:
-                    instrObj.instr_name = 'packw'
-                    instrObj.rs1 = rs1
-                    instrObj.rs2 = rs2
-                    instrObj.rd = rd
+# packw and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
+# for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
+# then cannot distinguish from each other, hence using isa to differentiate.
+# zext.h is part of Zbb, packw is part of Zbkb
+                instrObj.instr_name = 'packw'
+                instrObj.rs1 = rs1
+                instrObj.rs2 = rs2
+                instrObj.rd = rd
             elif funct7 == 0b0010000:
                 instrObj.instr_name = 'sh2add.uw'
                 instrObj.rs1 = rs1
diff --git a/riscv_isac/plugins/specification.py b/riscv_isac/plugins/specification.py
index 2dcd765..4c8b529 100644
--- a/riscv_isac/plugins/specification.py
+++ b/riscv_isac/plugins/specification.py
@@ -19,4 +19,4 @@ def setup(self,trace,arch):
 
     @parserHookSpec
     def __iter__(self):
-        pass
\ No newline at end of file
+        pass