SystemVerilog Generation - Missing Decoder Module #761
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NicolasVanPhan
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I think the issue is you need to tell Sail to preserve it in the output. The However right now the generator gets stuck generating the decoder because of the size of the decoding logic. That's something I'm working on. |
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Hello Sail team,
I'm opening this discussion because I encountered an issue while generating SystemVerilog code from a RISC-V-based model written in Sail. In the generated SV code, I couldn't locate a decoder module or function.
This seems specific to the SystemVerilog generation, as:
Is decoder generation supported for the SV backend? If so, could you advise on any troubleshooting steps or settings that might address this?
Thank you for your time and help!
Best regards,
Nicolas
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