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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
# Start of session at: Wed Apr 19 13:07:24 2017
# Process ID: 9052
# Current directory: H:/EECS_443/Final_project
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9964 H:\EECS_443\Final_project\Final_project.xpr
# Log file: H:/EECS_443/Final_project/vivado.log
# Journal file: H:/EECS_443/Final_project\vivado.jou
#-----------------------------------------------------------
start_gui
open_project H:/EECS_443/Final_project/Final_project.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.2/data/ip'.
update_compile_order -fileset sources_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'voter_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'H:/EECS_443/Final_project/Final_project.sim/sim_1/behav'
"xvhdl -m64 --relax -prj voter_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "H:/EECS_443/Final_project/Final_project.srcs/sources_1/new/voter.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity voter
INFO: [VRFC 10-163] Analyzing VHDL file "H:/EECS_443/Final_project/Final_project.srcs/sim_1/imports/EECS_443/voter_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity voter_tb
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'H:/EECS_443/Final_project/Final_project.sim/sim_1/behav'
Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto a3056170f645485bac051c51decfeefa --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot voter_tb_behav xil_defaultlib.voter_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.voter [voter_default]
Compiling architecture behavioral of entity xil_defaultlib.voter_tb
Built simulation snapshot voter_tb_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'H:/EECS_443/Final_project/Final_project.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "voter_tb_behav -key {Behavioral:sim_1:Functional:voter_tb} -tclbatch {voter_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.2
Time resolution is 1 ps
source voter_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'voter_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 777.422 ; gain = 0.000