From ed39f906845c10f3145bb4d7b9301c59e0a71809 Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Wed, 2 Nov 2022 08:10:07 +0100 Subject: [PATCH 1/2] vcs-sim: Add scripts to run VCS sims, modify TBs to properly run in batch mode --- Makefile | 31 +++- scripts/compile_vcs.sh | 30 ++++ scripts/run_vcs.sh | 278 +++++++++++++++++++++++++++++++++++ scripts/run_vsim.sh | 23 --- test/tb_axi_addr_test.sv | 4 + test/tb_axi_dw_downsizer.sv | 4 + test/tb_axi_dw_upsizer.sv | 6 +- test/tb_axi_fifo.sv | 4 + test/tb_axi_isolate.sv | 4 + test/tb_axi_lite_mailbox.sv | 10 +- test/tb_axi_lite_regs.sv | 4 + test/tb_axi_lite_to_apb.sv | 4 + test/tb_axi_lite_xbar.sv | 4 + test/tb_axi_serializer.sv | 4 + test/tb_axi_to_axi_lite.sv | 4 + test/tb_axi_to_mem_banked.sv | 4 + test/tb_axi_xbar.sv | 4 + 17 files changed, 391 insertions(+), 31 deletions(-) create mode 100755 scripts/compile_vcs.sh create mode 100755 scripts/run_vcs.sh diff --git a/Makefile b/Makefile index 5d97a9542..82d75dfcf 100644 --- a/Makefile +++ b/Makefile @@ -14,37 +14,46 @@ ifneq (,$(wildcard /etc/iis.version)) VSIM ?= questa-2022.3 vsim SYNOPSYS_DC ?= synopsys-2022.03 dcnxt_shell + VLOGAN ?= vcs-2020.12 vlogan + VCS ?= vcs-2020.12 vcs else VSIM ?= vsim SYNOPSYS_DC ?= dc_shell + VLOGAN ?= vlogan + VCS ?= vcs endif TBS ?= axi_addr_test \ axi_atop_filter \ - axi_cdc axi_delayer \ + axi_bus_compare \ + axi_cdc \ + axi_delayer \ axi_dw_downsizer \ axi_dw_upsizer \ axi_fifo \ axi_isolate \ axi_iw_converter \ + axi_lite_mailbox \ axi_lite_regs \ axi_lite_to_apb \ axi_lite_to_axi \ - axi_lite_mailbox \ axi_lite_xbar \ axi_modify_address \ axi_serializer \ axi_sim_mem \ + axi_slave_compare \ axi_to_axi_lite \ axi_to_mem_banked \ axi_xbar -SIM_TARGETS := $(addsuffix .log,$(addprefix sim-,$(TBS))) + +SIM_TARGETS := $(addsuffix .log,$(addprefix sim-,$(TBS))) +SIMVCS_TARGETS := $(addsuffix .log,$(addprefix sim_vcs-,$(TBS))) .SHELL: bash -.PHONY: help all sim_all clean +.PHONY: help all sim_all sim_vcs_all clean help: @@ -65,6 +74,9 @@ all: compile.log elab.log sim_all sim_all: $(SIM_TARGETS) +sim_vcs_all: $(SIMVCS_TARGETS) + + build: mkdir -p $@ @@ -85,6 +97,17 @@ sim-%.log: compile.log (! grep -n "Fatal:" $@) +compile_vcs.log: Bender.yml | build + export VLOGAN="$(VLOGAN)"; cd build && ../scripts/compile_vcs.sh | tee ../$@ + (! grep -n "Error-" $@) + + +sim_vcs-%.log: compile_vcs.log + export VCS="$(VCS)"; cd build && ../scripts/run_vcs.sh --random-seed $* | tee ../$@ + (! grep -n "Error" $@) + (! grep -n "Fatal" $@) + + clean: rm -rf build rm -f *.log diff --git a/scripts/compile_vcs.sh b/scripts/compile_vcs.sh new file mode 100755 index 000000000..a71982838 --- /dev/null +++ b/scripts/compile_vcs.sh @@ -0,0 +1,30 @@ +#!/bin/bash +# Copyright (c) 2022 ETH Zurich, University of Bologna +# +# Copyright and related rights are licensed under the Solderpad Hardware +# License, Version 0.51 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# or agreed to in writing, software, hardware and materials distributed under +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# Authors: +# - Thomas Benz + +set -e + +[ ! -z "$VLOGAN" ] || VLOGAN=vlogan + +bender script vcs -t test -t rtl -t simulation \ + --vlog-arg="-full64" \ + --vlog-arg="-nc" \ + --vlog-arg="-q" \ + --vlog-arg="-assert svaext" \ + --vlog-arg="-timescale=1ns/1ps" \ + --vlogan-bin="$VLOGAN" \ + | grep -v "ROOT=" | sed '3 i ROOT="../"' \ + > compile_vcs.sh + +source compile_vcs.sh diff --git a/scripts/run_vcs.sh b/scripts/run_vcs.sh new file mode 100755 index 000000000..7dfdd9e55 --- /dev/null +++ b/scripts/run_vcs.sh @@ -0,0 +1,278 @@ +#!/bin/bash +# Copyright (c) 2022 ETH Zurich, University of Bologna +# +# Copyright and related rights are licensed under the Solderpad Hardware +# License, Version 0.51 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +# or agreed to in writing, software, hardware and materials distributed under +# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# Authors: +# - Thomas Benz + +set -euo pipefail +ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) + +# Seed values for `sv_seed`; can be extended with specific values on a per-TB basis, as well as with +# a random number by passing the `--random` flag. The default value, 0, is always included to stay +# regression-consistent. +SEEDS=(0) + +call_vcs() { + $VCS -Mlib=work-"${@: -1}" -Mdir=work-"${@: -1}" -debug_access+r -CFLAGS "-Os" -full64 -xprop=xmerge "$@" + for seed in ${SEEDS[@]}; do + echo + echo "----" + echo "Running with seed: $seed" + ./"${@: -1}" +ntb_random_seed=$seed -exitstatus | tee "${@: -1}"_$seed.log 2>&1 + (! grep -n "Error" "${@: -1}"_$seed.log) + (! grep -n "Fatal" "${@: -1}"_$seed.log) + done + # cleanup + echo + echo "----" + echo "Cleanup" + rm -rf work-"${@: -1}" + rm -rf "${@: -1}".daidir + rm -f "${@: -1}" + echo "Done" + echo "----" + echo + echo +} + +exec_test() { + if [ ! -e "$ROOT/test/tb_$1.sv" ]; then + echo "Testbench for '$1' not found!" + exit 1 + fi + case "$1" in + axi_atop_filter) + for MAX_TXNS in 1 3 12; do + call_vcs tb_axi_atop_filter \ + -pvalue+TB_N_TXNS=1000 \ + -pvalue+TB_AXI_MAX_WRITE_TXNS=$MAX_TXNS \ + -o tb_axi_atop_filter_${MAX_TXNS}.vcs + done + ;; + axi_cdc) + call_vcs tb_axi_cdc -o tb_axi_cdc.vcs + ;; + axi_delayer) + call_vcs tb_axi_delayer -o tb_axi_delayer.vcs + ;; + axi_dw_downsizer) + for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do + for (( AxiMstPortDataWidth = 8; \ + AxiMstPortDataWidth < $AxiSlvPortDataWidth; \ + AxiMstPortDataWidth *= 2 )); \ + do + call_vcs tb_axi_dw_downsizer \ + -pvalue+TbAxiSlvPortDataWidth=$AxiSlvPortDataWidth \ + -pvalue+TbAxiMstPortDataWidth=$AxiMstPortDataWidth \ + -o tb_axi_dw_downsizer_${AxiSlvPortDataWidth}_${AxiMstPortDataWidth}.vcs + done + done + ;; + axi_dw_upsizer) + for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do + for (( AxiMstPortDataWidth = $AxiSlvPortDataWidth*2; \ + AxiMstPortDataWidth <= 1024; \ + AxiMstPortDataWidth *= 2 )); \ + do + call_vcs tb_axi_dw_upsizer \ + -pvalue+TbAxiSlvPortDataWidth=$AxiSlvPortDataWidth \ + -pvalue+TbAxiMstPortDataWidth=$AxiMstPortDataWidth \ + -o tb_axi_dw_upsizer_${AxiSlvPortDataWidth}_${AxiMstPortDataWidth}.vcs + done + done + ;; + axi_fifo) + for DEPTH in 0 1 16; do + for FALL_THROUGH in 0 1; do + call_vcs tb_axi_fifo \ + -pvalue+Depth=$DEPTH \ + -pvalue+FallThrough=$FALL_THROUGH \ + -o tb_axi_fifo_${DEPTH}_${FALL_THROUGH}.vcs + done + done + ;; + axi_iw_converter) + for SLV_PORT_IW in 1 2 3 4 8; do + MAX_SLV_PORT_IDS=$((2**SLV_PORT_IW)) + MAX_UNIQ_SLV_PORT_IDS_OPTS=(1 2) + EXCL_OPTS=(0) + if [ $SLV_PORT_IW -eq 3 ]; then + # Save time by not testing exclusive accesses for every parametrization. + EXCL_OPTS+=(1) + fi + for EXCL in "${EXCL_OPTS[@]}"; do + if [ $MAX_SLV_PORT_IDS -gt 2 ]; then + MAX_UNIQ_SLV_PORT_IDS_OPTS+=(3 4) + fi + if [ $(($MAX_SLV_PORT_IDS/2)) -ge 4 ]; then + MAX_UNIQ_SLV_PORT_IDS_OPTS+=($((MAX_SLV_PORT_IDS/2-1))) + fi + MAX_UNIQ_SLV_PORT_IDS_OPTS+=($MAX_SLV_PORT_IDS) + for MST_PORT_IW in 1 2 3 4; do + if [ $MST_PORT_IW -lt $SLV_PORT_IW ]; then # downsize + for MAX_UNIQ_SLV_PORT_IDS in "${MAX_UNIQ_SLV_PORT_IDS_OPTS[@]}"; do + MAX_MST_PORT_IDS=$((2**MST_PORT_IW)) + if [ $MAX_UNIQ_SLV_PORT_IDS -le $MAX_MST_PORT_IDS ]; then + call_vcs tb_axi_iw_converter \ + -pvalue+TbEnExcl=$EXCL \ + -pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \ + -pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \ + -pvalue+TbAxiSlvPortMaxUniqIds=$MAX_UNIQ_SLV_PORT_IDS \ + -pvalue+TbAxiSlvPortMaxTxnsPerId=5 \ + -o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}_${MAX_UNIQ_SLV_PORT_IDS}.vcs + else + call_vcs tb_axi_iw_converter \ + -pvalue+TbEnExcl=$EXCL \ + -pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \ + -pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \ + -pvalue+TbAxiSlvPortMaxUniqIds=$MAX_UNIQ_SLV_PORT_IDS \ + -pvalue+TbAxiSlvPortMaxTxns=31 \ + -pvalue+TbAxiMstPortMaxUniqIds=$((2**MST_PORT_IW)) \ + -pvalue+TbAxiMstPortMaxTxnsPerId=7 \ + -o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}_${MAX_UNIQ_SLV_PORT_IDS}_$((2**MST_PORT_IW)).vcs + fi + done + else + call_vcs tb_axi_iw_converter \ + -pvalue+TbEnExcl=$EXCL \ + -pvalue+TbAxiSlvPortIdWidth=$SLV_PORT_IW \ + -pvalue+TbAxiMstPortIdWidth=$MST_PORT_IW \ + -pvalue+TbAxiSlvPortMaxTxnsPerId=3 \ + -o tb_axi_iw_converter_${EXCL}_${SLV_PORT_IW}_${MST_PORT_IW}.vcs + fi + done + done + done + ;; + axi_lite_regs) + for PRIV in 0 1; do + for SECU in 0 1; do + for BYTES in 42 369; do + call_vcs tb_axi_lite_regs \ + -pvalue+TbPrivProtOnly=$PRIV \ + -pvalue+TbSecuProtOnly=$SECU \ + -pvalue+TbRegNumBytes=$BYTES \ + -o tb_axi_lite_regs_${PRIV}_${SECU}_${BYTES}.vcs + done + done + done + ;; + axi_lite_to_apb) + for PIPE_REQ in 0 1; do + for PIPE_RESP in 0 1; do + call_vcs tb_axi_lite_to_apb \ + -pvalue+TbPipelineRequest=$PIPE_REQ \ + -pvalue+TbPipelineResponse=$PIPE_RESP \ + -o tb_axi_lite_to_apb_${PIPE_REQ}_${PIPE_RESP}.vcs + done + done + ;; + axi_lite_to_axi) + for DW in 8 16 32 64 128 256 512 1024; do + call_vcs tb_axi_lite_to_axi \ + -pvalue+TB_DW=$DW \ + -o tb_axi_lite_to_axi_${DW}.vcs + done + ;; + axi_sim_mem) + for AW in 16 32 64; do + for DW in 32 64 128 256 512 1024; do + call_vcs tb_axi_sim_mem \ + -pvalue+TbAddrWidth=$AW \ + -pvalue+TbDataWidth=$DW \ + -o tb_axi_sim_mem_${AW}_${DW}.vcs + done + done + ;; + axi_xbar) + for NumMst in 1 6; do + for NumSlv in 1 8; do + for Atop in 0 1; do + for Exclusive in 0 1; do + for UniqueIds in 0 1; do + for DataWidth in 64 256; do + for Pipe in 0 1; do + call_vcs tb_axi_xbar \ + -pvalue+TbNumMasters=$NumMst \ + -pvalue+TbNumSlaves=$NumSlv \ + -pvalue+TbEnAtop=$Atop \ + -pvalue+TbEnExcl=$Exclusive \ + -pvalue+TbUniqueIds=$UniqueIds \ + -pvalue+TbAxiDataWidth=$DataWidth \ + -pvalue+TbPipeline=$Pipe \ + -o tb_axi_xbar_${NumMst}_${NumSlv}_${Atop}_${Exclusive}_${UniqueIds}_${DataWidth}_${Pipe}.vcs + done + done + done + done + done + done + done + ;; + axi_to_mem_banked) + for MEM_LAT in 1 2; do + for BANK_FACTOR in 1 2; do + for NUM_BANKS in 1 2 ; do + for AXI_DATA_WIDTH in 64 256 ; do + ACT_BANKS=$((2*$BANK_FACTOR*$NUM_BANKS)) + MEM_DATA_WIDTH=$(($AXI_DATA_WIDTH/$NUM_BANKS)) + call_vcs tb_axi_to_mem_banked \ + -pvalue+TbAxiDataWidth=$AXI_DATA_WIDTH \ + -pvalue+TbNumWords=2048 \ + -pvalue+TbNumBanks=$ACT_BANKS \ + -pvalue+TbMemDataWidth=$MEM_DATA_WIDTH \ + -pvalue+TbMemLatency=$MEM_LAT \ + -pvalue+TbNumWrites=2000 \ + -pvalue+TbNumReads=2000 \ + -o tb_axi_to_mem_banked_${AXI_DATA_WIDTH}_${ACT_BANKS}_${MEM_DATA_WIDTH}_${MEM_LAT}.vcs + done + done + done + done + ;; + *) + call_vcs tb_$1 -o tb_${1}.vcs + ;; + esac +} + +# Parse flags. +PARAMS="" +while (( "$#" )); do + case "$1" in + --random-seed) + SEEDS+=($RANDOM) + shift;; + -*--*) # unsupported flag + echo "Error: Unsupported flag '$1'." >&2 + exit 1;; + *) # preserve positional arguments + PARAMS="$PARAMS $1" + shift;; + esac +done +eval set -- "$PARAMS" + +if [ "$#" -eq 0 ]; then + tests=() + while IFS= read -r -d $'\0'; do + tb_name="$(basename -s .sv $REPLY)" + dut_name="${tb_name#tb_}" + tests+=("$dut_name") + done < <(find "$ROOT/test" -name 'tb_*.sv' -a \( ! -name '*_pkg.sv' \) -print0) +else + tests=("$@") +fi + +for t in "${tests[@]}"; do + exec_test $t +done diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index aaf8c3f22..7214c9d38 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -211,29 +211,6 @@ exec_test() { done done ;; - axi_xbar) - for GEN_ATOP in 0 1; do - for NUM_MST in 1 6; do - for NUM_SLV in 2 9; do - for MST_ID_USE in 3 5; do - MST_ID=5 - for DATA_WIDTH in 64 256; do - for PIPE in 0 1; do - call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \ - -gTbNumMasters=$NUM_MST \ - -gTbNumSlaves=$NUM_SLV \ - -gTbAxiIdWidthMasters=$MST_ID \ - -gTbAxiIdUsed=$MST_ID_USE \ - -gTbAxiDataWidth=$DATA_WIDTH \ - -gTbPipeline=$PIPE \ - -gTbEnAtop=$GEN_ATOP - done - done - done - done - done - done - ;; axi_lite_dw_converter) for DWSLV in 32 64 128; do for DWMST in 16 32 64; do diff --git a/test/tb_axi_addr_test.sv b/test/tb_axi_addr_test.sv index 49d8c3f1a..a74b69c66 100644 --- a/test/tb_axi_addr_test.sv +++ b/test/tb_axi_addr_test.sv @@ -121,7 +121,11 @@ module tb_axi_addr_test #( axi_rand_master.run(0, NumTests); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end initial begin : proc_axi_slave diff --git a/test/tb_axi_dw_downsizer.sv b/test/tb_axi_dw_downsizer.sv index a11baf9d3..31c8e6a26 100644 --- a/test/tb_axi_dw_downsizer.sv +++ b/test/tb_axi_dw_downsizer.sv @@ -201,7 +201,11 @@ module tb_axi_dw_downsizer #( #TbTestTime; if(eos) begin monitor.print_result(); + `ifdef TARGET_VCS + $finish(1) ; + `else $stop() ; + `endif end @(posedge clk); end diff --git a/test/tb_axi_dw_upsizer.sv b/test/tb_axi_dw_upsizer.sv index 8a8e03392..7b742e0e9 100644 --- a/test/tb_axi_dw_upsizer.sv +++ b/test/tb_axi_dw_upsizer.sv @@ -171,7 +171,11 @@ module tb_axi_dw_upsizer #( #TbTestTime; if(eos) begin monitor.print_result(); - $stop() ; + `ifdef TARGET_VCS + $finish(1); + `else + $stop(); + `endif end @(posedge clk); end diff --git a/test/tb_axi_fifo.sv b/test/tb_axi_fifo.sv index 2e79044e0..2367228d0 100644 --- a/test/tb_axi_fifo.sv +++ b/test/tb_axi_fifo.sv @@ -127,7 +127,11 @@ module tb_axi_fifo #( axi_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end initial begin : proc_axi_slave diff --git a/test/tb_axi_isolate.sv b/test/tb_axi_isolate.sv index e148afbd0..8b887b2a2 100644 --- a/test/tb_axi_isolate.sv +++ b/test/tb_axi_isolate.sv @@ -141,7 +141,11 @@ module tb_axi_isolate #( axi_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; repeat (10000) @(posedge clk); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end initial begin : proc_axi_slave diff --git a/test/tb_axi_lite_mailbox.sv b/test/tb_axi_lite_mailbox.sv index 255702922..368e95e2b 100644 --- a/test/tb_axi_lite_mailbox.sv +++ b/test/tb_axi_lite_mailbox.sv @@ -151,7 +151,7 @@ module tb_axi_lite_mailbox; assert (data == data_t'(3'b100)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Acknowledge Error by writing to IRQS", $time()); + $display("%0t MST_0> Acknowledge error by writing to IRQS", $time()); lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), 64'h4, 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end @@ -175,7 +175,7 @@ module tb_axi_lite_mailbox; // ------------------------------- repeat (50) @(posedge clk); $info("Test error interrupt"); - $display("%0t MST_0> Enable Error interrupt ", $time()); + $display("%0t MST_0> Enable error interrupt ", $time()); lite_axi_master.write(IRQEN, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end @@ -189,7 +189,7 @@ module tb_axi_lite_mailbox; assert (data == data_t'(1)) else begin test_failed[0]++; $error("Unexpected result"); end assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end - $display("%0t MST_0> Acknowledge Error by writing to IRQS", $time()); + $display("%0t MST_0> Acknowledge error by writing to IRQS", $time()); lite_axi_master.write(IRQS, axi_pkg::prot_t'('0), data_t'(3'b100), 8'hFF, resp); assert (resp == axi_pkg::RESP_OKAY) else begin test_failed[0]++; $error("Unexpected result"); end @@ -430,7 +430,11 @@ module tb_axi_lite_mailbox; end else begin $info("Simulation stopped as all Masters transferred their data, Success.",); end + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end //----------------------------------- diff --git a/test/tb_axi_lite_regs.sv b/test/tb_axi_lite_regs.sv index 32168d483..2e7064a97 100644 --- a/test/tb_axi_lite_regs.sv +++ b/test/tb_axi_lite_regs.sv @@ -325,7 +325,11 @@ module tb_axi_lite_regs #( wait (end_of_sim); repeat (1000) @(posedge clk); $display("Simulation stopped as Master transferred its data."); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end //----------------------------------- diff --git a/test/tb_axi_lite_to_apb.sv b/test/tb_axi_lite_to_apb.sv index 8910198e4..7dce861fa 100644 --- a/test/tb_axi_lite_to_apb.sv +++ b/test/tb_axi_lite_to_apb.sv @@ -164,7 +164,11 @@ module tb_axi_lite_to_apb #( initial begin : proc_sim_stop @(posedge rst_n); wait (end_of_sim); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end // pragma translate_off diff --git a/test/tb_axi_lite_xbar.sv b/test/tb_axi_lite_xbar.sv index 54697344a..8fcd4ad76 100644 --- a/test/tb_axi_lite_xbar.sv +++ b/test/tb_axi_lite_xbar.sv @@ -152,7 +152,11 @@ module tb_axi_lite_xbar; wait (&end_of_sim); repeat (1000) @(posedge clk); $display("Simulation stopped as all Masters transferred their data, Success.",); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end //----------------------------------- diff --git a/test/tb_axi_serializer.sv b/test/tb_axi_serializer.sv index b23e5cbc0..cca5ac708 100644 --- a/test/tb_axi_serializer.sv +++ b/test/tb_axi_serializer.sv @@ -137,7 +137,11 @@ module tb_axi_serializer #( axi_rand_master.run(NoReads, NoWrites); end_of_sim <= 1'b1; repeat (100) @(posedge clk); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end initial begin : proc_axi_slave diff --git a/test/tb_axi_to_axi_lite.sv b/test/tb_axi_to_axi_lite.sv index e854cb106..f86df7c2c 100644 --- a/test/tb_axi_to_axi_lite.sv +++ b/test/tb_axi_to_axi_lite.sv @@ -130,7 +130,11 @@ module tb_axi_to_axi_lite; done = 1'b1; $info("All AXI4+ATOP Bursts converted to AXI4-Lite"); repeat (4) @(posedge clk); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end initial begin diff --git a/test/tb_axi_to_mem_banked.sv b/test/tb_axi_to_mem_banked.sv index 64667998d..42f298e25 100644 --- a/test/tb_axi_to_mem_banked.sv +++ b/test/tb_axi_to_mem_banked.sv @@ -352,7 +352,11 @@ module tb_axi_to_mem_banked #( $display("Sum bank utilization: %0f", bank_busy_percent); $display("Sum axi utilization: %0f", axi_busy_percent); $display("###############################################################################"); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end end end diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index 6056be919..b4d90e857 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -258,7 +258,11 @@ module tb_axi_xbar #( #TestTime; if(end_of_sim == '1) begin monitor.print_result(); + `ifdef TARGET_VCS + $finish(1); + `else $stop(); + `endif end @(posedge clk); end while (1'b1); From bf32b9fbc578ebc28fcbbb5381319b3bf0f6ed3e Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Wed, 30 Nov 2022 09:53:00 +0100 Subject: [PATCH 2/2] Add VCS to CI --- .gitlab-ci.yml | 104 +++++++++++++++++++++++++++++++++++++++++++++ Makefile | 7 ++- scripts/run_vcs.sh | 3 +- 3 files changed, 112 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 1ac12d887..b37b9fe5e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -5,6 +5,10 @@ before_script: - export PATH=~/.cargo/bin:$PATH - mkdir -p build +stages: + - build + - test + vsim: stage: build script: @@ -179,3 +183,103 @@ axi_xbar: <<: *run_vsim variables: TEST_MODULE: axi_xbar + +vcs_axi_addr_test: + stage: test + script: + - make sim_vcs-axi_addr_test.log + +vcs_axi_atop_filter: + stage: test + script: + - make sim_vcs-axi_atop_filter.log + +vcs_axi_cdc: + stage: test + script: + - make sim_vcs-axi_cdc.log + +vcs_axi_delayer: + stage: test + script: + - make sim_vcs-axi_delayer.log + +vcs_axi_dw_downsizer: + stage: test + script: + - make sim_vcs-axi_dw_downsizer.log + +vcs_axi_dw_upsizer: + stage: test + script: + - make sim_vcs-axi_dw_upsizer.log + +vcs_axi_fifo: + stage: test + script: + - make sim_vcs-axi_fifo.log + +vcs_axi_isolate: + stage: test + script: + - make sim_vcs-axi_isolate.log + +vcs_axi_iw_converter: + stage: test + script: + - make sim_vcs-axi_iw_converter.log + +vcs_axi_lite_regs: + stage: test + script: + - make sim_vcs-axi_lite_regs.log + +vcs_axi_lite_to_apb: + stage: test + script: + - make sim_vcs-axi_lite_to_apb.log + +vcs_axi_lite_to_axi: + stage: test + script: + - make sim_vcs-axi_lite_to_axi.log + +vcs_axi_lite_mailbox: + stage: test + script: + - make sim_vcs-axi_lite_mailbox.log + +vcs_axi_lite_xbar: + stage: test + script: + - make sim_vcs-axi_lite_xbar.log + +vcs_axi_modify_address: + stage: test + script: + - make sim_vcs-axi_modify_address.log + +vcs_axi_serializer: + stage: test + script: + - make sim_vcs-axi_serializer.log + +vcs_axi_sim_mem: + stage: test + script: + - make sim_vcs-axi_sim_mem.log + +vcs_axi_to_axi_lite: + stage: test + script: + - make sim_vcs-axi_to_axi_lite.log + +vcs_axi_to_mem_banked: + stage: test + script: + - make sim_vcs-axi_to_mem_banked.log + +vcs_axi_xbar: + stage: test + script: + - make sim_vcs-axi_xbar.log diff --git a/Makefile b/Makefile index 82d75dfcf..1dad6b349 100644 --- a/Makefile +++ b/Makefile @@ -23,6 +23,11 @@ else VCS ?= vcs endif +# VCS_DEBUG ?= -debug_access+r +VCS_DEBUG ?= -debug_access+nomemcbk +VCS_XPROP ?= -xprop=xmerge +VCS_OPT ?= $(VCS_XPROP) $(VCS_DEBUG) -full64 -CFLAGS \"-O4\" -O4 -j9 + TBS ?= axi_addr_test \ axi_atop_filter \ axi_bus_compare \ @@ -103,7 +108,7 @@ compile_vcs.log: Bender.yml | build sim_vcs-%.log: compile_vcs.log - export VCS="$(VCS)"; cd build && ../scripts/run_vcs.sh --random-seed $* | tee ../$@ + export VCS="$(VCS)"; export VCS_OPT="$(VCS_OPT)"; cd build && ../scripts/run_vcs.sh --random-seed $* | tee ../$@ (! grep -n "Error" $@) (! grep -n "Fatal" $@) diff --git a/scripts/run_vcs.sh b/scripts/run_vcs.sh index 7dfdd9e55..58dfdf16b 100755 --- a/scripts/run_vcs.sh +++ b/scripts/run_vcs.sh @@ -22,11 +22,12 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd) SEEDS=(0) call_vcs() { - $VCS -Mlib=work-"${@: -1}" -Mdir=work-"${@: -1}" -debug_access+r -CFLAGS "-Os" -full64 -xprop=xmerge "$@" + $VCS -Mlib=work-"${@: -1}" -Mdir=work-"${@: -1}" $VCS_OPT "$@" for seed in ${SEEDS[@]}; do echo echo "----" echo "Running with seed: $seed" + echo "VCS options: $VCS_OPT" ./"${@: -1}" +ntb_random_seed=$seed -exitstatus | tee "${@: -1}"_$seed.log 2>&1 (! grep -n "Error" "${@: -1}"_$seed.log) (! grep -n "Fatal" "${@: -1}"_$seed.log)