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top.syr
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top.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.14 secs
--> Reading design: top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "top.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "top"
Output Format : NGC
Target Device : xc3s400-4-pq208
---- Source Options
Top Module Name : top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/AMIN/Desktop/Project/Dot_Matrix/loadshiftregisters.vhd" in Library work.
Architecture behavioral of Entity loadshiftregisters is up to date.
Compiling vhdl file "C:/Users/AMIN/Desktop/Project/Dot_Matrix/keypad.vhd" in Library work.
Architecture behavioral of Entity keypad is up to date.
Compiling vhdl file "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" in Library work.
Architecture behavioral of Entity num_decode is up to date.
Compiling vhdl file "C:/Users/AMIN/Desktop/Project/Dot_Matrix/Shift_Registers.vhd" in Library work.
Architecture behavioral of Entity shift_registers is up to date.
Compiling vhdl file "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" in Library work.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <top> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <loadshiftregisters> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <keypad> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <num_decode> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <Shift_Registers> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <top> in library <work> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 29: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 25: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 26: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 28: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 29: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 30: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 31: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 32: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 33: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 34: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
INFO:Xst:1739 - HDL ADVISOR - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd" line 35: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <top> analyzed. Unit <top> generated.
Analyzing Entity <loadshiftregisters> in library <work> (Architecture <behavioral>).
Entity <loadshiftregisters> analyzed. Unit <loadshiftregisters> generated.
Analyzing Entity <keypad> in library <work> (Architecture <behavioral>).
Entity <keypad> analyzed. Unit <keypad> generated.
Analyzing Entity <num_decode> in library <work> (Architecture <behavioral>).
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 58: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 79: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 100: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 121: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 142: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 163: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 184: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 205: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 226: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 247: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 268: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 289: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 310: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 331: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 352: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 373: Mux is complete : default of case is discarded
INFO:Xst:1561 - "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd" line 373: Mux is complete : default of case is discarded
Entity <num_decode> analyzed. Unit <num_decode> generated.
Analyzing Entity <Shift_Registers> in library <work> (Architecture <behavioral>).
Entity <Shift_Registers> analyzed. Unit <Shift_Registers> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <loadshiftregisters>.
Related source file is "C:/Users/AMIN/Desktop/Project/Dot_Matrix/loadshiftregisters.vhd".
Found 3-bit register for signal <CURRENT_STATE>.
Found 2-bit register for signal <CURRENT_LED>.
Found 1-bit register for signal <DATA>.
Found 1-bit register for signal <clk_temp>.
Found 5-bit up counter for signal <counter>.
Found 5-bit up counter for signal <prescale>.
Summary:
inferred 2 Counter(s).
inferred 7 D-type flip-flop(s).
Unit <loadshiftregisters> synthesized.
Synthesizing Unit <keypad>.
Related source file is "C:/Users/AMIN/Desktop/Project/Dot_Matrix/keypad.vhd".
WARNING:Xst:1780 - Signal <last_key_temp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 4 |
| Inputs | 0 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Power Up State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 4-bit register for signal <keyout>.
Found 4-bit register for signal <number>.
Found 1-bit register for signal <key_changed>.
Found 1-bit register for signal <key_changed_temp>.
Found 1-bit register for signal <start_timer>.
Found 21-bit up counter for signal <timer>.
Summary:
inferred 1 Finite State Machine(s).
inferred 1 Counter(s).
inferred 11 D-type flip-flop(s).
Unit <keypad> synthesized.
Synthesizing Unit <num_decode>.
Related source file is "C:/Users/AMIN/Desktop/Project/Dot_Matrix/num_decode.vhd".
Found 8x128-bit ROM for signal <horizontal$rom0000>.
Found 8-bit register for signal <rout>.
Found 8-bit 16-to-1 multiplexer for signal <rout$mux0003> created at line 40.
Summary:
inferred 1 ROM(s).
inferred 8 D-type flip-flop(s).
inferred 8 Multiplexer(s).
Unit <num_decode> synthesized.
Synthesizing Unit <Shift_Registers>.
Related source file is "C:/Users/AMIN/Desktop/Project/Dot_Matrix/Shift_Registers.vhd".
Found 4-bit register for signal <Fifth_number>.
Found 4-bit register for signal <Seventh_number>.
Found 4-bit register for signal <Eighth_number>.
Found 4-bit register for signal <First_number>.
Found 4-bit register for signal <Forth_number>.
Found 4-bit register for signal <Second_number>.
Found 4-bit register for signal <Third_number>.
Found 4-bit register for signal <Sixth_number>.
Found 32-bit register for signal <All_Data>.
Summary:
inferred 64 D-type flip-flop(s).
Unit <Shift_Registers> synthesized.
Synthesizing Unit <top>.
Related source file is "C:/Users/AMIN/Desktop/Project/Dot_Matrix/top.vhd".
WARNING:Xst:653 - Signal <empty_flag> is used but never assigned. This sourceless signal will be automatically connected to value 0.
Found 4-bit register for signal <number_temp0>.
Found 4-bit 4-to-1 multiplexer for signal <number_temp0$mux0000>.
Found 4-bit register for signal <number_temp1>.
Found 4-bit 4-to-1 multiplexer for signal <number_temp1$mux0000>.
Summary:
inferred 8 D-type flip-flop(s).
inferred 8 Multiplexer(s).
Unit <top> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 2
8x128-bit ROM : 2
# Counters : 3
21-bit up counter : 1
5-bit up counter : 2
# Registers : 22
1-bit register : 5
2-bit register : 1
3-bit register : 1
32-bit register : 1
4-bit register : 12
8-bit register : 2
# Multiplexers : 4
4-bit 4-to-1 multiplexer : 2
8-bit 16-to-1 multiplexer : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <Inst_keypad/state/FSM> on signal <state[1:4]> with one-hot encoding.
-------------------
State | Encoding
-------------------
00 | 0001
01 | 0010
10 | 0100
11 | 1000
-------------------
Synthesizing (advanced) Unit <top>.
INFO:Xst:3044 - The ROM <Inst_num_decode_UP/Mrom_horizontal_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <Inst_loadshiftregisters/CURRENT_STATE>.
INFO:Xst:3044 - The ROM <Inst_num_decode_DOWN/Mrom_horizontal_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <Inst_loadshiftregisters/CURRENT_STATE>.
INFO:Xst:3225 - The RAM <Inst_num_decode_UP/Mrom_horizontal_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 128-bit | |
| mode | write-first | |
| clkA | connected to signal <CLK_20M> | rise |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <Inst_loadshiftregisters/counter> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
INFO:Xst:3225 - The RAM <Inst_num_decode_DOWN/Mrom_horizontal_rom0000> will be implemented as BLOCK RAM
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 128-bit | |
| mode | write-first | |
| clkA | connected to signal <CLK_20M> | rise |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <Inst_loadshiftregisters/counter> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <top> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 2
8x128-bit single-port block RAM : 2
# Counters : 3
21-bit up counter : 1
5-bit up counter : 2
# Registers : 107
Flip-Flops : 107
# Multiplexers : 4
4-bit 4-to-1 multiplexer : 2
8-bit 16-to-1 multiplexer : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
INFO:Xst:2697 - Unit <top> : the RAMs <Inst_num_decode_UP/Mrom_horizontal_rom0000>, <Inst_num_decode_DOWN/Mrom_horizontal_rom0000> are packed into the single block RAM <Inst_num_decode_UP/Mrom_horizontal_rom00001>
Optimizing unit <top> ...
Optimizing unit <keypad> ...
Optimizing unit <Shift_Registers> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 4.
Final Macro Processing ...
Processing Unit <top> :
Found 2-bit shift register for signal <Inst_Shift_Registers/Eighth_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Eighth_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Eighth_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Eighth_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Fifth_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Fifth_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Fifth_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Fifth_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Sixth_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Sixth_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Sixth_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Sixth_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Third_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Third_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Third_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Third_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Seventh_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Seventh_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Seventh_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Seventh_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Forth_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Forth_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Forth_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Forth_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/First_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/First_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/First_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/First_number_0>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Second_number_3>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Second_number_2>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Second_number_1>.
Found 2-bit shift register for signal <Inst_Shift_Registers/Second_number_0>.
Unit <top> processed.
=========================================================================
Final Register Report
Macro Statistics
# Registers : 74
Flip-Flops : 74
# Shift Registers : 32
2-bit shift register : 32
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : top.ngr
Top Level Output File Name : top
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 28
Cell Usage :
# BELS : 386
# GND : 5
# INV : 3
# LUT1 : 21
# LUT2 : 2
# LUT2_L : 1
# LUT3 : 148
# LUT3_L : 2
# LUT4 : 25
# LUT4_D : 1
# LUT4_L : 3
# MUXCY : 32
# MUXF5 : 73
# MUXF6 : 32
# MUXF7 : 16
# VCC : 1
# XORCY : 21
# FlipFlops/Latches : 106
# FD : 58
# FDE : 22
# FDR : 25
# FDRE : 1
# RAMS : 4
# RAMB16 : 4
# Shift Registers : 32
# SRL16 : 32
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 27
# IBUF : 4
# OBUF : 23
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 129 out of 3584 3%
Number of Slice Flip Flops: 105 out of 7168 1%
Number of 4 input LUTs: 238 out of 7168 3%
Number used as logic: 206
Number used as Shift registers: 32
Number of IOs: 28
Number of bonded IOBs: 28 out of 141 19%
IOB Flip Flops: 1
Number of BRAMs: 4 out of 16 25%
Number of GCLKs: 2 out of 8 25%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+----------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+----------------------------------------+-------+
CLK_20M | BUFGP | 73 |
Inst_loadshiftregisters/clk_temp | NONE(Inst_loadshiftregisters/counter_2)| 5 |
Inst_keypad/key_changed1 | BUFG | 64 |
-----------------------------------+----------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 5.667ns (Maximum Frequency: 176.460MHz)
Minimum input arrival time before clock: 7.724ns
Maximum output required time after clock: 7.430ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK_20M'
Clock period: 5.667ns (frequency: 176.460MHz)
Total number of paths / destination ports: 638 / 89
-------------------------------------------------------------------------
Delay: 5.667ns (Levels of Logic = 2)
Source: Inst_keypad/keyout_0 (FF)
Destination: Inst_keypad/key_changed_temp (FF)
Source Clock: CLK_20M rising
Destination Clock: CLK_20M rising
Data Path: Inst_keypad/keyout_0 to Inst_keypad/key_changed_temp
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 6 0.720 1.071 Inst_keypad/keyout_0 (Inst_keypad/keyout_0)
LUT4:I2->O 1 0.551 0.827 Inst_keypad/key_changed_temp_or0000137_SW0 (N18)
LUT4:I3->O 5 0.551 0.921 Inst_keypad/key_changed_temp_or0000137 (Inst_keypad/key_changed_temp_or0000)
FDR:R 1.026 Inst_keypad/key_changed_temp
----------------------------------------
Total 5.667ns (2.848ns logic, 2.819ns route)
(50.3% logic, 49.7% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_loadshiftregisters/clk_temp'
Clock period: 3.719ns (frequency: 268.889MHz)
Total number of paths / destination ports: 15 / 5
-------------------------------------------------------------------------
Delay: 3.719ns (Levels of Logic = 2)
Source: Inst_loadshiftregisters/counter_1 (FF)
Destination: Inst_loadshiftregisters/counter_5 (FF)
Source Clock: Inst_loadshiftregisters/clk_temp rising
Destination Clock: Inst_loadshiftregisters/clk_temp rising
Data Path: Inst_loadshiftregisters/counter_1 to Inst_loadshiftregisters/counter_5
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 14 0.720 1.526 Inst_loadshiftregisters/counter_1 (Inst_loadshiftregisters/Mcount_counter_cy<0>)
LUT3_L:I0->LO 1 0.551 0.168 Inst_loadshiftregisters/Mcount_counter_xor<3>111 (N3)
LUT3:I2->O 1 0.551 0.000 Inst_loadshiftregisters/Mcount_counter_xor<4>11 (Result<4>1)
FD:D 0.203 Inst_loadshiftregisters/counter_5
----------------------------------------
Total 3.719ns (2.025ns logic, 1.694ns route)
(54.5% logic, 45.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_keypad/key_changed1'
Clock period: 3.398ns (frequency: 294.291MHz)
Total number of paths / destination ports: 60 / 60
-------------------------------------------------------------------------
Delay: 3.398ns (Levels of Logic = 0)
Source: Inst_Shift_Registers/Mshreg_First_number_3 (FF)
Destination: Inst_Shift_Registers/First_number_3 (FF)
Source Clock: Inst_keypad/key_changed1 rising
Destination Clock: Inst_keypad/key_changed1 rising
Data Path: Inst_Shift_Registers/Mshreg_First_number_3 to Inst_Shift_Registers/First_number_3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
SRL16:CLK->Q 1 3.195 0.000 Inst_Shift_Registers/Mshreg_First_number_3 (Inst_Shift_Registers/Mshreg_First_number_3)
FD:D 0.203 Inst_Shift_Registers/First_number_3
----------------------------------------
Total 3.398ns (3.398ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK_20M'
Total number of paths / destination ports: 96 / 5
-------------------------------------------------------------------------
Offset: 7.724ns (Levels of Logic = 4)
Source: column<0> (PAD)
Destination: Inst_keypad/key_changed_temp (FF)
Destination Clock: CLK_20M rising
Data Path: column<0> to Inst_keypad/key_changed_temp
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.821 1.260 column_0_IBUF (column_0_IBUF)
LUT4:I0->O 2 0.551 1.216 Inst_keypad/key_changed_temp_or000054 (Inst_keypad/key_changed_temp_or000054)
LUT4:I0->O 1 0.551 0.827 Inst_keypad/key_changed_temp_or0000137_SW0 (N18)
LUT4:I3->O 5 0.551 0.921 Inst_keypad/key_changed_temp_or0000137 (Inst_keypad/key_changed_temp_or0000)
FDR:R 1.026 Inst_keypad/key_changed_temp
----------------------------------------
Total 7.724ns (3.500ns logic, 4.224ns route)
(45.3% logic, 54.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_20M'
Total number of paths / destination ports: 22 / 22
-------------------------------------------------------------------------
Offset: 7.430ns (Levels of Logic = 1)
Source: Inst_loadshiftregisters/clk_temp (FF)
Destination: DOTMATRIX_CLK (PAD)
Source Clock: CLK_20M rising
Data Path: Inst_loadshiftregisters/clk_temp to DOTMATRIX_CLK
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 7 0.720 1.066 Inst_loadshiftregisters/clk_temp (Inst_loadshiftregisters/clk_temp)
OBUF:I->O 5.644 DOTMATRIX_CLK_OBUF (DOTMATRIX_CLK)
----------------------------------------
Total 7.430ns (6.364ns logic, 1.066ns route)
(85.7% logic, 14.3% route)
=========================================================================
Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 9.52 secs
-->
Total memory usage is 4537092 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 34 ( 0 filtered)