diff --git a/.github/workflows/bcm2711.yaml b/.github/workflows/bcm2711.yaml new file mode 100644 index 00000000000000..7d530001f0deeb --- /dev/null +++ b/.github/workflows/bcm2711.yaml @@ -0,0 +1,86 @@ +name: Build bcm2711 RPi 4B +on: [push] + +jobs: + build: + name: Build Raspberry Pi 4 images + runs-on: ubuntu-latest + + steps: + - name: Maximize build space + uses: easimon/maximize-build-space@master + with: + root-reserve-mb: 512 + swap-size-mb: 1024 + remove-dotnet: 'true' + overprovision-lvm: 'true' + remove-android: 'true' + remove-haskell: 'true' + remove-codeql: 'true' + remove-docker-images: 'true' + - name: Checkout + uses: actions/checkout@v4 + + - name: Build + run: | + ./scripts/feeds update -a + ./scripts/feeds install -a + cd feeds/luci + wget https://gist.githubusercontent.com/mj22226/363cefecd314e45b49d8eafff8473fcf/raw/69b47c9a972e15056f94870d76d93a5146893f99/01-diskman.patch + + git apply 01-diskman.patch + + cd - + cd feeds/packages + wget https://gist.githubusercontent.com/mj22226/351f11e66f08f06e37a985719a31ddb4/raw/b35ba7a3aac1949bd6bbeaad065a0a93dc3c34f0/01-cpu.patch + wget https://gist.githubusercontent.com/mj22226/b66f5c1bd5fc7e1cb3cf2c690b5dbd5a/raw/b955e726cbb0948d932c8d6143229ad604320149/20-lxc.patch + wget https://github.com/mj22226/packages/commit/37264a2e636b790df9cb037db695505341030e98.patch + git apply 01-cpu.patch + git apply 20-lxc.patch + + cd - + sed -i "71s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "84s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "195s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "212s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "13s/'1'/'0'/" feeds/packages/utils/dockerd/files/etc/config/dockerd + sed -i 's/default n/default y/g' feeds/packages/utils/dockerd/Config.in + ./scripts/feeds update -a + ./scripts/feeds install -a -f + wget https://downloads.openwrt.org/snapshots/targets/bcm27xx/bcm2711/llvm-bpf-18.1.7.Linux-x86_64.tar.zst + tar -xvf llvm-bpf-18.1.7.Linux-x86_64.tar.zst + cp .github/workflows/config.buildinfo4 .config + make defconfig + wget https://gist.githubusercontent.com/mj22226/23edc25efeb65ef69d8eb6598f4f8179/raw/29c862e3e2558852523f4e8edd5f3d0cc145067e/01-key.patch + git apply 01-key.patch + make download -j32 + rm 01-key.patch + + + mkdir -p files/www/repo + wget https://gist.githubusercontent.com/mj22226/681178b344f588b4625a7f83febd9131/raw/73ff0c720a0eefb99fe086ec2d715e0052976df0/03.patch + git apply 03.patch + make -j$(nproc) 'IGNORE_ERRORS=n m' + cp -R bin/targets/bcm27xx/bcm2711/packages/ files/www/repo/ + make -j$(nproc) 'IGNORE_ERRORS=n m' + rm -rf bin/targets/bcm27xx/bcm2711/packages + echo "DATE=$(date +'%Y.%m.%d')" >> $GITHUB_ENV + echo "HASH=$(git log -1 --format="%H")" >> $GITHUB_ENV + - name: Delete tag + uses: ClementTsang/delete-tag-and-release@v0.4.0 + with: + delete_release: true + tag_name: bcm2711-6.6 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Create release + uses: ncipollo/release-action@v1.14.0 + with: + allowUpdates: true + commit: ${{ env.HASH }} + name: Raspberry Pi 4 Firmware Images + tag: bcm2711-6.6 + replacesArtifacts: true + prerelease: true + token: "${{ secrets.GITHUB_TOKEN }}" + artifacts: bin/targets/bcm27xx/bcm2711/* diff --git a/.github/workflows/bcm2712.yaml b/.github/workflows/bcm2712.yaml new file mode 100644 index 00000000000000..d1c4dcf3dece2e --- /dev/null +++ b/.github/workflows/bcm2712.yaml @@ -0,0 +1,92 @@ +name: Build bcm2712 RPi 5B +on: [push] + +jobs: + build: + name: Build Raspberry Pi 5 images + runs-on: ubuntu-latest + + steps: + - name: Maximize build space + uses: easimon/maximize-build-space@master + with: + root-reserve-mb: 512 + swap-size-mb: 1024 + remove-dotnet: 'true' + overprovision-lvm: 'true' + remove-android: 'true' + remove-haskell: 'true' + remove-codeql: 'true' + remove-docker-images: 'true' + - name: Checkout + uses: actions/checkout@v4 + - name: Build + run: | + ./scripts/feeds update -a + ./scripts/feeds install -a + cd feeds/luci + wget https://gist.githubusercontent.com/mj22226/363cefecd314e45b49d8eafff8473fcf/raw/69b47c9a972e15056f94870d76d93a5146893f99/01-diskman.patch + + git apply 01-diskman.patch + + cd - + cd feeds/packages + wget https://gist.githubusercontent.com/mj22226/351f11e66f08f06e37a985719a31ddb4/raw/b35ba7a3aac1949bd6bbeaad065a0a93dc3c34f0/01-cpu.patch + wget https://gist.githubusercontent.com/mj22226/b66f5c1bd5fc7e1cb3cf2c690b5dbd5a/raw/b955e726cbb0948d932c8d6143229ad604320149/20-lxc.patch + wget https://github.com/mj22226/packages/commit/37264a2e636b790df9cb037db695505341030e98.patch + + + + + git apply 01-cpu.patch + git apply 20-lxc.patch + + + + + + cd - + sed -i "71s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "84s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "195s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "212s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "13s/'1'/'0'/" feeds/packages/utils/dockerd/files/etc/config/dockerd + sed -i 's/default n/default y/g' feeds/packages/utils/dockerd/Config.in + ./scripts/feeds update -a + ./scripts/feeds install -a -f + wget https://downloads.openwrt.org/snapshots/targets/bcm27xx/bcm2712/llvm-bpf-18.1.7.Linux-x86_64.tar.zst + tar -xvf llvm-bpf-18.1.7.Linux-x86_64.tar.zst + wget https://gist.githubusercontent.com/mj22226/23edc25efeb65ef69d8eb6598f4f8179/raw/29c862e3e2558852523f4e8edd5f3d0cc145067e/01-key.patch + + git apply 01-key.patch + + rm 01-key.patch + cp .github/workflows/config.buildinfo .config + make defconfig + make download -j32 + + + mkdir -p files/www/repo + wget https://gist.githubusercontent.com/mj22226/242ed658f24ee582678ab50b553641ac/raw/ba143f1f72fe9be44c61288ac80267299ea9701e/03.patch + git apply 03.patch + make -j$(nproc) 'IGNORE_ERRORS=n m' + cp -R bin/targets/bcm27xx/bcm2712/packages/ files/www/repo/ + make -j$(nproc) 'IGNORE_ERRORS=n m' + rm -rf bin/targets/bcm27xx/bcm2712/packages + echo "DATE=$(date +'%Y.%m.%d')" >> $GITHUB_ENV + echo "HASH=$(git log -1 --format="%H")" >> $GITHUB_ENV + - name: Delete tag + run: gh release delete bcm2712-6.6 --cleanup-tag || true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Create release + uses: ncipollo/release-action@v1.14.0 + with: + allowUpdates: true + commit: ${{ env.HASH }} + name: Raspberry Pi 5 v6.6 Firmware Images ${{ env.DATE }} + tag: bcm2712-6.6 + replacesArtifacts: true + prerelease: true + token: "${{ secrets.GITHUB_TOKEN }}" + artifacts: bin/targets/bcm27xx/bcm2712/* diff --git a/.github/workflows/config.buildinfo b/.github/workflows/config.buildinfo new file mode 100644 index 00000000000000..e3f1043607acea --- /dev/null +++ b/.github/workflows/config.buildinfo @@ -0,0 +1,698 @@ +CONFIG_TARGET_bcm27xx=y +CONFIG_TARGET_bcm27xx_bcm2712=y +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_DEVICE_bcm27xx_bcm2712_DEVICE_rpi-5=y +CONFIG_TARGET_DEVICE_PACKAGES_bcm27xx_bcm2712_DEVICE_rpi-5="" +CONFIG_ALL_KMODS=y +CONFIG_ALL_NONSHARED=y +CONFIG_DEVEL=y +CONFIG_BUSYBOX_CUSTOM=y +CONFIG_TARGET_PER_DEVICE_ROOTFS=y +CONFIG_BUILDBOT=y +CONFIG_BUILD_LOG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_GETOPT_LONG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ=y +CONFIG_BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS=y +CONFIG_BUSYBOX_CONFIG_GETOPT=y +CONFIG_BUSYBOX_CONFIG_MOUNTPOINT=y +CONFIG_BUSYBOX_CONFIG_UNXZ=y +CONFIG_BUSYBOX_CONFIG_XZ=y +CONFIG_CGROUPFS_MOUNT_KERNEL_CGROUPS=y +CONFIG_DOCKER_CGROUP_OPTIONS=y +CONFIG_DOCKER_CHECK_CONFIG=y +CONFIG_DOCKER_NET_ENCRYPT=y +CONFIG_DOCKER_NET_MACVLAN=y +CONFIG_DOCKER_NET_OVERLAY=y +CONFIG_DOCKER_NET_TFTP=y +CONFIG_DOCKER_OPTIONAL_FEATURES=y +CONFIG_DOCKER_STO_BTRFS=y +CONFIG_DOCKER_STO_DEVMAPPER=y +CONFIG_DOCKER_STO_EXT4=y +CONFIG_GNUTLS_ALPN=y +CONFIG_GNUTLS_ANON=y +CONFIG_GNUTLS_DTLS_SRTP=y +CONFIG_GNUTLS_HEARTBEAT=y +CONFIG_GNUTLS_OCSP=y +CONFIG_GNUTLS_PSK=y +CONFIG_HTOP_LMSENSORS=y +CONFIG_JSON_CYCLONEDX_SBOM=n +CONFIG_KERNEL_ARM_PMU=y +CONFIG_KERNEL_BTRFS_FS_POSIX_ACL=y +CONFIG_KERNEL_BUILD_DOMAIN="buildhost" +CONFIG_KERNEL_BUILD_USER="builder" +CONFIG_KERNEL_CFQ_GROUP_IOSCHED=y +CONFIG_KERNEL_CGROUP_DEVICE=y +CONFIG_KERNEL_CGROUP_FREEZER=y +CONFIG_KERNEL_CGROUP_HUGETLB=y +CONFIG_KERNEL_CGROUP_NET_PRIO=y +CONFIG_KERNEL_CGROUP_PERF=y +CONFIG_KERNEL_EXT4_FS_POSIX_ACL=y +CONFIG_KERNEL_EXT4_FS_SECURITY=y +CONFIG_KERNEL_FS_POSIX_ACL=y +CONFIG_KERNEL_HUGETLBFS=y +CONFIG_KERNEL_HUGETLB_PAGE=y +CONFIG_KERNEL_MEMCG_SWAP_ENABLED=y +CONFIG_KERNEL_NET_CLS_CGROUP=y +CONFIG_KERNEL_PERF_EVENTS=y +CONFIG_KERNEL_RPI_AXIPERF=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS=y +CONFIG_LIBCURL_COOKIES=y +CONFIG_LIBCURL_FILE=y +CONFIG_LIBCURL_FTP=y +CONFIG_LIBCURL_HTTP=y +CONFIG_LIBCURL_MBEDTLS=y +CONFIG_LIBCURL_NGHTTP2=y +CONFIG_LIBCURL_NO_SMB="!" +CONFIG_LIBCURL_PROXY=y +CONFIG_LIBCURL_UNIX_SOCKETS=y +CONFIG_LXC_BUSYBOX_OPTIONS=y +CONFIG_LXC_KERNEL_OPTIONS=y +CONFIG_LXC_NETWORKING=y +CONFIG_LXC_SECCOMP=y +CONFIG_OPENSSL_ENGINE=y +CONFIG_OPENSSL_ENGINE_BUILTIN=y +CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO=y +CONFIG_OPENSSL_OPTIMIZE_SPEED=y +CONFIG_OPENSSL_WITH_ASM=y +CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y +CONFIG_OPENSSL_WITH_CMS=y +CONFIG_OPENSSL_WITH_DEPRECATED=y +CONFIG_OPENSSL_WITH_ERROR_MESSAGES=y +CONFIG_OPENSSL_WITH_IDEA=y +CONFIG_OPENSSL_WITH_MDC2=y +CONFIG_OPENSSL_WITH_PSK=y +CONFIG_OPENSSL_WITH_SEED=y +CONFIG_OPENSSL_WITH_SRP=y +CONFIG_OPENSSL_WITH_TLS13=y +CONFIG_OPENSSL_WITH_WHIRLPOOL=y +CONFIG_OPENVPN_openssl_ENABLE_FRAGMENT=y +CONFIG_OPENVPN_openssl_ENABLE_LZ4=y +CONFIG_OPENVPN_openssl_ENABLE_LZO=y +CONFIG_OPENVPN_openssl_ENABLE_PORT_SHARE=y +CONFIG_OPENVPN_openssl_ENABLE_X509_ALT_USERNAME=y +CONFIG_PACKAGE_NTFS-3G_HAS_PROBE=y +CONFIG_PACKAGE_TAR_BZIP2=y +CONFIG_PACKAGE_TAR_GZIP=y +CONFIG_PACKAGE_TAR_POSIX_ACL=y +CONFIG_PACKAGE_TAR_XATTR=y +CONFIG_PACKAGE_TAR_XZ=y +CONFIG_PACKAGE_TAR_ZSTD=y +CONFIG_PACKAGE_adb=y +CONFIG_PACKAGE_adblock=y +CONFIG_PACKAGE_arp-scan=y +CONFIG_PACKAGE_arp-scan-database=y +CONFIG_PACKAGE_atop=y +CONFIG_PACKAGE_bash=y +CONFIG_PACKAGE_bcm2712-eeprom=y +CONFIG_PACKAGE_bcm27xx-eeprom=y +CONFIG_PACKAGE_blkdiscard=y +CONFIG_PACKAGE_blkid=y +CONFIG_PACKAGE_block-mount=y +CONFIG_PACKAGE_blockd=y +CONFIG_PACKAGE_blockdev=y +CONFIG_PACKAGE_bluez-daemon=y +CONFIG_PACKAGE_bluez-libs=y +CONFIG_PACKAGE_bluez-tools=y +CONFIG_PACKAGE_bluez-utils=y +CONFIG_PACKAGE_bluez-utils-extra=y +CONFIG_PACKAGE_btop=y +CONFIG_PACKAGE_btrfs-progs=y +CONFIG_PACKAGE_bzip2=y +CONFIG_PACKAGE_ca-certificates=y +CONFIG_PACKAGE_ccrypt=y +CONFIG_PACKAGE_certtool=y +CONFIG_PACKAGE_cfdisk=y +CONFIG_PACKAGE_cgdisk=y +CONFIG_PACKAGE_cgi-io=y +CONFIG_PACKAGE_cgroup-tools=y +CONFIG_PACKAGE_cgroupfs-mount=y +CONFIG_PACKAGE_collectd=y +CONFIG_PACKAGE_collectd-mod-conntrack=y +CONFIG_PACKAGE_collectd-mod-cpu=y +CONFIG_PACKAGE_collectd-mod-cpufreq=y +CONFIG_PACKAGE_collectd-mod-interface=y +CONFIG_PACKAGE_collectd-mod-irq=y +CONFIG_PACKAGE_collectd-mod-iwinfo=y +CONFIG_PACKAGE_collectd-mod-load=y +CONFIG_PACKAGE_collectd-mod-memory=y +CONFIG_PACKAGE_collectd-mod-network=y +CONFIG_PACKAGE_collectd-mod-rrdtool=y +CONFIG_PACKAGE_collectd-mod-sensors=y +CONFIG_PACKAGE_collectd-mod-thermal=y +CONFIG_PACKAGE_containerd=y +CONFIG_PACKAGE_coreutils=y +CONFIG_PACKAGE_coreutils-od=y +CONFIG_PACKAGE_coreutils-sort=y +CONFIG_PACKAGE_cryptsetup=y +CONFIG_PACKAGE_cryptsetup-ssh=y +CONFIG_PACKAGE_dbus=y +CONFIG_PACKAGE_debugfs=y +CONFIG_PACKAGE_dnsmasq=m +CONFIG_PACKAGE_dnsmasq-full=y +CONFIG_PACKAGE_dnsmasq_full_auth=y +CONFIG_PACKAGE_dnsmasq_full_conntrack=y +CONFIG_PACKAGE_dnsmasq_full_dhcp=y +CONFIG_PACKAGE_dnsmasq_full_dhcpv6=y +CONFIG_PACKAGE_dnsmasq_full_dnssec=y +CONFIG_PACKAGE_dnsmasq_full_nftset=y +CONFIG_PACKAGE_dnsmasq_full_noid=y +CONFIG_PACKAGE_dnsmasq_full_tftp=y +CONFIG_PACKAGE_docker=y +CONFIG_PACKAGE_docker-compose=y +CONFIG_PACKAGE_dockerd=y +CONFIG_PACKAGE_dosfstools=y +CONFIG_PACKAGE_dumpe2fs=y +CONFIG_PACKAGE_e2freefrag=y +CONFIG_PACKAGE_e4crypt=y +CONFIG_PACKAGE_eject=y +CONFIG_PACKAGE_ethtool-full=y +CONFIG_PACKAGE_exfat-fsck=y +CONFIG_PACKAGE_exfat-mkfs=y +CONFIG_PACKAGE_f2fs-tools=m +CONFIG_PACKAGE_f2fs-tools-selinux=y +CONFIG_PACKAGE_f2fsck=m +CONFIG_PACKAGE_f2fsck-selinux=y +CONFIG_PACKAGE_fdisk=y +CONFIG_PACKAGE_findfs=y +CONFIG_PACKAGE_fixparts=y +CONFIG_PACKAGE_flock=y +CONFIG_PACKAGE_fuse-utils=y +CONFIG_PACKAGE_gdisk=y +CONFIG_PACKAGE_getopt=y +CONFIG_PACKAGE_glib2=y +CONFIG_PACKAGE_gnupg=y +CONFIG_PACKAGE_gnupg-utils=y +CONFIG_PACKAGE_gnupg2=y +CONFIG_PACKAGE_gnupg2-utils=y +CONFIG_PACKAGE_gzip=y +CONFIG_PACKAGE_hdparm=y +CONFIG_PACKAGE_hostapd-common=y +CONFIG_PACKAGE_htop=y +CONFIG_PACKAGE_hwclock=y +CONFIG_PACKAGE_ip-full=y +CONFIG_PACKAGE_ip6tables-nft=y +CONFIG_PACKAGE_iperf3-ssl=y +CONFIG_PACKAGE_ipset=y + +CONFIG_PACKAGE_iptables-mod-ipopt=y +CONFIG_PACKAGE_iptables-nft=y +CONFIG_PACKAGE_irqbalance=y +CONFIG_PACKAGE_iw=y +CONFIG_PACKAGE_iwinfo=y +CONFIG_PACKAGE_kmod-asn1-decoder=y +CONFIG_PACKAGE_kmod-asn1-encoder=y +CONFIG_PACKAGE_kmod-ata-ahci=y +CONFIG_PACKAGE_kmod-ata-core=y +CONFIG_PACKAGE_kmod-atm=y +# CONFIG_PACKAGE_kmod-b43 is not set +CONFIG_PACKAGE_kmod-bluetooth=y +CONFIG_PACKAGE_kmod-br-netfilter=y +CONFIG_PACKAGE_kmod-cdrom=y +CONFIG_PACKAGE_kmod-cfg80211=y +CONFIG_PACKAGE_kmod-crypto-aead=y +CONFIG_PACKAGE_kmod-crypto-arc4=y +CONFIG_PACKAGE_kmod-crypto-authenc=y +CONFIG_PACKAGE_kmod-crypto-cbc=y +CONFIG_PACKAGE_kmod-crypto-ccm=y +CONFIG_PACKAGE_kmod-crypto-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-cmac=y +CONFIG_PACKAGE_kmod-crypto-crc32=y +CONFIG_PACKAGE_kmod-crypto-ctr=y +CONFIG_PACKAGE_kmod-crypto-cts=y +CONFIG_PACKAGE_kmod-crypto-deflate=y +CONFIG_PACKAGE_kmod-crypto-des=y +CONFIG_PACKAGE_kmod-crypto-ecb=y +CONFIG_PACKAGE_kmod-crypto-ecdh=y +CONFIG_PACKAGE_kmod-crypto-echainiv=y +CONFIG_PACKAGE_kmod-crypto-essiv=y +CONFIG_PACKAGE_kmod-crypto-fcrypt=y +CONFIG_PACKAGE_kmod-crypto-gcm=y +CONFIG_PACKAGE_kmod-crypto-gf128=y +CONFIG_PACKAGE_kmod-crypto-ghash=y +CONFIG_PACKAGE_kmod-crypto-hmac=y +CONFIG_PACKAGE_kmod-crypto-kpp=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-lib-curve25519=y +CONFIG_PACKAGE_kmod-crypto-lib-poly1305=y +CONFIG_PACKAGE_kmod-crypto-manager=y +CONFIG_PACKAGE_kmod-crypto-md4=y +CONFIG_PACKAGE_kmod-crypto-md5=y +CONFIG_PACKAGE_kmod-crypto-michael-mic=y +CONFIG_PACKAGE_kmod-crypto-misc=y +CONFIG_PACKAGE_kmod-crypto-null=y +CONFIG_PACKAGE_kmod-crypto-pcbc=y +CONFIG_PACKAGE_kmod-crypto-rmd160=y +CONFIG_PACKAGE_kmod-crypto-rng=y +CONFIG_PACKAGE_kmod-crypto-seqiv=y +CONFIG_PACKAGE_kmod-crypto-sha1=y +CONFIG_PACKAGE_kmod-crypto-sha256=y +CONFIG_PACKAGE_kmod-crypto-sha512=y +CONFIG_PACKAGE_kmod-crypto-test=y +CONFIG_PACKAGE_kmod-crypto-user=y +CONFIG_PACKAGE_kmod-crypto-xcbc=y +CONFIG_PACKAGE_kmod-crypto-xts=y +CONFIG_PACKAGE_kmod-cryptodev=y +CONFIG_PACKAGE_kmod-dax=y +CONFIG_PACKAGE_kmod-dm=y +CONFIG_PACKAGE_kmod-dummy=y +CONFIG_PACKAGE_kmod-fs-autofs4=y +CONFIG_PACKAGE_kmod-fs-btrfs=y +CONFIG_PACKAGE_kmod-fs-configfs=y +CONFIG_PACKAGE_kmod-fs-exfat=y +CONFIG_PACKAGE_kmod-fs-exportfs=y +CONFIG_PACKAGE_kmod-fs-ext4=y +CONFIG_PACKAGE_kmod-fs-f2fs=y +CONFIG_PACKAGE_kmod-fs-hfs=y +CONFIG_PACKAGE_kmod-fs-hfsplus=y +CONFIG_PACKAGE_kmod-fs-ksmbd=y +CONFIG_PACKAGE_kmod-fs-msdos=y +CONFIG_PACKAGE_kmod-fs-netfs=y +CONFIG_PACKAGE_kmod-fs-ntfs3=y +CONFIG_PACKAGE_kmod-fs-smbfs-common=y +CONFIG_PACKAGE_kmod-fs-squashfs=y +CONFIG_PACKAGE_kmod-fs-xfs=y +CONFIG_PACKAGE_kmod-fuse=y +CONFIG_PACKAGE_kmod-gre=y +CONFIG_PACKAGE_kmod-hwmon-core=y +CONFIG_PACKAGE_kmod-i2c-bcm2835=y +CONFIG_PACKAGE_kmod-i2c-core=y +CONFIG_PACKAGE_kmod-ifb=y +CONFIG_PACKAGE_kmod-ikconfig=y +CONFIG_PACKAGE_kmod-ip6tables=y +CONFIG_PACKAGE_kmod-ipsec=y +CONFIG_PACKAGE_kmod-ipt-conntrack=y +CONFIG_PACKAGE_kmod-ipt-core=y +CONFIG_PACKAGE_kmod-ipt-extra=y +CONFIG_PACKAGE_kmod-ipt-ipopt=y +CONFIG_PACKAGE_kmod-ipt-ipset=y +CONFIG_PACKAGE_kmod-ipt-nat=y +CONFIG_PACKAGE_kmod-ipt-nat6=y +CONFIG_PACKAGE_kmod-ipt-physdev=y +CONFIG_PACKAGE_kmod-iptunnel=y +CONFIG_PACKAGE_kmod-keys-encrypted=y +CONFIG_PACKAGE_kmod-keys-trusted=y +CONFIG_PACKAGE_kmod-l2tp=y +CONFIG_PACKAGE_kmod-lib-crc16=y +CONFIG_PACKAGE_kmod-lib-raid6=y +CONFIG_PACKAGE_kmod-lib-textsearch=y +CONFIG_PACKAGE_kmod-lib-xor=y +CONFIG_PACKAGE_kmod-lib-zlib-deflate=y +CONFIG_PACKAGE_kmod-lib-zlib-inflate=y +CONFIG_PACKAGE_kmod-lib-zstd=y +CONFIG_PACKAGE_kmod-libphy=y +CONFIG_PACKAGE_kmod-mac80211=y +CONFIG_PACKAGE_kmod-macvlan=y +CONFIG_PACKAGE_kmod-md-mod=y +CONFIG_PACKAGE_kmod-md-raid0=y +CONFIG_PACKAGE_kmod-md-raid1=y +CONFIG_PACKAGE_kmod-md-raid10=y +CONFIG_PACKAGE_kmod-mdio-devres=y +CONFIG_PACKAGE_kmod-mii=y +CONFIG_PACKAGE_kmod-mppe=y +CONFIG_PACKAGE_kmod-mt76-connac=y +CONFIG_PACKAGE_kmod-mt76-core=y +CONFIG_PACKAGE_kmod-mt76-usb=y +CONFIG_PACKAGE_kmod-mt76x02-common=y +CONFIG_PACKAGE_kmod-mt76x02-usb=y +CONFIG_PACKAGE_kmod-mt76x2-common=y +CONFIG_PACKAGE_kmod-mt76x2u=y +CONFIG_PACKAGE_kmod-mt7921-common=y +CONFIG_PACKAGE_kmod-mt7921-firmware=y +CONFIG_PACKAGE_kmod-mt7921u=y +CONFIG_PACKAGE_kmod-mt792x-common=y +CONFIG_PACKAGE_kmod-mt792x-usb=y +CONFIG_PACKAGE_kmod-net-selftests=y +CONFIG_PACKAGE_kmod-nf-conntrack-netlink=y +CONFIG_PACKAGE_kmod-nf-ipt=y +CONFIG_PACKAGE_kmod-nf-ipt6=y +CONFIG_PACKAGE_kmod-nf-ipvs=y +CONFIG_PACKAGE_kmod-nf-nat6=y +CONFIG_PACKAGE_kmod-nf-nathelper=y +CONFIG_PACKAGE_kmod-nf-nathelper-extra=y +CONFIG_PACKAGE_kmod-nft-compat=y +CONFIG_PACKAGE_kmod-nls-cp932=y +CONFIG_PACKAGE_kmod-nls-cp936=y +CONFIG_PACKAGE_kmod-nls-cp950=y +CONFIG_PACKAGE_kmod-nls-ucs2-utils=y +CONFIG_PACKAGE_kmod-nvme=y +CONFIG_PACKAGE_kmod-oid-registry=y +CONFIG_PACKAGE_kmod-phy-ax88796b=y +CONFIG_PACKAGE_kmod-phy-realtek=y +CONFIG_PACKAGE_kmod-phylink=y +CONFIG_PACKAGE_kmod-pppoa=y +CONFIG_PACKAGE_kmod-pppol2tp=y +CONFIG_PACKAGE_kmod-pptp=y +CONFIG_PACKAGE_kmod-r8169=y +CONFIG_PACKAGE_kmod-random-core=y +CONFIG_PACKAGE_kmod-regmap-core=y +CONFIG_PACKAGE_kmod-rtl8812au-ac=y +CONFIG_PACKAGE_kmod-rtw88=y +CONFIG_PACKAGE_kmod-rtw88-8821c=y +CONFIG_PACKAGE_kmod-rtw88-8821cu=y +CONFIG_PACKAGE_kmod-rtw88-8822b=y +CONFIG_PACKAGE_kmod-rtw88-8822bu=y +CONFIG_PACKAGE_kmod-rtw88-8822c=y +CONFIG_PACKAGE_kmod-rtw88-8822cu=y +CONFIG_PACKAGE_kmod-rtw88-usb=y +CONFIG_PACKAGE_kmod-sched-bpf=y +CONFIG_PACKAGE_kmod-sched-cake=y +CONFIG_PACKAGE_kmod-sched-core=y +CONFIG_PACKAGE_kmod-scsi-core=y +CONFIG_PACKAGE_kmod-tpm=y +CONFIG_PACKAGE_kmod-tun=y +CONFIG_PACKAGE_kmod-udptunnel4=y +CONFIG_PACKAGE_kmod-udptunnel6=y +CONFIG_PACKAGE_kmod-usb-net=y +CONFIG_PACKAGE_kmod-usb-net-aqc111=y +CONFIG_PACKAGE_kmod-usb-net-asix=y +CONFIG_PACKAGE_kmod-usb-net-asix-ax88179=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ether=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ncm=y +CONFIG_PACKAGE_kmod-usb-net-ipheth=y +CONFIG_PACKAGE_kmod-usb-net-rndis=y +CONFIG_PACKAGE_kmod-usb-net-rtl8150=y +CONFIG_PACKAGE_kmod-usb-net-rtl8152=y +CONFIG_PACKAGE_kmod-usb-ohci=y +CONFIG_PACKAGE_kmod-usb-storage=y +CONFIG_PACKAGE_kmod-usb-storage-extras=y +CONFIG_PACKAGE_kmod-usb-storage-uas=y +CONFIG_PACKAGE_kmod-usb-wdm=y +CONFIG_PACKAGE_kmod-veth=y +CONFIG_PACKAGE_kmod-vxlan=y +CONFIG_PACKAGE_kmod-wireguard=y +CONFIG_PACKAGE_ksmbd-server=y +CONFIG_PACKAGE_libacl=y +CONFIG_PACKAGE_libaio=y +CONFIG_PACKAGE_libassuan=y +CONFIG_PACKAGE_libatomic=y +CONFIG_PACKAGE_libattr=y +CONFIG_PACKAGE_libbfd=m +CONFIG_PACKAGE_libbpf=y +CONFIG_PACKAGE_libbz2=y +CONFIG_PACKAGE_libcap=y +CONFIG_PACKAGE_libcap-ng=y +CONFIG_PACKAGE_libcgroup=y +CONFIG_PACKAGE_libctf=m +CONFIG_PACKAGE_libcurl=y +CONFIG_PACKAGE_libdbus=y +CONFIG_PACKAGE_libdevmapper=y +CONFIG_PACKAGE_libdw=m +CONFIG_PACKAGE_libelf=y +CONFIG_PACKAGE_libevdev=y +CONFIG_PACKAGE_libexpat=y +CONFIG_PACKAGE_libf2fs=m +CONFIG_PACKAGE_libf2fs-selinux=y +CONFIG_PACKAGE_libfdisk=y +CONFIG_PACKAGE_libffi=y +CONFIG_PACKAGE_libfuse=y +CONFIG_PACKAGE_libgcrypt=y +CONFIG_PACKAGE_libgmp=y +CONFIG_PACKAGE_libgnutls=y +CONFIG_PACKAGE_libgpg-error=y +CONFIG_PACKAGE_libical=y +CONFIG_PACKAGE_libipset=y +CONFIG_PACKAGE_libiptext=y +CONFIG_PACKAGE_libiptext-nft=y +CONFIG_PACKAGE_libiptext6=y +CONFIG_PACKAGE_libiwinfo=y +CONFIG_PACKAGE_libiwinfo-data=y +CONFIG_PACKAGE_libkmod=y +CONFIG_PACKAGE_libksba=y +CONFIG_PACKAGE_libltdl=y +CONFIG_PACKAGE_liblua=y +CONFIG_PACKAGE_liblucihttp=y +CONFIG_PACKAGE_liblucihttp-lua=y +CONFIG_PACKAGE_liblucihttp-ucode=y +CONFIG_PACKAGE_liblxc=y +CONFIG_PACKAGE_liblz4=y +CONFIG_PACKAGE_liblzma=y +CONFIG_PACKAGE_liblzo=y +CONFIG_PACKAGE_libmount=y +CONFIG_PACKAGE_libncurses=y +CONFIG_PACKAGE_libnetfilter-conntrack=y +CONFIG_PACKAGE_libnettle=y +CONFIG_PACKAGE_libnfnetlink=y +CONFIG_PACKAGE_libnghttp2=y +CONFIG_PACKAGE_libnl-core=y +CONFIG_PACKAGE_libnl-genl=y +CONFIG_PACKAGE_libnpth=y +CONFIG_PACKAGE_libopcodes=m +CONFIG_PACKAGE_libopenssl=y +CONFIG_PACKAGE_libopenssl-conf=y +CONFIG_PACKAGE_libparted=y +CONFIG_PACKAGE_libpcap=y +CONFIG_PACKAGE_libpci=y +CONFIG_PACKAGE_libpcre2=y +CONFIG_PACKAGE_libpopt=y +CONFIG_PACKAGE_libpython3=y +CONFIG_PACKAGE_libqrencode=y +CONFIG_PACKAGE_libreadline=y +CONFIG_PACKAGE_librrd1=y +CONFIG_PACKAGE_libseccomp=y +CONFIG_PACKAGE_libselinux=y +CONFIG_PACKAGE_libsensors=y +CONFIG_PACKAGE_libsepol=y +CONFIG_PACKAGE_libssh=y +CONFIG_PACKAGE_libstdcpp=y +CONFIG_PACKAGE_libsysfs=y +CONFIG_PACKAGE_libtirpc=y +CONFIG_PACKAGE_libubus-lua=y +CONFIG_PACKAGE_libudev-zero=y +CONFIG_PACKAGE_libusb-1.0=y +CONFIG_PACKAGE_libuv=y +CONFIG_PACKAGE_libwebsockets-full=y +CONFIG_PACKAGE_libxtables=y +CONFIG_PACKAGE_libzstd=y +CONFIG_PACKAGE_linux-atm=y +CONFIG_PACKAGE_lm-sensors=y +CONFIG_PACKAGE_losetup=y +CONFIG_PACKAGE_lsblk=y +CONFIG_PACKAGE_lscpu=y +CONFIG_PACKAGE_lua=y +CONFIG_PACKAGE_luci=y +CONFIG_PACKAGE_luci-app-adblock=y +CONFIG_PACKAGE_luci-app-commands=y +CONFIG_PACKAGE_luci-app-diskman=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_btrfs_progs=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_lsblk=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_ntfs_3g_utils=y +CONFIG_PACKAGE_luci-app-dockerman=y +CONFIG_PACKAGE_luci-app-filebrowser=y +CONFIG_PACKAGE_luci-app-firewall=y +CONFIG_PACKAGE_luci-app-ksmbd=y +CONFIG_PACKAGE_luci-app-lxc=y +CONFIG_PACKAGE_luci-app-nlbwmon=y +CONFIG_PACKAGE_luci-app-openvpn=y +CONFIG_PACKAGE_luci-app-opkg=y +CONFIG_PACKAGE_luci-app-pbr=y +CONFIG_PACKAGE_luci-app-sqm=y +CONFIG_PACKAGE_luci-app-statistics=y +CONFIG_PACKAGE_luci-app-ttyd=y +CONFIG_PACKAGE_luci-base=y +CONFIG_PACKAGE_luci-compat=y +CONFIG_PACKAGE_luci-lib-base=y +CONFIG_PACKAGE_luci-lib-docker=y +CONFIG_PACKAGE_luci-lib-ip=y +CONFIG_PACKAGE_luci-lib-ipkg=y +CONFIG_PACKAGE_luci-lib-jsonc=y +CONFIG_PACKAGE_luci-lib-nixio=y +CONFIG_PACKAGE_luci-light=y +CONFIG_PACKAGE_luci-lua-runtime=y +CONFIG_PACKAGE_luci-mod-admin-full=y +CONFIG_PACKAGE_luci-mod-network=y +CONFIG_PACKAGE_luci-mod-status=y +CONFIG_PACKAGE_luci-mod-system=y +CONFIG_PACKAGE_luci-proto-ipv6=y +CONFIG_PACKAGE_luci-proto-ppp=y +CONFIG_PACKAGE_luci-proto-vxlan=y +CONFIG_PACKAGE_luci-proto-wireguard=y +CONFIG_PACKAGE_luci-theme-bootstrap=y +CONFIG_PACKAGE_lvm2=y +CONFIG_PACKAGE_lxc=y +CONFIG_PACKAGE_lxc-attach=y +CONFIG_PACKAGE_lxc-auto=y +CONFIG_PACKAGE_lxc-autostart=y +CONFIG_PACKAGE_lxc-cgroup=y +CONFIG_PACKAGE_lxc-checkconfig=y +CONFIG_PACKAGE_lxc-common=y +CONFIG_PACKAGE_lxc-config=y +CONFIG_PACKAGE_lxc-configs=y +CONFIG_PACKAGE_lxc-console=y +CONFIG_PACKAGE_lxc-copy=y +CONFIG_PACKAGE_lxc-create=y +CONFIG_PACKAGE_lxc-destroy=y +CONFIG_PACKAGE_lxc-device=y +CONFIG_PACKAGE_lxc-execute=y +CONFIG_PACKAGE_lxc-freeze=y +CONFIG_PACKAGE_lxc-hooks=y +CONFIG_PACKAGE_lxc-info=y +CONFIG_PACKAGE_lxc-init=y +CONFIG_PACKAGE_lxc-ls=y +CONFIG_PACKAGE_lxc-monitor=y +CONFIG_PACKAGE_lxc-monitord=y +CONFIG_PACKAGE_lxc-snapshot=y +CONFIG_PACKAGE_lxc-start=y +CONFIG_PACKAGE_lxc-stop=y +CONFIG_PACKAGE_lxc-templates=y +CONFIG_PACKAGE_lxc-top=y +CONFIG_PACKAGE_lxc-unfreeze=y +CONFIG_PACKAGE_lxc-unprivileged=y +CONFIG_PACKAGE_lxc-unshare=y +CONFIG_PACKAGE_lxc-user-nic=y +CONFIG_PACKAGE_lxc-usernsexec=y +CONFIG_PACKAGE_lxc-wait=y +CONFIG_PACKAGE_lz4=y +CONFIG_PACKAGE_lzmadec=y +CONFIG_PACKAGE_lzmainfo=y +CONFIG_PACKAGE_mdadm=y +CONFIG_PACKAGE_mkf2fs=m +CONFIG_PACKAGE_mkf2fs-selinux=y +CONFIG_PACKAGE_mmc-utils=y +CONFIG_PACKAGE_mount-utils=y +CONFIG_PACKAGE_mtools=y +CONFIG_PACKAGE_musl-fts=y +CONFIG_PACKAGE_nano=y +CONFIG_PACKAGE_nfs-utils=y +CONFIG_PACKAGE_nlbwmon=y +CONFIG_PACKAGE_ntfs-3g=y +CONFIG_PACKAGE_ntfs-3g-utils=y +CONFIG_PACKAGE_objdump=m +CONFIG_PACKAGE_openssl-util=y +CONFIG_PACKAGE_openvpn-easy-rsa=y +CONFIG_PACKAGE_openvpn-openssl=y +CONFIG_PACKAGE_parted=y +CONFIG_PACKAGE_pbr=y +CONFIG_PACKAGE_pciids=y +CONFIG_PACKAGE_pciutils=y +CONFIG_PACKAGE_perf=m +CONFIG_PACKAGE_ppp-mod-passwordfd=y +CONFIG_PACKAGE_ppp-mod-pppoa=y +CONFIG_PACKAGE_ppp-mod-pppol2tp=y +CONFIG_PACKAGE_ppp-mod-pptp=y +CONFIG_PACKAGE_ppp-mod-radius=y +CONFIG_PACKAGE_pppdump=y +CONFIG_PACKAGE_pppoe-discovery=y +CONFIG_PACKAGE_pptpd=y +CONFIG_PACKAGE_python3-base=y +CONFIG_PACKAGE_python3-light=y +CONFIG_PACKAGE_qosify=y +CONFIG_PACKAGE_qrencode=y +CONFIG_PACKAGE_r8152-firmware=y +CONFIG_PACKAGE_r8169-firmware=y +CONFIG_PACKAGE_resize2fs=y +CONFIG_PACKAGE_resolveip=y +CONFIG_PACKAGE_rpcd=y +CONFIG_PACKAGE_rpcd-mod-file=y +CONFIG_PACKAGE_rpcd-mod-iwinfo=y +CONFIG_PACKAGE_rpcd-mod-luci=y +CONFIG_PACKAGE_rpcd-mod-lxc=y +CONFIG_PACKAGE_rpcd-mod-rrdns=y +CONFIG_PACKAGE_rpcd-mod-ucode=y +CONFIG_PACKAGE_rrdtool1=y +CONFIG_PACKAGE_rtl8821ce-firmware=y +CONFIG_PACKAGE_rtl8822be-firmware=y +CONFIG_PACKAGE_rtl8822ce-firmware=y +CONFIG_PACKAGE_runc=y +CONFIG_PACKAGE_sfdisk=y +CONFIG_PACKAGE_sgdisk=y +CONFIG_PACKAGE_shadow=y +CONFIG_PACKAGE_shadow-chage=y +CONFIG_PACKAGE_shadow-chfn=y +CONFIG_PACKAGE_shadow-chgpasswd=y +CONFIG_PACKAGE_shadow-chpasswd=y +CONFIG_PACKAGE_shadow-chsh=y +CONFIG_PACKAGE_shadow-common=y +CONFIG_PACKAGE_shadow-expiry=y +CONFIG_PACKAGE_shadow-faillog=y +CONFIG_PACKAGE_shadow-gpasswd=y +CONFIG_PACKAGE_shadow-groupadd=y +CONFIG_PACKAGE_shadow-groupdel=y +CONFIG_PACKAGE_shadow-groupmems=y +CONFIG_PACKAGE_shadow-groupmod=y +CONFIG_PACKAGE_shadow-groups=y +CONFIG_PACKAGE_shadow-grpck=y +CONFIG_PACKAGE_shadow-grpconv=y +CONFIG_PACKAGE_shadow-grpunconv=y +CONFIG_PACKAGE_shadow-lastlog=y +CONFIG_PACKAGE_shadow-login=y +CONFIG_PACKAGE_shadow-logoutd=y +CONFIG_PACKAGE_shadow-newgidmap=y +CONFIG_PACKAGE_shadow-newgrp=y +CONFIG_PACKAGE_shadow-newuidmap=y +CONFIG_PACKAGE_shadow-newusers=y +CONFIG_PACKAGE_shadow-nologin=y +CONFIG_PACKAGE_shadow-passwd=y +CONFIG_PACKAGE_shadow-pwck=y +CONFIG_PACKAGE_shadow-pwconv=y +CONFIG_PACKAGE_shadow-pwunconv=y +CONFIG_PACKAGE_shadow-su=y +CONFIG_PACKAGE_shadow-useradd=y +CONFIG_PACKAGE_shadow-userdel=y +CONFIG_PACKAGE_shadow-usermod=y +CONFIG_PACKAGE_shadow-utils=y +CONFIG_PACKAGE_shadow-vipw=y +CONFIG_PACKAGE_smartmontools=y +CONFIG_PACKAGE_smartmontools-drivedb=y +CONFIG_PACKAGE_sqm-scripts=y +CONFIG_PACKAGE_sqm-scripts-extra=y +CONFIG_PACKAGE_squashfs-tools-mksquashfs=y +CONFIG_PACKAGE_squashfs-tools-unsquashfs=y +CONFIG_PACKAGE_sysfsutils=y +CONFIG_PACKAGE_tar=y +CONFIG_PACKAGE_tc-full=y +CONFIG_PACKAGE_tc-mod-iptables=y +CONFIG_PACKAGE_tc-tiny=y +CONFIG_PACKAGE_tcpdump-mini=y +CONFIG_PACKAGE_terminfo=y +CONFIG_PACKAGE_tini=y +CONFIG_PACKAGE_ttyd=y +CONFIG_PACKAGE_ucert-full=y +CONFIG_PACKAGE_ucode-mod-html=y +CONFIG_PACKAGE_ucode-mod-lua=y +CONFIG_PACKAGE_ucode-mod-math=y +CONFIG_PACKAGE_ucode-mod-nl80211=y +CONFIG_PACKAGE_uencrypt-openssl=y +CONFIG_PACKAGE_uhttpd=y +CONFIG_PACKAGE_uhttpd-mod-ubus=y +CONFIG_PACKAGE_usb-modeswitch=y +CONFIG_PACKAGE_usbids=y +CONFIG_PACKAGE_usbutils=y +CONFIG_PACKAGE_uuidd=y +CONFIG_PACKAGE_uuidgen=y +CONFIG_PACKAGE_vsftpd-tls=y +CONFIG_PACKAGE_vxlan=y +CONFIG_PACKAGE_wget-ssl=y +CONFIG_PACKAGE_wifi-scripts=y +CONFIG_PACKAGE_wireguard-tools=y +CONFIG_PACKAGE_wireless-regdb=y +CONFIG_PACKAGE_wireless-tools=y +CONFIG_PACKAGE_wsdd2=y +CONFIG_PACKAGE_xl2tpd=y +CONFIG_PACKAGE_xtables-nft=y +CONFIG_PACKAGE_xz=y +CONFIG_PACKAGE_xz-utils=y +CONFIG_PACKAGE_xzdec=y +CONFIG_PACKAGE_xzdiff=y +CONFIG_PACKAGE_xzgrep=y +CONFIG_PACKAGE_xzless=y +CONFIG_PACKAGE_xzmore=y +CONFIG_PACKAGE_zlib=y +CONFIG_PARTED_READLINE=y +CONFIG_REPRODUCIBLE_DEBUG_INFO=y +CONFIG_SQUASHFS_TOOLS_XZ_SUPPORT=y +CONFIG_SQUASHFS_TOOLS_ZSTD_SUPPORT=y +CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_OPTIONS=y +CONFIG_ZSTD_OPTIMIZE_O3=y +CONFIG_shadow-all=y +# CONFIG_BPF_TOOLCHAIN_BUILD_LLVM is not set +CONFIG_BPF_TOOLCHAIN_PREBUILT=y +# CONFIG_COLLECT_KERNEL_DEBUG is not set +# CONFIG_IB is not set +# CONFIG_KERNEL_WERROR is not set +# CONFIG_MAKE_TOOLCHAIN is not set +# CONFIG_OPENVPN_openssl_ENABLE_SMALL is not set +# CONFIG_SDK is not set +CONFIG_USE_LLVM_PREBUILT=y diff --git a/.github/workflows/config.buildinfo4 b/.github/workflows/config.buildinfo4 new file mode 100644 index 00000000000000..41df4844e6f162 --- /dev/null +++ b/.github/workflows/config.buildinfo4 @@ -0,0 +1,687 @@ +CONFIG_TARGET_bcm27xx=y +CONFIG_TARGET_bcm27xx_bcm2711=y +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_DEVICE_bcm27xx_bcm2711_DEVICE_rpi-4=y +CONFIG_TARGET_DEVICE_PACKAGES_bcm27xx_bcm2711_DEVICE_rpi-4="" +CONFIG_ALL_KMODS=y +CONFIG_ALL_NONSHARED=y +CONFIG_DEVEL=y +CONFIG_BUSYBOX_CUSTOM=y +CONFIG_TARGET_PER_DEVICE_ROOTFS=y +CONFIG_BUILDBOT=y +CONFIG_BUILD_LOG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_GETOPT_LONG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ=y +CONFIG_BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS=y +CONFIG_BUSYBOX_CONFIG_GETOPT=y +CONFIG_BUSYBOX_CONFIG_MOUNTPOINT=y +CONFIG_BUSYBOX_CONFIG_UNXZ=y +CONFIG_BUSYBOX_CONFIG_XZ=y +CONFIG_CGROUPFS_MOUNT_KERNEL_CGROUPS=y +CONFIG_DOCKER_CGROUP_OPTIONS=y +CONFIG_DOCKER_CHECK_CONFIG=y +CONFIG_DOCKER_NET_ENCRYPT=y +CONFIG_DOCKER_NET_MACVLAN=y +CONFIG_DOCKER_NET_OVERLAY=y +CONFIG_DOCKER_NET_TFTP=y +CONFIG_DOCKER_OPTIONAL_FEATURES=y +CONFIG_DOCKER_STO_BTRFS=y +CONFIG_DOCKER_STO_DEVMAPPER=y +CONFIG_DOCKER_STO_EXT4=y +CONFIG_GNUTLS_ALPN=y +CONFIG_GNUTLS_ANON=y +CONFIG_GNUTLS_DTLS_SRTP=y +CONFIG_GNUTLS_HEARTBEAT=y +CONFIG_GNUTLS_OCSP=y +CONFIG_GNUTLS_PSK=y +CONFIG_HTOP_LMSENSORS=y +CONFIG_JSON_CYCLONEDX_SBOM=n +CONFIG_KERNEL_ARM_PMU=y +CONFIG_KERNEL_BTRFS_FS_POSIX_ACL=y +CONFIG_KERNEL_BUILD_DOMAIN="buildhost" +CONFIG_KERNEL_BUILD_USER="builder" +CONFIG_KERNEL_CFQ_GROUP_IOSCHED=y +CONFIG_KERNEL_CGROUP_DEVICE=y +CONFIG_KERNEL_CGROUP_FREEZER=y +CONFIG_KERNEL_CGROUP_HUGETLB=y +CONFIG_KERNEL_CGROUP_NET_PRIO=y +CONFIG_KERNEL_CGROUP_PERF=y +CONFIG_KERNEL_EXT4_FS_POSIX_ACL=y +CONFIG_KERNEL_EXT4_FS_SECURITY=y +CONFIG_KERNEL_FS_POSIX_ACL=y +CONFIG_KERNEL_HUGETLBFS=y +CONFIG_KERNEL_HUGETLB_PAGE=y +CONFIG_KERNEL_MEMCG_SWAP_ENABLED=y +CONFIG_KERNEL_NET_CLS_CGROUP=y +CONFIG_KERNEL_PERF_EVENTS=y +CONFIG_KERNEL_RPI_AXIPERF=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_KERNEL_WERROR is not set +CONFIG_LIBCURL_COOKIES=y +CONFIG_LIBCURL_FILE=y +CONFIG_LIBCURL_FTP=y +CONFIG_LIBCURL_HTTP=y +CONFIG_LIBCURL_MBEDTLS=y +CONFIG_LIBCURL_NGHTTP2=y +CONFIG_LIBCURL_NO_SMB="!" +CONFIG_LIBCURL_PROXY=y +CONFIG_LIBCURL_UNIX_SOCKETS=y +CONFIG_LXC_BUSYBOX_OPTIONS=y +CONFIG_LXC_KERNEL_OPTIONS=y +CONFIG_LXC_NETWORKING=y +CONFIG_LXC_SECCOMP=y +CONFIG_OPENSSL_ENGINE=y +CONFIG_OPENSSL_ENGINE_BUILTIN=y +CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO=y +CONFIG_OPENSSL_OPTIMIZE_SPEED=y +CONFIG_OPENSSL_WITH_ASM=y +CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y +CONFIG_OPENSSL_WITH_CMS=y +CONFIG_OPENSSL_WITH_DEPRECATED=y +CONFIG_OPENSSL_WITH_ERROR_MESSAGES=y +CONFIG_OPENSSL_WITH_IDEA=y +CONFIG_OPENSSL_WITH_MDC2=y +CONFIG_OPENSSL_WITH_PSK=y +CONFIG_OPENSSL_WITH_SEED=y +CONFIG_OPENSSL_WITH_SRP=y +CONFIG_OPENSSL_WITH_TLS13=y +CONFIG_OPENSSL_WITH_WHIRLPOOL=y +CONFIG_OPENVPN_openssl_ENABLE_FRAGMENT=y +CONFIG_OPENVPN_openssl_ENABLE_LZ4=y +CONFIG_OPENVPN_openssl_ENABLE_LZO=y +CONFIG_OPENVPN_openssl_ENABLE_PORT_SHARE=y +CONFIG_OPENVPN_openssl_ENABLE_X509_ALT_USERNAME=y +CONFIG_PACKAGE_TAR_BZIP2=y +CONFIG_PACKAGE_TAR_GZIP=y +CONFIG_PACKAGE_TAR_POSIX_ACL=y +CONFIG_PACKAGE_TAR_XATTR=y +CONFIG_PACKAGE_TAR_XZ=y +CONFIG_PACKAGE_TAR_ZSTD=y +CONFIG_PACKAGE_adb=y +CONFIG_PACKAGE_adblock=y +CONFIG_PACKAGE_arp-scan=y +CONFIG_PACKAGE_arp-scan-database=y +CONFIG_PACKAGE_atop=y +CONFIG_PACKAGE_bash=y +CONFIG_PACKAGE_bcm2711-eeprom=y +CONFIG_PACKAGE_bcm27xx-eeprom=y +CONFIG_PACKAGE_luci-app-filebrowser=y +CONFIG_PACKAGE_bcm27xx-utils=y +CONFIG_PACKAGE_blkdiscard=y +CONFIG_PACKAGE_blkid=y +CONFIG_PACKAGE_block-mount=y +CONFIG_PACKAGE_blockd=y +CONFIG_PACKAGE_blockdev=y +CONFIG_PACKAGE_bluez-daemon=y +CONFIG_PACKAGE_bluez-libs=y +CONFIG_PACKAGE_bluez-tools=y +CONFIG_PACKAGE_bluez-utils=y +CONFIG_PACKAGE_bluez-utils-extra=y +CONFIG_PACKAGE_btop=y +CONFIG_PACKAGE_btrfs-progs=y +CONFIG_PACKAGE_bzip2=y +CONFIG_PACKAGE_ca-certificates=y +CONFIG_PACKAGE_ccrypt=y +CONFIG_PACKAGE_certtool=y +CONFIG_PACKAGE_cfdisk=y +CONFIG_PACKAGE_cgdisk=y +CONFIG_PACKAGE_cgi-io=y +CONFIG_PACKAGE_cgroup-tools=y +CONFIG_PACKAGE_cgroupfs-mount=y +CONFIG_PACKAGE_collectd=y +CONFIG_PACKAGE_collectd-mod-conntrack=y +CONFIG_PACKAGE_collectd-mod-cpu=y +CONFIG_PACKAGE_collectd-mod-cpufreq=y +CONFIG_PACKAGE_collectd-mod-interface=y +CONFIG_PACKAGE_collectd-mod-irq=y +CONFIG_PACKAGE_collectd-mod-iwinfo=y +CONFIG_PACKAGE_collectd-mod-load=y +CONFIG_PACKAGE_collectd-mod-memory=y +CONFIG_PACKAGE_collectd-mod-network=y +CONFIG_PACKAGE_collectd-mod-rrdtool=y +CONFIG_PACKAGE_collectd-mod-sensors=y +CONFIG_PACKAGE_collectd-mod-thermal=y +CONFIG_PACKAGE_containerd=y +CONFIG_PACKAGE_coreutils=y +CONFIG_PACKAGE_coreutils-od=y +CONFIG_PACKAGE_coreutils-sort=y +CONFIG_PACKAGE_cryptsetup=y +CONFIG_PACKAGE_cryptsetup-ssh=y +CONFIG_PACKAGE_dbus=y +CONFIG_PACKAGE_debugfs=y +CONFIG_PACKAGE_dnsmasq=m +CONFIG_PACKAGE_dnsmasq-full=y +CONFIG_PACKAGE_dnsmasq_full_auth=y +CONFIG_PACKAGE_dnsmasq_full_conntrack=y +CONFIG_PACKAGE_dnsmasq_full_dhcp=y +CONFIG_PACKAGE_dnsmasq_full_dhcpv6=y +CONFIG_PACKAGE_dnsmasq_full_dnssec=y +CONFIG_PACKAGE_dnsmasq_full_nftset=y +CONFIG_PACKAGE_dnsmasq_full_noid=y +CONFIG_PACKAGE_dnsmasq_full_tftp=y +CONFIG_PACKAGE_docker=y +CONFIG_PACKAGE_docker-compose=y +CONFIG_PACKAGE_dockerd=y +CONFIG_PACKAGE_dosfstools=y +CONFIG_PACKAGE_dumpe2fs=y +CONFIG_PACKAGE_e2freefrag=y +CONFIG_PACKAGE_e4crypt=y +CONFIG_PACKAGE_eject=y +CONFIG_PACKAGE_ethtool-full=y +CONFIG_PACKAGE_exfat-fsck=y +CONFIG_PACKAGE_exfat-mkfs=y +CONFIG_PACKAGE_f2fs-tools=m +CONFIG_PACKAGE_f2fs-tools-selinux=y +CONFIG_PACKAGE_f2fsck=m +CONFIG_PACKAGE_f2fsck-selinux=y +CONFIG_PACKAGE_fdisk=y +CONFIG_PACKAGE_findfs=y +CONFIG_PACKAGE_fixparts=y +CONFIG_PACKAGE_flock=y +CONFIG_PACKAGE_fuse-utils=y +CONFIG_PACKAGE_gdisk=y +CONFIG_PACKAGE_getopt=y +CONFIG_PACKAGE_glib2=y +CONFIG_PACKAGE_gnupg=y +CONFIG_PACKAGE_gnupg-utils=y +CONFIG_PACKAGE_gnupg2=y +CONFIG_PACKAGE_gnupg2-utils=y +CONFIG_PACKAGE_gzip=y +CONFIG_PACKAGE_hdparm=y +CONFIG_PACKAGE_hostapd-common=y +CONFIG_PACKAGE_htop=y +CONFIG_PACKAGE_hwclock=y +CONFIG_PACKAGE_ip-full=y +CONFIG_PACKAGE_ip6tables-nft=y +CONFIG_PACKAGE_iperf3-ssl=y +CONFIG_PACKAGE_ipset=y + +CONFIG_PACKAGE_iptables-mod-ipopt=y +CONFIG_PACKAGE_iptables-nft=y +CONFIG_PACKAGE_irqbalance=y +CONFIG_PACKAGE_iw=y +CONFIG_PACKAGE_iwinfo=y +CONFIG_PACKAGE_kmod-asn1-decoder=y +CONFIG_PACKAGE_kmod-asn1-encoder=y +CONFIG_PACKAGE_kmod-ata-ahci=y +CONFIG_PACKAGE_kmod-ata-core=y +CONFIG_PACKAGE_kmod-atm=y +CONFIG_PACKAGE_kmod-bluetooth=y +CONFIG_PACKAGE_kmod-br-netfilter=y +CONFIG_PACKAGE_kmod-cdrom=y +CONFIG_PACKAGE_kmod-cfg80211=y +CONFIG_PACKAGE_kmod-crypto-aead=y +CONFIG_PACKAGE_kmod-crypto-arc4=y +CONFIG_PACKAGE_kmod-crypto-authenc=y +CONFIG_PACKAGE_kmod-crypto-cbc=y +CONFIG_PACKAGE_kmod-crypto-ccm=y +CONFIG_PACKAGE_kmod-crypto-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-cmac=y +CONFIG_PACKAGE_kmod-crypto-crc32=y +CONFIG_PACKAGE_kmod-crypto-ctr=y +CONFIG_PACKAGE_kmod-crypto-cts=y +CONFIG_PACKAGE_kmod-crypto-deflate=y +CONFIG_PACKAGE_kmod-crypto-des=y +CONFIG_PACKAGE_kmod-crypto-ecb=y +CONFIG_PACKAGE_kmod-crypto-ecdh=y +CONFIG_PACKAGE_kmod-crypto-echainiv=y +CONFIG_PACKAGE_kmod-crypto-essiv=y +CONFIG_PACKAGE_kmod-crypto-fcrypt=y +CONFIG_PACKAGE_kmod-crypto-gcm=y +CONFIG_PACKAGE_kmod-crypto-gf128=y +CONFIG_PACKAGE_kmod-crypto-ghash=y +CONFIG_PACKAGE_kmod-crypto-hmac=y +CONFIG_PACKAGE_kmod-crypto-kpp=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-lib-curve25519=y +CONFIG_PACKAGE_kmod-crypto-lib-poly1305=y +CONFIG_PACKAGE_kmod-crypto-manager=y +CONFIG_PACKAGE_kmod-crypto-md4=y +CONFIG_PACKAGE_kmod-crypto-md5=y +CONFIG_PACKAGE_kmod-crypto-michael-mic=y +CONFIG_PACKAGE_kmod-crypto-misc=y +CONFIG_PACKAGE_kmod-crypto-null=y +CONFIG_PACKAGE_kmod-crypto-pcbc=y +CONFIG_PACKAGE_kmod-crypto-rmd160=y +CONFIG_PACKAGE_kmod-crypto-rng=y +CONFIG_PACKAGE_kmod-crypto-seqiv=y +CONFIG_PACKAGE_kmod-crypto-sha1=y +CONFIG_PACKAGE_kmod-crypto-sha256=y +CONFIG_PACKAGE_kmod-crypto-sha512=y +CONFIG_PACKAGE_kmod-crypto-test=y +CONFIG_PACKAGE_kmod-crypto-user=y +CONFIG_PACKAGE_kmod-crypto-xcbc=y +CONFIG_PACKAGE_kmod-crypto-xts=y +CONFIG_PACKAGE_kmod-cryptodev=y +CONFIG_PACKAGE_kmod-dax=y +CONFIG_PACKAGE_kmod-dm=y +CONFIG_PACKAGE_kmod-dummy=y +CONFIG_PACKAGE_kmod-fs-autofs4=y +CONFIG_PACKAGE_kmod-fs-btrfs=y +CONFIG_PACKAGE_kmod-fs-configfs=y +CONFIG_PACKAGE_kmod-fs-exfat=y +CONFIG_PACKAGE_kmod-fs-exportfs=y +CONFIG_PACKAGE_kmod-fs-ext4=y +CONFIG_PACKAGE_kmod-fs-f2fs=y +CONFIG_PACKAGE_kmod-fs-hfs=y +CONFIG_PACKAGE_kmod-fs-hfsplus=y +CONFIG_PACKAGE_kmod-fs-ksmbd=y +CONFIG_PACKAGE_kmod-fs-ntfs3=y +CONFIG_PACKAGE_kmod-fs-smbfs-common=y +CONFIG_PACKAGE_kmod-fs-squashfs=y +CONFIG_PACKAGE_kmod-fs-xfs=y +CONFIG_PACKAGE_kmod-fuse=y +CONFIG_PACKAGE_kmod-gre=y +CONFIG_PACKAGE_kmod-hwmon-core=y +CONFIG_PACKAGE_kmod-i2c-bcm2835=y +CONFIG_PACKAGE_kmod-i2c-core=y +CONFIG_PACKAGE_kmod-ifb=y +CONFIG_PACKAGE_kmod-ikconfig=y +CONFIG_PACKAGE_kmod-ip6tables=y +CONFIG_PACKAGE_kmod-ipsec=y +CONFIG_PACKAGE_kmod-ipt-conntrack=y +CONFIG_PACKAGE_kmod-ipt-core=y +CONFIG_PACKAGE_kmod-ipt-extra=y +CONFIG_PACKAGE_kmod-ipt-ipopt=y +CONFIG_PACKAGE_kmod-ipt-ipset=y +CONFIG_PACKAGE_kmod-ipt-nat=y +CONFIG_PACKAGE_kmod-ipt-nat6=y +CONFIG_PACKAGE_kmod-ipt-physdev=y +CONFIG_PACKAGE_kmod-iptunnel=y +CONFIG_PACKAGE_kmod-keys-encrypted=y +CONFIG_PACKAGE_kmod-keys-trusted=y +CONFIG_PACKAGE_kmod-l2tp=y +CONFIG_PACKAGE_kmod-lib-crc16=y +CONFIG_PACKAGE_kmod-lib-raid6=y +CONFIG_PACKAGE_kmod-lib-textsearch=y +CONFIG_PACKAGE_kmod-lib-xor=y +CONFIG_PACKAGE_kmod-lib-zlib-deflate=y +CONFIG_PACKAGE_kmod-lib-zlib-inflate=y +CONFIG_PACKAGE_kmod-lib-zstd=y +CONFIG_PACKAGE_kmod-libphy=y +CONFIG_PACKAGE_kmod-mac80211=y +CONFIG_PACKAGE_kmod-macvlan=y +CONFIG_PACKAGE_kmod-md-mod=y +CONFIG_PACKAGE_kmod-md-raid0=y +CONFIG_PACKAGE_kmod-md-raid1=y +CONFIG_PACKAGE_kmod-md-raid10=y +CONFIG_PACKAGE_kmod-mdio-devres=y +CONFIG_PACKAGE_kmod-mii=y +CONFIG_PACKAGE_kmod-mppe=y +CONFIG_PACKAGE_kmod-mt76-connac=y +CONFIG_PACKAGE_kmod-mt76-core=y +CONFIG_PACKAGE_kmod-mt76-usb=y +CONFIG_PACKAGE_kmod-mt76x02-common=y +CONFIG_PACKAGE_kmod-mt76x02-usb=y +CONFIG_PACKAGE_kmod-mt76x2-common=y +CONFIG_PACKAGE_kmod-mt76x2u=y +CONFIG_PACKAGE_kmod-mt7921-common=y +CONFIG_PACKAGE_kmod-mt7921-firmware=y +CONFIG_PACKAGE_kmod-mt7921u=y +CONFIG_PACKAGE_kmod-mt792x-common=y +CONFIG_PACKAGE_kmod-mt792x-usb=y +CONFIG_PACKAGE_kmod-net-selftests=y +CONFIG_PACKAGE_kmod-nf-conntrack-netlink=y +CONFIG_PACKAGE_kmod-nf-ipt=y +CONFIG_PACKAGE_kmod-nf-ipt6=y +CONFIG_PACKAGE_kmod-nf-ipvs=y +CONFIG_PACKAGE_kmod-nf-nat6=y +CONFIG_PACKAGE_kmod-nf-nathelper=y +CONFIG_PACKAGE_kmod-nf-nathelper-extra=y +CONFIG_PACKAGE_kmod-nft-compat=y +CONFIG_PACKAGE_kmod-nvme=y +CONFIG_PACKAGE_kmod-oid-registry=y +CONFIG_PACKAGE_kmod-phy-ax88796b=y +CONFIG_PACKAGE_kmod-phy-realtek=y +CONFIG_PACKAGE_kmod-phylink=y +CONFIG_PACKAGE_kmod-pppoa=y +CONFIG_PACKAGE_kmod-pppol2tp=y +CONFIG_PACKAGE_kmod-pptp=y +CONFIG_PACKAGE_kmod-r8169=y +CONFIG_PACKAGE_kmod-random-core=y +CONFIG_PACKAGE_kmod-regmap-core=y +CONFIG_PACKAGE_kmod-rtl8812au-ac=y +CONFIG_PACKAGE_kmod-rtw88=y +CONFIG_PACKAGE_kmod-rtw88-8821c=y +CONFIG_PACKAGE_kmod-rtw88-8821cu=y +CONFIG_PACKAGE_kmod-rtw88-8822b=y +CONFIG_PACKAGE_kmod-rtw88-8822bu=y +CONFIG_PACKAGE_kmod-rtw88-8822c=y +CONFIG_PACKAGE_kmod-rtw88-8822cu=y +CONFIG_PACKAGE_kmod-rtw88-usb=y +CONFIG_PACKAGE_kmod-sched-bpf=y +CONFIG_PACKAGE_kmod-sched-cake=y +CONFIG_PACKAGE_kmod-sched-core=y +CONFIG_PACKAGE_kmod-scsi-core=y +CONFIG_PACKAGE_kmod-tpm=y +CONFIG_PACKAGE_kmod-tun=y +CONFIG_PACKAGE_kmod-udptunnel4=y +CONFIG_PACKAGE_kmod-udptunnel6=y +CONFIG_PACKAGE_kmod-usb-net=y +CONFIG_PACKAGE_kmod-usb-net-aqc111=y +CONFIG_PACKAGE_kmod-usb-net-asix=y +CONFIG_PACKAGE_kmod-usb-net-asix-ax88179=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ether=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ncm=y +CONFIG_PACKAGE_kmod-usb-net-ipheth=y +CONFIG_PACKAGE_kmod-usb-net-rndis=y +CONFIG_PACKAGE_kmod-usb-net-rtl8150=y +CONFIG_PACKAGE_kmod-usb-net-rtl8152=y +CONFIG_PACKAGE_kmod-usb-ohci=y +CONFIG_PACKAGE_kmod-usb-storage=y +CONFIG_PACKAGE_kmod-usb-storage-extras=y +CONFIG_PACKAGE_kmod-usb-storage-uas=y +CONFIG_PACKAGE_kmod-usb-wdm=y +CONFIG_PACKAGE_kmod-veth=y +CONFIG_PACKAGE_kmod-vxlan=y +CONFIG_PACKAGE_kmod-wireguard=y +CONFIG_PACKAGE_ksmbd-server=y +CONFIG_PACKAGE_libacl=y +CONFIG_PACKAGE_libaio=y +CONFIG_PACKAGE_libassuan=y +CONFIG_PACKAGE_libatomic=y +CONFIG_PACKAGE_libattr=y +CONFIG_PACKAGE_libbfd=m +CONFIG_PACKAGE_libbpf=y +CONFIG_PACKAGE_libbz2=y +CONFIG_PACKAGE_libcap=y +CONFIG_PACKAGE_libcap-ng=y +CONFIG_PACKAGE_libcgroup=y +CONFIG_PACKAGE_libctf=m +CONFIG_PACKAGE_libcurl=y +CONFIG_PACKAGE_libdbus=y +CONFIG_PACKAGE_libdevmapper=y +CONFIG_PACKAGE_libdw=m +CONFIG_PACKAGE_libelf=y +CONFIG_PACKAGE_libevdev=y +CONFIG_PACKAGE_libexpat=y +CONFIG_PACKAGE_libf2fs=m +CONFIG_PACKAGE_libf2fs-selinux=y +CONFIG_PACKAGE_libfdisk=y +CONFIG_PACKAGE_libffi=y +CONFIG_PACKAGE_libfuse=y +CONFIG_PACKAGE_libgcrypt=y +CONFIG_PACKAGE_libgmp=y +CONFIG_PACKAGE_libgnutls=y +CONFIG_PACKAGE_libgpg-error=y +CONFIG_PACKAGE_libical=y +CONFIG_PACKAGE_libipset=y +CONFIG_PACKAGE_libiptext=y +CONFIG_PACKAGE_libiptext-nft=y +CONFIG_PACKAGE_libiptext6=y +CONFIG_PACKAGE_libiwinfo=y +CONFIG_PACKAGE_libiwinfo-data=y +CONFIG_PACKAGE_libkmod=y +CONFIG_PACKAGE_libksba=y +CONFIG_PACKAGE_libltdl=y +CONFIG_PACKAGE_liblua=y +CONFIG_PACKAGE_liblucihttp=y +CONFIG_PACKAGE_liblucihttp-lua=y +CONFIG_PACKAGE_liblucihttp-ucode=y +CONFIG_PACKAGE_liblxc=y +CONFIG_PACKAGE_liblz4=y +CONFIG_PACKAGE_liblzma=y +CONFIG_PACKAGE_liblzo=y +CONFIG_PACKAGE_libmount=y +CONFIG_PACKAGE_libncurses=y +CONFIG_PACKAGE_libnetfilter-conntrack=y +CONFIG_PACKAGE_libnettle=y +CONFIG_PACKAGE_libnfnetlink=y +CONFIG_PACKAGE_libnghttp2=y +CONFIG_PACKAGE_libnl-core=y +CONFIG_PACKAGE_libnl-genl=y +CONFIG_PACKAGE_libnpth=y +CONFIG_PACKAGE_libopcodes=m +CONFIG_PACKAGE_libopenssl=y +CONFIG_PACKAGE_libopenssl-conf=y +CONFIG_PACKAGE_libparted=y +CONFIG_PACKAGE_libpcap=y +CONFIG_PACKAGE_libpci=y +CONFIG_PACKAGE_libpcre2=y +CONFIG_PACKAGE_libpopt=y +CONFIG_PACKAGE_libpython3=y +CONFIG_PACKAGE_libqrencode=y +CONFIG_PACKAGE_libreadline=y +CONFIG_PACKAGE_librrd1=y +CONFIG_PACKAGE_libseccomp=y +CONFIG_PACKAGE_libselinux=y +CONFIG_PACKAGE_libsensors=y +CONFIG_PACKAGE_libsepol=y +CONFIG_PACKAGE_libssh=y +CONFIG_PACKAGE_libstdcpp=y +CONFIG_PACKAGE_libsysfs=y +CONFIG_PACKAGE_libtirpc=y +CONFIG_PACKAGE_libubus-lua=y +CONFIG_PACKAGE_libudev-zero=y +CONFIG_PACKAGE_libusb-1.0=y +CONFIG_PACKAGE_libuv=y +CONFIG_PACKAGE_libwebsockets-full=y +CONFIG_PACKAGE_libxtables=y +CONFIG_PACKAGE_libzstd=y +CONFIG_PACKAGE_linux-atm=y +CONFIG_PACKAGE_lm-sensors=y +CONFIG_PACKAGE_losetup=y +CONFIG_PACKAGE_lsblk=y +CONFIG_PACKAGE_lscpu=y +CONFIG_PACKAGE_lua=y +CONFIG_PACKAGE_luci=y +CONFIG_PACKAGE_luci-app-adblock=y +CONFIG_PACKAGE_luci-app-commands=y +CONFIG_PACKAGE_luci-app-diskman=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_btrfs_progs=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_lsblk=y +CONFIG_PACKAGE_luci-app-dockerman=y +CONFIG_PACKAGE_luci-app-firewall=y +CONFIG_PACKAGE_luci-app-ksmbd=y +CONFIG_PACKAGE_luci-app-lxc=y +CONFIG_PACKAGE_luci-app-nlbwmon=y +CONFIG_PACKAGE_luci-app-openvpn=y +CONFIG_PACKAGE_luci-app-opkg=y +CONFIG_PACKAGE_luci-app-pbr=y +CONFIG_PACKAGE_luci-app-sqm=y +CONFIG_PACKAGE_luci-app-statistics=y +CONFIG_PACKAGE_luci-app-ttyd=y +CONFIG_PACKAGE_luci-base=y +CONFIG_PACKAGE_luci-compat=y +CONFIG_PACKAGE_luci-lib-base=y +CONFIG_PACKAGE_luci-lib-docker=y +CONFIG_PACKAGE_luci-lib-ip=y +CONFIG_PACKAGE_luci-lib-jsonc=y +CONFIG_PACKAGE_luci-lib-nixio=y +CONFIG_PACKAGE_luci-light=y +CONFIG_PACKAGE_luci-lua-runtime=y +CONFIG_PACKAGE_luci-mod-admin-full=y +CONFIG_PACKAGE_luci-mod-network=y +CONFIG_PACKAGE_luci-mod-status=y +CONFIG_PACKAGE_luci-mod-system=y +CONFIG_PACKAGE_luci-proto-ipv6=y +CONFIG_PACKAGE_luci-proto-ppp=y +CONFIG_PACKAGE_luci-proto-vxlan=y +CONFIG_PACKAGE_luci-proto-wireguard=y +CONFIG_PACKAGE_luci-theme-bootstrap=y +CONFIG_PACKAGE_lvm2=y +CONFIG_PACKAGE_lxc=y +CONFIG_PACKAGE_lxc-attach=y +CONFIG_PACKAGE_lxc-auto=y +CONFIG_PACKAGE_lxc-autostart=y +CONFIG_PACKAGE_lxc-cgroup=y +CONFIG_PACKAGE_lxc-checkconfig=y +CONFIG_PACKAGE_lxc-common=y +CONFIG_PACKAGE_lxc-config=y +CONFIG_PACKAGE_lxc-configs=y +CONFIG_PACKAGE_lxc-console=y +CONFIG_PACKAGE_lxc-copy=y +CONFIG_PACKAGE_lxc-create=y +CONFIG_PACKAGE_lxc-destroy=y +CONFIG_PACKAGE_lxc-device=y +CONFIG_PACKAGE_lxc-execute=y +CONFIG_PACKAGE_lxc-freeze=y +CONFIG_PACKAGE_lxc-hooks=y +CONFIG_PACKAGE_lxc-info=y +CONFIG_PACKAGE_lxc-init=y +CONFIG_PACKAGE_lxc-ls=y +CONFIG_PACKAGE_lxc-monitor=y +CONFIG_PACKAGE_lxc-monitord=y +CONFIG_PACKAGE_lxc-snapshot=y +CONFIG_PACKAGE_lxc-start=y +CONFIG_PACKAGE_lxc-stop=y +CONFIG_PACKAGE_lxc-templates=y +CONFIG_PACKAGE_lxc-top=y +CONFIG_PACKAGE_lxc-unfreeze=y +CONFIG_PACKAGE_lxc-unprivileged=y +CONFIG_PACKAGE_lxc-unshare=y +CONFIG_PACKAGE_lxc-user-nic=y +CONFIG_PACKAGE_lxc-usernsexec=y +CONFIG_PACKAGE_lxc-wait=y +CONFIG_PACKAGE_lz4=y +CONFIG_PACKAGE_lzmadec=y +CONFIG_PACKAGE_lzmainfo=y +CONFIG_PACKAGE_mdadm=y +CONFIG_PACKAGE_mkf2fs=m +CONFIG_PACKAGE_mkf2fs-selinux=y +CONFIG_PACKAGE_mmc-utils=y +CONFIG_PACKAGE_mount-utils=y +CONFIG_PACKAGE_mtools=y +CONFIG_PACKAGE_musl-fts=y +CONFIG_PACKAGE_nano=y +CONFIG_PACKAGE_nfs-utils=y +CONFIG_PACKAGE_nlbwmon=y +CONFIG_PACKAGE_objdump=m +CONFIG_PACKAGE_openssl-util=y +CONFIG_PACKAGE_openvpn-easy-rsa=y +CONFIG_PACKAGE_openvpn-openssl=y +CONFIG_PACKAGE_parted=y +CONFIG_PACKAGE_pbr=y +CONFIG_PACKAGE_pciids=y +CONFIG_PACKAGE_pciutils=y +CONFIG_PACKAGE_perf=m +CONFIG_PACKAGE_ppp-mod-passwordfd=y +CONFIG_PACKAGE_ppp-mod-pppoa=y +CONFIG_PACKAGE_ppp-mod-pppol2tp=y +CONFIG_PACKAGE_ppp-mod-pptp=y +CONFIG_PACKAGE_ppp-mod-radius=y +CONFIG_PACKAGE_pppdump=y +CONFIG_PACKAGE_pppoe-discovery=y +CONFIG_PACKAGE_pptpd=y +CONFIG_PACKAGE_python3-base=y +CONFIG_PACKAGE_python3-light=y +CONFIG_PACKAGE_qosify=y +CONFIG_PACKAGE_qrencode=y +CONFIG_PACKAGE_r8152-firmware=y +CONFIG_PACKAGE_r8169-firmware=y +CONFIG_PACKAGE_resize2fs=y +CONFIG_PACKAGE_resolveip=y +CONFIG_PACKAGE_rpcd=y +CONFIG_PACKAGE_rpcd-mod-file=y +CONFIG_PACKAGE_rpcd-mod-iwinfo=y +CONFIG_PACKAGE_rpcd-mod-luci=y +CONFIG_PACKAGE_rpcd-mod-lxc=y +CONFIG_PACKAGE_rpcd-mod-rrdns=y +CONFIG_PACKAGE_rpcd-mod-ucode=y +CONFIG_PACKAGE_rrdtool1=y +CONFIG_PACKAGE_rtl8821ce-firmware=y +CONFIG_PACKAGE_rtl8822be-firmware=y +CONFIG_PACKAGE_rtl8822ce-firmware=y +CONFIG_PACKAGE_runc=y +CONFIG_PACKAGE_sfdisk=y +CONFIG_PACKAGE_sgdisk=y +CONFIG_PACKAGE_shadow=y +CONFIG_PACKAGE_shadow-chage=y +CONFIG_PACKAGE_shadow-chfn=y +CONFIG_PACKAGE_shadow-chgpasswd=y +CONFIG_PACKAGE_shadow-chpasswd=y +CONFIG_PACKAGE_shadow-chsh=y +CONFIG_PACKAGE_shadow-common=y +CONFIG_PACKAGE_shadow-expiry=y +CONFIG_PACKAGE_shadow-faillog=y +CONFIG_PACKAGE_shadow-gpasswd=y +CONFIG_PACKAGE_shadow-groupadd=y +CONFIG_PACKAGE_shadow-groupdel=y +CONFIG_PACKAGE_shadow-groupmems=y +CONFIG_PACKAGE_shadow-groupmod=y +CONFIG_PACKAGE_shadow-groups=y +CONFIG_PACKAGE_shadow-grpck=y +CONFIG_PACKAGE_shadow-grpconv=y +CONFIG_PACKAGE_shadow-grpunconv=y +CONFIG_PACKAGE_shadow-lastlog=y +CONFIG_PACKAGE_shadow-login=y +CONFIG_PACKAGE_shadow-logoutd=y +CONFIG_PACKAGE_shadow-newgidmap=y +CONFIG_PACKAGE_shadow-newgrp=y +CONFIG_PACKAGE_shadow-newuidmap=y +CONFIG_PACKAGE_shadow-newusers=y +CONFIG_PACKAGE_shadow-nologin=y +CONFIG_PACKAGE_shadow-passwd=y +CONFIG_PACKAGE_shadow-pwck=y +CONFIG_PACKAGE_shadow-pwconv=y +CONFIG_PACKAGE_shadow-pwunconv=y +CONFIG_PACKAGE_shadow-su=y +CONFIG_PACKAGE_shadow-useradd=y +CONFIG_PACKAGE_shadow-userdel=y +CONFIG_PACKAGE_shadow-usermod=y +CONFIG_PACKAGE_shadow-utils=y +CONFIG_PACKAGE_shadow-vipw=y +CONFIG_PACKAGE_smartmontools=y +CONFIG_PACKAGE_smartmontools-drivedb=y +CONFIG_PACKAGE_sqm-scripts=y +CONFIG_PACKAGE_sqm-scripts-extra=y +CONFIG_PACKAGE_squashfs-tools-mksquashfs=y +CONFIG_PACKAGE_squashfs-tools-unsquashfs=y +CONFIG_PACKAGE_sysfsutils=y +CONFIG_PACKAGE_tar=y +CONFIG_PACKAGE_tc-full=y +CONFIG_PACKAGE_tc-mod-iptables=y +CONFIG_PACKAGE_tc-tiny=y +CONFIG_PACKAGE_tcpdump-mini=y +CONFIG_PACKAGE_terminfo=y +CONFIG_PACKAGE_tini=y +CONFIG_PACKAGE_ttyd=y +CONFIG_PACKAGE_ucert-full=y +CONFIG_PACKAGE_ucode-mod-html=y +CONFIG_PACKAGE_ucode-mod-lua=y +CONFIG_PACKAGE_ucode-mod-math=y +CONFIG_PACKAGE_uencrypt-openssl=y +CONFIG_PACKAGE_uhttpd=y +CONFIG_PACKAGE_uhttpd-mod-ubus=y +CONFIG_PACKAGE_usb-modeswitch=y +CONFIG_PACKAGE_usbutils=y +CONFIG_PACKAGE_uuidd=y +CONFIG_PACKAGE_uuidgen=y +CONFIG_PACKAGE_vsftpd-tls=y +CONFIG_PACKAGE_vxlan=y +CONFIG_PACKAGE_wget-ssl=y +CONFIG_PACKAGE_wireguard-tools=y +CONFIG_PACKAGE_wireless-regdb=y +CONFIG_PACKAGE_wireless-tools=y +CONFIG_PACKAGE_wsdd2=y +CONFIG_PACKAGE_xdp-filter=m +CONFIG_PACKAGE_xdp-loader=m +CONFIG_PACKAGE_xdpdump=m +CONFIG_PACKAGE_xl2tpd=y +CONFIG_PACKAGE_xtables-nft=y +CONFIG_PACKAGE_xz=y +CONFIG_PACKAGE_xz-utils=y +CONFIG_PACKAGE_xzdec=y +CONFIG_PACKAGE_xzdiff=y +CONFIG_PACKAGE_xzgrep=y +CONFIG_PACKAGE_xzless=y +CONFIG_PACKAGE_xzmore=y +CONFIG_PACKAGE_zlib=y +CONFIG_PARTED_READLINE=y +CONFIG_REPRODUCIBLE_DEBUG_INFO=y +CONFIG_SQUASHFS_TOOLS_XZ_SUPPORT=y +CONFIG_SQUASHFS_TOOLS_ZSTD_SUPPORT=y +CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_OPTIONS=y +CONFIG_ZSTD_OPTIMIZE_O3=y +CONFIG_shadow-all=y +# CONFIG_BPF_TOOLCHAIN_BUILD_LLVM is not set +CONFIG_BPF_TOOLCHAIN_PREBUILT=y +# CONFIG_COLLECT_KERNEL_DEBUG is not set +# CONFIG_IB is not set +# CONFIG_MAKE_TOOLCHAIN is not set +# CONFIG_OPENVPN_openssl_ENABLE_SMALL is not set +# CONFIG_SDK is not set +CONFIG_USE_LLVM_PREBUILT=y diff --git a/.github/workflows/coverity.yml b/.github/workflows/coverityyml similarity index 100% rename from .github/workflows/coverity.yml rename to .github/workflows/coverityyml diff --git a/.github/workflows/formal.yml b/.github/workflows/formalyml similarity index 100% rename from .github/workflows/formal.yml rename to .github/workflows/formalyml diff --git a/.github/workflows/github-release.yml b/.github/workflows/github-releaseyml similarity index 100% rename from .github/workflows/github-release.yml rename to .github/workflows/github-releaseyml diff --git a/.github/workflows/issue-labeller.yml b/.github/workflows/issue-labelleryml similarity index 100% rename from .github/workflows/issue-labeller.yml rename to .github/workflows/issue-labelleryml diff --git a/.github/workflows/kernel.yml b/.github/workflows/kernelyml similarity index 100% rename from .github/workflows/kernel.yml rename to .github/workflows/kernelyml diff --git a/.github/workflows/label-kernel.yml b/.github/workflows/label-kernelyml similarity index 100% rename from .github/workflows/label-kernel.yml rename to .github/workflows/label-kernelyml diff --git a/.github/workflows/label-target.yml b/.github/workflows/label-targetyml similarity index 100% rename from .github/workflows/label-target.yml rename to .github/workflows/label-targetyml diff --git a/.github/workflows/labeler.yml b/.github/workflows/labeleryml similarity index 100% rename from .github/workflows/labeler.yml rename to .github/workflows/labeleryml diff --git a/.github/workflows/packages.yml b/.github/workflows/packagesyml similarity index 100% rename from .github/workflows/packages.yml rename to .github/workflows/packagesyml diff --git a/.github/workflows/push-containers.yml b/.github/workflows/push-containersyml similarity index 100% rename from .github/workflows/push-containers.yml rename to .github/workflows/push-containersyml diff --git a/.github/workflows/rk-config b/.github/workflows/rk-config new file mode 100644 index 00000000000000..b03fa154284e99 --- /dev/null +++ b/.github/workflows/rk-config @@ -0,0 +1,708 @@ +CONFIG_TARGET_rockchip=y +CONFIG_TARGET_rockchip_armv8=y +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_firefly_roc-rk3328-cc=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_firefly_roc-rk3328-cc="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyarm_nanopi-r2s=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyarm_nanopi-r2s="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyarm_nanopi-r4s=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyarm_nanopi-r4s="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyelec_nanopi-r5c=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyelec_nanopi-r5c="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyelec_nanopi-r5s=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyelec_nanopi-r5s="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyelec_nanopi-r6c=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyelec_nanopi-r6c="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyelec_nanopi-r6s=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_friendlyelec_nanopi-r6s="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_pine64_quartz64-a=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_pine64_quartz64-a="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_radxa_rock-pi-4=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_radxa_rock-pi-4="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_radxa_rock-3a=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_radxa_rock-3a="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_rockchip_bpi-r2-pro=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_rockchip_bpi-r2-pro="" +CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_xunlong_orangepi-5-plus=y +CONFIG_TARGET_DEVICE_PACKAGES_rockchip_armv8_DEVICE_xunlong_orangepi-5-plus="" +CONFIG_ALL_KMODS=y +CONFIG_ALL_NONSHARED=y +CONFIG_DEVEL=y +CONFIG_BUSYBOX_CUSTOM=y +CONFIG_TARGET_PER_DEVICE_ROOTFS=y +CONFIG_AUTOREMOVE=y +CONFIG_BUILDBOT=y +CONFIG_BUILD_LOG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_GETOPT_LONG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ=y +CONFIG_BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS=y +CONFIG_BUSYBOX_CONFIG_GETOPT=y +CONFIG_BUSYBOX_CONFIG_MOUNTPOINT=y +CONFIG_BUSYBOX_CONFIG_UNXZ=y +CONFIG_BUSYBOX_CONFIG_XZ=y +CONFIG_CGROUPFS_MOUNT_KERNEL_CGROUPS=y +CONFIG_DOCKER_CGROUP_OPTIONS=y +CONFIG_DOCKER_CHECK_CONFIG=y +CONFIG_DOCKER_NET_ENCRYPT=y +CONFIG_DOCKER_NET_MACVLAN=y +CONFIG_DOCKER_NET_OVERLAY=y +CONFIG_DOCKER_NET_TFTP=y +CONFIG_DOCKER_OPTIONAL_FEATURES=y +CONFIG_DOCKER_STO_BTRFS=y +CONFIG_DOCKER_STO_DEVMAPPER=y +CONFIG_DOCKER_STO_EXT4=y +CONFIG_GNUTLS_ALPN=y +CONFIG_GNUTLS_ANON=y +CONFIG_GNUTLS_DTLS_SRTP=y +CONFIG_GNUTLS_HEARTBEAT=y +CONFIG_GNUTLS_OCSP=y +CONFIG_GNUTLS_PSK=y +CONFIG_HTOP_LMSENSORS=y +CONFIG_KERNEL_ARM_PMU=y +CONFIG_KERNEL_BTRFS_FS_POSIX_ACL=y +CONFIG_KERNEL_BUILD_DOMAIN="buildhost" +CONFIG_KERNEL_BUILD_USER="builder" +CONFIG_KERNEL_CFQ_GROUP_IOSCHED=y +CONFIG_KERNEL_CGROUP_DEVICE=y +CONFIG_KERNEL_CGROUP_FREEZER=y +CONFIG_KERNEL_CGROUP_HUGETLB=y +CONFIG_KERNEL_CGROUP_NET_PRIO=y +CONFIG_KERNEL_CGROUP_PERF=y +CONFIG_KERNEL_EXT4_FS_POSIX_ACL=y +CONFIG_KERNEL_EXT4_FS_SECURITY=y +CONFIG_KERNEL_FS_POSIX_ACL=y +CONFIG_KERNEL_HUGETLBFS=y +CONFIG_KERNEL_HUGETLB_PAGE=y +CONFIG_KERNEL_MEMCG_SWAP_ENABLED=y +CONFIG_KERNEL_NET_CLS_CGROUP=y +CONFIG_KERNEL_PERF_EVENTS=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS=y +CONFIG_LIBCURL_COOKIES=y +CONFIG_LIBCURL_FILE=y +CONFIG_LIBCURL_FTP=y +CONFIG_LIBCURL_HTTP=y +CONFIG_LIBCURL_MBEDTLS=y +CONFIG_LIBCURL_NGHTTP2=y +CONFIG_LIBCURL_NO_SMB="!" +CONFIG_LIBCURL_PROXY=y +CONFIG_LIBCURL_UNIX_SOCKETS=y +CONFIG_LXC_BUSYBOX_OPTIONS=y +CONFIG_LXC_KERNEL_OPTIONS=y +CONFIG_LXC_NETWORKING=y +CONFIG_LXC_SECCOMP=y +CONFIG_OPENSSL_ENGINE_BUILTIN=y +CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO=y +CONFIG_OPENSSL_OPTIMIZE_SPEED=y +CONFIG_OPENVPN_openssl_ENABLE_FRAGMENT=y +CONFIG_OPENVPN_openssl_ENABLE_LZ4=y +CONFIG_OPENVPN_openssl_ENABLE_LZO=y +CONFIG_OPENVPN_openssl_ENABLE_PORT_SHARE=y +CONFIG_PACKAGE_NTFS-3G_HAS_PROBE=y +CONFIG_PACKAGE_adb=y +CONFIG_PACKAGE_adblock=y +CONFIG_PACKAGE_arp-scan=y +CONFIG_PACKAGE_arp-scan-database=y +CONFIG_PACKAGE_ath10k-firmware-qca6174=y +CONFIG_PACKAGE_atop=y +CONFIG_PACKAGE_attr=y +CONFIG_PACKAGE_avahi-dbus-daemon=y +CONFIG_PACKAGE_bash=y +CONFIG_PACKAGE_blkdiscard=y +CONFIG_PACKAGE_blkid=y +CONFIG_PACKAGE_block-mount=y +CONFIG_PACKAGE_blockd=y +CONFIG_PACKAGE_blockdev=y +CONFIG_PACKAGE_bluez-daemon=y +CONFIG_PACKAGE_bluez-libs=y +CONFIG_PACKAGE_bluez-tools=y +CONFIG_PACKAGE_bluez-utils=y +CONFIG_PACKAGE_bluez-utils-extra=y +CONFIG_PACKAGE_btop=y +CONFIG_PACKAGE_btrfs-progs=y +CONFIG_PACKAGE_ca-certificates=y +CONFIG_PACKAGE_ccrypt=y +CONFIG_PACKAGE_certtool=y +CONFIG_PACKAGE_cgi-io=y +CONFIG_PACKAGE_cgroup-tools=y +CONFIG_PACKAGE_cgroupfs-mount=y +CONFIG_PACKAGE_collectd=y +CONFIG_PACKAGE_collectd-mod-conntrack=y +CONFIG_PACKAGE_collectd-mod-cpu=y +CONFIG_PACKAGE_collectd-mod-cpufreq=y +CONFIG_PACKAGE_collectd-mod-interface=y +CONFIG_PACKAGE_collectd-mod-irq=y +CONFIG_PACKAGE_collectd-mod-iwinfo=y +CONFIG_PACKAGE_collectd-mod-load=y +CONFIG_PACKAGE_collectd-mod-memory=y +CONFIG_PACKAGE_collectd-mod-network=y +CONFIG_PACKAGE_collectd-mod-rrdtool=y +CONFIG_PACKAGE_collectd-mod-sensors=y +CONFIG_PACKAGE_collectd-mod-thermal=y +CONFIG_PACKAGE_containerd=y +CONFIG_PACKAGE_coreutils=y +CONFIG_PACKAGE_coreutils-sort=y +CONFIG_PACKAGE_cryptsetup=y +CONFIG_PACKAGE_cryptsetup-ssh=y +CONFIG_PACKAGE_dbus=y +CONFIG_PACKAGE_dnsmasq=m +CONFIG_PACKAGE_dnsmasq-full=y +CONFIG_PACKAGE_dnsmasq_full_auth=y +CONFIG_PACKAGE_dnsmasq_full_conntrack=y +CONFIG_PACKAGE_dnsmasq_full_dhcp=y +CONFIG_PACKAGE_dnsmasq_full_dhcpv6=y +CONFIG_PACKAGE_dnsmasq_full_dnssec=y +CONFIG_PACKAGE_dnsmasq_full_nftset=y +CONFIG_PACKAGE_dnsmasq_full_noid=y +CONFIG_PACKAGE_dnsmasq_full_tftp=y +CONFIG_PACKAGE_docker=y +CONFIG_PACKAGE_docker-compose=y +CONFIG_PACKAGE_dockerd=y +CONFIG_PACKAGE_dosfstools=y +CONFIG_PACKAGE_dropbearconvert=y +CONFIG_PACKAGE_ethtool-full=y +CONFIG_PACKAGE_exfat-fsck=y +CONFIG_PACKAGE_exfat-mkfs=y +CONFIG_PACKAGE_f2fs-tools=y +CONFIG_PACKAGE_f2fsck=y +CONFIG_PACKAGE_fdisk=y +CONFIG_PACKAGE_findfs=y +CONFIG_PACKAGE_fixparts=y +CONFIG_PACKAGE_flock=y +CONFIG_PACKAGE_fuse-utils=y +CONFIG_PACKAGE_fuse3-utils=y +CONFIG_PACKAGE_gdisk=y +CONFIG_PACKAGE_getopt=y +CONFIG_PACKAGE_glib2=y +CONFIG_PACKAGE_gnupg=y +CONFIG_PACKAGE_gnupg2=y +CONFIG_PACKAGE_gnupg2-utils=y +CONFIG_PACKAGE_gnutls-utils=y +CONFIG_PACKAGE_hdparm=y +CONFIG_PACKAGE_hostapd-common=y +CONFIG_PACKAGE_htop=y +CONFIG_PACKAGE_hwclock=y +CONFIG_PACKAGE_ip-full=y +CONFIG_PACKAGE_ip6tables-nft=y +CONFIG_PACKAGE_iperf3-ssl=y +CONFIG_PACKAGE_ipset=y +mt7921bt-firmware=y +CONFIG_PACKAGE_iptables-mod-ipopt=y +CONFIG_PACKAGE_iptables-nft=y +CONFIG_PACKAGE_irqbalance=y +# CONFIG_PACKAGE_iw is not set +CONFIG_PACKAGE_iw-full=y +CONFIG_PACKAGE_iwinfo=y +CONFIG_PACKAGE_kmod-asn1-decoder=y +CONFIG_PACKAGE_kmod-asn1-encoder=y +CONFIG_PACKAGE_kmod-ata-ahci=y +CONFIG_PACKAGE_kmod-ata-core=y +CONFIG_PACKAGE_kmod-ata-dwc=y +CONFIG_PACKAGE_kmod-ath=y +CONFIG_PACKAGE_kmod-ath10k=y +CONFIG_PACKAGE_kmod-ath9k=y +CONFIG_PACKAGE_kmod-ath9k-common=y +CONFIG_PACKAGE_kmod-atm=y +# CONFIG_PACKAGE_kmod-b43 is not set +CONFIG_PACKAGE_kmod-bluetooth=y +CONFIG_PACKAGE_kmod-br-netfilter=y +CONFIG_PACKAGE_kmod-cdrom=y +CONFIG_PACKAGE_kmod-cfg80211=y +CONFIG_PACKAGE_kmod-crypto-aead=y +CONFIG_PACKAGE_kmod-crypto-arc4=y +CONFIG_PACKAGE_kmod-crypto-authenc=y +CONFIG_PACKAGE_kmod-crypto-cbc=y +CONFIG_PACKAGE_kmod-crypto-ccm=y +CONFIG_PACKAGE_kmod-crypto-cmac=y +CONFIG_PACKAGE_kmod-crypto-crc32=y +CONFIG_PACKAGE_kmod-crypto-ctr=y +CONFIG_PACKAGE_kmod-crypto-deflate=y +CONFIG_PACKAGE_kmod-crypto-des=y +CONFIG_PACKAGE_kmod-crypto-ecb=y +CONFIG_PACKAGE_kmod-crypto-ecdh=y +CONFIG_PACKAGE_kmod-crypto-echainiv=y +CONFIG_PACKAGE_kmod-crypto-gcm=y +CONFIG_PACKAGE_kmod-crypto-gf128=y +CONFIG_PACKAGE_kmod-crypto-ghash=y +CONFIG_PACKAGE_kmod-crypto-hmac=y +CONFIG_PACKAGE_kmod-crypto-kpp=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-lib-curve25519=y +CONFIG_PACKAGE_kmod-crypto-lib-poly1305=y +CONFIG_PACKAGE_kmod-crypto-manager=y +CONFIG_PACKAGE_kmod-crypto-md5=y +CONFIG_PACKAGE_kmod-crypto-misc=y +CONFIG_PACKAGE_kmod-crypto-null=y +CONFIG_PACKAGE_kmod-crypto-rng=y +CONFIG_PACKAGE_kmod-crypto-seqiv=y +CONFIG_PACKAGE_kmod-crypto-sha1=y +CONFIG_PACKAGE_kmod-crypto-sha256=y +CONFIG_PACKAGE_kmod-crypto-sha512=y +CONFIG_PACKAGE_kmod-crypto-user=y +CONFIG_PACKAGE_kmod-crypto-xts=y +CONFIG_PACKAGE_kmod-cryptodev=y +CONFIG_PACKAGE_kmod-dax=y +CONFIG_PACKAGE_kmod-dm=y +CONFIG_PACKAGE_kmod-dummy=y +CONFIG_PACKAGE_kmod-fs-autofs4=y +CONFIG_PACKAGE_kmod-fs-btrfs=y +CONFIG_PACKAGE_kmod-fs-exfat=y +CONFIG_PACKAGE_kmod-fs-exportfs=y +CONFIG_PACKAGE_kmod-fs-ext4=y +CONFIG_PACKAGE_kmod-fs-f2fs=y +CONFIG_PACKAGE_kmod-fs-hfs=y +CONFIG_PACKAGE_kmod-fs-hfsplus=y +CONFIG_PACKAGE_kmod-fs-ksmbd=y +CONFIG_PACKAGE_kmod-fs-msdos=y +CONFIG_PACKAGE_kmod-fs-netfs=y +CONFIG_PACKAGE_kmod-fs-ntfs3=y +CONFIG_PACKAGE_kmod-fs-smbfs-common=y +CONFIG_PACKAGE_kmod-fs-squashfs=y +CONFIG_PACKAGE_kmod-fs-vfat=y +CONFIG_PACKAGE_kmod-fs-xfs=y +CONFIG_PACKAGE_kmod-fuse=y +CONFIG_PACKAGE_kmod-gre=y +CONFIG_PACKAGE_kmod-hid=y +CONFIG_PACKAGE_kmod-hwmon-gpiofan=y +CONFIG_PACKAGE_kmod-hwmon-pwmfan=y +CONFIG_PACKAGE_kmod-i2c-core=y +CONFIG_PACKAGE_kmod-ifb=y +CONFIG_PACKAGE_kmod-ikconfig=y +CONFIG_PACKAGE_kmod-input-core=y +CONFIG_PACKAGE_kmod-input-evdev=y +CONFIG_PACKAGE_kmod-ip6tables=y +CONFIG_PACKAGE_kmod-ipsec=y +CONFIG_PACKAGE_kmod-ipt-conntrack=y +CONFIG_PACKAGE_kmod-ipt-conntrack-extra=y +CONFIG_PACKAGE_kmod-ipt-core=y +CONFIG_PACKAGE_kmod-ipt-extra=y +CONFIG_PACKAGE_kmod-ipt-ipopt=y +CONFIG_PACKAGE_kmod-ipt-ipset=y +CONFIG_PACKAGE_kmod-ipt-nat=y +CONFIG_PACKAGE_kmod-ipt-nat6=y +CONFIG_PACKAGE_kmod-ipt-physdev=y +CONFIG_PACKAGE_kmod-iptunnel=y +CONFIG_PACKAGE_kmod-keys-encrypted=y +CONFIG_PACKAGE_kmod-keys-trusted=y +CONFIG_PACKAGE_kmod-l2tp=y +CONFIG_PACKAGE_kmod-lib-crc16=y +CONFIG_PACKAGE_kmod-lib-raid6=y +CONFIG_PACKAGE_kmod-lib-textsearch=y +CONFIG_PACKAGE_kmod-lib-xor=y +CONFIG_PACKAGE_kmod-lib-zlib-deflate=y +CONFIG_PACKAGE_kmod-lib-zlib-inflate=y +CONFIG_PACKAGE_kmod-lib-zstd=y +CONFIG_PACKAGE_kmod-libphy=y +CONFIG_PACKAGE_kmod-mac80211=y +CONFIG_PACKAGE_kmod-macvlan=y +CONFIG_PACKAGE_kmod-md-mod=y +CONFIG_PACKAGE_kmod-md-raid0=y +CONFIG_PACKAGE_kmod-md-raid1=y +CONFIG_PACKAGE_kmod-md-raid10=y +CONFIG_PACKAGE_kmod-mdio-devres=y +CONFIG_PACKAGE_kmod-mii=y +CONFIG_PACKAGE_kmod-mppe=y +CONFIG_PACKAGE_kmod-mt76-connac=y +CONFIG_PACKAGE_kmod-mt76-core=y +CONFIG_PACKAGE_kmod-mt76-usb=y +CONFIG_PACKAGE_kmod-mt76x02-common=y +CONFIG_PACKAGE_kmod-mt76x02-usb=y +CONFIG_PACKAGE_kmod-mt76x2-common=y +CONFIG_PACKAGE_kmod-mt76x2u=y +CONFIG_PACKAGE_kmod-mt7915-firmware=y +CONFIG_PACKAGE_kmod-mt7915e=y +CONFIG_PACKAGE_kmod-mt7916-firmware=y +CONFIG_PACKAGE_kmod-mt7921-common=y +CONFIG_PACKAGE_kmod-mt7921-firmware=y +CONFIG_PACKAGE_kmod-mt7921e=y +CONFIG_PACKAGE_kmod-mt7921u=y +CONFIG_PACKAGE_kmod-mt7922-firmware=y +CONFIG_PACKAGE_kmod-mt792x-common=y +CONFIG_PACKAGE_kmod-mt792x-usb=y +CONFIG_PACKAGE_kmod-nf-conncount=y +CONFIG_PACKAGE_kmod-nf-conntrack-netlink=y +CONFIG_PACKAGE_kmod-nf-ipt=y +CONFIG_PACKAGE_kmod-nf-ipt6=y +CONFIG_PACKAGE_kmod-nf-ipvs=y +CONFIG_PACKAGE_kmod-nf-nat6=y +CONFIG_PACKAGE_kmod-nf-nathelper=y +CONFIG_PACKAGE_kmod-nf-nathelper-extra=y +CONFIG_PACKAGE_kmod-nft-arp=y +CONFIG_PACKAGE_kmod-nft-bridge=y +CONFIG_PACKAGE_kmod-nft-compat=y +CONFIG_PACKAGE_kmod-nls-base=y +CONFIG_PACKAGE_kmod-nls-cp437=y +CONFIG_PACKAGE_kmod-nls-cp932=y +CONFIG_PACKAGE_kmod-nls-cp936=y +CONFIG_PACKAGE_kmod-nls-cp950=y +CONFIG_PACKAGE_kmod-nls-iso8859-1=y +CONFIG_PACKAGE_kmod-nls-ucs2-utils=y +CONFIG_PACKAGE_kmod-nls-utf8=y +CONFIG_PACKAGE_kmod-nvme=y +CONFIG_PACKAGE_kmod-oid-registry=y +CONFIG_PACKAGE_kmod-phy-realtek=y +CONFIG_PACKAGE_kmod-pppoa=y +CONFIG_PACKAGE_kmod-pppol2tp=y +CONFIG_PACKAGE_kmod-pptp=y +CONFIG_PACKAGE_kmod-r8169=y +CONFIG_PACKAGE_kmod-random-core=y +CONFIG_PACKAGE_kmod-regmap-core=y +CONFIG_PACKAGE_kmod-rtl8812au-ac=y +CONFIG_PACKAGE_kmod-rtl8821ae=y +CONFIG_PACKAGE_kmod-rtlwifi=y +CONFIG_PACKAGE_kmod-rtlwifi-btcoexist=y +CONFIG_PACKAGE_kmod-rtlwifi-pci=y +CONFIG_PACKAGE_kmod-rtw88=y +CONFIG_PACKAGE_kmod-rtw88-8723d=y +CONFIG_PACKAGE_kmod-rtw88-8723de=y +CONFIG_PACKAGE_kmod-rtw88-8821c=y +CONFIG_PACKAGE_kmod-rtw88-8821ce=y +CONFIG_PACKAGE_kmod-rtw88-8821cu=y +CONFIG_PACKAGE_kmod-rtw88-8822b=y +CONFIG_PACKAGE_kmod-rtw88-8822be=y +CONFIG_PACKAGE_kmod-rtw88-8822bu=y +CONFIG_PACKAGE_kmod-rtw88-8822c=y +CONFIG_PACKAGE_kmod-rtw88-8822ce=y +CONFIG_PACKAGE_kmod-rtw88-8822cu=y +CONFIG_PACKAGE_kmod-rtw88-pci=y +CONFIG_PACKAGE_kmod-rtw88-usb=y +CONFIG_PACKAGE_kmod-rtw89=y +CONFIG_PACKAGE_kmod-sched-bpf=y +CONFIG_PACKAGE_kmod-sched-cake=y +CONFIG_PACKAGE_kmod-sched-core=y +CONFIG_PACKAGE_kmod-scsi-core=y +CONFIG_PACKAGE_kmod-tpm=y +CONFIG_PACKAGE_kmod-tun=y +CONFIG_PACKAGE_kmod-udptunnel4=y +CONFIG_PACKAGE_kmod-udptunnel6=y +CONFIG_PACKAGE_kmod-usb-core=y +CONFIG_PACKAGE_kmod-usb-dwc2=y +CONFIG_PACKAGE_kmod-usb-dwc3=y +CONFIG_PACKAGE_kmod-usb-ehci=y +CONFIG_PACKAGE_kmod-usb-gadget=y +CONFIG_PACKAGE_kmod-usb-net=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ether=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ncm=y +CONFIG_PACKAGE_kmod-usb-net-ipheth=y +CONFIG_PACKAGE_kmod-usb-net-rndis=y +CONFIG_PACKAGE_kmod-usb-net-rtl8152=y +CONFIG_PACKAGE_kmod-usb-ohci=y +CONFIG_PACKAGE_kmod-usb-printer=y +CONFIG_PACKAGE_kmod-usb-roles=y +CONFIG_PACKAGE_kmod-usb-storage=y +CONFIG_PACKAGE_kmod-usb-storage-extras=y +CONFIG_PACKAGE_kmod-usb-storage-uas=y +CONFIG_PACKAGE_kmod-usb-xhci-hcd=y +CONFIG_PACKAGE_kmod-usb2=y +CONFIG_PACKAGE_kmod-usb2-pci=y +CONFIG_PACKAGE_kmod-usb3=y +CONFIG_PACKAGE_kmod-veth=y +CONFIG_PACKAGE_kmod-vxlan=y +CONFIG_PACKAGE_kmod-wireguard=y +CONFIG_PACKAGE_ksmbd-server=y +CONFIG_PACKAGE_libaio=y +CONFIG_PACKAGE_libassuan=y +CONFIG_PACKAGE_libatomic=y +CONFIG_PACKAGE_libattr=y +CONFIG_PACKAGE_libavahi-client=y +CONFIG_PACKAGE_libavahi-dbus-support=y +CONFIG_PACKAGE_libbfd=m +CONFIG_PACKAGE_libbpf=y +CONFIG_PACKAGE_libbz2=m +CONFIG_PACKAGE_libcap=y +CONFIG_PACKAGE_libcap-ng=y +CONFIG_PACKAGE_libcgroup=y +CONFIG_PACKAGE_libctf=m +CONFIG_PACKAGE_libcurl=y +CONFIG_PACKAGE_libdaemon=y +CONFIG_PACKAGE_libdbus=y +CONFIG_PACKAGE_libdevmapper=y +CONFIG_PACKAGE_libdw=m +CONFIG_PACKAGE_libelf=y +CONFIG_PACKAGE_libevdev=y +CONFIG_PACKAGE_libexpat=y +CONFIG_PACKAGE_libfdisk=y +CONFIG_PACKAGE_libffi=y +CONFIG_PACKAGE_libfuse=y +CONFIG_PACKAGE_libfuse3=y +CONFIG_PACKAGE_libgcrypt=y +CONFIG_PACKAGE_libgmp=y +CONFIG_PACKAGE_libgnutls=y +CONFIG_PACKAGE_libgpg-error=y +CONFIG_PACKAGE_libical=y +CONFIG_PACKAGE_libipset=y +CONFIG_PACKAGE_libiptext=y +CONFIG_PACKAGE_libiptext-nft=y +CONFIG_PACKAGE_libiptext6=y +CONFIG_PACKAGE_libiwinfo=y +CONFIG_PACKAGE_libiwinfo-data=y +CONFIG_PACKAGE_libkmod=y +CONFIG_PACKAGE_libksba=y +CONFIG_PACKAGE_libltdl=y +CONFIG_PACKAGE_liblua=y +CONFIG_PACKAGE_liblucihttp=y +CONFIG_PACKAGE_liblucihttp-lua=y +CONFIG_PACKAGE_liblucihttp-ucode=y +CONFIG_PACKAGE_liblxc=y +CONFIG_PACKAGE_liblz4=y +CONFIG_PACKAGE_liblzma=y +CONFIG_PACKAGE_liblzo=y +CONFIG_PACKAGE_libmount=y +CONFIG_PACKAGE_libncurses=y +CONFIG_PACKAGE_libnetfilter-conntrack=y +CONFIG_PACKAGE_libnettle=y +CONFIG_PACKAGE_libnfnetlink=y +CONFIG_PACKAGE_libnghttp2=y +CONFIG_PACKAGE_libnl-core=y +CONFIG_PACKAGE_libnl-genl=y +CONFIG_PACKAGE_libnpth=y +CONFIG_PACKAGE_libopcodes=m +CONFIG_PACKAGE_libopenssl=y +CONFIG_PACKAGE_libopenssl-conf=y +CONFIG_PACKAGE_libopenssl-legacy=y +CONFIG_PACKAGE_libparted=y +CONFIG_PACKAGE_libpcap=y +CONFIG_PACKAGE_libpci=y +CONFIG_PACKAGE_libpcre=y +CONFIG_PACKAGE_libpcre2=y +CONFIG_PACKAGE_libpopt=y +CONFIG_PACKAGE_libqrencode=y +CONFIG_PACKAGE_libreadline=y +CONFIG_PACKAGE_librrd1=y +CONFIG_PACKAGE_libseccomp=y +CONFIG_PACKAGE_libsensors=y +CONFIG_PACKAGE_libssh=y +CONFIG_PACKAGE_libstdcpp=y +CONFIG_PACKAGE_libsysfs=y +CONFIG_PACKAGE_libtasn1=y +CONFIG_PACKAGE_libtirpc=y +CONFIG_PACKAGE_libtraceevent=m +CONFIG_PACKAGE_libubus-lua=y +CONFIG_PACKAGE_libudev-zero=y +CONFIG_PACKAGE_liburing=y +CONFIG_PACKAGE_libusb-1.0=y +CONFIG_PACKAGE_libuv=y +CONFIG_PACKAGE_libwebsockets-full=y +CONFIG_PACKAGE_libxtables=y +CONFIG_PACKAGE_libzstd=y +CONFIG_PACKAGE_linux-atm=y +CONFIG_PACKAGE_lm-sensors=y +CONFIG_PACKAGE_losetup=y +CONFIG_PACKAGE_lsblk=y +CONFIG_PACKAGE_lua=y +CONFIG_PACKAGE_luci=y +CONFIG_PACKAGE_luci-app-adblock=y +CONFIG_PACKAGE_luci-app-commands=y +CONFIG_PACKAGE_luci-app-diskman=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_btrfs_progs=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_lsblk=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_ntfs_3g_utils=y +CONFIG_PACKAGE_luci-app-dockerman=y +CONFIG_PACKAGE_luci-app-filebrowser=y +CONFIG_PACKAGE_luci-app-firewall=y +CONFIG_PACKAGE_luci-app-irqbalance=y +CONFIG_PACKAGE_luci-app-ksmbd=y +CONFIG_PACKAGE_luci-app-lxc=y +CONFIG_PACKAGE_luci-app-nlbwmon=y +CONFIG_PACKAGE_luci-app-openvpn=y +CONFIG_PACKAGE_luci-app-opkg=y +CONFIG_PACKAGE_luci-app-pbr=y +CONFIG_PACKAGE_luci-app-sqm=y +CONFIG_PACKAGE_luci-app-statistics=y +CONFIG_PACKAGE_luci-app-ttyd=y +CONFIG_PACKAGE_luci-base=y +CONFIG_PACKAGE_luci-compat=y +CONFIG_PACKAGE_luci-lib-base=y +CONFIG_PACKAGE_luci-lib-docker=y +CONFIG_PACKAGE_luci-lib-ip=y +CONFIG_PACKAGE_luci-lib-ipkg=y +CONFIG_PACKAGE_luci-lib-jsonc=y +CONFIG_PACKAGE_luci-lib-nixio=y +CONFIG_PACKAGE_luci-light=y +CONFIG_PACKAGE_luci-lua-runtime=y +CONFIG_PACKAGE_luci-mod-admin-full=y +CONFIG_PACKAGE_luci-mod-network=y +CONFIG_PACKAGE_luci-mod-status=y +CONFIG_PACKAGE_luci-mod-system=y +CONFIG_PACKAGE_luci-proto-ipv6=y +CONFIG_PACKAGE_luci-proto-ppp=y +CONFIG_PACKAGE_luci-proto-wireguard=y +CONFIG_PACKAGE_luci-theme-bootstrap=y +CONFIG_PACKAGE_lvm2=y +CONFIG_PACKAGE_lxc=y +CONFIG_PACKAGE_lxc-attach=y +CONFIG_PACKAGE_lxc-auto=y +CONFIG_PACKAGE_lxc-autostart=y +CONFIG_PACKAGE_lxc-cgroup=y +CONFIG_PACKAGE_lxc-checkconfig=y +CONFIG_PACKAGE_lxc-common=y +CONFIG_PACKAGE_lxc-config=y +CONFIG_PACKAGE_lxc-configs=y +CONFIG_PACKAGE_lxc-console=y +CONFIG_PACKAGE_lxc-copy=y +CONFIG_PACKAGE_lxc-create=y +CONFIG_PACKAGE_lxc-destroy=y +CONFIG_PACKAGE_lxc-device=y +CONFIG_PACKAGE_lxc-execute=y +CONFIG_PACKAGE_lxc-freeze=y +CONFIG_PACKAGE_lxc-hooks=y +CONFIG_PACKAGE_lxc-info=y +CONFIG_PACKAGE_lxc-init=y +CONFIG_PACKAGE_lxc-ls=y +CONFIG_PACKAGE_lxc-monitor=y +CONFIG_PACKAGE_lxc-monitord=y +CONFIG_PACKAGE_lxc-snapshot=y +CONFIG_PACKAGE_lxc-start=y +CONFIG_PACKAGE_lxc-stop=y +CONFIG_PACKAGE_lxc-templates=y +CONFIG_PACKAGE_lxc-top=y +CONFIG_PACKAGE_lxc-unfreeze=y +CONFIG_PACKAGE_lxc-unprivileged=y +CONFIG_PACKAGE_lxc-unshare=y +CONFIG_PACKAGE_lxc-user-nic=y +CONFIG_PACKAGE_lxc-usernsexec=y +CONFIG_PACKAGE_lxc-wait=y +CONFIG_PACKAGE_mdadm=y +CONFIG_PACKAGE_mmc-utils=y +CONFIG_PACKAGE_mount-utils=y +CONFIG_PACKAGE_mt7921bt-firmware=y +CONFIG_PACKAGE_mt7922bt-firmware=y +CONFIG_PACKAGE_musl-fts=y +CONFIG_PACKAGE_nano-full=y +CONFIG_PACKAGE_nlbwmon=y +CONFIG_PACKAGE_ntfs-3g=y +CONFIG_PACKAGE_ntfs-3g-utils=y +CONFIG_PACKAGE_objdump=m +CONFIG_PACKAGE_openssl-util=y +CONFIG_PACKAGE_openvpn-easy-rsa=y +CONFIG_PACKAGE_openvpn-openssl=y +CONFIG_PACKAGE_parted=y +CONFIG_PACKAGE_pbr=y +CONFIG_PACKAGE_pciids=y +CONFIG_PACKAGE_pciutils=y +CONFIG_PACKAGE_perf=m +CONFIG_PACKAGE_ppp-mod-pppoa=y +CONFIG_PACKAGE_ppp-mod-pppol2tp=y +CONFIG_PACKAGE_ppp-mod-pptp=y +CONFIG_PACKAGE_pptpd=y +CONFIG_PACKAGE_qosify=y +CONFIG_PACKAGE_qrencode=y +CONFIG_PACKAGE_r8152-firmware=y +CONFIG_PACKAGE_r8169-firmware=y +CONFIG_PACKAGE_realtek-bluetooth-firmware=y +CONFIG_PACKAGE_resize2fs=y +CONFIG_PACKAGE_resolveip=y +CONFIG_PACKAGE_rpcd=y +CONFIG_PACKAGE_rpcd-mod-file=y +CONFIG_PACKAGE_rpcd-mod-iwinfo=y +CONFIG_PACKAGE_rpcd-mod-luci=y +CONFIG_PACKAGE_rpcd-mod-lxc=y +CONFIG_PACKAGE_rpcd-mod-rrdns=y +CONFIG_PACKAGE_rpcd-mod-ucode=y +CONFIG_PACKAGE_rrdtool1=y +CONFIG_PACKAGE_rtl8723bu-firmware=y +CONFIG_PACKAGE_rtl8723de-firmware=y +CONFIG_PACKAGE_rtl8821ae-firmware=y +CONFIG_PACKAGE_rtl8821ce-firmware=y +CONFIG_PACKAGE_rtl8822be-firmware=y +CONFIG_PACKAGE_rtl8822ce-firmware=y +CONFIG_PACKAGE_rtl8851be-firmware=y +CONFIG_PACKAGE_rtl8852ae-firmware=y +CONFIG_PACKAGE_rtl8852be-firmware=y +CONFIG_PACKAGE_rtl8852ce-firmware=y +CONFIG_PACKAGE_runc=y +CONFIG_PACKAGE_sfdisk=y +CONFIG_PACKAGE_shadow=y +CONFIG_PACKAGE_shadow-chage=y +CONFIG_PACKAGE_shadow-chfn=y +CONFIG_PACKAGE_shadow-chgpasswd=y +CONFIG_PACKAGE_shadow-chpasswd=y +CONFIG_PACKAGE_shadow-chsh=y +CONFIG_PACKAGE_shadow-common=y +CONFIG_PACKAGE_shadow-expiry=y +CONFIG_PACKAGE_shadow-faillog=y +CONFIG_PACKAGE_shadow-gpasswd=y +CONFIG_PACKAGE_shadow-groupadd=y +CONFIG_PACKAGE_shadow-groupdel=y +CONFIG_PACKAGE_shadow-groupmems=y +CONFIG_PACKAGE_shadow-groupmod=y +CONFIG_PACKAGE_shadow-groups=y +CONFIG_PACKAGE_shadow-grpck=y +CONFIG_PACKAGE_shadow-grpconv=y +CONFIG_PACKAGE_shadow-grpunconv=y +CONFIG_PACKAGE_shadow-lastlog=y +CONFIG_PACKAGE_shadow-login=y +CONFIG_PACKAGE_shadow-logoutd=y +CONFIG_PACKAGE_shadow-newgidmap=y +CONFIG_PACKAGE_shadow-newgrp=y +CONFIG_PACKAGE_shadow-newuidmap=y +CONFIG_PACKAGE_shadow-newusers=y +CONFIG_PACKAGE_shadow-nologin=y +CONFIG_PACKAGE_shadow-passwd=y +CONFIG_PACKAGE_shadow-pwck=y +CONFIG_PACKAGE_shadow-pwconv=y +CONFIG_PACKAGE_shadow-pwunconv=y +CONFIG_PACKAGE_shadow-su=y +CONFIG_PACKAGE_shadow-useradd=y +CONFIG_PACKAGE_shadow-userdel=y +CONFIG_PACKAGE_shadow-usermod=y +CONFIG_PACKAGE_shadow-utils=y +CONFIG_PACKAGE_shadow-vipw=y +CONFIG_PACKAGE_smartmontools=y +CONFIG_PACKAGE_smartmontools-drivedb=y +CONFIG_PACKAGE_sqm-scripts=y +CONFIG_PACKAGE_sqm-scripts-extra=y +CONFIG_PACKAGE_squashfs-tools-mksquashfs=y +CONFIG_PACKAGE_sysfsutils=y +CONFIG_PACKAGE_tc-tiny=y +CONFIG_PACKAGE_tcpdump-mini=y +CONFIG_PACKAGE_terminfo=y +CONFIG_PACKAGE_tini=y +CONFIG_PACKAGE_ttyd=y +CONFIG_PACKAGE_ucert-full=y +CONFIG_PACKAGE_ucode-mod-html=y +CONFIG_PACKAGE_ucode-mod-lua=y +CONFIG_PACKAGE_ucode-mod-math=y +CONFIG_PACKAGE_ucode-mod-nl80211=y +CONFIG_PACKAGE_ucode-mod-rtnl=y +CONFIG_PACKAGE_ucode-mod-uloop=y +CONFIG_PACKAGE_uencrypt-openssl=y +CONFIG_PACKAGE_uhttpd=y +CONFIG_PACKAGE_uhttpd-mod-ubus=y +CONFIG_PACKAGE_usb-modeswitch=y +CONFIG_PACKAGE_usbids=y +CONFIG_PACKAGE_usbutils=y +CONFIG_PACKAGE_uuidd=y +CONFIG_PACKAGE_vsftpd-tls=y +CONFIG_PACKAGE_wget-ssl=y +CONFIG_PACKAGE_wifi-scripts=y +CONFIG_PACKAGE_wireguard-tools=y +CONFIG_PACKAGE_wireless-regdb=y +CONFIG_PACKAGE_wpad-openssl=y +CONFIG_PACKAGE_wsdd2=y +CONFIG_PACKAGE_xl2tpd=y +CONFIG_PACKAGE_xtables-nft=y +CONFIG_PACKAGE_zlib=y +CONFIG_PARTED_READLINE=y +CONFIG_REPRODUCIBLE_DEBUG_INFO=y +CONFIG_SQUASHFS_TOOLS_XZ_SUPPORT=y +CONFIG_SQUASHFS_TOOLS_ZSTD_SUPPORT=y +CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_OPTIONS=y +CONFIG_TARGET_ROOTFS_PARTSIZE=512 +CONFIG_ZSTD_OPTIMIZE_O3=y +CONFIG_shadow-all=y +# CONFIG_BPF_TOOLCHAIN_BUILD_LLVM is not set +CONFIG_BPF_TOOLCHAIN_PREBUILT=y +# CONFIG_COLLECT_KERNEL_DEBUG is not set +# CONFIG_IB is not set +# CONFIG_JSON_CYCLONEDX_SBOM is not set +# CONFIG_KERNEL_WERROR is not set +# CONFIG_MAKE_TOOLCHAIN is not set +# CONFIG_OPENVPN_openssl_ENABLE_SMALL is not set +# CONFIG_SDK is not set +# CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyarm_nanopi-neo3 is not set +# CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_friendlyelec_nanopi-r6c-plus is not set +# CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_pine64_rockpro64 is not set +CONFIG_USE_LLVM_PREBUILT=y diff --git a/.github/workflows/rockchip.yaml b/.github/workflows/rockchip.yaml new file mode 100755 index 00000000000000..f4e9c362905ce7 --- /dev/null +++ b/.github/workflows/rockchip.yaml @@ -0,0 +1,95 @@ +name: Build rockchip openwrt firmware v6.6 +on: [push] + +jobs: + build: + name: Build rockchip linux v6.6 images + runs-on: ubuntu-latest + + steps: + - name: Setup Ubuntu + run: | + sudo apt update + sudo apt install -y python3 python3-pip python3-ply python3-distutils python3-pyelftools libpython3-dev swig + - name: Maximize build space + uses: AdityaGarg8/remove-unwanted-software@master + with: + remove-dotnet: 'true' + remove-android: 'true' + remove-haskell: 'true' + remove-codeql: 'true' + remove-docker-images: 'true' + remove-large-packages: 'true' + remove-cached-tools: 'true' + remove-swapfile: 'true' + - name: Checkout + uses: actions/checkout@v4 + + - name: Build + run: | + ./scripts/feeds update -a + ./scripts/feeds install -a + cd feeds/luci + + wget https://gist.githubusercontent.com/mj22226/363cefecd314e45b49d8eafff8473fcf/raw/69b47c9a972e15056f94870d76d93a5146893f99/01-diskman.patch + + git apply 01-diskman.patch + cd - + cd feeds/packages + wget https://gist.githubusercontent.com/mj22226/351f11e66f08f06e37a985719a31ddb4/raw/b35ba7a3aac1949bd6bbeaad065a0a93dc3c34f0/01-cpu.patch + wget https://gist.githubusercontent.com/mj22226/b66f5c1bd5fc7e1cb3cf2c690b5dbd5a/raw/b955e726cbb0948d932c8d6143229ad604320149/20-lxc.patch + wget https://github.com/mj22226/packages/commit/37264a2e636b790df9cb037db695505341030e98.patch + + + + git apply 01-cpu.patch + git apply 20-lxc.patch + + + + + cd - + sed -i "71s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "84s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "195s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "212s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "13s/'1'/'0'/" feeds/packages/utils/dockerd/files/etc/config/dockerd + + ./scripts/feeds update -a + ./scripts/feeds install -a -f + wget https://downloads.openwrt.org/snapshots/targets/rockchip/armv8/llvm-bpf-18.1.7.Linux-x86_64.tar.zst + tar -xvf llvm-bpf-18.1.7.Linux-x86_64.tar.zst + cp .github/workflows/rk-config .config + make defconfig + wget https://gist.githubusercontent.com/mj22226/23edc25efeb65ef69d8eb6598f4f8179/raw/29c862e3e2558852523f4e8edd5f3d0cc145067e/01-key.patch + git apply 01-key.patch + make download -j32 + rm 01-key.patch + + + mkdir -p files/www/repo + wget https://gist.githubusercontent.com/mj22226/b55f1575d30418ca2988804c70d9cc60/raw/e3b213211d937587169def6b3d91a5e34ba26f67/04.patch + git apply 04.patch + make -j$(nproc) 'IGNORE_ERRORS=n m' + cp -R bin/targets/rockchip/armv8/packages/ files/www/repo/ + rm -rf bin/targets/rockchip/armv8/*.gz + make -j$(nproc) 'IGNORE_ERRORS=n m' + rm -rf bin/targets/rockchip/armv8/packages + echo "DATE=$(date +'%Y.%m.%d')" >> $GITHUB_ENV + echo "HASH=$(git log -1 --format="%H")" >> $GITHUB_ENV + - name: Delete tag + run: gh release delete rockchip-6.6 --cleanup-tag || true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Create release + uses: ncipollo/release-action@v1.14.0 + with: + allowUpdates: true + commit: ${{ env.HASH }} + name: Rockchip v6.6 Images ${{ env.DATE }} + tag: rockchip-6.6 + replacesArtifacts: true + prerelease: false + token: "${{ secrets.GITHUB_TOKEN }}" + artifacts: bin/targets/rockchip/armv8/* + diff --git a/.github/workflows/toolchain.yml b/.github/workflows/toolchainyml similarity index 100% rename from .github/workflows/toolchain.yml rename to .github/workflows/toolchainyml diff --git a/.github/workflows/tools.yml b/.github/workflows/toolsyml similarity index 100% rename from .github/workflows/tools.yml rename to .github/workflows/toolsyml diff --git a/.github/workflows/x86_64-config b/.github/workflows/x86_64-config new file mode 100644 index 00000000000000..e2d1563c7d3be6 --- /dev/null +++ b/.github/workflows/x86_64-config @@ -0,0 +1,681 @@ +CONFIG_TARGET_x86=y +CONFIG_TARGET_x86_64=y +CONFIG_TARGET_MULTI_PROFILE=y +CONFIG_TARGET_DEVICE_x86_64_DEVICE_generic=y +CONFIG_TARGET_DEVICE_PACKAGES_x86_64_DEVICE_generic="" +CONFIG_ALL_KMODS=y +CONFIG_ALL_NONSHARED=y +CONFIG_DEVEL=y +CONFIG_BUSYBOX_CUSTOM=y +CONFIG_TARGET_PER_DEVICE_ROOTFS=y +CONFIG_AUTOREMOVE=y +CONFIG_BUILDBOT=y +CONFIG_BUILD_LOG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_GETOPT_LONG=y +CONFIG_BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ=y +CONFIG_BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS=y +CONFIG_BUSYBOX_CONFIG_GETOPT=y +CONFIG_BUSYBOX_CONFIG_MOUNTPOINT=y +CONFIG_BUSYBOX_CONFIG_UNXZ=y +CONFIG_BUSYBOX_CONFIG_XZ=y +CONFIG_CGROUPFS_MOUNT_KERNEL_CGROUPS=y +CONFIG_DOCKER_CGROUP_OPTIONS=y +CONFIG_DOCKER_CHECK_CONFIG=y +CONFIG_DOCKER_NET_ENCRYPT=y +CONFIG_DOCKER_NET_MACVLAN=y +CONFIG_DOCKER_NET_OVERLAY=y +CONFIG_DOCKER_NET_TFTP=y +CONFIG_DOCKER_OPTIONAL_FEATURES=y +CONFIG_DOCKER_STO_BTRFS=y +CONFIG_DOCKER_STO_DEVMAPPER=y +CONFIG_DOCKER_STO_EXT4=y +CONFIG_GNUTLS_ALPN=y +CONFIG_GNUTLS_ANON=y +CONFIG_GNUTLS_DTLS_SRTP=y +CONFIG_GNUTLS_HEARTBEAT=y +CONFIG_GNUTLS_OCSP=y +CONFIG_GNUTLS_PSK=y +# CONFIG_GRUB_IMAGES is not set +CONFIG_HTOP_LMSENSORS=y +# CONFIG_JSON_OVERVIEW_IMAGE_INFO is not set +CONFIG_KERNEL_BTRFS_FS_POSIX_ACL=y +CONFIG_KERNEL_BUILD_DOMAIN="buildhost" +CONFIG_KERNEL_BUILD_USER="builder" +CONFIG_KERNEL_CFQ_GROUP_IOSCHED=y +CONFIG_KERNEL_CGROUP_DEVICE=y +CONFIG_KERNEL_CGROUP_FREEZER=y +CONFIG_KERNEL_CGROUP_HUGETLB=y +CONFIG_KERNEL_CGROUP_NET_PRIO=y +CONFIG_KERNEL_CGROUP_PERF=y +CONFIG_KERNEL_EXT4_FS_POSIX_ACL=y +CONFIG_KERNEL_EXT4_FS_SECURITY=y +CONFIG_KERNEL_FS_POSIX_ACL=y +CONFIG_KERNEL_HUGETLBFS=y +CONFIG_KERNEL_HUGETLB_PAGE=y +CONFIG_KERNEL_MEMCG_SWAP_ENABLED=y +CONFIG_KERNEL_NET_CLS_CGROUP=y +CONFIG_KERNEL_PERF_EVENTS=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE=y +CONFIG_KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS=y +CONFIG_LIBCURL_COOKIES=y +CONFIG_LIBCURL_FILE=y +CONFIG_LIBCURL_FTP=y +CONFIG_LIBCURL_HTTP=y +CONFIG_LIBCURL_MBEDTLS=y +CONFIG_LIBCURL_NGHTTP2=y +CONFIG_LIBCURL_NO_SMB="!" +CONFIG_LIBCURL_PROXY=y +CONFIG_LIBCURL_UNIX_SOCKETS=y +CONFIG_LIBQMI_COLLECTION_BASIC=y +CONFIG_LIBQMI_WITH_MBIM_QMUX=y +CONFIG_LIBQMI_WITH_QRTR_GLIB=y +CONFIG_LXC_BUSYBOX_OPTIONS=y +CONFIG_LXC_KERNEL_OPTIONS=y +CONFIG_LXC_NETWORKING=y +CONFIG_LXC_SECCOMP=y +CONFIG_MODEMMANAGER_WITH_MBIM=y +CONFIG_MODEMMANAGER_WITH_QMI=y +CONFIG_MODEMMANAGER_WITH_QRTR=y +CONFIG_OPENSSL_ENGINE=y +CONFIG_OPENSSL_ENGINE_BUILTIN=y +CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO=y +CONFIG_OPENSSL_OPTIMIZE_SPEED=y +CONFIG_OPENSSL_WITH_ASM=y +CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y +CONFIG_OPENSSL_WITH_CMS=y +CONFIG_OPENSSL_WITH_DEPRECATED=y +CONFIG_OPENSSL_WITH_ERROR_MESSAGES=y +CONFIG_OPENSSL_WITH_IDEA=y +CONFIG_OPENSSL_WITH_MDC2=y +CONFIG_OPENSSL_WITH_PSK=y +CONFIG_OPENSSL_WITH_SEED=y +CONFIG_OPENSSL_WITH_SRP=y +CONFIG_OPENSSL_WITH_TLS13=y +CONFIG_OPENSSL_WITH_WHIRLPOOL=y +CONFIG_OPENVPN_openssl_ENABLE_FRAGMENT=y +CONFIG_OPENVPN_openssl_ENABLE_LZ4=y +CONFIG_OPENVPN_openssl_ENABLE_LZO=y +CONFIG_OPENVPN_openssl_ENABLE_PORT_SHARE=y +CONFIG_PACKAGE_NTFS-3G_HAS_PROBE=y +CONFIG_PACKAGE_adb=y +CONFIG_PACKAGE_adblock=y +CONFIG_PACKAGE_arp-scan=y +CONFIG_PACKAGE_arp-scan-database=y +CONFIG_PACKAGE_atop=y +CONFIG_PACKAGE_attr=y +CONFIG_PACKAGE_autopart=y +CONFIG_PACKAGE_avahi-dbus-daemon=y +CONFIG_PACKAGE_bash=y +CONFIG_PACKAGE_blkdiscard=y +CONFIG_PACKAGE_blkid=y +CONFIG_PACKAGE_block-mount=y +CONFIG_PACKAGE_blockd=y +CONFIG_PACKAGE_blockdev=y +CONFIG_PACKAGE_bluez-daemon=y +CONFIG_PACKAGE_bluez-libs=y +CONFIG_PACKAGE_bluez-tools=y +CONFIG_PACKAGE_bluez-utils=y +CONFIG_PACKAGE_bluez-utils-extra=y +CONFIG_PACKAGE_btop=y +CONFIG_PACKAGE_btrfs-progs=y +CONFIG_PACKAGE_ca-certificates=y +CONFIG_PACKAGE_ccrypt=y +CONFIG_PACKAGE_certtool=y +CONFIG_PACKAGE_cfdisk=y +CONFIG_PACKAGE_cgdisk=y +CONFIG_PACKAGE_cgi-io=y +CONFIG_PACKAGE_cgroup-tools=y +CONFIG_PACKAGE_cgroupfs-mount=y +CONFIG_PACKAGE_collectd=y +CONFIG_PACKAGE_collectd-mod-conntrack=y +CONFIG_PACKAGE_collectd-mod-cpu=y +CONFIG_PACKAGE_collectd-mod-cpufreq=y +CONFIG_PACKAGE_collectd-mod-interface=y +CONFIG_PACKAGE_collectd-mod-irq=y +CONFIG_PACKAGE_collectd-mod-iwinfo=y +CONFIG_PACKAGE_collectd-mod-load=y +CONFIG_PACKAGE_collectd-mod-memory=y +CONFIG_PACKAGE_collectd-mod-network=y +CONFIG_PACKAGE_collectd-mod-rrdtool=y +CONFIG_PACKAGE_collectd-mod-sensors=y +CONFIG_PACKAGE_collectd-mod-thermal=y +CONFIG_PACKAGE_containerd=y +CONFIG_PACKAGE_coreutils=y +CONFIG_PACKAGE_coreutils-sort=y +CONFIG_PACKAGE_cryptsetup=y +CONFIG_PACKAGE_dbus=y +CONFIG_PACKAGE_dnsmasq=m +CONFIG_PACKAGE_dnsmasq-full=y +CONFIG_PACKAGE_dnsmasq_full_auth=y +CONFIG_PACKAGE_dnsmasq_full_conntrack=y +CONFIG_PACKAGE_dnsmasq_full_dhcp=y +CONFIG_PACKAGE_dnsmasq_full_dhcpv6=y +CONFIG_PACKAGE_dnsmasq_full_dnssec=y +CONFIG_PACKAGE_dnsmasq_full_nftset=y +CONFIG_PACKAGE_dnsmasq_full_noid=y +CONFIG_PACKAGE_dnsmasq_full_tftp=y +CONFIG_PACKAGE_docker=y +CONFIG_PACKAGE_docker-compose=y +CONFIG_PACKAGE_dockerd=y +CONFIG_PACKAGE_dosfstools=y +CONFIG_PACKAGE_dumpe2fs=y +CONFIG_PACKAGE_e4crypt=y +CONFIG_PACKAGE_eject=y +CONFIG_PACKAGE_exfat-fsck=y +CONFIG_PACKAGE_exfat-mkfs=y +CONFIG_PACKAGE_f2fs-tools=y +CONFIG_PACKAGE_f2fsck=y +CONFIG_PACKAGE_fatresize=y +CONFIG_PACKAGE_fdisk=y +CONFIG_PACKAGE_findfs=y +CONFIG_PACKAGE_fixparts=y +CONFIG_PACKAGE_flock=y +CONFIG_PACKAGE_fuse3-utils=y +CONFIG_PACKAGE_gdisk=y +CONFIG_PACKAGE_getopt=y +CONFIG_PACKAGE_glib2=y +CONFIG_PACKAGE_gnu-efi=y +CONFIG_PACKAGE_gnu-efi-programs=y +CONFIG_PACKAGE_gnupg=y +CONFIG_PACKAGE_gnupg-utils=y +CONFIG_PACKAGE_gnupg2=y +CONFIG_PACKAGE_gnupg2-utils=y +CONFIG_PACKAGE_gnutls-utils=y +CONFIG_PACKAGE_hdparm=y +CONFIG_PACKAGE_hostapd-common=y +CONFIG_PACKAGE_htop=y +CONFIG_PACKAGE_hwclock=y +CONFIG_PACKAGE_ip-full=y +CONFIG_PACKAGE_ip6tables-nft=y +CONFIG_PACKAGE_iperf3-ssl=y + +CONFIG_PACKAGE_iptables-mod-ipopt=y +CONFIG_PACKAGE_iptables-nft=y +CONFIG_PACKAGE_irqbalance=y +# CONFIG_PACKAGE_iw is not set +CONFIG_PACKAGE_iw-full=y +CONFIG_PACKAGE_iwinfo=y +CONFIG_PACKAGE_iwlwifi-firmware-ax200=y +CONFIG_PACKAGE_iwlwifi-firmware-ax210=y +CONFIG_PACKAGE_iwlwifi-firmware-iwl9000=y +CONFIG_PACKAGE_iwlwifi-firmware-iwl9260=y +CONFIG_PACKAGE_kmod-asn1-decoder=y +CONFIG_PACKAGE_kmod-asn1-encoder=y +CONFIG_PACKAGE_kmod-ata-ahci=y +CONFIG_PACKAGE_kmod-ata-artop=y +CONFIG_PACKAGE_kmod-ata-core=y +CONFIG_PACKAGE_kmod-ata-dwc=y +CONFIG_PACKAGE_kmod-bluetooth=y +CONFIG_PACKAGE_kmod-br-netfilter=y +CONFIG_PACKAGE_kmod-cfg80211=y +CONFIG_PACKAGE_kmod-crypto-aead=y +CONFIG_PACKAGE_kmod-crypto-arc4=y +CONFIG_PACKAGE_kmod-crypto-authenc=y +CONFIG_PACKAGE_kmod-crypto-cbc=y +CONFIG_PACKAGE_kmod-crypto-ccm=y +CONFIG_PACKAGE_kmod-crypto-cmac=y +CONFIG_PACKAGE_kmod-crypto-crc32=y +CONFIG_PACKAGE_kmod-crypto-ctr=y +CONFIG_PACKAGE_kmod-crypto-deflate=y +CONFIG_PACKAGE_kmod-crypto-des=y +CONFIG_PACKAGE_kmod-crypto-ecb=y +CONFIG_PACKAGE_kmod-crypto-ecdh=y +CONFIG_PACKAGE_kmod-crypto-echainiv=y +CONFIG_PACKAGE_kmod-crypto-gcm=y +CONFIG_PACKAGE_kmod-crypto-geniv=y +CONFIG_PACKAGE_kmod-crypto-gf128=y +CONFIG_PACKAGE_kmod-crypto-ghash=y +CONFIG_PACKAGE_kmod-crypto-hmac=y +CONFIG_PACKAGE_kmod-crypto-kpp=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20=y +CONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y +CONFIG_PACKAGE_kmod-crypto-lib-curve25519=y +CONFIG_PACKAGE_kmod-crypto-lib-poly1305=y +CONFIG_PACKAGE_kmod-crypto-manager=y +CONFIG_PACKAGE_kmod-crypto-md5=y +CONFIG_PACKAGE_kmod-crypto-null=y +CONFIG_PACKAGE_kmod-crypto-rng=y +CONFIG_PACKAGE_kmod-crypto-seqiv=y +CONFIG_PACKAGE_kmod-crypto-sha1=y +CONFIG_PACKAGE_kmod-crypto-sha256=y +CONFIG_PACKAGE_kmod-crypto-sha3=y +CONFIG_PACKAGE_kmod-crypto-sha512=y +CONFIG_PACKAGE_kmod-crypto-user=y +CONFIG_PACKAGE_kmod-cryptodev=y +CONFIG_PACKAGE_kmod-dax=y +CONFIG_PACKAGE_kmod-dm=y +# CONFIG_PACKAGE_kmod-drm-amdgpu is not set +# CONFIG_PACKAGE_kmod-drm-display-helper is not set +# CONFIG_PACKAGE_kmod-drm-radeon is not set +# CONFIG_PACKAGE_kmod-drm-ttm is not set +CONFIG_PACKAGE_kmod-dummy=y +CONFIG_PACKAGE_kmod-fs-autofs4=y +CONFIG_PACKAGE_kmod-fs-btrfs=y +CONFIG_PACKAGE_kmod-fs-exfat=y +CONFIG_PACKAGE_kmod-fs-ext4=y +CONFIG_PACKAGE_kmod-fs-f2fs=y +CONFIG_PACKAGE_kmod-fs-ksmbd=y +CONFIG_PACKAGE_kmod-fs-msdos=y +CONFIG_PACKAGE_kmod-fs-netfs=y +CONFIG_PACKAGE_kmod-fs-ntfs3=y +CONFIG_PACKAGE_kmod-fs-smbfs-common=y +CONFIG_PACKAGE_kmod-fs-squashfs=y +CONFIG_PACKAGE_kmod-fuse=y +CONFIG_PACKAGE_kmod-gre=y +CONFIG_PACKAGE_kmod-hid=y +CONFIG_PACKAGE_kmod-hwmon-core=y +CONFIG_PACKAGE_kmod-ifb=y +CONFIG_PACKAGE_kmod-ikconfig=y +CONFIG_PACKAGE_kmod-input-evdev=y +CONFIG_PACKAGE_kmod-ip6tables=y +CONFIG_PACKAGE_kmod-ipsec=y +CONFIG_PACKAGE_kmod-ipt-conntrack=y +CONFIG_PACKAGE_kmod-ipt-core=y +CONFIG_PACKAGE_kmod-ipt-extra=y +CONFIG_PACKAGE_kmod-ipt-ipopt=y +CONFIG_PACKAGE_kmod-ipt-nat=y +CONFIG_PACKAGE_kmod-ipt-nat6=y +CONFIG_PACKAGE_kmod-ipt-physdev=y +CONFIG_PACKAGE_kmod-iptunnel=y +CONFIG_PACKAGE_kmod-iwlwifi=y +CONFIG_PACKAGE_kmod-keys-encrypted=y +CONFIG_PACKAGE_kmod-keys-trusted=y +CONFIG_PACKAGE_kmod-l2tp=y +CONFIG_PACKAGE_kmod-lib-crc16=y +CONFIG_PACKAGE_kmod-lib-raid6=y +CONFIG_PACKAGE_kmod-lib-textsearch=y +CONFIG_PACKAGE_kmod-lib-xor=y +CONFIG_PACKAGE_kmod-lib-zlib-deflate=y +CONFIG_PACKAGE_kmod-lib-zlib-inflate=y +CONFIG_PACKAGE_kmod-lib-zstd=y +CONFIG_PACKAGE_kmod-mac80211=y +CONFIG_PACKAGE_kmod-macvlan=y +CONFIG_PACKAGE_kmod-md-mod=y +CONFIG_PACKAGE_kmod-md-raid0=y +CONFIG_PACKAGE_kmod-md-raid1=y +CONFIG_PACKAGE_kmod-md-raid10=y +CONFIG_PACKAGE_kmod-mii=y +CONFIG_PACKAGE_kmod-mppe=y +CONFIG_PACKAGE_kmod-mt76-connac=y +CONFIG_PACKAGE_kmod-mt76-core=y +CONFIG_PACKAGE_kmod-mt76-usb=y +CONFIG_PACKAGE_kmod-mt76x02-common=y +CONFIG_PACKAGE_kmod-mt76x02-usb=y +CONFIG_PACKAGE_kmod-mt76x2-common=y +CONFIG_PACKAGE_kmod-mt76x2u=y +CONFIG_PACKAGE_kmod-mt7915-firmware=y +CONFIG_PACKAGE_kmod-mt7915e=y +CONFIG_PACKAGE_kmod-mt7916-firmware=y +CONFIG_PACKAGE_kmod-mt7921-common=y +CONFIG_PACKAGE_kmod-mt7921-firmware=y +CONFIG_PACKAGE_kmod-mt7921e=y +CONFIG_PACKAGE_kmod-mt7921u=y +CONFIG_PACKAGE_kmod-mt7922-firmware=y +CONFIG_PACKAGE_kmod-mt792x-common=y +CONFIG_PACKAGE_kmod-mt792x-usb=y +CONFIG_PACKAGE_kmod-nf-conntrack-netlink=y +CONFIG_PACKAGE_kmod-nf-ipt=y +CONFIG_PACKAGE_kmod-nf-ipt6=y +CONFIG_PACKAGE_kmod-nf-ipvs=y +CONFIG_PACKAGE_kmod-nf-nat6=y +CONFIG_PACKAGE_kmod-nf-nathelper=y +CONFIG_PACKAGE_kmod-nf-nathelper-extra=y +CONFIG_PACKAGE_kmod-nft-compat=y +CONFIG_PACKAGE_kmod-nls-cp932=y +CONFIG_PACKAGE_kmod-nls-cp936=y +CONFIG_PACKAGE_kmod-nls-cp950=y +CONFIG_PACKAGE_kmod-nls-ucs2-utils=y +CONFIG_PACKAGE_kmod-nvme=y +CONFIG_PACKAGE_kmod-oid-registry=y +CONFIG_PACKAGE_kmod-pppol2tp=y +CONFIG_PACKAGE_kmod-pps=y +CONFIG_PACKAGE_kmod-pptp=y +CONFIG_PACKAGE_kmod-ptp=y +CONFIG_PACKAGE_kmod-random-core=y +CONFIG_PACKAGE_kmod-regmap-core=y +CONFIG_PACKAGE_kmod-rtl8812au-ac=y +CONFIG_PACKAGE_kmod-rtw88=y +CONFIG_PACKAGE_kmod-rtw88-8723d=y +CONFIG_PACKAGE_kmod-rtw88-8723de=y +CONFIG_PACKAGE_kmod-rtw88-8821c=y +CONFIG_PACKAGE_kmod-rtw88-8821ce=y +CONFIG_PACKAGE_kmod-rtw88-8821cu=y +CONFIG_PACKAGE_kmod-rtw88-8822b=y +CONFIG_PACKAGE_kmod-rtw88-8822be=y +CONFIG_PACKAGE_kmod-rtw88-8822bu=y +CONFIG_PACKAGE_kmod-rtw88-8822c=y +CONFIG_PACKAGE_kmod-rtw88-8822ce=y +CONFIG_PACKAGE_kmod-rtw88-pci=y +CONFIG_PACKAGE_kmod-rtw88-usb=y +CONFIG_PACKAGE_kmod-rtw89=y +CONFIG_PACKAGE_kmod-sched-cake=y +CONFIG_PACKAGE_kmod-sched-core=y +CONFIG_PACKAGE_kmod-scsi-core=y +CONFIG_PACKAGE_kmod-thermal=y +CONFIG_PACKAGE_kmod-tpm=y +CONFIG_PACKAGE_kmod-tun=y +CONFIG_PACKAGE_kmod-udptunnel4=y +CONFIG_PACKAGE_kmod-udptunnel6=y +CONFIG_PACKAGE_kmod-usb-core=y +CONFIG_PACKAGE_kmod-usb-net=y +CONFIG_PACKAGE_kmod-usb-net-aqc111=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ether=y +CONFIG_PACKAGE_kmod-usb-net-cdc-mbim=y +CONFIG_PACKAGE_kmod-usb-net-cdc-ncm=y +CONFIG_PACKAGE_kmod-usb-net-ipheth=y +CONFIG_PACKAGE_kmod-usb-net-qmi-wwan=y +CONFIG_PACKAGE_kmod-usb-net-rtl8152=y +CONFIG_PACKAGE_kmod-usb-storage=y +CONFIG_PACKAGE_kmod-usb-storage-extras=y +CONFIG_PACKAGE_kmod-usb-storage-uas=y +CONFIG_PACKAGE_kmod-usb-uhci=y +CONFIG_PACKAGE_kmod-usb-wdm=y +CONFIG_PACKAGE_kmod-usb-xhci-hcd=y +CONFIG_PACKAGE_kmod-usb3=y +CONFIG_PACKAGE_kmod-veth=y +CONFIG_PACKAGE_kmod-vxlan=y +CONFIG_PACKAGE_kmod-wireguard=y +CONFIG_PACKAGE_ksmbd-server=y +CONFIG_PACKAGE_libaio=y +CONFIG_PACKAGE_libassuan=y +CONFIG_PACKAGE_libatomic=y +CONFIG_PACKAGE_libattr=y +CONFIG_PACKAGE_libavahi-client=y +CONFIG_PACKAGE_libavahi-dbus-support=y +CONFIG_PACKAGE_libbfd=m +CONFIG_PACKAGE_libbpf=y +CONFIG_PACKAGE_libbz2=m +CONFIG_PACKAGE_libcap=y +CONFIG_PACKAGE_libcap-ng=y +CONFIG_PACKAGE_libcgroup=y +CONFIG_PACKAGE_libctf=m +CONFIG_PACKAGE_libcurl=y +CONFIG_PACKAGE_libdaemon=y +CONFIG_PACKAGE_libdbus=y +CONFIG_PACKAGE_libdevmapper=y +CONFIG_PACKAGE_libdw=m +CONFIG_PACKAGE_libelf=y +CONFIG_PACKAGE_libevdev=y +CONFIG_PACKAGE_libexpat=y +CONFIG_PACKAGE_libfdisk=y +CONFIG_PACKAGE_libffi=y +CONFIG_PACKAGE_libfuse3=y +CONFIG_PACKAGE_libgcrypt=y +CONFIG_PACKAGE_libgmp=y +CONFIG_PACKAGE_libgnutls=y +CONFIG_PACKAGE_libgpg-error=y +CONFIG_PACKAGE_libical=y +CONFIG_PACKAGE_libiptext=y +CONFIG_PACKAGE_libiptext-nft=y +CONFIG_PACKAGE_libiptext6=y +CONFIG_PACKAGE_libiwinfo=y +CONFIG_PACKAGE_libiwinfo-data=y +CONFIG_PACKAGE_libkmod=y +CONFIG_PACKAGE_libksba=y +CONFIG_PACKAGE_libltdl=y +CONFIG_PACKAGE_liblua=y +CONFIG_PACKAGE_liblucihttp=y +CONFIG_PACKAGE_liblucihttp-lua=y +CONFIG_PACKAGE_liblucihttp-ucode=y +CONFIG_PACKAGE_liblxc=y +CONFIG_PACKAGE_liblz4=y +CONFIG_PACKAGE_liblzma=y +CONFIG_PACKAGE_liblzo=y +CONFIG_PACKAGE_libmbim=y +CONFIG_PACKAGE_libmount=y +CONFIG_PACKAGE_libncurses=y +CONFIG_PACKAGE_libnetfilter-conntrack=y +CONFIG_PACKAGE_libnettle=y +CONFIG_PACKAGE_libnfnetlink=y +CONFIG_PACKAGE_libnghttp2=y +CONFIG_PACKAGE_libnl-core=y +CONFIG_PACKAGE_libnl-genl=y +CONFIG_PACKAGE_libnpth=y +CONFIG_PACKAGE_libnvme=y +CONFIG_PACKAGE_libopcodes=m +CONFIG_PACKAGE_libopenssl=y +CONFIG_PACKAGE_libopenssl-conf=y +CONFIG_PACKAGE_libopenssl-legacy=y +CONFIG_PACKAGE_libparted=y +CONFIG_PACKAGE_libpcap=y +CONFIG_PACKAGE_libpci=y +CONFIG_PACKAGE_libpcre2=y +CONFIG_PACKAGE_libpopt=y +CONFIG_PACKAGE_libqmi=y +CONFIG_PACKAGE_libqrtr-glib=y +CONFIG_PACKAGE_libreadline=y +CONFIG_PACKAGE_librrd1=y +CONFIG_PACKAGE_libseccomp=y +CONFIG_PACKAGE_libsensors=y +CONFIG_PACKAGE_libstdcpp=y +CONFIG_PACKAGE_libsysfs=y +CONFIG_PACKAGE_libtasn1=y +CONFIG_PACKAGE_libtirpc=y +CONFIG_PACKAGE_libubus-lua=y +CONFIG_PACKAGE_libudev-zero=y +CONFIG_PACKAGE_liburing=y +CONFIG_PACKAGE_libusb-1.0=y +CONFIG_PACKAGE_libuv=y +CONFIG_PACKAGE_libwebsockets-full=y +CONFIG_PACKAGE_libxtables=y +CONFIG_PACKAGE_libzstd=y +CONFIG_PACKAGE_lm-sensors=y +CONFIG_PACKAGE_losetup=y +CONFIG_PACKAGE_lsblk=y +CONFIG_PACKAGE_lscpu=y +CONFIG_PACKAGE_lua=y +CONFIG_PACKAGE_luci=y +CONFIG_PACKAGE_luci-app-adblock=y +CONFIG_PACKAGE_luci-app-commands=y +CONFIG_PACKAGE_luci-app-diskman=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_btrfs_progs=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_lsblk=y +CONFIG_PACKAGE_luci-app-diskman_INCLUDE_ntfs_3g_utils=y +CONFIG_PACKAGE_luci-app-dockerman=y +CONFIG_PACKAGE_luci-app-filebrowser=y +CONFIG_PACKAGE_luci-app-firewall=y +CONFIG_PACKAGE_luci-app-irqbalance=y +CONFIG_PACKAGE_luci-app-ksmbd=y +CONFIG_PACKAGE_luci-app-lxc=y +CONFIG_PACKAGE_luci-app-nlbwmon=y +CONFIG_PACKAGE_luci-app-openvpn=y +CONFIG_PACKAGE_luci-app-opkg=y +CONFIG_PACKAGE_luci-app-pbr=y +CONFIG_PACKAGE_luci-app-sqm=y +CONFIG_PACKAGE_luci-app-statistics=y +CONFIG_PACKAGE_luci-app-ttyd=y +CONFIG_PACKAGE_luci-base=y +CONFIG_PACKAGE_luci-compat=y +CONFIG_PACKAGE_luci-lib-base=y +CONFIG_PACKAGE_luci-lib-docker=y +CONFIG_PACKAGE_luci-lib-ip=y +CONFIG_PACKAGE_luci-lib-ipkg=y +CONFIG_PACKAGE_luci-lib-jsonc=y +CONFIG_PACKAGE_luci-lib-nixio=y +CONFIG_PACKAGE_luci-light=y +CONFIG_PACKAGE_luci-lua-runtime=y +CONFIG_PACKAGE_luci-mod-admin-full=y +CONFIG_PACKAGE_luci-mod-network=y +CONFIG_PACKAGE_luci-mod-status=y +CONFIG_PACKAGE_luci-mod-system=y +CONFIG_PACKAGE_luci-proto-ipv6=y +CONFIG_PACKAGE_luci-proto-mbim=y +CONFIG_PACKAGE_luci-proto-modemmanager=y +CONFIG_PACKAGE_luci-proto-ppp=y +CONFIG_PACKAGE_luci-proto-wireguard=y +CONFIG_PACKAGE_luci-theme-bootstrap=y +CONFIG_PACKAGE_lvm2=y +CONFIG_PACKAGE_lxc=y +CONFIG_PACKAGE_lxc-attach=y +CONFIG_PACKAGE_lxc-auto=y +CONFIG_PACKAGE_lxc-autostart=y +CONFIG_PACKAGE_lxc-cgroup=y +CONFIG_PACKAGE_lxc-checkconfig=y +CONFIG_PACKAGE_lxc-common=y +CONFIG_PACKAGE_lxc-config=y +CONFIG_PACKAGE_lxc-configs=y +CONFIG_PACKAGE_lxc-console=y +CONFIG_PACKAGE_lxc-copy=y +CONFIG_PACKAGE_lxc-create=y +CONFIG_PACKAGE_lxc-destroy=y +CONFIG_PACKAGE_lxc-device=y +CONFIG_PACKAGE_lxc-execute=y +CONFIG_PACKAGE_lxc-freeze=y +CONFIG_PACKAGE_lxc-hooks=y +CONFIG_PACKAGE_lxc-info=y +CONFIG_PACKAGE_lxc-init=y +CONFIG_PACKAGE_lxc-ls=y +CONFIG_PACKAGE_lxc-monitor=y +CONFIG_PACKAGE_lxc-monitord=y +CONFIG_PACKAGE_lxc-snapshot=y +CONFIG_PACKAGE_lxc-start=y +CONFIG_PACKAGE_lxc-stop=y +CONFIG_PACKAGE_lxc-templates=y +CONFIG_PACKAGE_lxc-top=y +CONFIG_PACKAGE_lxc-unfreeze=y +CONFIG_PACKAGE_lxc-unprivileged=y +CONFIG_PACKAGE_lxc-unshare=y +CONFIG_PACKAGE_lxc-user-nic=y +CONFIG_PACKAGE_lxc-usernsexec=y +CONFIG_PACKAGE_lxc-wait=y +CONFIG_PACKAGE_mdadm=y +CONFIG_PACKAGE_mkhfs=y +CONFIG_PACKAGE_modemmanager=y +CONFIG_PACKAGE_mount-utils=y +CONFIG_PACKAGE_musl-fts=y +CONFIG_PACKAGE_nano=y +CONFIG_PACKAGE_nlbwmon=y +CONFIG_PACKAGE_ntfs-3g=y +CONFIG_PACKAGE_ntfs-3g-utils=y +CONFIG_PACKAGE_nvme-cli=y +CONFIG_PACKAGE_objdump=m +CONFIG_PACKAGE_openssl-util=y +CONFIG_PACKAGE_openvpn-easy-rsa=y +CONFIG_PACKAGE_openvpn-openssl=y +CONFIG_PACKAGE_parted=y +CONFIG_PACKAGE_pbr=y +CONFIG_PACKAGE_pciids=y +CONFIG_PACKAGE_pciutils=y +CONFIG_PACKAGE_perf=m +CONFIG_PACKAGE_ppp-mod-pppol2tp=y +CONFIG_PACKAGE_ppp-mod-pptp=y +CONFIG_PACKAGE_r8152-firmware=y +CONFIG_PACKAGE_resize2fs=y +CONFIG_PACKAGE_resolveip=y +CONFIG_PACKAGE_rpcd=y +CONFIG_PACKAGE_rpcd-mod-file=y +CONFIG_PACKAGE_rpcd-mod-iwinfo=y +CONFIG_PACKAGE_rpcd-mod-luci=y +CONFIG_PACKAGE_rpcd-mod-lxc=y +CONFIG_PACKAGE_rpcd-mod-rrdns=y +CONFIG_PACKAGE_rpcd-mod-ucode=y +CONFIG_PACKAGE_rrdtool1=y +CONFIG_PACKAGE_rtl8723de-firmware=y +CONFIG_PACKAGE_rtl8821ce-firmware=y +CONFIG_PACKAGE_rtl8822be-firmware=y +CONFIG_PACKAGE_rtl8822ce-firmware=y +CONFIG_PACKAGE_rtl8851be-firmware=y +CONFIG_PACKAGE_rtl8852ae-firmware=y +CONFIG_PACKAGE_rtl8852be-firmware=y +CONFIG_PACKAGE_rtl8852ce-firmware=y +CONFIG_PACKAGE_runc=y +CONFIG_PACKAGE_sfdisk=y +CONFIG_PACKAGE_sgdisk=y +CONFIG_PACKAGE_shadow=y +CONFIG_PACKAGE_shadow-chage=y +CONFIG_PACKAGE_shadow-chfn=y +CONFIG_PACKAGE_shadow-chgpasswd=y +CONFIG_PACKAGE_shadow-chpasswd=y +CONFIG_PACKAGE_shadow-chsh=y +CONFIG_PACKAGE_shadow-common=y +CONFIG_PACKAGE_shadow-expiry=y +CONFIG_PACKAGE_shadow-faillog=y +CONFIG_PACKAGE_shadow-gpasswd=y +CONFIG_PACKAGE_shadow-groupadd=y +CONFIG_PACKAGE_shadow-groupdel=y +CONFIG_PACKAGE_shadow-groupmems=y +CONFIG_PACKAGE_shadow-groupmod=y +CONFIG_PACKAGE_shadow-groups=y +CONFIG_PACKAGE_shadow-grpck=y +CONFIG_PACKAGE_shadow-grpconv=y +CONFIG_PACKAGE_shadow-grpunconv=y +CONFIG_PACKAGE_shadow-lastlog=y +CONFIG_PACKAGE_shadow-login=y +CONFIG_PACKAGE_shadow-logoutd=y +CONFIG_PACKAGE_shadow-newgidmap=y +CONFIG_PACKAGE_shadow-newgrp=y +CONFIG_PACKAGE_shadow-newuidmap=y +CONFIG_PACKAGE_shadow-newusers=y +CONFIG_PACKAGE_shadow-nologin=y +CONFIG_PACKAGE_shadow-passwd=y +CONFIG_PACKAGE_shadow-pwck=y +CONFIG_PACKAGE_shadow-pwconv=y +CONFIG_PACKAGE_shadow-pwunconv=y +CONFIG_PACKAGE_shadow-su=y +CONFIG_PACKAGE_shadow-useradd=y +CONFIG_PACKAGE_shadow-userdel=y +CONFIG_PACKAGE_shadow-usermod=y +CONFIG_PACKAGE_shadow-utils=y +CONFIG_PACKAGE_shadow-vipw=y +CONFIG_PACKAGE_smartmontools=y +CONFIG_PACKAGE_smartmontools-drivedb=y +CONFIG_PACKAGE_sqm-scripts=y +CONFIG_PACKAGE_sqm-scripts-extra=y +CONFIG_PACKAGE_squashfs-tools-mksquashfs=y +CONFIG_PACKAGE_squashfs-tools-unsquashfs=y +CONFIG_PACKAGE_sysfsutils=y +CONFIG_PACKAGE_tc-tiny=y +CONFIG_PACKAGE_tcpdump-mini=y +CONFIG_PACKAGE_terminfo=y +CONFIG_PACKAGE_tini=y +CONFIG_PACKAGE_tree=y +CONFIG_PACKAGE_ttyd=y +CONFIG_PACKAGE_ucode-mod-html=y +CONFIG_PACKAGE_ucode-mod-lua=y +CONFIG_PACKAGE_ucode-mod-math=y +CONFIG_PACKAGE_ucode-mod-nl80211=y +CONFIG_PACKAGE_ucode-mod-rtnl=y +CONFIG_PACKAGE_ucode-mod-uloop=y +CONFIG_PACKAGE_uhttpd=y +CONFIG_PACKAGE_uhttpd-mod-ubus=y +CONFIG_PACKAGE_umbim=y +CONFIG_PACKAGE_usb-modeswitch=y +CONFIG_PACKAGE_usbids=y +CONFIG_PACKAGE_usbutils=y +CONFIG_PACKAGE_vsftpd-tls=y +CONFIG_PACKAGE_wget-ssl=y +CONFIG_PACKAGE_wifi-scripts=y +CONFIG_PACKAGE_wipefs=y +CONFIG_PACKAGE_wireguard-tools=y +CONFIG_PACKAGE_wireless-regdb=y +CONFIG_PACKAGE_wireless-tools=y +CONFIG_PACKAGE_wpad-openssl=y +CONFIG_PACKAGE_wsdd2=y +CONFIG_PACKAGE_wwan=y +CONFIG_PACKAGE_xl2tpd=y +CONFIG_PACKAGE_xtables-nft=y +CONFIG_PACKAGE_zlib=y +CONFIG_PARTED_LVM2=y +CONFIG_PARTED_READLINE=y +CONFIG_PCRE2_JIT_ENABLED=y +CONFIG_SQUASHFS_TOOLS_XZ_SUPPORT=y +CONFIG_SQUASHFS_TOOLS_ZSTD_SUPPORT=y +CONFIG_TARGET_ALL_PROFILES=y +CONFIG_TARGET_OPTIONS=y +# CONFIG_TARGET_ROOTFS_TARGZ is not set +CONFIG_WPA_MSG_MIN_PRIORITY=3 +CONFIG_ZSTD_OPTIMIZE_O3=y +CONFIG_shadow-all=y +# CONFIG_BPF_TOOLCHAIN_BUILD_LLVM is not set +CONFIG_BPF_TOOLCHAIN_PREBUILT=y +# CONFIG_COLLECT_KERNEL_DEBUG is not set +# CONFIG_IB is not set +# CONFIG_JSON_CYCLONEDX_SBOM is not set +# CONFIG_KERNEL_WERROR is not set +# CONFIG_MAKE_TOOLCHAIN is not set +# CONFIG_OPENVPN_openssl_ENABLE_SMALL is not set +CONFIG_PACKAGE_amdgpu-firmware=m +CONFIG_PACKAGE_radeon-firmware=m +# CONFIG_REPRODUCIBLE_DEBUG_INFO is not set +# CONFIG_SDK is not set +CONFIG_USE_LLVM_PREBUILT=y diff --git a/.github/workflows/x86_64.yaml b/.github/workflows/x86_64.yaml new file mode 100644 index 00000000000000..820c9b71a5137a --- /dev/null +++ b/.github/workflows/x86_64.yaml @@ -0,0 +1,95 @@ +name: Build x86_64 v6.6 +on: [push] + +jobs: + build: + name: Build x86 linux v6.6 images + runs-on: ubuntu-latest + + steps: + - name: Setup Ubuntu + run: | + sudo apt update + sudo apt install -y python3 python3-pip python3-ply python3-distutils python3-pyelftools libpython3-dev swig + - name: Maximize build space + uses: easimon/maximize-build-space@master + with: + root-reserve-mb: 512 + swap-size-mb: 1024 + remove-dotnet: 'true' + overprovision-lvm: 'true' + remove-android: 'true' + remove-haskell: 'true' + remove-codeql: 'true' + remove-docker-images: 'true' + - name: Checkout + uses: actions/checkout@v4 + + - name: Build + run: | + ./scripts/feeds update -a + ./scripts/feeds install -a + cd feeds/luci + + wget https://gist.githubusercontent.com/mj22226/363cefecd314e45b49d8eafff8473fcf/raw/69b47c9a972e15056f94870d76d93a5146893f99/01-diskman.patch + + git apply 01-diskman.patch + cd - + cd feeds/packages + wget https://gist.githubusercontent.com/mj22226/351f11e66f08f06e37a985719a31ddb4/raw/b35ba7a3aac1949bd6bbeaad065a0a93dc3c34f0/01-cpu.patch + wget https://gist.githubusercontent.com/mj22226/b66f5c1bd5fc7e1cb3cf2c690b5dbd5a/raw/b955e726cbb0948d932c8d6143229ad604320149/20-lxc.patch + wget https://github.com/mj22226/packages/commit/37264a2e636b790df9cb037db695505341030e98.patch + + + + git apply 01-cpu.patch + git apply 20-lxc.patch + + + + + cd - + sed -i "71s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "84s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "195s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "212s/'0'/'1'/" feeds/luci/applications/luci-app-statistics/root/etc/config/luci_statistics + sed -i "13s/'1'/'0'/" feeds/packages/utils/dockerd/files/etc/config/dockerd + + ./scripts/feeds update -a + ./scripts/feeds install -a -f + wget https://downloads.openwrt.org/snapshots/targets/x86/64/llvm-bpf-18.1.7.Linux-x86_64.tar.zst + tar -xvf llvm-bpf-18.1.7.Linux-x86_64.tar.zst + cp .github/workflows/x86_64-config .config + make defconfig + wget https://gist.githubusercontent.com/mj22226/23edc25efeb65ef69d8eb6598f4f8179/raw/29c862e3e2558852523f4e8edd5f3d0cc145067e/01-key.patch + git apply 01-key.patch + make download -j32 + rm 01-key.patch + + + mkdir -p files/www/repo + wget https://gist.githubusercontent.com/mj22226/d464a1c7bf9802f03ad182a1a979c564/raw/c6147ceb53c2308c7272bd1b8f05a31b52603e43/86.patch + git apply 86.patch + make -j$(nproc) 'IGNORE_ERRORS=n m' + cp -R bin/targets/x86/64/packages files/www/repo/ + rm -rf bin/targets/rockchip/armv8/*.gz + make -j$(nproc) 'IGNORE_ERRORS=n m' + rm -rf bin/targets/x86/64/packages + echo "DATE=$(date +'%Y.%m.%d')" >> $GITHUB_ENV + echo "HASH=$(git log -1 --format="%H")" >> $GITHUB_ENV + - name: Delete tag + run: gh release delete x86-6.6 --cleanup-tag || true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + - name: Create release + uses: ncipollo/release-action@v1.14.0 + with: + allowUpdates: true + commit: ${{ env.HASH }} + name: x86_64 v6.6 Images ${{ env.DATE }} + tag: x86-6.6 + replacesArtifacts: true + prerelease: true + token: "${{ secrets.GITHUB_TOKEN }}" + artifacts: bin/targets/x86/64/* + diff --git a/LICENSES/LICENCE.broadcom_bcm43xx b/LICENSES/LICENCE.broadcom_bcm43xx new file mode 100644 index 00000000000000..ff26fdd72fe125 --- /dev/null +++ b/LICENSES/LICENCE.broadcom_bcm43xx @@ -0,0 +1,65 @@ +SOFTWARE LICENSE AGREEMENT + +The accompanying software in binary code form (“Software”), is licensed to you, +or, if you are accepting on behalf of an entity, the entity and its affiliates +exercising rights hereunder (“Licensee”) subject to the terms of this software +license agreement (“Agreement”), unless Licensee and Broadcom Corporation +(“Broadcom”) execute a separate written software license agreement governing +use of the Software. ANY USE, REPRODUCTION, OR DISTRIBUTION OF THE SOFTWARE +CONSTITUTES LICENSEE’S ACCEPTANCE OF THIS AGREEMENT. + +1. License. Subject to the terms and conditions of this Agreement, +Broadcom hereby grants to Licensee a limited, non-exclusive, non-transferable, +royalty-free license: (i) to use and integrate the Software with any other +software; and (ii) to reproduce and distribute the Software complete, +unmodified, and as provided by Broadcom, solely for use with Broadcom +proprietary integrated circuit product(s) sold by Broadcom with which the +Software was designed to be used, or their successors. + +2. Restrictions. Licensee shall distribute Software with a copy of this +Agreement. Licensee shall not remove, efface or obscure any copyright or +trademark notices from the Software. Reproductions of the Broadcom copyright +notice shall be included with each copy of the Software, except where such +Software is embedded in a manner not readily accessible to the end user. +Licensee shall not: (i) use, license, sell or otherwise distribute the Software +except as provided in this Agreement; (ii) attempt to modify in any way, +reverse engineer, decompile or disassemble any portion of the Software; or +(iii) use the Software or other material in violation of any applicable law or +regulation, including but not limited to any regulatory agency. This Agreement +shall automatically terminate upon Licensee’s failure to comply with any of the +terms of this Agreement. In such event, Licensee will destroy all copies of the +Software and its component parts. + +3. Ownership. The Software is licensed and not sold. Title to and +ownership of the Software, including all intellectual property rights thereto, +and any portion thereof remain with Broadcom or its licensors. Licensee hereby +covenants that it will not assert any claim that the Software created by or for +Broadcom infringe any intellectual property right owned or controlled by +Licensee. + +4. Disclaimer. THE SOFTWARE IS OFFERED “AS IS,” AND BROADCOM PROVIDES AND +GRANTS AND LICENSEE RECEIVES NO SUPPORT AND NO WARRANTIES OF ANY KIND, EXPRESS +OR IMPLIED, BY STATUTE, COMMUNICATION OR CONDUCT WITH LICENSEE, OR OTHERWISE. +BROADCOM SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A SPECIFIC PURPOSE, OR NONINFRINGEMENT CONCERNING THE SOFTWARE OR +ANY UPGRADES TO OR DOCUMENTATION FOR THE SOFTWARE. WITHOUT LIMITATION OF THE +ABOVE, BROADCOM GRANTS NO WARRANTY THAT THE SOFTWARE IS ERROR-FREE OR WILL +OPERATE WITHOUT INTERRUPTION, AND GRANTS NO WARRANTY REGARDING ITS USE OR THE +RESULTS THEREFROM INCLUDING, WITHOUT LIMITATION, ITS CORRECTNESS, ACCURACY, OR +RELIABILITY. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM +OR ANY OF ITS LICENSORS HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND ON ANY THEORY +OF LIABILITY, WHETHER FOR BREACH OF CONTRACT, TORT (INCLUDING NEGLIGENCE) OR +OTHERWISE, ARISING OUT OF THIS AGREEMENT OR USE, REPRODUCTION, OR DISTRIBUTION +OF THE SOFTWARE, INCLUDING BUT NOT LIMITED TO LOSS OF DATA AND LOSS OF PROFITS, +EVEN IF SUCH PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THESE +LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY +LIMITED REMEDY. + +5. Export Laws. LICENSEE UNDERSTANDS AND AGREES THAT THE SOFTWARE IS +SUBJECT TO UNITED STATES AND OTHER APPLICABLE EXPORT-RELATED LAWS AND +REGULATIONS AND THAT LICENSEE MAY NOT EXPORT, RE-EXPORT OR TRANSFER THE +SOFTWARE OR ANY DIRECT PRODUCT OF THE SOFTWARE EXCEPT AS PERMITTED UNDER THOSE +LAWS. WITHOUT LIMITING THE FOREGOING, EXPORT, RE-EXPORT, OR TRANSFER OF THE +SOFTWARE TO CUBA, IRAN, NORTH KOREA, SUDAN, AND SYRIA IS PROHIBITED. + diff --git a/config/Config-images.in b/config/Config-images.in index 47f3dfc0d9603f..aa3542f3f200b9 100644 --- a/config/Config-images.in +++ b/config/Config-images.in @@ -127,7 +127,6 @@ menu "Target Images" config TARGET_EXT4_JOURNAL bool "Create a journaling filesystem" depends on TARGET_ROOTFS_EXT4FS - default y help Create an ext4 filesystem with a journal. @@ -303,7 +302,7 @@ menu "Target Images" depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS default 232 if TARGET_loongarch64 default 448 if TARGET_mediatek - default 104 + default 1040 help Select the root filesystem partition size. diff --git a/feeds.conf.default b/feeds.conf.default index fc679335e0e47f..afa01cf060b14c 100644 --- a/feeds.conf.default +++ b/feeds.conf.default @@ -1,7 +1,7 @@ -src-git packages https://git.openwrt.org/feed/packages.git -src-git luci https://git.openwrt.org/project/luci.git -src-git routing https://git.openwrt.org/feed/routing.git -src-git telephony https://git.openwrt.org/feed/telephony.git +src-git packages https://github.com/openwrt/packages.git +src-git luci https://github.com/openwrt/luci.git +src-git routing https://github.com/openwrt/routing.git +src-git telephony https://github.com/openwrt/telephony.git #src-git video https://github.com/openwrt/video.git #src-git targets https://github.com/openwrt/targets.git #src-git oldpackages http://git.openwrt.org/packages.git diff --git a/include/kernel-6.6 b/include/kernel-6.6 index 24fff19d3bc93a..4c6596969da4db 100644 --- a/include/kernel-6.6 +++ b/include/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .41 -LINUX_KERNEL_HASH-6.6.41 = 9ec99c578158ab85d99b37791a76643d2ea4c3f72ecbef7b5eb6d60f3de032ef +LINUX_VERSION-6.6 = .43 +LINUX_KERNEL_HASH-6.6.43 = 0ad83b1a1a780a1aad948d55aa55ee63c50c626f2d46910b9d2180028d100a5e diff --git a/include/target.mk b/include/target.mk index d13902ad6e78ec..9e31018fe15b5c 100644 --- a/include/target.mk +++ b/include/target.mk @@ -278,6 +278,8 @@ ifeq ($(DUMP),1) CPU_TYPE ?= generic CPU_CFLAGS_generic = -mcpu=generic CPU_CFLAGS_cortex-a53 = -mcpu=cortex-a53 + CPU_CFLAGS_cortex-a55 = -mcpu=cortex-a55 + CPU_CFLAGS_cortex-a76 = -mcpu=cortex-a76 endif ifeq ($(ARCH),arc) CPU_TYPE ?= arc700 diff --git a/package/base-files/Makefile b/package/base-files/Makefile index 313bf377b492fe..f273896a0cc060 100644 --- a/package/base-files/Makefile +++ b/package/base-files/Makefile @@ -134,14 +134,12 @@ ifdef CONFIG_SIGNED_PACKAGES endef -ifndef CONFIG_BUILDBOT define Package/base-files/install-key mkdir -p $(1)/etc/opkg/keys $(CP) $(BUILD_KEY).pub $(1)/etc/opkg/keys/`$(STAGING_DIR_HOST)/bin/usign -F -p $(BUILD_KEY).pub` endef endif endif -endif ifeq ($(CONFIG_NAND_SUPPORT),) define Package/base-files/nand-support diff --git a/package/boot/arm-trusted-firmware-rockchip/Makefile b/package/boot/arm-trusted-firmware-rockchip/Makefile index 6fbcbef0a8b305..bb17fffc9b7561 100644 --- a/package/boot/arm-trusted-firmware-rockchip/Makefile +++ b/package/boot/arm-trusted-firmware-rockchip/Makefile @@ -7,66 +7,44 @@ include $(TOPDIR)/rules.mk -PKG_VERSION:=2.10 +PKG_NAME:=arm-trusted-firmware-rockchip +PKG_VERSION:=2.10.2 PKG_RELEASE:=1 -PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201 +PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz +PKG_SOURCE_URL:=https://github.com/mj22226/atf/releases/download/v$(PKG_VERSION)-1709568560/atf-v$(PKG_VERSION).tar.gz? +PKG_HASH:=d5ff131ef11c3898ed3701526cd81202528d6686c5e4c62c71dbfde8fa35368c + +PKG_LICENSE:=BSD-3-Clause +PKG_LICENSE_FILES:=license.md PKG_MAINTAINER:=Tobias Maedel -include $(INCLUDE_DIR)/kernel.mk -include $(INCLUDE_DIR)/trusted-firmware-a.mk +MAKE_PATH:=$(PKG_NAME) + include $(INCLUDE_DIR)/package.mk -define Trusted-Firmware-A/Default - NAME:=Rockchip $(1) SoCs - BUILD_TARGET:=rockchip +define Package/arm-trusted-firmware-rockchip + SECTION:=boot + CATEGORY:=Boot Loaders + TITLE:=ARM Trusted Firmware for Rockchip + DEPENDS:=@TARGET_rockchip_armv8 endef -define Trusted-Firmware-A/rk3328 - BUILD_SUBTARGET:=armv8 - PLAT=rk3328 +define Build/Prepare + $(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE) endef -define Trusted-Firmware-A/rk3399 - BUILD_SUBTARGET:=armv8 - PLAT:=rk3399 +define Build/Compile endef -TFA_TARGETS:= \ - rk3328 \ - rk3399 - -ifeq ($(BUILD_VARIANT),rk3399) - M0_GCC_NAME:=gcc-arm - M0_GCC_RELEASE:=11.2-2022.02 - M0_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi - M0_GCC_SOURCE:=$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION).tar.xz - - define Download/m0-gcc - FILE:=$(M0_GCC_SOURCE) - URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(M0_GCC_RELEASE)/binrel - ifeq ($(HOST_ARCH),aarch64) - HASH:=ef1d82e5894e3908cb7ed49c5485b5b95deefa32872f79c2b5f6f5447cabf55f - else - HASH:=8c5acd5ae567c0100245b0556941c237369f210bceb196edfe5a2e7532c60326 - endif - endef - - define Build/Prepare - $(eval $(call Download,m0-gcc)) - $(call Build/Prepare/Default) - - xzcat $(DL_DIR)/$(M0_GCC_SOURCE) | $(HOST_TAR) -C $(PKG_BUILD_DIR)/ $(TAR_OPTIONS) - endef - - TFA_MAKE_FLAGS+= \ - M0_CROSS_COMPILE=$(PKG_BUILD_DIR)/$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION)/bin/arm-none-eabi- -endif +define Build/InstallDev + $(INSTALL_DIR) -p $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/ + $(CP) $(PKG_BUILD_DIR)/rk*.bin $(STAGING_DIR_IMAGE)/ +endef -define Package/trusted-firmware-a/install - $(INSTALL_DIR) $(STAGING_DIR_IMAGE) - $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31/bl31.elf $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)_bl31.elf +define Package/arm-trusted-firmware-rockchip/install endef -$(eval $(call BuildPackage/Trusted-Firmware-A)) +$(eval $(call BuildPackage,arm-trusted-firmware-rockchip)) diff --git a/package/boot/uboot-friendlyarm/Makefile b/package/boot/uboot-friendlyarm/Makefile new file mode 100644 index 00000000000000..6df4734fadf536 --- /dev/null +++ b/package/boot/uboot-friendlyarm/Makefile @@ -0,0 +1,61 @@ +# +# Copyright (C) 2021 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=uboot-friendlyarm +PKG_SOURCE_DATE:=2021-01-05 +PKG_SOURCE_VERSION:=c5a1b04b8f35489fa3b0524996e65fd863cf9d79 +PKG_MIRROR_HASH:=bb19d56d2eeef93bc5021a6c89dc7ec1d1a542358882bd86effb81df45807d04 +PKG_RELEASE:=1 +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/friendlyarm/uboot-rockchip.git + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk + + +define U-Boot/Default + BUILD_TARGET:=rockchip + UENV:=default + HIDDEN:=1 +endef + +define U-Boot/nanopi-r4s-rk3399 + BUILD_SUBTARGET:=armv8 + NAME:=NanoPi R4S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r4s + DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3399_bl31.elf +endef + +UBOOT_TARGETS :=nanopi-r4s-rk3399 + +UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes + +UBOOT_MAKE_FLAGS += \ + BL31=$(STAGING_DIR_IMAGE)/$(ATF) + +define Build/Configure + $(call Build/Configure/U-Boot) + + $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config + echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config +endef + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img + $(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb +endef + +define Package/u-boot/install/default +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index cf650cb82a185f..0f637a8b1bc726 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,14 +5,14 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2024.07 +PKG_VERSION:=2024.04 PKG_RELEASE:=1 -PKG_HASH:=f591da9ab90ef3d6b3d173766d0ddff90c4ed7330680897486117df390d83c8f +PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a PKG_MAINTAINER:=Tobias Maedel -UBOOT_USE_BINMAN:=1 -UBOOT_USE_INTREE_DTC:=1 +# UBOOT_USE_BINMAN:=1 +# UBOOT_USE_INTREE_DTC:=1 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk @@ -24,222 +24,203 @@ define U-Boot/Default endef -# RK3308 boards - -define U-Boot/rk3308/Default - BUILD_SUBTARGET:=armv8 - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308 - ATF:=rk3308_bl31_v2.26.elf - TPL:=rk3308_ddr_589MHz_uart2_m1_v2.07.bin -endef - -define U-Boot/rock-pi-s-rk3308 - $(U-Boot/rk3308/Default) - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308-rock-pi-s - TPL:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin - NAME:=ROCK Pi S - BUILD_DEVICES:= \ - radxa_rock-pi-s -endef - # RK3328 boards -define U-Boot/rk3328/Default - BUILD_SUBTARGET:=armv8 - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3328 - ATF:=rk3328_bl31.elf -endef - -define U-Boot/nanopi-r2c-rk3328 - $(U-Boot/rk3328/Default) - NAME:=NanoPi R2C - BUILD_DEVICES:= \ - friendlyarm_nanopi-r2c -endef - -define U-Boot/nanopi-r2c-plus-rk3328 - $(U-Boot/rk3328/Default) - NAME:=NanoPi R2C Plus - BUILD_DEVICES:= \ - friendlyarm_nanopi-r2c-plus -endef - define U-Boot/nanopi-r2s-rk3328 - $(U-Boot/rk3328/Default) + BUILD_SUBTARGET:=armv8 NAME:=NanoPi R2S BUILD_DEVICES:= \ friendlyarm_nanopi-r2s -endef - -define U-Boot/orangepi-r1-plus-rk3328 - $(U-Boot/rk3328/Default) - NAME:=Orange Pi R1 Plus - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus -endef - -define U-Boot/orangepi-r1-plus-lts-rk3328 - $(U-Boot/rk3328/Default) - NAME:=Orange Pi R1 Plus LTS - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus-lts + DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3328_bl31.elf endef define U-Boot/roc-cc-rk3328 - $(U-Boot/rk3328/Default) + BUILD_SUBTARGET:=armv8 NAME:=ROC-RK3328-CC BUILD_DEVICES:= \ firefly_roc-rk3328-cc + DEPENDS:=+PACKAGE_u-boot-roc-cc-rk3328:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3328_bl31.elf endef -define U-Boot/rock64-rk3328 - $(U-Boot/rk3328/Default) - NAME:=Rock64 - BUILD_DEVICES:= \ - pine64_rock64 -endef - -define U-Boot/rock-pi-e-rk3328 - $(U-Boot/rk3328/Default) - NAME:=ROCK Pi E - BUILD_DEVICES:= \ - radxa_rock-pi-e -endef # RK3399 boards -define U-Boot/rk3399/Default - BUILD_SUBTARGET:=armv8 - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3399 - ATF:=rk3399_bl31.elf -endef - -define U-Boot/nanopc-t4-rk3399 - $(U-Boot/rk3399/Default) - NAME:=NanoPC T4 - BUILD_DEVICES:= \ - friendlyarm_nanopc-t4 -endef - -define U-Boot/nanopi-r4s-rk3399 - $(U-Boot/rk3399/Default) - NAME:=NanoPi R4S - BUILD_DEVICES:= \ - friendlyarm_nanopi-r4s \ - friendlyarm_nanopi-r4s-enterprise -endef define U-Boot/rock-pi-4-rk3399 - $(U-Boot/rk3399/Default) + BUILD_SUBTARGET:=armv8 NAME:=Rock Pi 4 BUILD_DEVICES:= \ - radxa_rock-pi-4a + radxa_rock-pi-4 + DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3399_bl31.elf endef define U-Boot/rockpro64-rk3399 - $(U-Boot/rk3399/Default) + BUILD_SUBTARGET:=armv8 NAME:=RockPro64 BUILD_DEVICES:= \ pine64_rockpro64 + DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3399_bl31.elf endef +# RK356x boards -# RK3566 boards - -define U-Boot/rk3566/Default +define U-Boot/bpi-r2-pro-rk3568 BUILD_SUBTARGET:=armv8 - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3566 - ATF:=rk3568_bl31_v1.44.elf - TPL:=rk3566_ddr_1056MHz_v1.21.bin + NAME:=BPI-R2-PRO + BUILD_DEVICES:= \ + rockchip_bpi-r2-pro + DEPENDS:=+PACKAGE_u-boot-bpi-r2-pro-rk3568:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3568_bl31.elf + DDR_3568:=$(1) endef -define U-Boot/radxa-cm3-io-rk3566 - $(U-Boot/rk3566/Default) - NAME:=CM3 IO +define U-Boot/quartz64-a-rk3566 + BUILD_SUBTARGET:=armv8 + NAME:=QUARTZ64 BUILD_DEVICES:= \ - radxa_cm3-io + pine64_quartz64-a + DEPENDS:=+PACKAGE_u-boot-quartz64-a-rk3566:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3568_bl31.elf + DDR_3568:=$(1) endef -# RK3568 boards +define U-Boot/nanopi-r5c-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=NANOPI-R5C + BUILD_DEVICES:= \ + friendlyelec_nanopi-r5c + DEPENDS:=+PACKAGE_u-boot-nanopi-r5c-rk3568:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3568_bl31.elf + DDR_3568:=$(1) +endef -define U-Boot/rk3568/Default +define U-Boot/nanopi-r5s-rk3568 BUILD_SUBTARGET:=armv8 - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568 - ATF:=rk3568_bl31_v1.44.elf - TPL:=rk3568_ddr_1560MHz_v1.21.bin + NAME:=NANOPI-R5S + BUILD_DEVICES:= \ + friendlyelec_nanopi-r5s + DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3568_bl31.elf + DDR_3568:=$(1) endef -define U-Boot/bpi-r2-pro-rk3568 - $(U-Boot/rk3568/Default) - NAME:=Bananapi-R2 Pro +define U-Boot/rock-3a-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=ROCK-3A BUILD_DEVICES:= \ - sinovoip_bpi-r2-pro + radxa_rock-3a + DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3568_bl31.elf + DDR_3568:=$(1) endef -define U-Boot/nanopi-r5c-rk3568 - $(U-Boot/rk3568/Default) - NAME:=NanoPi R5C +# RK3588 boards + +define U-Boot/nanopi-r6c-rk3588 + BUILD_SUBTARGET:=armv8 + NAME:=NANOPI-R6C BUILD_DEVICES:= \ - friendlyarm_nanopi-r5c + friendlyelec_nanopi-r6c + DEPENDS:=+PACKAGE_u-boot-nanopi-r6c-rk3588:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3588_bl31.elf + DDR_3588:=$(1) + endef -define U-Boot/nanopi-r5s-rk3568 - $(U-Boot/rk3568/Default) - NAME:=NanoPi R5S +define U-Boot/nanopi-r6s-rk3588 + BUILD_SUBTARGET:=armv8 + NAME:=NANOPI-R6C BUILD_DEVICES:= \ - friendlyarm_nanopi-r5s + friendlyelec_nanopi-r6s + DEPENDS:=+PACKAGE_u-boot-nanopi-r6c-rk3588:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + DEVICE_DTS := rk3588-nanopi-r6c.dts + UBOOT_CONFIG:= nanopi-r6c-rk3588 + ATF:=rk3588_bl31.elf + DDR_3588:=$(1) + endef -define U-Boot/radxa-e25-rk3568 - $(U-Boot/rk3568/Default) - DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568-e25 - TPL:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin - NAME:=E25 +define U-Boot/orangepi-5-plus-rk3588 + BUILD_SUBTARGET:=armv8 + NAME:=ORANGEPI-5-PLUS BUILD_DEVICES:= \ - radxa_e25 + xunlong_orangepi-5-plus + DEPENDS:=+PACKAGE_u-boot-orangepi-5-plus-rk3588:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + ATF:=rk3588_bl31.elf + DDR_3588:=$(1) endef -define U-Boot/rock-3a-rk3568 - $(U-Boot/rk3568/Default) - NAME:=ROCK 3A +define U-Boot/rock-5b-rk3588 + BUILD_SUBTARGET:=armv8 + NAME:=ROCK-5B BUILD_DEVICES:= \ - radxa_rock-3a + radxa_rock-5b + DEPENDS:=+PACKAGE_u-boot-rock-5b-rk3588:arm-trusted-firmware-rockchip + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip + UBOOT_CONFIG:= rock5b-rk3588 + ATF:=rk3588_bl31.elf + DDR_3588:=$(1) + DEFAULT := n endef UBOOT_TARGETS := \ - nanopc-t4-rk3399 \ - nanopi-r4s-rk3399 \ - rock-pi-4-rk3399 \ - rockpro64-rk3399 \ - rock-pi-s-rk3308 \ - nanopi-r2c-rk3328 \ - nanopi-r2c-plus-rk3328 \ - nanopi-r2s-rk3328 \ - orangepi-r1-plus-rk3328 \ - orangepi-r1-plus-lts-rk3328 \ - roc-cc-rk3328 \ - rock64-rk3328 \ - rock-pi-e-rk3328 \ - radxa-cm3-io-rk3566 \ + nanopi-r6c-rk3588 \ + nanopi-r6s-rk3588 \ + orangepi-5-plus-rk3588 \ + rock-5b-rk3588 \ bpi-r2-pro-rk3568 \ nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ - radxa-e25-rk3568 \ - rock-3a-rk3568 + quartz64-a-rk3566 \ + rock-3a-rk3568 \ + rock-pi-4-rk3399 \ + rockpro64-rk3399 \ + nanopi-r2s-rk3328 \ + roc-cc-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes -UBOOT_CUSTOMIZE_CONFIG := \ - --disable TOOLS_MKEFICAPSULE \ - --set-str MKIMAGE_DTC_PATH $(PKG_BUILD_DIR)/scripts/dtc/dtc - UBOOT_MAKE_FLAGS += \ - BL31=$(STAGING_DIR_IMAGE)/$(ATF) \ - $(if $(TPL),ROCKCHIP_TPL=$(STAGING_DIR_IMAGE)/$(TPL)) + PATH=$(STAGING_DIR_HOST)/bin:$(PATH) \ + BL31=$(STAGING_DIR_IMAGE)/$(ATF) +export ROCKCHIP_TPL=./ddr.bin + +define Build/Configure + $(call Build/Configure/U-Boot) + +ifneq ($(DDR_3568),) + $(CP) $(STAGING_DIR_IMAGE)/rk3568_ddr.bin $(PKG_BUILD_DIR)/ddr.bin +endif + +ifneq ($(DDR_3588),) + $(CP) $(STAGING_DIR_IMAGE)/rk3588_ddr.bin $(PKG_BUILD_DIR)/ddr.bin +endif + + $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config + echo 'CONFIG_TOOLS_MKEFICAPSULE=n' >> $(PKG_BUILD_DIR)/.config + echo 'CONFIG_OF_LIBFDT_OVERLAY=n' >> $(PKG_BUILD_DIR)/.config +endef define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/u-boot-rockchip.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot-rockchip.bin + $(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img + $(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb endef define Package/u-boot/install/default diff --git a/package/boot/uboot-rockchip/patches/100-force-build-dtc.patch b/package/boot/uboot-rockchip/patches/100-force-build-dtc.patch new file mode 100644 index 00000000000000..c3e813cf4644cf --- /dev/null +++ b/package/boot/uboot-rockchip/patches/100-force-build-dtc.patch @@ -0,0 +1,20 @@ +--- a/Makefile ++++ b/Makefile +@@ -416,7 +416,7 @@ PYTHON3 ?= python3 + + # The devicetree compiler and pylibfdt are automatically built unless DTC is + # provided. If DTC is provided, it is assumed the pylibfdt is available too. +-DTC_INTREE := $(objtree)/scripts/dtc/dtc ++DTC := $(objtree)/scripts/dtc/dtc + DTC ?= $(DTC_INTREE) + DTC_MIN_VERSION := 010406 + +@@ -2012,7 +2012,7 @@ endif + # Check dtc and pylibfdt, if DTC is provided, else build them + PHONY += scripts_dtc + scripts_dtc: scripts_basic +- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ ++ $(Q)if test "$(DTC)" = "$(DTC)"; then \ + $(MAKE) $(build)=scripts/dtc; \ + else \ + if ! $(DTC) -v >/dev/null; then \ diff --git a/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch b/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch deleted file mode 100644 index b467f48f72b5d3..00000000000000 --- a/package/boot/uboot-rockchip/patches/105-nanopc-t4-fix-memory-unstability.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 445502bc21ecf1b5120faee785cea578b810c759 Mon Sep 17 00:00:00 2001 -From: Lu jicong -Date: Wed, 5 Jul 2023 17:13:55 +0800 -Subject: [PATCH] rockchip: rk3399: nanopc-t4: use 1600MHz sdram config - -Current 1866MHz sdram config is too high for NanoPC-T4. -On this frequency, its lpddr3 sdram becomes unstable, -causing memtest failures and random kernel crashes. - -Signed-off-by: Lu jicong ---- - arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi -+++ b/arch/arm/dts/rk3399-nanopc-t4-u-boot.dtsi -@@ -4,4 +4,4 @@ - */ - - #include "rk3399-nanopi4-u-boot.dtsi" --#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi" -+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" diff --git a/package/boot/uboot-rockchip/patches/106-uboot-rockchip-add-nanopi-r6c.patch b/package/boot/uboot-rockchip/patches/106-uboot-rockchip-add-nanopi-r6c.patch new file mode 100644 index 00000000000000..d3a20cd251abb2 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/106-uboot-rockchip-add-nanopi-r6c.patch @@ -0,0 +1,442 @@ +From 64e26c0cf06fa59285fdd4593ef01d3294506170 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Thu, 20 Apr 2023 14:24:36 -0400 +Subject: [PATCH] uboot: rockchip: add nanopi r6c + +Signed-off-by: Marty Jones +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/rk3588-nanopi-r6c-u-boot.dtsi | 22 ++++++ + arch/arm/dts/rk3588-nanopi-r6c.dts | 45 ++++++++++++ + arch/arm/mach-rockchip/rk3588/Kconfig | 7 ++ + board/friendlyelec/nanopi-r6c-rk3588/Kconfig | 15 ++++ + board/friendlyelec/nanopi-r6c-rk3588/Makefile | 4 ++ + .../nanopi-r6c-rk3588/nanopi-r6c-rk3588.c | 4 ++ + configs/nanopi-r5c-rk3588_defconfig | 72 +++++++++++++++++++ + include/configs/nanopi-r6c-rk3588.h | 15 ++++ + 9 files changed, 185 insertions(+) + create mode 100644 arch/arm/dts/rk3588-nanopi-r6c-u-boot.dtsi + create mode 100644 arch/arm/dts/rk3588-nanopi-r6c.dts + create mode 100644 board/friendlyelec/nanopi-r6c-rk3588/Kconfig + create mode 100644 board/friendlyelec/nanopi-r6c-rk3588/Makefile + create mode 100644 board/friendlyelec/nanopi-r6c-rk3588/nanopi-r6c-rk3588.c + create mode 100644 configs/nanopi-r6c-rk3588_defconfig + create mode 100644 include/configs/nanopi-r6c-rk3588.h + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -200,6 +200,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588-quartzpro64.dtb \ + rk3588-turing-rk1.dtb \ + rk3588s-rock-5a.dtb \ ++ rk3588-nanopi-r6c.dtb \ + rk3588-rock-5b.dtb + + dtb-$(CONFIG_ROCKCHIP_RV1108) += \ +--- /dev/null ++++ b/arch/arm/dts/rk3588-nanopi-r6c-u-boot.dtsi +@@ -0,0 +1,178 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3588-u-boot.dtsi" ++#include ++#include ++#include ++ ++/ { ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&emmc_bus8 { ++ bootph-all; ++}; ++ ++&emmc_clk { ++ bootph-all; ++}; ++ ++&emmc_cmd { ++ bootph-all; ++}; ++ ++&emmc_data_strobe { ++ bootph-all; ++}; ++ ++&emmc_rstnout { ++ bootph-all; ++}; ++ ++&fspim2_pins { ++ bootph-all; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>; ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bootph-all; ++ ++ pcie { ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2x1l2_pins: pcie2x1l2-pins { ++ rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, ++ <3 RK_PD0 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pcfg_pull_none { ++ bootph-all; ++}; ++ ++&pcfg_pull_up_drv_level_2 { ++ bootph-all; ++}; ++ ++&pcfg_pull_up { ++ bootph-all; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&sdmmc_bus4 { ++ bootph-all; ++}; ++ ++&sdmmc_clk { ++ bootph-all; ++}; ++ ++&sdmmc_cmd { ++ bootph-all; ++}; ++ ++&sdmmc_det { ++ bootph-all; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; ++}; ++ ++&usb_host0_ehci { ++ companion = <&usb_host0_ohci>; ++ phys = <&u2phy2_host>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ phys = <&u2phy2_host>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb2phy2_grf { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ companion = <&usb_host1_ohci>; ++ phys = <&u2phy3_host>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ phys = <&u2phy3_host>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb2phy3_grf { ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3588-nanopi-r6c.dts +@@ -0,0 +1,45 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3588.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi R6C"; ++ compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <200000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; +--- a/arch/arm/mach-rockchip/rk3588/Kconfig ++++ b/arch/arm/mach-rockchip/rk3588/Kconfig +@@ -100,6 +100,12 @@ config TARGET_ROCK5A_RK3588 + USB PD over USB Type-C + Size: 85mm x 56mm (Raspberry Pi 4 form factor) + ++config TARGET_NANOPI_R6C_RK3588 ++ bool "NanoPi R6C board" ++ select BOARD_LATE_INIT ++ help ++ FriendlyElec NANOPI-R6C is a Rockchip RK3588 based SBC (Single Board Computer) ++ + config TARGET_ROCK5B_RK3588 + bool "Radxa ROCK5B RK3588 board" + select BOARD_LATE_INIT +@@ -172,6 +178,7 @@ source board/friendlyelec/nanopc-t6-rk35 + source board/pine64/quartzpro64-rk3588/Kconfig + source board/turing/turing-rk1-rk3588/Kconfig + source board/rockchip/evb_rk3588/Kconfig ++source board/friendlyelec/nanopi-r6c-rk3588/Kconfig + source board/radxa/rock5a-rk3588s/Kconfig + source board/radxa/rock5b-rk3588/Kconfig + +--- /dev/null ++++ b/board/friendlyelec/nanopi-r6c-rk3588/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_NANOPI_R6C_RK3588 ++ ++config SYS_BOARD ++ default "nanopi-r6c-rk3588" ++ ++config SYS_VENDOR ++ default "friendlyelec" ++ ++config SYS_CONFIG_NAME ++ default "nanopi-r6c-rk3588" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++endif +--- /dev/null ++++ b/board/friendlyelec/nanopi-r6c-rk3588/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += nanopi-r6c-rk3588.o +--- /dev/null ++++ b/board/friendlyelec/nanopi-r6c-rk3588/nanopi-r6c-rk3588.c +@@ -0,0 +1,4 @@ ++ // SPDX-License-Identifier: GPL-2.0+ ++/* ++ * ++ */ +--- /dev/null ++++ b/configs/nanopi-r6c-rk3588_defconfig +@@ -0,0 +1,102 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopi-r6c" ++CONFIG_DM_RESET=y ++CONFIG_ROCKCHIP_RK3588=y ++CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_MMC=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_TARGET_NANOPI_R6C_RK3588=y ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFEB50000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopi-r6c.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x20000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++# CONFIG_SPL_MMC_SDHCI_SDMA is not set ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_RTL8169=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_LAN75XX=y ++CONFIG_USB_ETHER_LAN78XX=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++# CONFIG_BINMAN_FDT is not set ++CONFIG_ERRNO_STR=y +--- /dev/null ++++ b/include/configs/nanopi-r6c-rk3588.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (c) 2023 ++ */ ++ ++#ifndef __NANOPI_R6C_RK3588_H ++#define __NANOPI_R6C_RK3588_H ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#include ++ ++#endif /* __NANOPI_R6C_RK3588_H */ diff --git a/package/firmware/brcmfmac-sdio-firmware/Makefile b/package/firmware/brcmfmac-sdio-firmware/Makefile new file mode 100644 index 00000000000000..6a8f74f6d61ea2 --- /dev/null +++ b/package/firmware/brcmfmac-sdio-firmware/Makefile @@ -0,0 +1,61 @@ +# +# Copyright (C) 2019-2020 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=brcmfmac-sdio-firmware +PKG_SOURCE_DATE:=2022-07-06 +PKG_SOURCE_VERSION:=afc477e807c407736cfaff6a6188d09197dfbceb +PKG_MIRROR_HASH:=2d1bbca5f569b098eb15ed1aee6670f4ef9413f173b94a3d3a2d800966762971 +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/LibreELEC/brcmfmac_sdio-firmware + +PKG_MAINTAINER:=Florian Fainelli +PKG_LICENSE:=Proprietary +PKG_LICENSE_FILES:=LICENCE.broadcom_bcm43xx + +include $(INCLUDE_DIR)/package.mk + +define Package/brcmfmac-sdio-firmware-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=https://github.com/LibreELEC/brcmfmac_sdio-firmware +endef + +define Build/Compile + true +endef + +define Package/brcmfmac-sdio-firmware-43430-bt + $(Package/brcmfmac-sdio-firmware-default) + TITLE:=CYW43430 BT firmware and patch RAM +endef + +define Package/brcmfmac-sdio-firmware-43430-bt/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BCM43430*.hcd \ + $(1)/lib/firmware/brcm/ +endef + +$(eval $(call BuildPackage,brcmfmac-sdio-firmware-43430-bt)) + +define Package/brcmfmac-sdio-firmware-4345-bt + $(Package/brcmfmac-sdio-firmware-default) + TITLE:=CYW4345 BT firmware and patch RAM +endef + +define Package/brcmfmac-sdio-firmware-4345-bt/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/BCM4345*.hcd \ + $(1)/lib/firmware/brcm/ +endef + +$(eval $(call BuildPackage,brcmfmac-sdio-firmware-4345-bt)) diff --git a/package/firmware/cypress-firmware/Makefile b/package/firmware/cypress-firmware/Makefile index 4d836176055bca..3163c17ff6a3a3 100644 --- a/package/firmware/cypress-firmware/Makefile +++ b/package/firmware/cypress-firmware/Makefile @@ -191,6 +191,52 @@ endef $(eval $(call BuildPackage,cypress-firmware-43455-sdio)) +# Cypress 43455 4b SDIO Firmware +define Package/cypress-firmware-43455-4b-sdio + $(Package/cypress-firmware-default) + TITLE:=CYW43455 4b FullMac SDIO firmware + PROVIDES:=brcmfmac-firmware-43455-4b-sdio + CONFLICTS:=brcmfmac-firmware-43455-sdio +endef + +define Package/cypress-firmware-43455-4b-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.clm_blob + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,5-model-b.txt \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.txt +endef + +$(eval $(call BuildPackage,cypress-firmware-43455-4b-sdio)) + +# Cypress 43455 5b SDIO Firmware +define Package/cypress-firmware-43455-5b-sdio + $(Package/cypress-firmware-default) + TITLE:=CYW43455 5b FullMac SDIO firmware + PROVIDES:=brcmfmac-firmware-43455-5b-sdio + CONFLICTS:=brcmfmac-firmware-43455-sdio +endef + +define Package/cypress-firmware-43455-5b-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,5-model-b.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,5-model-b.clm_blob + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,5-model-b.txt \ + $(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,5-model-b.txt +endef + +$(eval $(call BuildPackage,cypress-firmware-43455-5b-sdio)) + # Cypress 4354 SDIO Firmware define Package/cypress-firmware-4354-sdio $(Package/cypress-firmware-default) diff --git a/package/firmware/cypress-firmware/src/brcmfmac43455-sdio.raspberrypi,5-model-b.txt b/package/firmware/cypress-firmware/src/brcmfmac43455-sdio.raspberrypi,5-model-b.txt new file mode 100644 index 00000000000000..8dda1683ec7593 --- /dev/null +++ b/package/firmware/cypress-firmware/src/brcmfmac43455-sdio.raspberrypi,5-model-b.txt @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2018 Raspberry Pi (Trading) Ltd. +# NVRAM config file for the BCM43455 WiFi/BT chip as found on the +# Raspberry Pi 4 Model B +aa2g=1 +aa5g=1 +AvVmid_c0=1,165,2,100,2,100,2,100,2,100 +boardflags=0x00480201 +boardflags2=0x40800000 +boardflags3=0x44200100 +boardrev=0x1304 +boardtype=0x6e4 +btc_mode=1 +btc_params1=0x7530 +btc_params8=0x4e20 +btc_params50=0x972c +cbfilttype=1 +cckPwrIdxCorr=3 +cckTssiDelay=150 +deadman_to=481500000 +devid=0x43ab +dot11agofdmhrbw202gpo=0x4442 +dot11b_opts=0x3aa85 +ed_thresh2g=-54 +ed_thresh5g=-54 +eu_edthresh2g=-54 +eu_edthresh5g=-54 +extpagain2g=2 +extpagain5g=2 +fdsslevel_ch11=6 +femctrl=0 +itrsw=1 +ldo1=4 +ltecxfnsel=0x22 +ltecxgcigpio=0x32 +ltecxmux=0 +ltecxpadnum=0x0504 +macaddr=b8:27:eb:74:f2:6c +manfid=0x2d0 +maxp2ga0=80 +maxp5ga0=82,82,82,82 +mcsbw202gpo=0x98444422 +mcsbw205ghpo=0xb9555000 +mcsbw205glpo=0xb9555000 +mcsbw205gmpo=0xb9555000 +mcsbw402gpo=0x98444422 +mcsbw405ghpo=0xb9555000 +mcsbw405glpo=0xb9555000 +mcsbw405gmpo=0xb9555000 +mcsbw805ghpo=0xb9555000 +mcsbw805glpo=0xb9555000 +mcsbw805gmpo=0xb9555000 +nocrc=1 +ofdmlrbw202gpo=0x0022 +ofdmTssiDelay=150 +pa2ga0=-129,6525,-718 +pa2ga1=-149,4408,-601 +pa5ga0=-185,6836,-815,-186,6838,-815,-184,6859,-815,-184,6882,-818 +pa5ga1=-202,4285,-574,-201,4312,-578,-196,4391,-586,-201,4294,-575 +pdoffset2g40ma0=16 +pdoffset2gperchan=0,-2,1,0,1,0,1,1,1,0,0,-1,-1,0 +pdoffset40ma0=0x8888 +pdoffset80ma0=0x8888 +pdoffsetcckma0=2 +phycal_tempdelta=15 +prodid=0x06e4 +rawtempsense=0x1ff +rxchain=1 +sromrev=11 +swctrlmap_2g=0x00000000,0x00000000,0x00000000,0x010000,0x3ff +swctrlmap_5g=0x00100010,0x00200020,0x00200020,0x010000,0x3fe +swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x3 +swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x3 +tssipos2g=1 +tssipos5g=1 +tworangetssi2g=1 +tworangetssi5g=1 +txchain=1 +txpwr2gAdcScale=1 +txpwr5gAdcScale=1 +vcodivmode=1 +vendid=0x14e4 +xtalfreq=37400 diff --git a/package/firmware/firmware-nonfree/Makefile b/package/firmware/firmware-nonfree/Makefile new file mode 100644 index 00000000000000..9423d596933396 --- /dev/null +++ b/package/firmware/firmware-nonfree/Makefile @@ -0,0 +1,78 @@ +# +# +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +include $(TOPDIR)/rules.mk + +PKG_NAME:=firmware-nonfree +PKG_SOURCE_DATE:=2022-04-11 +PKG_SOURCE_VERSION:=fdaf74c780ca7a29b12d62e5b0d37c38c2321e20 +PKG_MIRROR_HASH:=28aabe16622319df0a6d3a068fc34dcf239174beb9b2b5c73197377da841639c +PKG_RELEASE:=1 +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/RPi-Distro/firmware-nonfree.git + +PKG_MAINTAINER:= + +include $(INCLUDE_DIR)/package.mk + +define Package/firmware-nonfree-default + SECTION:=firmware + CATEGORY:=Firmware + URL:=https://github.com/RPi-Distro +endef + +define Build/Compile + true +endef + +# brcmfmac-firmware-43456-sdio +define Package/brcmfmac-firmware-43456-sdio + $(Package/firmware-nonfree-default) + TITLE:=BCM43456 FullMac SDIO firmware +endef + +define Package/brcmfmac-firmware-43456-sdio/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/debian/config/brcm80211/brcm/brcmfmac43456-sdio.bin \ + $(1)/lib/firmware/brcm/brcmfmac43456-sdio.bin + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/debian/config/brcm80211/brcm/brcmfmac43456-sdio.clm_blob \ + $(1)/lib/firmware/brcm/brcmfmac43456-sdio.clm_blob +endef + +$(eval $(call BuildPackage,brcmfmac-firmware-43456-sdio)) + +# brcmfmac-firmware-43456-sdio-rockpi-4 +define Package/brcmfmac-firmware-43456-sdio-rockpi-4 + $(Package/firmware-nonfree-default) + TITLE:=BCM43456 NVRAM for rockpi-4 +endef + +define Package/brcmfmac-firmware-43456-sdio-rockpi-4/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/debian/config/brcm80211/brcm/brcmfmac43456-sdio.txt \ + $(1)/lib/firmware/brcm/brcmfmac43456-sdio.radxa,rockpi4b.txt +endef + +$(eval $(call BuildPackage,brcmfmac-firmware-43456-sdio-rockpi-4)) + +# brcmfmac-firmware-43456-sdio-rpi-400 +define Package/brcmfmac-firmware-43456-sdio-rpi-400 + $(Package/firmware-nonfree-default) + TITLE:=BCM43456 NVRAM for rpi 400 +endef + +define Package/brcmfmac-firmware-43456-sdio-rpi-400/install + $(INSTALL_DIR) $(1)/lib/firmware/brcm + $(INSTALL_DATA) \ + $(PKG_BUILD_DIR)/debian/config/brcm80211/brcm/brcmfmac43456-sdio.txt \ + $(1)/lib/firmware/brcm/brcmfmac43456-sdio.raspberrypi,400.txt +endef + +$(eval $(call BuildPackage,brcmfmac-firmware-43456-sdio-rpi-400)) diff --git a/package/firmware/linux-firmware/mediatek.mk b/package/firmware/linux-firmware/mediatek.mk index 5c448e1033c3bb..c7c4856172578c 100644 --- a/package/firmware/linux-firmware/mediatek.mk +++ b/package/firmware/linux-firmware/mediatek.mk @@ -55,7 +55,7 @@ Package/mt7921bt-firmware = $(call Package/firmware-default,mt7921bt firmware,,L define Package/mt7921bt-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/mediatek $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin \ + $(PKG_BUILD_DIR)/mediate/BT_RAM_CODE_MT7961_1_2_hdr.bin \ $(1)/lib/firmware/mediatek endef $(eval $(call BuildPackage,mt7921bt-firmware)) @@ -64,7 +64,7 @@ Package/mt7922bt-firmware = $(call Package/firmware-default,mt7922bt firmware,,L define Package/mt7922bt-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/mediatek $(INSTALL_DATA) \ - $(PKG_BUILD_DIR)/mediatek/BT_RAM_CODE_MT7922_1_1_hdr.bin \ + $(PKG_BUILD_DIR)/mediate/BT_RAM_CODE_MT7922_1_1_hdr.bin \ $(1)/lib/firmware/mediatek endef $(eval $(call BuildPackage,mt7922bt-firmware)) diff --git a/package/firmware/linux-firmware/realtek.mk b/package/firmware/linux-firmware/realtek.mk index 5ba679d404922d..33467a41a803f5 100644 --- a/package/firmware/linux-firmware/realtek.mk +++ b/package/firmware/linux-firmware/realtek.mk @@ -133,6 +133,16 @@ define Package/rtl8761bu-firmware/install endef $(eval $(call BuildPackage,rtl8761bu-firmware)) +Package/realtek-bluetooth-firmware = $(call Package/firmware-default,RealTek bluetooth firmware) +define Package/realtek-bluetooth-firmware/install + $(INSTALL_DIR) $(1)/lib/firmware/rtl_bt + $(CP) \ + $(PKG_BUILD_DIR)/rtl_bt/* \ + $(1)/lib/firmware/rtl_bt +endef +$(eval $(call BuildPackage,realtek-bluetooth-firmware)) + + Package/rtl8821ae-firmware = $(call Package/firmware-default,RealTek RTL8821AE firmware,,LICENCE.rtlwifi_firmware.txt) define Package/rtl8821ae-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/rtlwifi diff --git a/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7922_1_1_hdr.bin b/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7922_1_1_hdr.bin new file mode 100644 index 00000000000000..e3bb907879c6cd Binary files /dev/null and b/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7922_1_1_hdr.bin differ diff --git a/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7961_1_2_hdr.bin b/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7961_1_2_hdr.bin new file mode 100644 index 00000000000000..4b637d5156f289 Binary files /dev/null and b/package/firmware/linux-firmware/src/mediate/BT_RAM_CODE_MT7961_1_2_hdr.bin differ diff --git a/package/firmware/wireless-regdb/patches/500-world-regd-5GHz.patch b/package/firmware/wireless-regdb/patches/500-world-regd-5GHz.patch index 3f6d4c7e8d0112..8270ebc90951ca 100644 --- a/package/firmware/wireless-regdb/patches/500-world-regd-5GHz.patch +++ b/package/firmware/wireless-regdb/patches/500-world-regd-5GHz.patch @@ -5,7 +5,7 @@ Signed-off-by: Felix Fietkau --- --- a/db.txt +++ b/db.txt -@@ -19,7 +19,7 @@ country 00: +@@ -19,13 +19,15 @@ country 00: # Channel 14. Only JP enables this and for 802.11b only (2474 - 2494 @ 20), (20), NO-IR, NO-OFDM # Channel 36 - 48 @@ -14,3 +14,20 @@ Signed-off-by: Felix Fietkau # Channel 52 - 64 (5250 - 5330 @ 80), (20), NO-IR, DFS, AUTO-BW # Channel 100 - 144 + (5490 - 5730 @ 160), (20), NO-IR, DFS + # Channel 149 - 165 + (5735 - 5835 @ 80), (20), NO-IR ++ # Channel 1 - 223 ++ (5925 - 7125 @ 320), (12), AUTO-BW + # IEEE 802.11ad (60GHz), channels 1..3 + (57240 - 63720 @ 2160), (0) + +@@ -1736,7 +1736,7 @@ country US: DFS-FCC + (5850 - 5895 @ 40), (27), NO-OUTDOOR, AUTO-BW, NO-IR + # 6g band + # https://www.federalregister.gov/documents/2020/05/26/2020-11236/unlicensed-use-of-the-6ghz-band +- (5925 - 7125 @ 320), (12), NO-OUTDOOR, NO-IR ++ (5925 - 7125 @ 320), (12), AUTO-BW + # 60g band + # reference: section IV-D https://docs.fcc.gov/public/attachments/FCC-16-89A1.pdf + # channels 1-6 EIRP=40dBm(43dBm peak) diff --git a/package/kernel/mac80211/realtek.mk b/package/kernel/mac80211/realtek.mk index 28ea6a65718bba..ba562e708d2f4a 100644 --- a/package/kernel/mac80211/realtek.mk +++ b/package/kernel/mac80211/realtek.mk @@ -3,7 +3,7 @@ PKG_DRIVERS += \ rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \ rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \ rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \ - rtw88-8822ce rtw88-8822cu rtw88-8723de + rtw88-8822ce rtw88-8822cu rtw88-8723de rtw89 config-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI config-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI @@ -43,6 +43,12 @@ config-$(call config_package,rtw88-8723de) += RTW88_8723DE config-$(CONFIG_PACKAGE_RTW88_DEBUG) += RTW88_DEBUG config-$(CONFIG_PACKAGE_RTW88_DEBUGFS) += RTW88_DEBUGFS +config-$(call config_package,rtw89) += RTW89 RTW89_CORE RTW89_PCI +config-y += RTW89_8852AE RTW89_8852BE RTW89_8852CE +config-$(CONFIG_PACKAGE_RTW89_DEBUG) += RTW89_DEBUG +config-$(CONFIG_PACKAGE_RTW89_DEBUGFS) += RTW89_DEBUGFS +config-$(CONFIG_PACKAGE_RTW89_DEBUGMSG) += RTW89_DEBUGMSG + define KernelPackage/rtlwifi/config config PACKAGE_RTLWIFI_DEBUG bool "Realtek wireless debugging" @@ -331,3 +337,40 @@ define KernelPackage/rtl8723bs/description on the 1st gen Intel Compute Stick, the CHIP and many other Intel Atom and ARM based devices. endef + +define KernelPackage/rtw89/config + config PACKAGE_RTW89_DEBUG + bool "Realtek wireless debugging (rtw89)" + depends on PACKAGE_kmod-rtw89 + help + Enable debugging output for rtw89 devices + + config PACKAGE_RTW89_DEBUGFS + bool "Enable rtw89 debugfs support" + select KERNEL_DEBUG_FS + depends on PACKAGE_kmod-rtw89 + help + Select this to see extensive information about + the internal state of rtw89 in debugfs. + config PACKAGE_RTW89_DEBUGMSG + bool "Realtek rtw89 debug message support" + depends on PACKAGE_kmod-rtw89 + help + Enable debug message support +endef + +define KernelPackage/rtw89 + $(call KernelPackage/mac80211/Default) + TITLE:=Realtek RTL8852AE/BE/CE + DEPENDS+= @(PCI_SUPPORT) +kmod-mac80211 +@DRIVER_11AX_SUPPORT +rtl8851be-firmware +rtl8852ae-firmware +rtl8852be-firmware +rtl8852ce-firmware + FILES:=\ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852a.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852ae.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852b.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852be.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852c.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_8852ce.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_core.ko \ + $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw89/rtw89_pci.ko + AUTOLOAD:=$(call AutoProbe,rtw89_8852ae rtw89_8852be rtw89_8852ce) +endef diff --git a/package/kernel/mt76/Makefile b/package/kernel/mt76/Makefile index f71070dbb9072f..0c0a1f169356fd 100644 --- a/package/kernel/mt76/Makefile +++ b/package/kernel/mt76/Makefile @@ -603,8 +603,8 @@ endef define KernelPackage/mt7921-firmware/install $(INSTALL_DIR) $(1)/lib/firmware/mediatek cp \ - $(PKG_BUILD_DIR)/firmware/WIFI_MT7961_patch_mcu_1_2_hdr.bin \ - $(PKG_BUILD_DIR)/firmware/WIFI_RAM_CODE_MT7961_1.bin \ + $(PKG_BUILD_DIR)/firm/WIFI_MT7961_patch_mcu_1_2_hdr.bin \ + $(PKG_BUILD_DIR)/firm/WIFI_RAM_CODE_MT7961_1.bin \ $(1)/lib/firmware/mediatek endef diff --git a/package/kernel/mt76/patches/0001-mt7921-add-CONFIG_MT76_LEDS-to-cflag.patch b/package/kernel/mt76/patches/0001-mt7921-add-CONFIG_MT76_LEDS-to-cflag.patch new file mode 100644 index 00000000000000..e1ba6cd1ebdc6f --- /dev/null +++ b/package/kernel/mt76/patches/0001-mt7921-add-CONFIG_MT76_LEDS-to-cflag.patch @@ -0,0 +1,19 @@ +From 01e4bf398aa1fe10eba68f9eae8d0f683f491007 Mon Sep 17 00:00:00 2001 +From: 76 <126417504+76@users.noreply.github.com> +Date: Sat, 25 May 2024 00:36:10 +0000 +Subject: [PATCH] mt7921: add CONFIG_MT76_LEDS to cflag + +Signed-off-by: 76 <126417504+76@users.noreply.github.com> +--- + mt7921/Makefile | 1 + + 1 file changed, 1 insertion(+) + +--- a/mt7921/Makefile ++++ b/mt7921/Makefile +@@ -1,5 +1,6 @@ + # SPDX-License-Identifier: ISC + ++EXTRA_CFLAGS += -DCONFIG_MT76_LEDS + obj-$(CONFIG_MT7921_COMMON) += mt7921-common.o + obj-$(CONFIG_MT7921E) += mt7921e.o + obj-$(CONFIG_MT7921S) += mt7921s.o diff --git a/package/kernel/mt76/src/firm/WIFI_MT7961_patch_mcu_1_2_hdr.bin b/package/kernel/mt76/src/firm/WIFI_MT7961_patch_mcu_1_2_hdr.bin new file mode 100644 index 00000000000000..ba21620dcedd7e Binary files /dev/null and b/package/kernel/mt76/src/firm/WIFI_MT7961_patch_mcu_1_2_hdr.bin differ diff --git a/package/kernel/mt76/src/firm/WIFI_RAM_CODE_MT7961_1.bin b/package/kernel/mt76/src/firm/WIFI_RAM_CODE_MT7961_1.bin new file mode 100644 index 00000000000000..2e9dcffa709d40 Binary files /dev/null and b/package/kernel/mt76/src/firm/WIFI_RAM_CODE_MT7961_1.bin differ diff --git a/package/kernel/rtl8812au-ac/Makefile b/package/kernel/rtl8812au-ac/Makefile new file mode 100644 index 00000000000000..1ac011cf812834 --- /dev/null +++ b/package/kernel/rtl8812au-ac/Makefile @@ -0,0 +1,67 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=rtl8812au-ac +PKG_RELEASE:=1 + +PKG_LICENSE:=GPLv2 +PKG_LICENSE_FILES:= + +PKG_SOURCE_URL:=https://github.com/mj22226/rtl8812au.git +PKG_SOURCE_PROTO:=git +PKG_SOURCE_DATE:=2024-07-13 +PKG_SOURCE_VERSION:=8aad89bb2a310cf80ebf33b94c36ec1a49d54a1c +PKG_MIRROR_HASH:=1ccfb9b8c28b147ef8cbb62c92a60b6020377e7c81264f2db277dceaaa193f36 + +# PKG_MAINTAINER:= +PKG_BUILD_PARALLEL:=1 + +STAMP_CONFIGURED_DEPENDS := $(STAGING_DIR)/usr/include/mac80211-backport/backport/autoconf.h + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/package.mk + +define KernelPackage/rtl8812au-ac + SUBMENU:=Wireless Drivers + TITLE:=Realtek rtl8812au/21au and rtl8814au driver + DEPENDS:=+kmod-cfg80211 +kmod-usb-core +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT + KCONFIG:=CONFIG_PLATFORM_I386_PC=n + FILES:=\ + $(PKG_BUILD_DIR)/rtl8812au.ko + AUTOLOAD:=$(call AutoProbe,rtl8812au) +endef + +NOSTDINC_FLAGS = \ + -I$(PKG_BUILD_DIR) \ + -I$(PKG_BUILD_DIR)/include \ + -I$(STAGING_DIR)/usr/include/mac80211-backport \ + -I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \ + -I$(STAGING_DIR)/usr/include/mac80211 \ + -I$(STAGING_DIR)/usr/include/mac80211/uapi \ + -include backport/autoconf.h \ + -include backport/backport.h \ + -Wno-error=address \ + -Wno-error=stringop-overread + +NOSTDINC_FLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT \ + -D_LINUX_BYTEORDER_SWAB_H -DBUILD_OPENWRT -DRTW_SINGLE_WIPHY +ifeq ($(CONFIG_BIG_ENDIAN), y) +NOSTDINC_FLAGS += -DCONFIG_BIG_ENDIAN +endif +ifeq ($(CONFIG_LITTLE_ENDIAN), y) +NOSTDINC_FLAGS += -DCONFIG_LITTLE_ENDIAN +endif + +PKG_MAKE_FLAGS += USER_MODULE_NAME=rtl8812au +PKG_MAKE_FLAGS += USER_DRV_NAME=rtl8812au +KERNEL_MAKE_FLAGS += CONFIG_88XXAU=m + +define Build/Compile + +$(MAKE) $(PKG_JOBS) -C "$(LINUX_DIR)" \ + $(KERNEL_MAKE_FLAGS) \ + $(PKG_MAKE_FLAGS) \ + M="$(PKG_BUILD_DIR)" \ + NOSTDINC_FLAGS="$(NOSTDINC_FLAGS)" \ + modules +endef + +$(eval $(call KernelPackage,rtl8812au-ac)) diff --git a/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc b/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc index 750e3ae71c27da..4c33779af935e1 100644 --- a/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc +++ b/package/network/config/wifi-scripts/files/usr/share/hostap/common.uc @@ -49,7 +49,7 @@ function __phy_is_fullmac(phyidx) { let data = nl80211.request(nl80211.const.NL80211_CMD_GET_WIPHY, 0, { wiphy: phyidx }); - return !data.software_iftypes.monitor; + return !data.software_iftypes.ap_vlan; } function phy_is_fullmac(phy) diff --git a/package/network/utils/iwinfo/patches/01.patch b/package/network/utils/iwinfo/patches/01.patch new file mode 100644 index 00000000000000..c78e78f3bdd29c --- /dev/null +++ b/package/network/utils/iwinfo/patches/01.patch @@ -0,0 +1,85 @@ +--- a/devices.txt ++++ b/devices.txt +@@ -263,3 +263,82 @@ + "ralink,rt3883-wmac" 0 0 "Ralink" "Rt3883" + "ralink,rt5350-wmac" 0 0 "Ralink" "Rt5350" + "ralink,rt7620-wmac" 0 0 "MediaTek" "MT7620" ++ ++ ++ ++# RTL8812A ++0x0000 0x0000 0x0409 0x0408 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0411 0x025D 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x04BB 0x0952 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x050D 0x1106 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x050D 0x1109 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0586 0x3426 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0789 0x016E 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x07B8 0x8812 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0846 0x9051 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0B05 0x17D2 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0DF6 0x0074 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x0E66 0x0022 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x1058 0x0632 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x13B1 0x003F 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x148F 0x9097 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x1740 0x0100 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2001 0x330E 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2001 0x3313 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2001 0x3315 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2001 0x3316 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2019 0xAB30 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x20F4 0x805B 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x0101 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x0103 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x010D 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x010E 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x010F 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2357 0x0122 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x2604 0x0012 0 0 "Realtek" "RTL8812" ++0x0000 0x0000 0x7392 0xA822 0 0 "Realtek" "RTL8812" ++# RTL8814A ++0x0000 0x0000 0x0B05 0x1817 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x0B05 0x1852 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x0B05 0x1853 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x056E 0x400B 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x056E 0x400D 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x0846 0x9054 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x0E66 0x0026 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x2001 0x331A 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x20F4 0x809A 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x20F4 0x809B 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x2357 0x0106 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x7392 0xA834 0 0 "Realtek" "RTL8814A" ++0x0000 0x0000 0x7392 0xA833 0 0 "Realtek" "RTL8814A" ++# RTL8821A ++0x0000 0x0000 0x0bda 0x0811 0 0 "Realtek" "RTL8821" /* Alfa AWUS036ACS */ ++0x0000 0x0000 0x0411 0x0242 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x0411 0x029B 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x04BB 0x0953 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x056E 0x4007 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x056E 0x400E 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x056E 0x400F 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x0846 0x9052 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x0E66 0x0023 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2001 0x3314 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2001 0x3318 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2019 0xAB32 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2357 0x011E 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2357 0x011F 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x2357 0x0120 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x3823 0x6249 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x7392 0xA811 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x7392 0xA812 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x7392 0xA813 0 0 "Realtek" "RTL8821" ++0x0000 0x0000 0x7392 0xB611 0 0 "Realtek" "RTL8821" ++ ++ ++# RTW88 USB ++0x0000 0x0000 0x2357 0x0138 0 0 "Realtek" "RTW88" /* TP-Link T3u Plus */ ++ ++##### ++ ++0x02d0 0xa9bf 0x0000 0x0000 0 0 "Broadcom" "BCM43456" ++0x14c3 0x7922 0x1A3B 0x5300 0 0 "MediaTek" "MT7922" ++0x10ec 0x8852 0x1e26 0x007f 0 0 "Realtek" "RTL8852AE" diff --git a/target/linux/bcm27xx/base-files/etc/board.d/02_network b/target/linux/bcm27xx/base-files/etc/board.d/02_network index f246139c385bd8..de2a6251e516c0 100644 --- a/target/linux/bcm27xx/base-files/etc/board.d/02_network +++ b/target/linux/bcm27xx/base-files/etc/board.d/02_network @@ -21,7 +21,7 @@ raspberrypi,5-model-b |\ raspberrypi,model-b |\ raspberrypi,model-b-plus |\ raspberrypi,model-b-rev2) - ucidef_set_interface_lan "eth0" + ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1" ;; raspberrypi,model-zero-2 |\ diff --git a/target/linux/bcm27xx/base-files/etc/init.d/resize-rootfs b/target/linux/bcm27xx/base-files/etc/init.d/resize-rootfs new file mode 100755 index 00000000000000..740b751499825a --- /dev/null +++ b/target/linux/bcm27xx/base-files/etc/init.d/resize-rootfs @@ -0,0 +1,9 @@ +#!/bin/sh /etc/rc.common + +START=22 +start() { + rm -rf /etc/rc.d/S22resize-rootfs + #service resize-rootfs disable + /usr/bin/resize-rootfs.sh +} + diff --git a/target/linux/bcm27xx/base-files/etc/rc.d/S22resize-rootfs b/target/linux/bcm27xx/base-files/etc/rc.d/S22resize-rootfs new file mode 100755 index 00000000000000..051d001b6cbe2b --- /dev/null +++ b/target/linux/bcm27xx/base-files/etc/rc.d/S22resize-rootfs @@ -0,0 +1 @@ +../init.d/resize-rootfs diff --git a/target/linux/bcm27xx/base-files/usr/bin/resize-rootfs.sh b/target/linux/bcm27xx/base-files/usr/bin/resize-rootfs.sh new file mode 100755 index 00000000000000..170c999ac0195a --- /dev/null +++ b/target/linux/bcm27xx/base-files/usr/bin/resize-rootfs.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +FDISK=$(which fdisk) || { echo "E: You must have fdisk" && exit 1; } +LOSETUP=$(which losetup) || { echo "E: You must have losetup" && exit 1; } +roottype=$(findmnt -n -o SOURCE / -o FSTYPE) +case ${roottype} in + overlay) + FSCKEXT4=$(which fsck.ext4) || { echo "E: You must have fsck.ext4" && exit 1; } + RESIZE2FS=$(which resize2fs) || { echo "E: You must have resize2fs" && exit 1; } + rootsource=$(findmnt -n -o SOURCE / | sed 's~\[.*\]~~') # i.e. /dev/mmcblk0p2 + rootdevice=${rootsource%p*} # i.e. /dev/mmcblk0 + partitions=${rootsource##*p} + ;; + ext4) + FSCKEXT4=$(which fsck.ext4) || { echo "E: You must have fsck.ext4" && exit 1; } + RESIZE2FS=$(which resize2fs) || { echo "E: You must have resize2fs" && exit 1; } + rootsource=$(findmnt -n -o SOURCE / | sed 's~\[.*\]~~') # i.e. /dev/mmcblk0p2 + rootdevice=${rootsource%p*} # i.e. /dev/mmcblk0 + partitions=${rootsource##*p} + + # Resizing partitions + lastsector=$(${FDISK} -l ${rootdevice} |grep "Disk ${rootdevice}" |awk '{print $7}') + lastsector=$(( $lastsector - 1 )) + startfrom=$(${FDISK} -l ${rootdevice} |grep ${rootsource} |awk '{print $2}') + partend=$(${FDISK} -l ${rootdevice} |grep ${rootsource} |awk '{print $3}') + [[ $lastsector -eq $partend ]] && exit 0 + (echo d; echo $partitions; echo n; echo p; echo ; echo $startfrom; echo $lastsector ; echo w;) | fdisk $rootdevice + + # Start resizing filesystem + LOOP="$(losetup -f)" + ${LOSETUP} ${LOOP} ${rootsource} + ${FSCKEXT4} -y ${LOOP} + ${RESIZE2FS} ${LOOP} + reboot + ;; +esac + +exit 0 + diff --git a/target/linux/bcm27xx/bcm2711/config-6.6 b/target/linux/bcm27xx/bcm2711/config-6.6 index 915fe29cae8f77..5aa61ff46861b9 100644 --- a/target/linux/bcm27xx/bcm2711/config-6.6 +++ b/target/linux/bcm27xx/bcm2711/config-6.6 @@ -269,6 +269,7 @@ CONFIG_HAS_IOPORT_MAP=y CONFIG_HOTPLUG_CORE_SYNC=y CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_HOTPLUG_CPU=y +CONFIG_HWMON=y CONFIG_HW_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_IPROC_RNG200=y @@ -431,6 +432,7 @@ CONFIG_SCSI=y CONFIG_SCSI_COMMON=y # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_PROC_FS is not set +# CONFIG_SENSORS_RASPBERRYPI_HWMON is not set CONFIG_SERIAL_8250_BCM2835AUX=y # CONFIG_SERIAL_8250_DMA is not set CONFIG_SERIAL_8250_EXTENDED=y diff --git a/target/linux/bcm27xx/bcm2712/config-6.6 b/target/linux/bcm27xx/bcm2712/config-6.6 index f61986338b0093..c246af2dac8603 100644 --- a/target/linux/bcm27xx/bcm2712/config-6.6 +++ b/target/linux/bcm27xx/bcm2712/config-6.6 @@ -556,7 +556,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y -# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SG_POOL=y diff --git a/target/linux/bcm27xx/image/Makefile b/target/linux/bcm27xx/image/Makefile index 23bc3a35c9edd8..aa9fec92cd40a4 100644 --- a/target/linux/bcm27xx/image/Makefile +++ b/target/linux/bcm27xx/image/Makefile @@ -123,6 +123,7 @@ define Device/rpi-2 raspberrypi,400 raspberrypi,4-compute-module raspberrypi,4-model-b \ raspberrypi,model-zero-2 raspberrypi,model-zero-2-w DEVICE_PACKAGES := \ + brcmfmac-sdio-firmware-4345-bt \ cypress-firmware-43430-sdio \ brcmfmac-nvram-43430-sdio \ cypress-firmware-43455-sdio \ @@ -180,8 +181,8 @@ define Device/rpi-4 raspberrypi,4-compute-module \ raspberrypi,4-model-b DEVICE_PACKAGES := \ - cypress-firmware-43455-sdio \ - brcmfmac-nvram-43455-sdio \ + brcmfmac-sdio-firmware-4345-bt \ + cypress-firmware-43455-4b-sdio \ kmod-brcmfmac wpad-basic-mbedtls \ kmod-usb-net-lan78xx \ kmod-r8169 @@ -198,8 +199,8 @@ define Device/rpi-5 DEVICE_DTS := broadcom/bcm2712-rpi-5-b SUPPORTED_DEVICES := raspberrypi,5-model-b DEVICE_PACKAGES := \ - cypress-firmware-43455-sdio \ - brcmfmac-nvram-43455-sdio \ + cypress-firmware-43455-5b-sdio \ + brcmfmac-sdio-firmware-4345-bt \ kmod-brcmfmac wpad-basic-mbedtls \ kmod-hwmon-pwmfan kmod-thermal IMAGE/sysupgrade.img.gz := boot-common | sdcard-img | gzip | append-metadata diff --git a/target/linux/bcm27xx/image/config.txt b/target/linux/bcm27xx/image/config.txt index db35d72ab7985e..1b0f4f91c0a4bd 100644 --- a/target/linux/bcm27xx/image/config.txt +++ b/target/linux/bcm27xx/image/config.txt @@ -12,3 +12,8 @@ include distroconfig.txt [all] # Place your custom settings here. +usb_max_current_enable=1 +# Enable the PCIe external connector +dtparam=pciex1 +# Force Gen 3.0 speeds +dtparam=pciex1_gen=3 diff --git a/target/linux/bcm27xx/image/distroconfig.txt b/target/linux/bcm27xx/image/distroconfig.txt index b09e5b8466f50d..d759cb582a6fcd 100644 --- a/target/linux/bcm27xx/image/distroconfig.txt +++ b/target/linux/bcm27xx/image/distroconfig.txt @@ -12,5 +12,15 @@ dtoverlay=disable-bt dtoverlay=disable-bt [pi4] dtoverlay=disable-bt +# Enable the Mini UART (ttyS0) as the console +# enable_uart=1 +# Enable Bluetooth over the PL011 (ttyAMA0) using the serial bus (serdev) +# dtparam=krnbt=on # Run as fast as firmware / board allows arm_boost=1 + +[pi5] +# Enable the Mini UART (ttyS0) as the console +enable_uart=1 +# Enable Bluetooth over the PL011 (ttyAMA0) using the serial bus (serdev) +dtparam=krnbt=on diff --git a/target/linux/bcm27xx/patches-6.6/950-0103-Improve-__copy_to_user-and-__copy_from_user-performa.patch b/target/linux/bcm27xx/patches-6.6/950-0103-Improve-__copy_to_user-and-__copy_from_user-performa.patch index 2d546c7502add9..92fd35d9361d5a 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0103-Improve-__copy_to_user-and-__copy_from_user-performa.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0103-Improve-__copy_to_user-and-__copy_from_user-performa.patch @@ -99,7 +99,7 @@ Signed-off-by: Phil Elwell #endif --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h -@@ -509,6 +509,9 @@ do { \ +@@ -499,6 +499,9 @@ do { \ extern unsigned long __must_check arm_copy_from_user(void *to, const void __user *from, unsigned long n); diff --git a/target/linux/bcm27xx/patches-6.6/950-0113-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch b/target/linux/bcm27xx/patches-6.6/950-0113-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch index 14f92dfadd2f7d..1a84fb14b1da92 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0113-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0113-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch @@ -10,7 +10,7 @@ Subject: [PATCH 0113/1085] ARM64: Force hardware emulation of deprecated --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c -@@ -539,9 +539,14 @@ static void __init register_insn_emulati +@@ -542,9 +542,14 @@ static void __init register_insn_emulati switch (insn->status) { case INSN_DEPRECATED: diff --git a/target/linux/bcm27xx/patches-6.6/950-0169-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch b/target/linux/bcm27xx/patches-6.6/950-0169-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch index a64754310d40f9..c3c3353f919db7 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0169-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0169-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch @@ -33,7 +33,7 @@ Signed-off-by: Jonathan Bell #define USB_VENDOR_ID_BELKIN 0x050d #define USB_DEVICE_ID_FLIP_KVM 0x3201 -@@ -1405,6 +1408,9 @@ +@@ -1407,6 +1410,9 @@ #define USB_VENDOR_ID_XIAOMI 0x2717 #define USB_DEVICE_ID_MI_SILENT_MOUSE 0x5014 diff --git a/target/linux/bcm27xx/patches-6.6/950-0416-gpio-pca953x-Add-ti-tca9554-compatible-string.patch b/target/linux/bcm27xx/patches-6.6/950-0416-gpio-pca953x-Add-ti-tca9554-compatible-string.patch index b9ec31caa5ff54..aa11729b717915 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0416-gpio-pca953x-Add-ti-tca9554-compatible-string.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0416-gpio-pca953x-Add-ti-tca9554-compatible-string.patch @@ -10,7 +10,7 @@ Signed-off-by: Phil Elwell --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c -@@ -1345,6 +1345,7 @@ static const struct of_device_id pca953x +@@ -1347,6 +1347,7 @@ static const struct of_device_id pca953x { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, diff --git a/target/linux/bcm27xx/patches-6.6/950-0441-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch b/target/linux/bcm27xx/patches-6.6/950-0441-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch index 9aa16d6b2566a9..218ad5dbe5eac9 100644 --- a/target/linux/bcm27xx/patches-6.6/950-0441-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch +++ b/target/linux/bcm27xx/patches-6.6/950-0441-Bluetooth-hci_sync-Add-fallback-bd-address-prop.patch @@ -20,7 +20,7 @@ Signed-off-by: Phil Elwell --- a/net/bluetooth/hci_sync.c +++ b/net/bluetooth/hci_sync.c -@@ -4659,6 +4659,7 @@ static const struct { +@@ -4672,6 +4672,7 @@ static const struct { */ static int hci_dev_setup_sync(struct hci_dev *hdev) { @@ -28,7 +28,7 @@ Signed-off-by: Phil Elwell int ret = 0; bool invalid_bdaddr; size_t i; -@@ -4687,7 +4688,8 @@ static int hci_dev_setup_sync(struct hci +@@ -4700,7 +4701,8 @@ static int hci_dev_setup_sync(struct hci test_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks); if (!ret) { if (test_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks) && diff --git a/target/linux/bcm27xx/patches-6.6/950-0490-input-ads7846-Add-missing-spi_device_id-strings.patch b/target/linux/bcm27xx/patches-6.6/950-0490-input-ads7846-Add-missing-spi_device_id-strings.patch deleted file mode 100644 index 1b0a29a777f120..00000000000000 --- a/target/linux/bcm27xx/patches-6.6/950-0490-input-ads7846-Add-missing-spi_device_id-strings.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 3b391ceadf0d4ab5ce45f98d2f1d41f40e5aedd7 Mon Sep 17 00:00:00 2001 -From: Dave Stevenson -Date: Fri, 1 Sep 2023 12:23:30 +0100 -Subject: [PATCH 0490/1085] input: ads7846: Add missing spi_device_id strings - -The SPI core logs error messages if a compatible string device -name is not also present as an spi_device_id. - -No spi_device_id values are specified by the driver, therefore -we get 4 log lines every time it is loaded: -SPI driver ads7846 has no spi_device_id for ti,tsc2046 -SPI driver ads7846 has no spi_device_id for ti,ads7843 -SPI driver ads7846 has no spi_device_id for ti,ads7845 -SPI driver ads7846 has no spi_device_id for ti,ads7873 - -Add the spi_device_id values for these devices. - -Signed-off-by: Dave Stevenson ---- - drivers/input/touchscreen/ads7846.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - ---- a/drivers/input/touchscreen/ads7846.c -+++ b/drivers/input/touchscreen/ads7846.c -@@ -1114,6 +1114,16 @@ static const struct of_device_id ads7846 - }; - MODULE_DEVICE_TABLE(of, ads7846_dt_ids); - -+static const struct spi_device_id ads7846_spi_ids[] = { -+ { "tsc2046", 0 }, -+ { "ads7843", 0 }, -+ { "ads7845", 0 }, -+ { "ads7846", 0 }, -+ { "ads7873", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(spi, ads7846_spi_ids); -+ - static const struct ads7846_platform_data *ads7846_get_props(struct device *dev) - { - struct ads7846_platform_data *pdata; -@@ -1390,6 +1400,7 @@ static struct spi_driver ads7846_driver - .pm = pm_sleep_ptr(&ads7846_pm), - .of_match_table = ads7846_dt_ids, - }, -+ .id_table = ads7846_spi_ids, - .probe = ads7846_probe, - .remove = ads7846_remove, - }; diff --git a/target/linux/bcm27xx/patches-6.6/950-1141-fs-ntfs3-Fix-memory-corruption-when-page_size-change.patch b/target/linux/bcm27xx/patches-6.6/950-1141-fs-ntfs3-Fix-memory-corruption-when-page_size-change.patch index 113b3fdf53a6f6..b05a8276dfffb2 100644 --- a/target/linux/bcm27xx/patches-6.6/950-1141-fs-ntfs3-Fix-memory-corruption-when-page_size-change.patch +++ b/target/linux/bcm27xx/patches-6.6/950-1141-fs-ntfs3-Fix-memory-corruption-when-page_size-change.patch @@ -25,7 +25,7 @@ Signed-off-by: Dom Cobley --- a/fs/ntfs3/fslog.c +++ b/fs/ntfs3/fslog.c -@@ -3907,6 +3907,8 @@ check_restart_area: +@@ -3914,6 +3914,8 @@ check_restart_area: log->l_size = log->orig_file_size; log->page_size = norm_file_page(t32, &log->l_size, t32 == DefaultLogPageSize); diff --git a/target/linux/generic/config-6.6 b/target/linux/generic/config-6.6 index 20fe98099f286b..c6acff2e803dfe 100644 --- a/target/linux/generic/config-6.6 +++ b/target/linux/generic/config-6.6 @@ -122,6 +122,7 @@ CONFIG_32BIT=y # CONFIG_ADT7316 is not set # CONFIG_ADUX1020 is not set CONFIG_ADVISE_SYSCALLS=y +# CONFIG_ADV_SWBUTTON is not set # CONFIG_ADXL313_I2C is not set # CONFIG_ADXL313_SPI is not set # CONFIG_ADXL345_I2C is not set @@ -191,6 +192,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_APDS9960 is not set # CONFIG_APM8018X is not set # CONFIG_APM_EMULATION is not set +# CONFIG_APPLE_AIC is not set # CONFIG_APPLE_GMUX is not set # CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_APPLE_PROPERTIES is not set @@ -217,6 +219,7 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_ARCH_BCM_281XX is not set # CONFIG_ARCH_BCM_5301X is not set # CONFIG_ARCH_BCM_53573 is not set +# CONFIG_ARCH_BCM_63XX is not set # CONFIG_ARCH_BCM_CYGNUS is not set # CONFIG_ARCH_BCM_HR2 is not set # CONFIG_ARCH_BCM_IPROC is not set @@ -226,7 +229,9 @@ CONFIG_ARCH_BINFMT_ELF_STATE=y # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE is not set # CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG is not set # CONFIG_ARCH_DIGICOLOR is not set # CONFIG_ARCH_DMA_ADDR_T_64BIT is not set # CONFIG_ARCH_DOVE is not set @@ -252,6 +257,7 @@ CONFIG_ARCH_FORCE_MAX_ORDER=11 # CONFIG_ARCH_MA35 is not set # CONFIG_ARCH_MEDIATEK is not set # CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE is not set # CONFIG_ARCH_MILBEAUT is not set CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 @@ -293,6 +299,7 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_SOCFPGA is not set # CONFIG_ARCH_SPARX5 is not set # CONFIG_ARCH_SPRD is not set # CONFIG_ARCH_STI is not set @@ -310,6 +317,7 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 # CONFIG_ARCH_VIRT is not set # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_WANTS_NO_INSTR is not set # CONFIG_ARCH_WANTS_THP_SWAP is not set # CONFIG_ARCH_WM8505 is not set # CONFIG_ARCH_WM8750 is not set @@ -321,10 +329,12 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 # CONFIG_ARC_EMAC is not set # CONFIG_ARC_IRQ_NO_AUTOSAVE is not set # CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_4K_PAGES is not set # CONFIG_ARM64_64K_PAGES is not set # CONFIG_ARM64_AMU_EXTN is not set # CONFIG_ARM64_BTI is not set # CONFIG_ARM64_E0PD is not set +# CONFIG_ARM64_EPAN is not set # CONFIG_ARM64_ERRATUM_1024718 is not set # CONFIG_ARM64_ERRATUM_1165522 is not set # CONFIG_ARM64_ERRATUM_1286807 is not set @@ -361,6 +371,7 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_PSEUDO_NMI is not set # CONFIG_ARM64_PTR_AUTH is not set +# CONFIG_ARM64_PTR_AUTH_KERNEL is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_RELOC_TEST is not set # CONFIG_ARM64_SME is not set @@ -368,9 +379,11 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_TLB_RANGE is not set # CONFIG_ARM64_USE_LSE_ATOMICS is not set +# CONFIG_ARM64_VA_BITS_39 is not set # CONFIG_ARM64_VA_BITS_48 is not set # CONFIG_ARM_APPENDED_DTB is not set # CONFIG_ARM_ARCH_TIMER is not set +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set # CONFIG_ARM_CCI is not set # CONFIG_ARM_CCI400_PMU is not set @@ -412,6 +425,7 @@ CONFIG_ARM_DMA_MEM_BUFFERABLE=y # CONFIG_ARM_ERRATA_857272 is not set # CONFIG_ARM_FFA_TRANSPORT is not set CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_ARM_GT_INITIAL_PRESCALER_VAL is not set # CONFIG_ARM_KIRKWOOD_CPUFREQ is not set # CONFIG_ARM_KPROBES_TEST is not set # CONFIG_ARM_LPAE is not set @@ -424,7 +438,9 @@ CONFIG_ARM_MODULE_PLTS=y # CONFIG_ARM_PSCI_CPUIDLE is not set # CONFIG_ARM_PTDUMP_DEBUGFS is not set # CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_ARM_SCMI_POWER_CONTROL is not set # CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set # CONFIG_ARM_SCPI_PROTOCOL is not set # CONFIG_ARM_SDE_INTERFACE is not set # CONFIG_ARM_SMCCC_SOC_ID is not set @@ -540,6 +556,7 @@ CONFIG_ATM_CLIP_NO_ICMP=y # CONFIG_BACKLIGHT_PANDORA is not set # CONFIG_BACKLIGHT_PWM is not set # CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_RPI is not set # CONFIG_BACKLIGHT_SAHARA is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_BACKTRACE_VERBOSE is not set @@ -569,6 +586,7 @@ CONFIG_BASE_SMALL=0 # CONFIG_BAYCOM_SER_FDX is not set # CONFIG_BAYCOM_SER_HDX is not set # CONFIG_BCACHE is not set +# CONFIG_BCM2712_MIP is not set # CONFIG_BCM47XX is not set # CONFIG_BCM54140_PHY is not set # CONFIG_BCM63XX is not set @@ -580,6 +598,7 @@ CONFIG_BASE_SMALL=0 # CONFIG_BCM84881_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BCMA is not set +# CONFIG_BCMASP is not set # CONFIG_BCMA_DRIVER_GPIO is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMGENET is not set @@ -612,6 +631,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_BSG_COMMON is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_DM is not set # CONFIG_BLK_DEV_DRBD is not set @@ -761,6 +781,7 @@ CONFIG_BT_HCIUART_H4=y # CONFIG_BT_HCIUART_RTL is not set # CONFIG_BT_HCIVHCI is not set # CONFIG_BT_HIDP is not set +# CONFIG_BT_HS is not set # CONFIG_BT_LE is not set # CONFIG_BT_LEDS is not set CONFIG_BT_LE_L2CAP_ECRED=y @@ -773,10 +794,13 @@ CONFIG_BT_LE_L2CAP_ECRED=y CONFIG_BT_RFCOMM_TTY=y # CONFIG_BT_SELFTEST is not set # CONFIG_BT_VIRTIO is not set +# CONFIG_BUFFER_HEAD is not set CONFIG_BUG=y # CONFIG_BUG_ON_DATA_CORRUPTION is not set CONFIG_BUILDTIME_TABLE_SORT=y +# CONFIG_BUILD_BIN2C is not set CONFIG_BUILD_SALT="" +# CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC is not set # CONFIG_C2PORT is not set # CONFIG_CACHESTAT_SYSCALL is not set CONFIG_CACHE_L2X0_PMU=y @@ -862,6 +886,7 @@ CONFIG_CFG80211_HEADERS=y # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_QCOM_SMB2 is not set # CONFIG_CHARGER_QCOM_SMBB is not set +# CONFIG_CHARGER_RK817 is not set # CONFIG_CHARGER_RT9455 is not set # CONFIG_CHARGER_RT9467 is not set # CONFIG_CHARGER_RT9471 is not set @@ -905,6 +930,7 @@ CONFIG_CLS_U32_MARK=y # CONFIG_CM3605 is not set # CONFIG_CM36651 is not set # CONFIG_CMA is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMDLINE="" # CONFIG_CMDLINE_BOOL is not set # CONFIG_CMDLINE_EXTEND is not set @@ -922,6 +948,7 @@ CONFIG_CMDLINE="" # CONFIG_COMMON_CLK_CS2000_CP is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set # CONFIG_COMMON_CLK_IPROC is not set +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_MEDIATEK_FHCTL is not set # CONFIG_COMMON_CLK_MT6765 is not set @@ -939,6 +966,10 @@ CONFIG_CMDLINE="" # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_PXA is not set # CONFIG_COMMON_CLK_QCOM is not set +# CONFIG_COMMON_CLK_RK808 is not set +# CONFIG_COMMON_CLK_ROCKCHIP is not set +# CONFIG_COMMON_CLK_RP1 is not set +# CONFIG_COMMON_CLK_RP1_SDIO is not set # CONFIG_COMMON_CLK_RS9_PCIE is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI521XX is not set @@ -954,6 +985,8 @@ CONFIG_CMDLINE="" CONFIG_COMPACTION=y # CONFIG_COMPAL_LAPTOP is not set # CONFIG_COMPAT is not set +# CONFIG_COMPAT_32BIT_TIME is not set +# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set # CONFIG_COMPAT_BRK is not set # CONFIG_COMPILE_TEST is not set # CONFIG_CONFIGFS_FS is not set @@ -1015,8 +1048,8 @@ CONFIG_CRC32_SARWATE=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC_ITU_T is not set # CONFIG_CRC_T10DIF is not set -# CONFIG_CROS_HPS_I2C is not set # CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_CROS_HPS_I2C is not set CONFIG_CRYPTO=y # CONFIG_CRYPTO_842 is not set CONFIG_CRYPTO_ACOMP2=y @@ -1044,6 +1077,7 @@ CONFIG_CRYPTO_ALGAPI2=y # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S is not set # CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_BLAKE2B is not set @@ -1129,6 +1163,7 @@ CONFIG_CRYPTO_CTR=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_GENIV is not set CONFIG_CRYPTO_GHASH=y # CONFIG_CRYPTO_GHASH_ARM64_CE is not set # CONFIG_CRYPTO_GHASH_ARM_CE is not set @@ -1188,6 +1223,7 @@ CONFIG_CRYPTO_PCRYPT=y # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA256_ARM is not set # CONFIG_CRYPTO_SHA256_ARM64 is not set +# CONFIG_CRYPTO_SHA256_SSSE3 is not set # CONFIG_CRYPTO_SHA2_ARM64_CE is not set # CONFIG_CRYPTO_SHA2_ARM_CE is not set # CONFIG_CRYPTO_SHA3 is not set @@ -1235,6 +1271,7 @@ CONFIG_CRYPTO_SKCIPHER2=y # CONFIG_CS89x0 is not set # CONFIG_CS89x0_PLATFORM is not set # CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# CONFIG_CURRENT_POINTER_IN_TPIDRURO is not set # CONFIG_CUSE is not set # CONFIG_CW1200 is not set # CONFIG_CXD2880_SPI_DRV is not set @@ -1378,6 +1415,7 @@ CONFIG_DEVPORT=y # CONFIG_DMARD10 is not set # CONFIG_DMATEST is not set # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC is not set CONFIG_DMA_COHERENT_POOL=y CONFIG_DMA_DECLARE_COHERENT=y # CONFIG_DMA_ENGINE is not set @@ -1385,6 +1423,7 @@ CONFIG_DMA_DECLARE_COHERENT=y # CONFIG_DMA_JZ4780 is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_DMA_NONCOHERENT_MMAP=y +# CONFIG_DMA_NUMA_CMA is not set # CONFIG_DMA_RESTRICTED_POOL is not set # CONFIG_DMA_SHARED_BUFFER is not set # CONFIG_DM_CACHE is not set @@ -1453,7 +1492,9 @@ CONFIG_DQL=y # CONFIG_DRM_DP_AUX_CHARDEV is not set # CONFIG_DRM_DP_CEC is not set # CONFIG_DRM_DW_HDMI_CEC is not set +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_EXEC is not set # CONFIG_DRM_EXYNOS is not set # CONFIG_DRM_FBDEV_EMULATION is not set # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set @@ -1470,6 +1511,11 @@ CONFIG_DQL=y # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_SIL164 is not set # CONFIG_DRM_I915 is not set +# CONFIG_DRM_I915_REQUEST_TIMEOUT is not set +# CONFIG_DRM_IMX8QM_LDB is not set +# CONFIG_DRM_IMX8QXP_LDB is not set +# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set # CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ITE_IT6505 is not set # CONFIG_DRM_ITE_IT66121 is not set @@ -1510,6 +1556,7 @@ CONFIG_DQL=y # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set @@ -1527,8 +1574,8 @@ CONFIG_DQL=y # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35560 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set @@ -1573,10 +1620,12 @@ CONFIG_DQL=y # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set # CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +# CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set # CONFIG_DRM_PANFROST is not set @@ -1591,6 +1640,9 @@ CONFIG_DQL=y # CONFIG_DRM_RCAR_USE_LVDS is not set # CONFIG_DRM_RCAR_USE_MIPI_DSI is not set # CONFIG_DRM_ROCKCHIP is not set +# CONFIG_DRM_RP1_DPI is not set +# CONFIG_DRM_RP1_DSI is not set +# CONFIG_DRM_RP1_VEC is not set # CONFIG_DRM_SAMSUNG_DSIM is not set # CONFIG_DRM_SII902X is not set # CONFIG_DRM_SII9234 is not set @@ -1616,6 +1668,7 @@ CONFIG_DQL=y # CONFIG_DRM_TOSHIBA_TC358775 is not set # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_UDL is not set +# CONFIG_DRM_USE_DYNAMIC_DEBUG is not set # CONFIG_DRM_V3D is not set # CONFIG_DRM_VBOXVIDEO is not set # CONFIG_DRM_VC4_HDMI_CEC is not set @@ -1838,6 +1891,7 @@ CONFIG_ETHERNET=y CONFIG_ETHTOOL_NETLINK=y CONFIG_EVENTFD=y # CONFIG_EVM is not set +# CONFIG_EXCLUSIVE_SYSTEM_RAM is not set # CONFIG_EXFAT_FS is not set CONFIG_EXPERT=y CONFIG_EXPORTFS=y @@ -1906,9 +1960,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FB_CFB_IMAGEBLIT is not set # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CORE is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_DA8XX is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_DEFERRED_IO is not set # CONFIG_FB_DEVICE is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_FSL_DIU is not set @@ -1919,6 +1975,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FB_IBM_GXT4500 is not set # CONFIG_FB_IMSTT is not set # CONFIG_FB_IMX is not set +# CONFIG_FB_IOMEM_HELPERS is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_LE80578 is not set # CONFIG_FB_LITTLE_ENDIAN is not set @@ -1940,6 +1997,7 @@ CONFIG_FB_NOTIFY=y # CONFIG_FB_PXA is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_RIVA is not set +# CONFIG_FB_RPISENSE is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set @@ -2016,6 +2074,7 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_FONT_6x8 is not set # CONFIG_FONT_TER16x32 is not set # CONFIG_FORCEDETH is not set +# CONFIG_FORCE_MAX_ZONEORDER is not set # CONFIG_FORCE_NR_CPUS is not set CONFIG_FORTIFY_SOURCE=y # CONFIG_FPGA is not set @@ -2024,6 +2083,7 @@ CONFIG_FORTIFY_SOURCE=y # CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set # CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set # CONFIG_FRAME_POINTER is not set +# CONFIG_FRAME_WARN is not set # CONFIG_FREEZER is not set # CONFIG_FSCACHE is not set # CONFIG_FSI is not set @@ -2057,6 +2117,8 @@ CONFIG_FSNOTIFY=y # CONFIG_FUJITSU_ES is not set # CONFIG_FUJITSU_LAPTOP is not set # CONFIG_FUJITSU_TABLET is not set +# CONFIG_FUNCTION_ALIGNMENT is not set +# CONFIG_FUNCTION_ALIGNMENT_4B is not set # CONFIG_FUNCTION_ERROR_INJECTION is not set # CONFIG_FUNCTION_GRAPH_RETVAL is not set # CONFIG_FUNCTION_TRACER is not set @@ -2068,6 +2130,7 @@ CONFIG_FSNOTIFY=y # CONFIG_FUSION_SPI is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y +# CONFIG_FWNODE_MDIO is not set # CONFIG_FW_CFG_SYSFS is not set # CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set CONFIG_FW_LOADER=y @@ -2084,7 +2147,9 @@ CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_GACT_PROB=y # CONFIG_GADGET_UAC1 is not set # CONFIG_GAMEPORT is not set +CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y # CONFIG_GCC_PLUGINS is not set +# CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS is not set # CONFIG_GCOV is not set # CONFIG_GCOV_KERNEL is not set # CONFIG_GDB_SCRIPTS is not set @@ -2097,8 +2162,12 @@ CONFIG_GENERIC_HWEIGHT=y # CONFIG_GENERIC_IRQ_DEBUGFS is not set CONFIG_GENERIC_IRQ_IPI=y CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED is not set CONFIG_GENERIC_NET_UTILS=y # CONFIG_GENERIC_PHY is not set +# CONFIG_GENERIC_PINCONF is not set +# CONFIG_GENERIC_PINCTRL_GROUPS is not set +# CONFIG_GENERIC_PINMUX_FUNCTIONS is not set CONFIG_GENERIC_PTDUMP=y CONFIG_GENERIC_VDSO_TIME_NS=y # CONFIG_GENEVE is not set @@ -2171,8 +2240,10 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 # CONFIG_GPIO_PCI_IDIO_16 is not set # CONFIG_GPIO_PISOSR is not set # CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_PWM is not set # CONFIG_GPIO_RCAR is not set # CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_ROCKCHIP is not set # CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SCH311X is not set @@ -2204,6 +2275,7 @@ CONFIG_GPIO_SYSFS=y CONFIG_HARDENED_USERCOPY=y CONFIG_HARDEN_BRANCH_HISTORY=y # CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_HAS_IOPORT is not set # CONFIG_HAVE_ARM_ARCH_TIMER is not set # CONFIG_HCALL_STATS is not set # CONFIG_HDC100X is not set @@ -2363,8 +2435,11 @@ CONFIG_HIGH_RES_TIMERS=y # CONFIG_HOSTAP_CS is not set # CONFIG_HOSTAP_PCI is not set # CONFIG_HOSTAP_PLX is not set +# CONFIG_HOTPLUG_CORE_SYNC is not set +# CONFIG_HOTPLUG_CORE_SYNC_DEAD is not set # CONFIG_HOTPLUG_CPU is not set # CONFIG_HOTPLUG_PCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set # CONFIG_HP03 is not set # CONFIG_HP206C is not set CONFIG_HPET_MMAP_DEFAULT=y @@ -2538,6 +2613,7 @@ CONFIG_HZ_100=y # CONFIG_ICP10100 is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_ICS932S401 is not set +# CONFIG_IDE is not set # CONFIG_IDEAPAD_LAPTOP is not set # CONFIG_IDLE_PAGE_TRACKING is not set # CONFIG_IEEE802154 is not set @@ -2549,6 +2625,7 @@ CONFIG_HZ_100=y # CONFIG_IFB is not set # CONFIG_IGB is not set # CONFIG_IGBVF is not set +# CONFIG_IGB_HWMON is not set # CONFIG_IGC is not set # CONFIG_IIO is not set # CONFIG_IIO_BUFFER is not set @@ -2564,6 +2641,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IIO_KX022A_SPI is not set # CONFIG_IIO_MUX is not set # CONFIG_IIO_RESCALE is not set +# CONFIG_IIO_SCMI is not set # CONFIG_IIO_SIMPLE_DUMMY is not set # CONFIG_IIO_SSP_SENSORHUB is not set # CONFIG_IIO_ST_ACCEL_3AXIS is not set @@ -2587,6 +2665,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_IMX8QXP_ADC is not set # CONFIG_IMX93_ADC is not set # CONFIG_IMX_IPUV3_CORE is not set +# CONFIG_IMX_MU_MSI is not set # CONFIG_IMX_THERMAL is not set # CONFIG_INA2XX_ADC is not set # CONFIG_INDIRECT_PIO is not set @@ -2715,6 +2794,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INTEL_SOC_PMIC is not set # CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set # CONFIG_INTEL_SOC_PMIC_CHTWC is not set +# CONFIG_INTEL_TCC_COOLING is not set # CONFIG_INTEL_TH is not set # CONFIG_INTEL_VBTN is not set # CONFIG_INTEL_XWAY_PHY is not set @@ -2725,6 +2805,9 @@ CONFIG_INPUT_MISC=y # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_IIO is not set # CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set # CONFIG_IOMMU_SUPPORT is not set # CONFIG_IONIC is not set # CONFIG_IOSCHED_BFQ is not set @@ -2969,6 +3052,8 @@ CONFIG_KERNFS=y # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_KFENCE is not set # CONFIG_KGDB is not set +# CONFIG_KMAP_LOCAL is not set +# CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY is not set # CONFIG_KMX61 is not set # CONFIG_KPROBES is not set # CONFIG_KPROBES_SANITY_TEST is not set @@ -3191,7 +3276,9 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 # CONFIG_MACH_NINTENDO64 is not set # CONFIG_MACH_PIC32 is not set # CONFIG_MACH_REALTEK_RTL is not set +# CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set +# CONFIG_MACH_VR41XX is not set # CONFIG_MACINTOSH_DRIVERS is not set # CONFIG_MACSEC is not set # CONFIG_MACVLAN is not set @@ -3408,6 +3495,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_PCF50633 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RASPBERRYPI_POE_HAT is not set # CONFIG_MFD_RC5T583 is not set # CONFIG_MFD_RDC321X is not set # CONFIG_MFD_RETU is not set @@ -3417,6 +3505,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_RP1 is not set +# CONFIG_MFD_RPISENSE_CORE is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3424,6 +3514,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_RT5120 is not set # CONFIG_MFD_SEC_CORE is not set # CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SIMPLE_MFD_I2C is not set # CONFIG_MFD_SKY81452 is not set # CONFIG_MFD_SL28CPLD is not set # CONFIG_MFD_SM501 is not set @@ -3475,6 +3566,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MICROCHIP_T1S_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set +# CONFIG_MICROSOFT_MANA is not set # CONFIG_MIGRATION is not set CONFIG_MII=y # CONFIG_MIKROTIK is not set @@ -3488,6 +3580,7 @@ CONFIG_MII=y # CONFIG_MIPS_CDMM is not set # CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set # CONFIG_MIPS_CMDLINE_FROM_DTB is not set +# CONFIG_MIPS_CMP is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MIPS_CPS is not set # CONFIG_MIPS_ELF_APPENDED_DTB is not set @@ -3513,6 +3606,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_MISDN_SPEEDFAX is not set # CONFIG_MISDN_W6692 is not set CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y +# CONFIG_MITIGATION_RFDS is not set # CONFIG_MKISS is not set # CONFIG_MLX4_CORE is not set # CONFIG_MLX4_EN is not set @@ -3542,6 +3636,7 @@ CONFIG_MMC_BLOCK_MINORS=8 # CONFIG_MMC_CQHCI is not set # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_DW is not set +# CONFIG_MMC_DW_ROCKCHIP is not set # CONFIG_MMC_HSQ is not set # CONFIG_MMC_JZ4740 is not set # CONFIG_MMC_MTK is not set @@ -3581,6 +3676,7 @@ CONFIG_MMC_BLOCK_MINORS=8 CONFIG_MMU=y CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_MMU_GATHER_TABLE_FREE=y +# CONFIG_MMU_LAZY_TLB_REFCOUNT is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES=y # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set @@ -3790,6 +3886,7 @@ CONFIG_MTD_SPLIT_SUPPORT=y # CONFIG_MTD_UBI_NVMEM is not set # CONFIG_MTD_VIRT_CONCAT is not set # CONFIG_MTK_DEVAPC is not set +# CONFIG_MTK_MMC is not set # CONFIG_MTK_MMSYS is not set # CONFIG_MTK_T7XX is not set # CONFIG_MTK_THERMAL is not set @@ -3817,6 +3914,7 @@ CONFIG_MULTIUSER=y # CONFIG_NCN26000_PHY is not set # CONFIG_NE2000 is not set # CONFIG_NE2K_PCI is not set +# CONFIG_NEED_SG_DMA_FLAGS is not set CONFIG_NET=y # CONFIG_NETCONSOLE is not set # CONFIG_NETCONSOLE_EXTENDED_LOG is not set @@ -3907,6 +4005,7 @@ CONFIG_NETDEVICES=y # CONFIG_NETFILTER_XT_TARGET_TPROXY is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set # CONFIG_NETFS_STATS is not set +# CONFIG_NETFS_SUPPORT is not set # CONFIG_NETLABEL is not set # CONFIG_NETLINK_DIAG is not set # CONFIG_NETPOLL is not set @@ -3959,6 +4058,8 @@ CONFIG_NET_CORE=y # CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set # CONFIG_NET_DSA_MT7530 is not set +# CONFIG_NET_DSA_MT7530_MDIO is not set +# CONFIG_NET_DSA_MT7530_MMIO is not set # CONFIG_NET_DSA_MV88E6060 is not set # CONFIG_NET_DSA_MV88E6XXX is not set # CONFIG_NET_DSA_MV88E6XXX_PTP is not set @@ -3974,6 +4075,7 @@ CONFIG_NET_CORE=y # CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set # CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set # CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_DSA_COMMON is not set # CONFIG_NET_DSA_TAG_EDSA is not set # CONFIG_NET_DSA_TAG_GSWIP is not set # CONFIG_NET_DSA_TAG_HELLCREEK is not set @@ -3995,6 +4097,7 @@ CONFIG_NET_CORE=y # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set # CONFIG_NET_DSA_XRS700X_I2C is not set # CONFIG_NET_DSA_XRS700X_MDIO is not set +# CONFIG_NET_EGRESS is not set # CONFIG_NET_EMATCH is not set # CONFIG_NET_EMATCH_CANID is not set # CONFIG_NET_EMATCH_CMP is not set @@ -4009,6 +4112,7 @@ CONFIG_NET_EMATCH_STACK=32 # CONFIG_NET_FOU is not set # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_IFE is not set +# CONFIG_NET_INGRESS is not set # CONFIG_NET_IPGRE is not set CONFIG_NET_IPGRE_BROADCAST=y # CONFIG_NET_IPGRE_DEMUX is not set @@ -4078,7 +4182,7 @@ CONFIG_NET_VENDOR_AMAZON=y CONFIG_NET_VENDOR_AMD=y CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_NET_VENDOR_ARC=y -# CONFIG_NET_VENDOR_ASIX is not set +CONFIG_NET_VENDOR_ASIX=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_NET_VENDOR_BROADCOM=y CONFIG_NET_VENDOR_BROCADE=y @@ -4092,25 +4196,25 @@ CONFIG_NET_VENDOR_DAVICOM=y CONFIG_NET_VENDOR_DEC=y CONFIG_NET_VENDOR_DLINK=y CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_NET_VENDOR_ENGLEDER is not set +CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_FARADAY=y CONFIG_NET_VENDOR_FREESCALE=y CONFIG_NET_VENDOR_FUJITSU=y -# CONFIG_NET_VENDOR_FUNGIBLE is not set +CONFIG_NET_VENDOR_FUNGIBLE=y CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_HISILICON=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_IBM=y CONFIG_NET_VENDOR_INTEL=y -# CONFIG_NET_VENDOR_LITEX is not set +CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y CONFIG_NET_VENDOR_MICROSEMI=y -# CONFIG_NET_VENDOR_MICROSOFT is not set +CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y CONFIG_NET_VENDOR_NATSEMI=y CONFIG_NET_VENDOR_NETERION=y @@ -4147,6 +4251,7 @@ CONFIG_NET_VENDOR_XILINX=y CONFIG_NET_VENDOR_XIRCOM=y # CONFIG_NET_VRF is not set # CONFIG_NET_XGENE is not set +# CONFIG_NET_XGRESS is not set CONFIG_NEW_LEDS=y # CONFIG_NFC is not set # CONFIG_NFP is not set @@ -4248,6 +4353,8 @@ CONFIG_NF_TABLES_NETDEV=y # CONFIG_NI_XGE_MANAGEMENT_ENET is not set CONFIG_NLATTR=y # CONFIG_NLMON is not set +# CONFIG_NLM_XLP_BOARD is not set +# CONFIG_NLM_XLR_BOARD is not set # CONFIG_NLS is not set # CONFIG_NLS_ASCII is not set # CONFIG_NLS_CODEPAGE_1250 is not set @@ -4308,6 +4415,7 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NO_HZ is not set # CONFIG_NO_HZ_FULL is not set # CONFIG_NO_HZ_IDLE is not set +# CONFIG_NR_CPUS is not set # CONFIG_NS83820 is not set # CONFIG_NTB is not set # CONFIG_NTFS3_64BIT_CLUSTER is not set @@ -4327,6 +4435,8 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NVMEM_IMX_OCOTP is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_NINTENDO_OTP is not set +# CONFIG_NVMEM_RASPBERRYPI_OTP is not set # CONFIG_NVMEM_REBOOT_MODE is not set # CONFIG_NVMEM_RMEM is not set # CONFIG_NVMEM_SYSFS is not set @@ -4362,6 +4472,7 @@ CONFIG_OF_RESERVED_MEM=y # CONFIG_OPEN_DICE is not set # CONFIG_OPT3001 is not set # CONFIG_OPT4001 is not set +CONFIG_OPTIMIZE_INLINING=y # CONFIG_ORANGEFS_FS is not set # CONFIG_ORION_WATCHDOG is not set # CONFIG_OSF_PARTITION is not set @@ -4389,6 +4500,7 @@ CONFIG_PACKET=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_LESS_THAN_64KB is not set # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PALMAS_GPADC is not set # CONFIG_PANASONIC_LAPTOP is not set @@ -4482,6 +4594,8 @@ CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_CADENCE_HOST is not set # CONFIG_PCIE_CADENCE_PLAT_HOST is not set # CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_DW is not set +# CONFIG_PCIE_DW_HOST is not set # CONFIG_PCIE_DW_PLAT is not set # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCIE_ECRC is not set @@ -4491,6 +4605,7 @@ CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_MEDIATEK_GEN3 is not set # CONFIG_PCIE_MICROCHIP_HOST is not set # CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set # CONFIG_PCIE_XILINX is not set # CONFIG_PCIPCWATCHDOG is not set # CONFIG_PCI_ATMEL is not set @@ -4557,6 +4672,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PERF_EVENTS is not set # CONFIG_PERF_EVENTS_AMD_POWER is not set # CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_PER_VMA_LOCK is not set # CONFIG_PER_VMA_LOCK_STATS is not set # CONFIG_PHANTOM is not set # CONFIG_PHONET is not set @@ -4589,6 +4705,10 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_QCOM_USB_HS is not set # CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set +# CONFIG_PHY_ROCKCHIP_INNO_USB2 is not set +# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHY_TUSB1210 is not set # CONFIG_PHY_XGENE is not set @@ -4599,6 +4719,7 @@ CONFIG_PINCONF=y # CONFIG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set # CONFIG_PINCTRL_AXP209 is not set +# CONFIG_PINCTRL_BCM2712 is not set # CONFIG_PINCTRL_CEDARFORK is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EXYNOS is not set @@ -4618,6 +4739,7 @@ CONFIG_PINCONF=y # CONFIG_PINCTRL_MTK_V2 is not set # CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_PISTACHIO is not set +# CONFIG_PINCTRL_RP1 is not set # CONFIG_PINCTRL_SC7280 is not set # CONFIG_PINCTRL_SC8180X is not set # CONFIG_PINCTRL_SDX55 is not set @@ -4651,6 +4773,7 @@ CONFIG_PINMUX=y # CONFIG_PM_DEVFREQ is not set # CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set +# CONFIG_POSIX_CPU_TIMERS_TASK_WORK is not set # CONFIG_POSIX_MQUEUE is not set CONFIG_POSIX_TIMERS=y # CONFIG_POWERCAP is not set @@ -4705,8 +4828,10 @@ CONFIG_PPP_MULTILINK=y # CONFIG_PPTP is not set # CONFIG_PREEMPT is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_PREEMPT_BUILD is not set # CONFIG_PREEMPT_DYNAMIC is not set CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_NONE_BUILD is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PRESTERA is not set @@ -4752,6 +4877,7 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 # CONFIG_PTP_1588_CLOCK_KVM is not set # CONFIG_PTP_1588_CLOCK_MOCK is not set # CONFIG_PTP_1588_CLOCK_OCP is not set +# CONFIG_PTP_1588_CLOCK_OPTIONAL is not set # CONFIG_PTP_1588_CLOCK_PCH is not set # CONFIG_PTP_1588_CLOCK_VMW is not set # CONFIG_PVPANIC is not set @@ -4766,6 +4892,7 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 # CONFIG_PWM_MEDIATEK is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_RASPBERRYPI_POE is not set +# CONFIG_PWM_RP1 is not set # CONFIG_PWM_XILINX is not set CONFIG_PWRSEQ_EMMC=y # CONFIG_PWRSEQ_SD8787 is not set @@ -4787,6 +4914,7 @@ CONFIG_PWRSEQ_SIMPLE=y # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPMI_ADC5 is not set # CONFIG_QCOM_SPMI_ADC_TM5 is not set # CONFIG_QCOM_SPMI_IADC is not set @@ -4795,6 +4923,7 @@ CONFIG_PWRSEQ_SIMPLE=y # CONFIG_QCOM_SSC_BLOCK_BUS is not set # CONFIG_QED is not set # CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set # CONFIG_QLGE is not set @@ -4839,6 +4968,7 @@ CONFIG_RANDOMIZE_KSTACK_OFFSET=y # CONFIG_RANDSTRUCT_NONE is not set # CONFIG_RAPIDIO is not set # CONFIG_RAS is not set +# CONFIG_RASPBERRYPI_GPIOMEM is not set # CONFIG_RBTREE_TEST is not set # CONFIG_RCU_BOOST is not set # CONFIG_RCU_CPU_STALL_CPUTIME is not set @@ -4930,6 +5060,7 @@ CONFIG_RCU_STALL_COMMON=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2 is not set # CONFIG_REGULATOR_RT4801 is not set # CONFIG_REGULATOR_RT4803 is not set # CONFIG_REGULATOR_RT5190A is not set @@ -4977,6 +5108,7 @@ CONFIG_REISERFS_FS_XATTR=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_LANTIQ is not set # CONFIG_RESET_LPC18XX is not set +# CONFIG_RESET_MCHP_SPARX5 is not set # CONFIG_RESET_MESON is not set # CONFIG_RESET_PISTACHIO is not set # CONFIG_RESET_SIMPLE is not set @@ -5002,8 +5134,16 @@ CONFIG_RFKILL=y # CONFIG_RISCV_PMU_SBI is not set # CONFIG_RMI4_CORE is not set # CONFIG_RMNET is not set +# CONFIG_ROCKCHIP_DW_HDMI is not set # CONFIG_ROCKCHIP_ERRATUM_3588001 is not set +# CONFIG_ROCKCHIP_IODOMAIN is not set +# CONFIG_ROCKCHIP_IOMMU is not set +# CONFIG_ROCKCHIP_MBOX is not set # CONFIG_ROCKCHIP_PHY is not set +# CONFIG_ROCKCHIP_PM_DOMAINS is not set +# CONFIG_ROCKCHIP_SARADC is not set +# CONFIG_ROCKCHIP_THERMAL is not set +# CONFIG_ROCKCHIP_VOP2 is not set # CONFIG_ROCKER is not set # CONFIG_ROHM_BU27008 is not set # CONFIG_ROHM_BU27034 is not set @@ -5087,6 +5227,7 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_PS3 is not set # CONFIG_RTC_DRV_R7301 is not set # CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RK808 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_RS5C348 is not set # CONFIG_RTC_DRV_RS5C372 is not set @@ -5203,6 +5344,7 @@ CONFIG_SCHED_STACK_END_CHECK=y # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_CHELSIO_FCOE is not set +# CONFIG_SCSI_COMMON is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_CXGB3_ISCSI is not set # CONFIG_SCSI_CXGB4_ISCSI is not set @@ -5256,6 +5398,7 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_VIRTIO is not set # CONFIG_SCSI_WD719X is not set # CONFIG_SC_CAMCC_7180 is not set @@ -5483,6 +5626,7 @@ CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_SENSORS_Q54SJ108A2 is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SENSORS_RP1_ADC is not set # CONFIG_SENSORS_SBRMI is not set # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SCH5627 is not set @@ -5641,6 +5785,8 @@ CONFIG_SHMEM=y # CONFIG_SI7005 is not set # CONFIG_SI7020 is not set # CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_RHONE is not set @@ -5648,12 +5794,14 @@ CONFIG_SHMEM=y # CONFIG_SIBYTE_SWARM is not set CONFIG_SIGNALFD=y # CONFIG_SIGNED_PE_FILE_VERIFICATION is not set +# CONFIG_SIMPLE_PM_BUS is not set # CONFIG_SIOX is not set # CONFIG_SIS190 is not set # CONFIG_SIS900 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set # CONFIG_SKY2_DEBUG is not set +# CONFIG_SLAB is not set # CONFIG_SLAB_DEPRECATED is not set CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y @@ -5670,6 +5818,7 @@ CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_SLUB_TINY is not set # CONFIG_SMARTJOYPLUS_FF is not set # CONFIG_SMB_SERVER is not set +# CONFIG_SMC911X is not set # CONFIG_SMC9194 is not set # CONFIG_SMC91X is not set # CONFIG_SMP is not set @@ -5973,6 +6122,7 @@ CONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y # CONFIG_SND_SOC_LPASS_TX_MACRO is not set # CONFIG_SND_SOC_LPASS_VA_MACRO is not set # CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_MA120X0P is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set @@ -6151,6 +6301,7 @@ CONFIG_SND_X86=y # CONFIG_SNI_RM is not set # CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set # CONFIG_SOCK_CGROUP_DATA is not set +# CONFIG_SOCK_RX_QUEUE_MAPPING is not set # CONFIG_SOC_AM33XX is not set # CONFIG_SOC_AM43XX is not set # CONFIG_SOC_BRCMSTB is not set @@ -6176,14 +6327,15 @@ CONFIG_SND_X86=y # CONFIG_SPI is not set # CONFIG_SPINLOCK_TEST is not set # CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_ALTERA_CORE is not set # CONFIG_SPI_AMD is not set # CONFIG_SPI_AU1550 is not set # CONFIG_SPI_AX88796C is not set # CONFIG_SPI_AXI_SPI_ENGINE is not set # CONFIG_SPI_BCM2835 is not set # CONFIG_SPI_BCM63XX_HSSPI is not set -# CONFIG_SPI_BCM_QSPI is not set # CONFIG_SPI_BCMBCA_HSSPI is not set +# CONFIG_SPI_BCM_QSPI is not set # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set @@ -6218,6 +6370,7 @@ CONFIG_SND_X86=y # CONFIG_SPI_PXA2XX_PCI is not set # CONFIG_SPI_QCOM_QSPI is not set # CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_ROCKCHIP_SFC is not set # CONFIG_SPI_S3C64XX is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set @@ -6238,16 +6391,20 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_SPS30_SERIAL is not set CONFIG_SQUASHFS=y # CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y # CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y # CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE is not set +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set CONFIG_SQUASHFS_EMBEDDED=y # CONFIG_SQUASHFS_FILE_CACHE is not set CONFIG_SQUASHFS_FILE_DIRECT=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_SQUASHFS_LZ4 is not set # CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y # CONFIG_SQUASHFS_XATTR is not set CONFIG_SQUASHFS_XZ=y # CONFIG_SQUASHFS_ZLIB is not set @@ -6349,6 +6506,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TARGET_CORE is not set # CONFIG_TASKSTATS is not set # CONFIG_TASKS_RCU is not set +# CONFIG_TASKS_TRACE_RCU_READ_MB is not set # CONFIG_TASK_XACCT is not set # CONFIG_TC35815 is not set # CONFIG_TCG_ATMEL is not set @@ -6452,6 +6610,7 @@ CONFIG_TEXTSEARCH=y # CONFIG_THERMAL_STATISTICS is not set # CONFIG_THERMAL_WRITABLE_TRIPS is not set # CONFIG_THINKPAD_ACPI is not set +# CONFIG_THREAD_INFO_IN_TASK is not set # CONFIG_THRUSTMASTER_FF is not set # CONFIG_THUMB2_KERNEL is not set # CONFIG_THUNDER_NIC_BGX is not set @@ -6665,6 +6824,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_TRACING_SUPPORT=y CONFIG_TRAD_SIGNALS=y # CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_TRANS_TABLE is not set # CONFIG_TREE_RCU is not set # CONFIG_TRIM_UNUSED_KSYMS is not set # CONFIG_TRUSTED_FOUNDATIONS is not set @@ -6691,6 +6851,7 @@ CONFIG_TTY=y # CONFIG_TXGBE is not set # CONFIG_TYPEC is not set # CONFIG_TYPEC_DP_ALTMODE is not set +# CONFIG_TYPEC_MUX_GPIO_SBU is not set # CONFIG_TYPEC_TCPM is not set # CONFIG_TYPEC_UCSI is not set # CONFIG_TYPHOON is not set @@ -6760,8 +6921,8 @@ CONFIG_USB_BELKIN=y # CONFIG_USB_CDNS3 is not set # CONFIG_USB_CDNS3_IMX is not set # CONFIG_USB_CDNS3_PCI_WRAP is not set -# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_CDNSP_PCI is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_CHAOSKEY is not set # CONFIG_USB_CHIPIDEA is not set # CONFIG_USB_CHIPIDEA_GENERIC is not set @@ -6798,6 +6959,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_EHCI_HCD_AT91 is not set # CONFIG_USB_EHCI_HCD_OMAP is not set # CONFIG_USB_EHCI_HCD_PPC_OF is not set +# CONFIG_USB_EHCI_MSM is not set # CONFIG_USB_EHCI_MV is not set CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y @@ -6808,6 +6970,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_ETH is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_FOTG210 is not set # CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_FOTG210_UDC is not set # CONFIG_USB_FSL_USB2 is not set @@ -7126,6 +7289,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VHOST_VSOCK is not set # CONFIG_VIA_RHINE is not set # CONFIG_VIA_VELOCITY is not set +# CONFIG_VIDEO_AD5398 is not set # CONFIG_VIDEO_AD5820 is not set # CONFIG_VIDEO_ADP1653 is not set # CONFIG_VIDEO_ADV7170 is not set @@ -7143,22 +7307,28 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_AK881X is not set # CONFIG_VIDEO_AM437X_VPFE is not set # CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_ARDUCAM_64MP is not set +# CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set # CONFIG_VIDEO_ASPEED is not set # CONFIG_VIDEO_ATMEL_ISC is not set # CONFIG_VIDEO_ATMEL_ISI is not set # CONFIG_VIDEO_AU0828 is not set # CONFIG_VIDEO_BCM2835 is not set +# CONFIG_VIDEO_BCM2835_UNICAM is not set # CONFIG_VIDEO_BT819 is not set # CONFIG_VIDEO_BT848 is not set # CONFIG_VIDEO_BT856 is not set # CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_BU64754 is not set # CONFIG_VIDEO_CADENCE_CSI2RX is not set # CONFIG_VIDEO_CADENCE_CSI2TX is not set # CONFIG_VIDEO_CAFE_CCIC is not set # CONFIG_VIDEO_CAMERA_SENSOR is not set # CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_CMDLINE is not set # CONFIG_VIDEO_COBALT is not set # CONFIG_VIDEO_CODA is not set +# CONFIG_VIDEO_CODEC_BCM2835 is not set # CONFIG_VIDEO_CS3308 is not set # CONFIG_VIDEO_CS5345 is not set # CONFIG_VIDEO_CS53L32A is not set @@ -7181,6 +7351,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set +# CONFIG_VIDEO_HANTRO_ROCKCHIP is not set # CONFIG_VIDEO_HDPVR is not set # CONFIG_VIDEO_HEXIUM_GEMINI is not set # CONFIG_VIDEO_HEXIUM_ORION is not set @@ -7200,14 +7371,20 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_IMX335 is not set # CONFIG_VIDEO_IMX355 is not set # CONFIG_VIDEO_IMX412 is not set +# CONFIG_VIDEO_IMX415 is not set +# CONFIG_VIDEO_IMX477 is not set +# CONFIG_VIDEO_IMX519 is not set +# CONFIG_VIDEO_IMX708 is not set # CONFIG_VIDEO_IMX7_CSI is not set # CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set # CONFIG_VIDEO_IMX8_ISI is not set # CONFIG_VIDEO_IMX8_JPEG is not set # CONFIG_VIDEO_IMX_MIPI_CSIS is not set # CONFIG_VIDEO_IMX_PXP is not set +# CONFIG_VIDEO_IRS1125 is not set # CONFIG_VIDEO_IR_I2C is not set # CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_ISP_BCM2835 is not set # CONFIG_VIDEO_IVTV is not set # CONFIG_VIDEO_KS0127 is not set # CONFIG_VIDEO_LM3560 is not set @@ -7230,13 +7407,16 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_OMAP2_VOUT is not set # CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV08D10 is not set +# CONFIG_VIDEO_OV08X40 is not set # CONFIG_VIDEO_OV13858 is not set # CONFIG_VIDEO_OV13B10 is not set +# CONFIG_VIDEO_OV2311 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set # CONFIG_VIDEO_OV2685 is not set # CONFIG_VIDEO_OV2740 is not set +# CONFIG_VIDEO_OV4689 is not set # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set @@ -7245,6 +7425,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_OV5675 is not set # CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV64A40 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV7640 is not set @@ -7252,12 +7433,14 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_OV772X is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV8858 is not set # CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9282 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV9734 is not set # CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set # CONFIG_VIDEO_RCAR_CSI2 is not set # CONFIG_VIDEO_RCAR_ISP is not set # CONFIG_VIDEO_RCAR_VIN is not set @@ -7265,6 +7448,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_ROCKCHIP_ISP1 is not set +# CONFIG_VIDEO_RP1_CFE is not set # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set @@ -7281,6 +7465,7 @@ CONFIG_VHOST_MENU=y # CONFIG_VIDEO_SONY_BTF_MPX is not set # CONFIG_VIDEO_STK1160 is not set # CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_ST_VGXY61 is not set # CONFIG_VIDEO_SUN4I_CSI is not set # CONFIG_VIDEO_SUN6I_CSI is not set # CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set @@ -7479,6 +7664,7 @@ CONFIG_XFRM=y # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_XIP_KERNEL is not set # CONFIG_XMON is not set +# CONFIG_XXHASH is not set CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_ARM is not set # CONFIG_XZ_DEC_ARMTHUMB is not set @@ -7507,6 +7693,7 @@ CONFIG_XZ_DEC=y # CONFIG_ZLIB_DEFLATE is not set # CONFIG_ZLIB_INFLATE is not set CONFIG_ZONE_DMA=y +# CONFIG_ZONE_DMA32 is not set # CONFIG_ZOPT2201 is not set # CONFIG_ZPA2326 is not set # CONFIG_ZPOOL is not set diff --git a/target/linux/generic/hack-6.6/253-ksmbd-config.patch b/target/linux/generic/hack-6.6/253-ksmbd-config.patch index 298a0787b7c8f7..b200d2ce60f114 100644 --- a/target/linux/generic/hack-6.6/253-ksmbd-config.patch +++ b/target/linux/generic/hack-6.6/253-ksmbd-config.patch @@ -21,7 +21,7 @@ Subject: [PATCH] Kconfig: add tristate for OID and ASNI string that can be interpreted by the ASN.1 stream decoder and used to --- a/lib/Kconfig +++ b/lib/Kconfig -@@ -647,7 +647,7 @@ config LIBFDT +@@ -641,7 +641,7 @@ config LIBFDT bool config OID_REGISTRY diff --git a/target/linux/generic/hack-6.6/902-debloat_proc.patch b/target/linux/generic/hack-6.6/902-debloat_proc.patch index 559d4032429eb3..bf14d959991ecd 100644 --- a/target/linux/generic/hack-6.6/902-debloat_proc.patch +++ b/target/linux/generic/hack-6.6/902-debloat_proc.patch @@ -29,7 +29,7 @@ Signed-off-by: Felix Fietkau --- a/fs/locks.c +++ b/fs/locks.c -@@ -2897,6 +2897,8 @@ static const struct seq_operations locks +@@ -2895,6 +2895,8 @@ static const struct seq_operations locks static int __init proc_locks_init(void) { diff --git a/target/linux/generic/hack-6.6/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch b/target/linux/generic/hack-6.6/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch deleted file mode 100644 index 1c5fb11ff540cd..00000000000000 --- a/target/linux/generic/hack-6.6/930-Revert-Revert-Revert-driver-core-Set-fw_devlink-on-b.patch +++ /dev/null @@ -1,30 +0,0 @@ -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Tue, 19 Jul 2022 06:17:48 +0200 -Subject: [PATCH] Revert "Revert "Revert "driver core: Set fw_devlink=on by - default""" -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This reverts commit ea718c699055c8566eb64432388a04974c43b2ea. - -With of_platform_populate() called for MTD partitions that commit breaks -probing devices which reference MTD in device tree. - -Link: https://lore.kernel.org/all/696cb2da-20b9-b3dd-46d9-de4bf91a1506@gmail.com/T/#u -Signed-off-by: Rafał Miłecki ---- - drivers/base/core.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/base/core.c -+++ b/drivers/base/core.c -@@ -1657,7 +1657,7 @@ static void device_links_purge(struct de - #define FW_DEVLINK_FLAGS_RPM (FW_DEVLINK_FLAGS_ON | \ - DL_FLAG_PM_RUNTIME) - --static u32 fw_devlink_flags = FW_DEVLINK_FLAGS_ON; -+static u32 fw_devlink_flags = FW_DEVLINK_FLAGS_PERMISSIVE; - static int __init fw_devlink_setup(char *arg) - { - if (!arg) diff --git a/target/linux/mediatek/patches-6.6/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/target/linux/mediatek/patches-6.6/432-drivers-spi-Add-support-for-dynamic-calibration.patch index 7ad07c3583716c..19fe984aa6179b 100644 --- a/target/linux/mediatek/patches-6.6/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ b/target/linux/mediatek/patches-6.6/432-drivers-spi-Add-support-for-dynamic-calibration.patch @@ -224,7 +224,7 @@ Signed-off-by: SkyLake.Huang int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); /* -@@ -1600,6 +1639,9 @@ spi_register_board_info(struct spi_board +@@ -1601,6 +1640,9 @@ spi_register_board_info(struct spi_board { return 0; } #endif diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile index 26af6855ac633b..0247b1abd43268 100644 --- a/target/linux/rockchip/Makefile +++ b/target/linux/rockchip/Makefile @@ -15,7 +15,7 @@ endef include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug +DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug kmod-thermal KERNELNAME:=Image dtbs diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index ef894610560f26..ff30e920c5a360 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -8,25 +8,52 @@ boardname="${board##*,}" board_config_update case $board in -friendlyarm,nanopi-r2c|\ -friendlyarm,nanopi-r2c-plus|\ -friendlyarm,nanopi-r2s|\ -friendlyarm,nanopi-r4s|\ -friendlyarm,nanopi-r4s-enterprise|\ -xunlong,orangepi-r1-plus|\ -xunlong,orangepi-r1-plus-lts) +friendlyarm,nanopi-neo3) + ucidef_set_led_netdev "stat" "STAT" "$boardname:green:stat" "eth0" + ;; +friendlyarm,nanopi-r2s) + ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0" + ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1" + ;; +friendlyarm,nanopi-r4s) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" ;; -friendlyarm,nanopi-r5c) +friendlyelec,nanopi-r5c) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" - ucidef_set_led_netdev "wlan" "WLAN" "green:wlan" "phy0-ap0" + ucidef_set_led_netdev "wlan" "WL" "green:wlan" "phy0-ap0" + ;; +friendlyelec,nanopi-r5s) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" + ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1" + ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2" ;; -friendlyarm,nanopi-r5s) +friendlyelec,nanopi-r6c) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" - ucidef_set_led_netdev "lan1" "LAN1" "green:lan-1" "eth1" - ucidef_set_led_netdev "lan2" "LAN2" "green:lan-2" "eth2" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1" + ucidef_set_led_netdev "led1" "LED1" "green:led1" "eth2" + ;; +friendlyelec,nanopi-r6s) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth2" + ucidef_set_led_netdev "lan2" "LAN2" "green:lan1" "eth0" + ;; +friendlyelec,nanopi-r6c-plus) + ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth2" + ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" + ucidef_set_led_netdev "lan2" "LAN2" "green:lan1" "eth1" + ;; +pine64,quartz64-a) + ucidef_set_led_netdev "lan" "LAN" "work-led" "br-lan" + ;; +radxa,rock3a) + ucidef_set_led_netdev "lan" "LAN" "user-led" "br-lan" + ;; +rockchip,rk3568-bpi-r2pro|\ +sinovoip,rk3568-bpi-r2pro) + ucidef_set_led_netdev "wan" "WAN" "blue:status" "eth0" + ucidef_set_led_netdev "lan" "LAN" "green:power" "eth1" ;; esac diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 8729bd52f22600..ab83cf1fc455fb 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -7,31 +7,72 @@ rockchip_setup_interfaces() local board="$1" case "$board" in - friendlyarm,nanopi-r2c|\ - friendlyarm,nanopi-r2c-plus|\ friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s|\ - friendlyarm,nanopi-r4s-enterprise|\ - xunlong,orangepi-r1-plus|\ - xunlong,orangepi-r1-plus-lts) + friendlyarm,nanopi-r4s) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; - friendlyarm,nanopi-r5c|\ - radxa,e25) + friendlyelec,nanopi-r5c) ucidef_set_interfaces_lan_wan 'eth0' 'eth1' ;; - friendlyarm,nanopi-r5s) + friendlyelec,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; + friendlyelec,nanopi-r6c) + ucidef_set_interfaces_lan_wan 'eth1' 'eth0' + ;; + friendlyelec,nanopi-r6s) + ucidef_set_interfaces_lan_wan 'eth0 eth1' 'eth2' + ;; + friendlyelec,nanopi-r6c-plus) + ucidef_set_interfaces_lan_wan 'eth0 eth1 eth3' 'eth2' + ;; + pine64,rockpro64|\ + pine64,rockpro64-v2.1|\ + pine64,quartz64-a|\ + radxa,rock3a) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; + rockchip,rk3588-orangepi-5-plus) + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' + ;; + rockchip,rk3568-bpi-r2pro|\ sinovoip,rk3568-bpi-r2pro) ucidef_set_interfaces_lan_wan 'lan0 lan1 lan2 lan3' 'eth0' ;; *) - ucidef_set_interface_lan 'eth0' + ucidef_set_interfaces_lan_wan 'eth0' 'eth1' ;; esac } +bpi_r2pro_generate_mac() +{ + local emmc_hash=$(sha256sum /sys/class/block/mmcblk*/device/cid) + local mac_base=$(macaddr_canonicalize "$(echo "${emmc_hash}" | dd bs=1 count=12 2>/dev/null)") + echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")" +} + +nanopi_r4s_get_mac() +{ + local interface=$1 + local eeprom_path="/sys/bus/i2c/devices/2-0051/eeprom" + local address + + if [ -f "$eeprom_path" ]; then + address=$(get_mac_binary "$eeprom_path" 0xfa) + if [ "$interface" = "lan" ]; then + address=$(macaddr_setbit_la "$address") + fi + else + address=$(macaddr_generate_from_mmc_cid mmcblk*) + if [ "$interface" = "lan" ]; then + address=$(macaddr_add "$address" 1) + fi + fi + + echo "$address" +} + rockchip_setup_macs() { local board="$1" @@ -40,30 +81,25 @@ rockchip_setup_macs() local label_mac="" case "$board" in - friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2s) wan_mac=$(macaddr_generate_from_mmc_cid mmcblk0) lan_mac=$(macaddr_add "$wan_mac" 1) ;; - friendlyarm,nanopi-r2c-plus|\ + friendlyelec,nanopi-r6c|\ + friendlyelec,nanopi-r6s|\ + friendlyelec,nanopi-r6c-plus|\ friendlyarm,nanopi-r4s|\ - friendlyarm,nanopi-r5s|\ - sinovoip,rk3568-bpi-r2pro) - wan_mac=$(macaddr_generate_from_mmc_cid mmcblk1) - lan_mac=$(macaddr_add "$wan_mac" 1) - ;; - friendlyarm,nanopi-r4s-enterprise) - wan_mac=$(get_mac_binary "/sys/bus/i2c/devices/2-0051/eeprom" 0xfa) - lan_mac=$(macaddr_setbit_la "$wan_mac") + rockchip,rk3588-orangepi-5-plus) + wan_mac=$(nanopi_r4s_get_mac wan) + lan_mac=$(nanopi_r4s_get_mac lan) ;; - friendlyarm,nanopi-r5c) - wan_mac=$(macaddr_generate_from_mmc_cid mmcblk*) + friendlyelec,nanopi-r5c|\ + friendlyelec,nanopi-r5s|\ + rockchip,rk3568-bpi-r2pro|\ + sinovoip,rk3568-bpi-r2pro) + wan_mac=$(bpi_r2pro_generate_mac) lan_mac=$(macaddr_add "$wan_mac" 1) ;; - xunlong,orangepi-r1-plus|\ - xunlong,orangepi-r1-plus-lts) - wan_mac=$(macaddr_add "$(cat /sys/class/net/eth1/address)" -1) - ;; esac [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 8bbce1c32857e4..a42fc5ef6bb2bd 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -29,30 +29,49 @@ set_interface_core() { } case "$(board_name)" in -friendlyarm,nanopi-r2c|\ -friendlyarm,nanopi-r2c-plus|\ -friendlyarm,nanopi-r2s|\ -radxa,cm3-io|\ -xunlong,orangepi-r1-plus|\ -xunlong,orangepi-r1-plus-lts) +friendlyarm,nanopi-r2s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb[0-9]+" ;; -friendlyarm,nanopi-r4s|\ -friendlyarm,nanopi-r4s-enterprise) +friendlyarm,nanopi-r4s) set_interface_core 10 "eth0" set_interface_core 20 "eth1" ;; -friendlyarm,nanopi-r5c|\ -radxa,e25|\ -sinovoip,rk3568-bpi-r2pro) +friendlyelec,nanopi-r5c) + set_interface_core 2 "eth0" + set_interface_core 4 "eth1" + ;; +friendlyelec,nanopi-r5s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" + set_interface_core 8 "eth2" ;; -friendlyarm,nanopi-r5s) +friendlyelec,nanopi-r6c) set_interface_core 2 "eth0" set_interface_core 4 "eth1" + ;; +friendlyelec,nanopi-r6s) + set_interface_core 1 "eth0" + set_interface_core 6 "eth1" set_interface_core 8 "eth2" ;; +friendlyelec,nanopi-r6c-plus) + set_interface_core 1 "eth0" + set_interface_core 4 "eth1" + set_interface_core 6 "eth2" + set_interface_core 8 "eth3" + ;; +rockchip,rk3568-bpi-r2pro) + set_interface_core 1 "eth0" + set_interface_core 3 "eth1" + ;; +sinovoip,rk3568-bpi-r2pro) + set_interface_core 1 "eth0" + set_interface_core 3 "eth1" + ;; +rockchip,rk3588-orangepi-5-plus) + set_interface_core 20 "eth0" + set_interface_core 40 "eth1" + ;; esac diff --git a/target/linux/rockchip/armv8/base-files/etc/init.d/resize-rootfs b/target/linux/rockchip/armv8/base-files/etc/init.d/resize-rootfs new file mode 100755 index 00000000000000..740b751499825a --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/etc/init.d/resize-rootfs @@ -0,0 +1,9 @@ +#!/bin/sh /etc/rc.common + +START=22 +start() { + rm -rf /etc/rc.d/S22resize-rootfs + #service resize-rootfs disable + /usr/bin/resize-rootfs.sh +} + diff --git a/target/linux/rockchip/armv8/base-files/etc/rc.d/S22resize-rootfs b/target/linux/rockchip/armv8/base-files/etc/rc.d/S22resize-rootfs new file mode 100755 index 00000000000000..051d001b6cbe2b --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/etc/rc.d/S22resize-rootfs @@ -0,0 +1 @@ +../init.d/resize-rootfs diff --git a/target/linux/rockchip/armv8/base-files/etc/uci-defaults/01_enable_packet_steering b/target/linux/rockchip/armv8/base-files/etc/uci-defaults/01_enable_packet_steering new file mode 100644 index 00000000000000..114c7e1a463f96 --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/etc/uci-defaults/01_enable_packet_steering @@ -0,0 +1,5 @@ +uci -q get network.globals.packet_steering > /dev/null || { + uci set network.globals='globals' + uci set network.globals.packet_steering=1 + uci commit network +} diff --git a/target/linux/rockchip/armv8/base-files/usr/bin/resize-rootfs.sh b/target/linux/rockchip/armv8/base-files/usr/bin/resize-rootfs.sh new file mode 100755 index 00000000000000..170c999ac0195a --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/usr/bin/resize-rootfs.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +FDISK=$(which fdisk) || { echo "E: You must have fdisk" && exit 1; } +LOSETUP=$(which losetup) || { echo "E: You must have losetup" && exit 1; } +roottype=$(findmnt -n -o SOURCE / -o FSTYPE) +case ${roottype} in + overlay) + FSCKEXT4=$(which fsck.ext4) || { echo "E: You must have fsck.ext4" && exit 1; } + RESIZE2FS=$(which resize2fs) || { echo "E: You must have resize2fs" && exit 1; } + rootsource=$(findmnt -n -o SOURCE / | sed 's~\[.*\]~~') # i.e. /dev/mmcblk0p2 + rootdevice=${rootsource%p*} # i.e. /dev/mmcblk0 + partitions=${rootsource##*p} + ;; + ext4) + FSCKEXT4=$(which fsck.ext4) || { echo "E: You must have fsck.ext4" && exit 1; } + RESIZE2FS=$(which resize2fs) || { echo "E: You must have resize2fs" && exit 1; } + rootsource=$(findmnt -n -o SOURCE / | sed 's~\[.*\]~~') # i.e. /dev/mmcblk0p2 + rootdevice=${rootsource%p*} # i.e. /dev/mmcblk0 + partitions=${rootsource##*p} + + # Resizing partitions + lastsector=$(${FDISK} -l ${rootdevice} |grep "Disk ${rootdevice}" |awk '{print $7}') + lastsector=$(( $lastsector - 1 )) + startfrom=$(${FDISK} -l ${rootdevice} |grep ${rootsource} |awk '{print $2}') + partend=$(${FDISK} -l ${rootdevice} |grep ${rootsource} |awk '{print $3}') + [[ $lastsector -eq $partend ]] && exit 0 + (echo d; echo $partitions; echo n; echo p; echo ; echo $startfrom; echo $lastsector ; echo w;) | fdisk $rootdevice + + # Start resizing filesystem + LOOP="$(losetup -f)" + ${LOSETUP} ${LOOP} ${rootsource} + ${FSCKEXT4} -y ${LOOP} + ${RESIZE2FS} ${LOOP} + reboot + ;; +esac + +exit 0 + diff --git a/target/linux/rockchip/armv8/config-6.6 b/target/linux/rockchip/armv8/config-6.6 index fb57fc62604f1d..979dcd44f0e333 100644 --- a/target/linux/rockchip/armv8/config-6.6 +++ b/target/linux/rockchip/armv8/config-6.6 @@ -1,4 +1,7 @@ CONFIG_64BIT=y +CONFIG_AHCI_DWC=y +# CONFIG_AIO is not set +CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y @@ -23,12 +26,11 @@ CONFIG_ARC_EMAC_CORE=y CONFIG_ARM64=y CONFIG_ARM64_4K_PAGES=y CONFIG_ARM64_CNP=y -CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1530923=y CONFIG_ARM64_ERRATUM_2051678=y -CONFIG_ARM64_ERRATUM_2054223=y -CONFIG_ARM64_ERRATUM_2067961=y CONFIG_ARM64_ERRATUM_2077057=y -CONFIG_ARM64_ERRATUM_2658417=y +CONFIG_ARM64_ERRATUM_3117295=y CONFIG_ARM64_ERRATUM_819472=y CONFIG_ARM64_ERRATUM_824069=y CONFIG_ARM64_ERRATUM_826319=y @@ -43,49 +45,48 @@ CONFIG_ARM64_PAN=y CONFIG_ARM64_PA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_PTR_AUTH_KERNEL=y CONFIG_ARM64_RAS_EXTN=y -CONFIG_ARM64_SME=y CONFIG_ARM64_SVE=y +# CONFIG_ARM64_SW_TTBR0_PAN is not set CONFIG_ARM64_TAGGED_ADDR_ABI=y CONFIG_ARM64_VA_BITS=48 -# CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y -CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y +CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER=y CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_ARM_FFA_SMCCC=y +CONFIG_ARM_FFA_TRANSPORT=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ITS_PCI=y CONFIG_ARM_MHU=y -CONFIG_ARM_MHU_V2=y +# CONFIG_ARM_MHU_V2 is not set CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set +CONFIG_ARM_ROCKCHIP_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_POWER_CONTROL=y CONFIG_ARM_SCMI_POWER_DOMAIN=y CONFIG_ARM_SCMI_PROTOCOL=y -# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y CONFIG_ARM_SCMI_TRANSPORT_SMC=y CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_ARM_SMMU=y -CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y -# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set -CONFIG_ARM_SMMU_V3=y -# CONFIG_ARM_SMMU_V3_SVA is not set +CONFIG_ARM_SMCCC_SOC_ID=y +CONFIG_ATA=y +CONFIG_ATA_GENERIC=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GPIO=y @@ -97,11 +98,16 @@ CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_NVME=y CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BRCMSTB_GISB_ARB=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y @@ -112,7 +118,6 @@ CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CHARGER_GPIO=y -# CONFIG_CHARGER_RK817 is not set CONFIG_CLKSRC_MMIO=y CONFIG_CLK_PX30=y CONFIG_CLK_RK3308=y @@ -127,19 +132,17 @@ CONFIG_CMA_ALIGNMENT=8 CONFIG_CMA_AREAS=7 # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_MBYTES=5 # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SYSFS is not set CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_ROCKCHIP=y CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONFIGFS_FS=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_CONTEXT_TRACKING=y @@ -161,49 +164,74 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_MENU=y CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -CONFIG_CPU_ISOLATION=y CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_CPU_PM=y CONFIG_CPU_RMAP=y CONFIG_CPU_THERMAL=y CONFIG_CRASH_CORE=y -CONFIG_CRASH_DUMP=y CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y CONFIG_CRC64=y CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC7=y +CONFIG_CRC_ITU_T=y CONFIG_CRC_T10DIF=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DEV_ROCKCHIP is not set +# CONFIG_CRYPTO_DEV_ROCKCHIP2 is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_GENIV=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_LIB_GF128MUL=y CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_POLYVAL=y -CONFIG_CRYPTO_POLYVAL_ARM64_CE=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA3_ARM64=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SHA512_ARM64_CE=y CONFIG_CRYPTO_SM3=y -CONFIG_CRYPTO_SM3_NEON=y +CONFIG_CRYPTO_SM3_ARM64_CE=y +CONFIG_CRYPTO_SM3_GENERIC=y CONFIG_CRYPTO_SM4=y +CONFIG_CRYPTO_SM4_ARM64_CE=y CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y -CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y +CONFIG_CRYPTO_XTS=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y @@ -218,9 +246,17 @@ CONFIG_DMA_CMA=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_ENGINE=y CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y CONFIG_DMA_SHARED_BUFFER=y CONFIG_DNOTIFY=y +CONFIG_DRM=y +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_DEBUG_MODESET_LOCK=y +CONFIG_DRM_GEM_DMA_HELPER=y +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_MALI_DISPLAY=y +CONFIG_DRM_PANEL=y +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y CONFIG_DTC=y CONFIG_DT_IDLE_GENPD=y CONFIG_DT_IDLE_STATES=y @@ -239,7 +275,6 @@ CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXTCON=y CONFIG_F2FS_FS=y CONFIG_FANOTIFY=y -CONFIG_FHANDLE=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y # CONFIG_FORTIFY_SOURCE is not set @@ -253,7 +288,6 @@ CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_GCC10_NO_ARRAY_BOUNDS=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y @@ -277,12 +311,14 @@ CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_DWAPB=y @@ -291,18 +327,20 @@ CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_ROCKCHIP=y CONFIG_GPIO_SYSCON=y CONFIG_GRO_CELLS=y +# CONFIG_HARDENED_USERCOPY is not set CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y +CONFIG_HDMI=y CONFIG_HOTPLUG_CORE_SYNC=y CONFIG_HOTPLUG_CORE_SYNC_DEAD=y CONFIG_HOTPLUG_CPU=y CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_PCIE is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_HOTPLUG_PCI_SHPC=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_HWMON=y @@ -310,14 +348,19 @@ CONFIG_HWSPINLOCK=y CONFIG_HW_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_ROCKCHIP=y +CONFIG_HZ=300 +# CONFIG_HZ_100 is not set +CONFIG_HZ_300=y CONFIG_I2C=y +CONFIG_I2C_ALGOBIT=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_RK3X=y -CONFIG_IIO=y -# CONFIG_IIO_SCMI is not set +CONFIG_IGB=y +CONFIG_IGB_HWMON=y +CONFIG_IGC=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INDIRECT_PIO=y CONFIG_INPUT=y @@ -326,33 +369,22 @@ CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_KEYBOARD=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_MATRIXKMAP=y +CONFIG_INPUT_MOUSE=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_RK805_PWRKEY=y -# CONFIG_IOMMUFD is not set -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set -CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y -CONFIG_IOMMU_DMA=y -CONFIG_IOMMU_IOVA=y -CONFIG_IOMMU_IO_PGTABLE=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# CONFIG_IOMMU_IO_PGTABLE_DART is not set -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -CONFIG_IOMMU_SUPPORT=y +CONFIG_INPUT_SPARSEKMAP=y # CONFIG_IO_STRICT_DEVMEM is not set CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MSI_IOMMU=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JFFS2_ZLIB=y -CONFIG_JUMP_LABEL=y -CONFIG_KALLSYMS=y CONFIG_KCMP=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC_FILE=y @@ -363,6 +395,8 @@ CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBCRC32C=y CONFIG_LIBFDT=y CONFIG_LOCALVERSION_AUTO=y @@ -398,17 +432,39 @@ CONFIG_MMC_DW=y # CONFIG_MMC_DW_EXYNOS is not set # CONFIG_MMC_DW_HI3798CV200 is not set # CONFIG_MMC_DW_K3 is not set -# CONFIG_MMC_DW_PCI is not set +CONFIG_MMC_DW_PCI=y CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_HSQ=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_DWCMSHC=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=y +CONFIG_MMC_USDHI6ROL0=y +CONFIG_MMC_USHC=y CONFIG_MMU_LAZY_TLB_REFCOUNT=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MOTORCOMM_PHY=y +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set CONFIG_MQ_IOSCHED_DEADLINE=y # CONFIG_MTD_CFI is not set CONFIG_MTD_CMDLINE_PARTS=y @@ -418,7 +474,6 @@ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_FLAGS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NET_DEVLINK=y CONFIG_NET_DSA=y @@ -438,22 +493,21 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NOP_USB_XCEIV=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=256 +CONFIG_NR_CPUS=8 CONFIG_NVMEM=y CONFIG_NVMEM_LAYOUTS=y CONFIG_NVMEM_ROCKCHIP_EFUSE=y -# CONFIG_NVMEM_ROCKCHIP_OTP is not set +CONFIG_NVMEM_ROCKCHIP_OTP=y CONFIG_NVMEM_SYSFS=y CONFIG_NVME_CORE=y # CONFIG_NVME_HWMON is not set -# CONFIG_NVME_MULTIPATH is not set +CONFIG_NVME_MULTIPATH=y CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_DYNAMIC=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y @@ -469,11 +523,12 @@ CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 # CONFIG_PARTITION_ADVANCED is not set CONFIG_PARTITION_PERCPU=y +CONFIG_PATA_SIS=y CONFIG_PCI=y CONFIG_PCIEAER=y CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_DEFAULT is not set +CONFIG_PCIEASPM_PERFORMANCE=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set CONFIG_PCIEPORTBUS=y @@ -485,6 +540,9 @@ CONFIG_PCIE_ROCKCHIP_DW_HOST=y CONFIG_PCIE_ROCKCHIP_HOST=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y CONFIG_PCI_MSI=y CONFIG_PCI_STUB=y CONFIG_PCS_MTK_LYNXI=y @@ -496,17 +554,18 @@ CONFIG_PHYLIB_LEDS=y CONFIG_PHYLINK=y CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_PHY_ROCKCHIP_DP=y -# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set +CONFIG_PHY_ROCKCHIP_DPHY_RX0=y CONFIG_PHY_ROCKCHIP_EMMC=y -# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set -# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set +CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y +CONFIG_PHY_ROCKCHIP_INNO_HDMI=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_PCIE=y CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y +CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_PINCTRL=y CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=y @@ -514,9 +573,10 @@ CONFIG_PINCTRL_ROCKCHIP=y CONFIG_PL330_DMA=y CONFIG_PLATFORM_MHU=y CONFIG_PM=y +CONFIG_PMBUS=y CONFIG_PM_CLK=y CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_DEVFREQ_EVENT=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_PM_OPP=y @@ -524,22 +584,20 @@ CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POWER_RESET=y CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PPP=y +CONFIG_PPPOE=y +CONFIG_PPPOE_HASH_BITS=4 CONFIG_PPS=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y # CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PREEMPT_VOLUNTARY_BUILD=y CONFIG_PRINTK_TIME=y CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_VMCORE=y CONFIG_PTP_1588_CLOCK=y CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_PWM_SYSFS=y -# CONFIG_QFMT_V2 is not set CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_QUOTA=y @@ -557,28 +615,25 @@ CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_SPI=y CONFIG_REGULATOR=y -CONFIG_REGULATOR_ARM_SCMI=y +# CONFIG_REGULATOR_ARM_SCMI is not set CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_RK808=y -CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y CONFIG_RFS_ACCEL=y +CONFIG_ROCKCHIP_ERRATUM_3588001=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=y -CONFIG_ROCKCHIP_IOMMU=y CONFIG_ROCKCHIP_MBOX=y CONFIG_ROCKCHIP_PHY=y CONFIG_ROCKCHIP_PM_DOMAINS=y -# CONFIG_ROCKCHIP_SARADC is not set CONFIG_ROCKCHIP_THERMAL=y CONFIG_ROCKCHIP_TIMER=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPS=y -CONFIG_RSEQ=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_HYM8563=y CONFIG_RTC_DRV_RK808=y @@ -586,22 +641,33 @@ CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTC_NVMEM=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_HOST=y +CONFIG_SATA_PMP=y +CONFIG_SATA_SIS=y +CONFIG_SATA_VIA=y CONFIG_SCHED_MC=y CONFIG_SCSI=y CONFIG_SCSI_COMMON=y # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_PROC_FS is not set +# CONFIG_SCSI_SAS_ATA is not set CONFIG_SCSI_SAS_ATTRS=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SDIO_UART=y # CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_FINTEK=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_PCI=y @@ -617,9 +683,14 @@ CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIO=y CONFIG_SERIO_AMBAKMI=y CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_PCIPS2=y +CONFIG_SERIO_RAW=y CONFIG_SG_POOL=y +CONFIG_SLHC=y +CONFIG_SLUB_DEBUG=y CONFIG_SMP=y CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y @@ -632,16 +703,13 @@ CONFIG_SPI_DYNAMIC=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_ROCKCHIP=y -CONFIG_SPI_ROCKCHIP_SFC=y CONFIG_SPI_SPIDEV=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y # CONFIG_SQUASHFS_EMBEDDED is not set CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SRAM=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_PER_TASK=y -CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKDEPOT=y CONFIG_STACKTRACE=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y @@ -652,8 +720,6 @@ CONFIG_SWIOTLB=y CONFIG_SWPHY=y CONFIG_SYNC_FILE=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSFS_SYSCALL=y -# CONFIG_TEXTSEARCH is not set CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 @@ -679,7 +745,6 @@ CONFIG_TYPEC=y CONFIG_TYPEC_FUSB302=y # CONFIG_TYPEC_HD3SS3220 is not set # CONFIG_TYPEC_MUX_FSA4480 is not set -# CONFIG_TYPEC_MUX_GPIO_SBU is not set # CONFIG_TYPEC_MUX_NB7VPQ904M is not set # CONFIG_TYPEC_MUX_PI3USB30532 is not set # CONFIG_TYPEC_RT1719 is not set @@ -690,7 +755,6 @@ CONFIG_TYPEC_TCPM=y # CONFIG_TYPEC_WUSB3801 is not set # CONFIG_UCLAMP_TASK is not set # CONFIG_UEVENT_HELPER is not set -CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_USB=y CONFIG_USB_COMMON=y @@ -711,6 +775,10 @@ CONFIG_USB_ULPI_BUS=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USERIO=y +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y # CONFIG_VIRTIO_MENU is not set CONFIG_VMAP_STACK=y CONFIG_VM_EVENT_COUNTERS=y diff --git a/target/linux/rockchip/armv8/target.mk b/target/linux/rockchip/armv8/target.mk index 085b475c4b3129..536e0f1286aaf1 100644 --- a/target/linux/rockchip/armv8/target.mk +++ b/target/linux/rockchip/armv8/target.mk @@ -1,8 +1,8 @@ ARCH:=aarch64 SUBTARGET:=armv8 -BOARDNAME:=RK33xx/RK356x boards (64 bit) +BOARDNAME:=RK33/35xx boards (64 bit) define Target/Description - Build firmware image for Rockchip RK33xx devices. + Build firmware image for Rockchip RK33/35xx devices. This firmware features a 64 bit kernel. endef diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-common.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-common.dtsi new file mode 100644 index 00000000000000..57795ff1b0f010 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-common.dtsi @@ -0,0 +1,529 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "FriendlyElec boards based on Rockchip RK3588"; + compatible = "friendlyelec,nanopi6", + "rockchip,rk3588"; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_20: vcc5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single: rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,no-vlhash; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&u2phy0 { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts new file mode 100644 index 00000000000000..66ee2bb4620f69 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -0,0 +1,983 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "RK3588 OPi 5 Plus"; + compatible = "rockchip,rk3588-orangepi-5-plus", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_rgb>; + status = "okay"; + + blue_led@1 { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + + green_led@2 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 70 75 80 100>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm3 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + enable-active-low; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-low; + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc_pwr { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-func { + leds_rgb: leds-rgb { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m2_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi0 { + assigned-clocks = <&cru CLK_SPI0>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "disabled"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fudr_moden0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&spi4 { + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "disabled"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart9 { + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + status = "okay"; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + dr_mode = "otg"; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 00000000000000..3c4dd0aba34187 --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588-nanopi6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + ethernet0 = &gmac1; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-sys { + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "red:sys"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-wan { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "green:wan"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan_led: led-lan { + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "green:lan"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + led1_led: led-led1 { + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + label = "green:led1"; + pinctrl-names = "default"; + pinctrl-0 = <&led1_led_pin>; + }; + }; +}; + + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led1_led_pin: led1-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 00000000000000..a509d58e136c1b --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3588-nanopi6-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + ethernet0 = &gmac1; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-sys { + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "red:sys"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-wan { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "green:wan"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan_led: led-lan { + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "green:lan"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-lan2 { + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + label = "green:lan1"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; +}; + + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + eeprom@53 { + compatible = "microchip,24c02", "atmel,24c02"; + reg = <0x53>; + #address-cells = <2>; + #size-cells = <0>; + pagesize = <16>; + size = <256>; + + eui_48: eui-48@fa { + reg = <0xfa 0x06>; + }; + }; +}; diff --git a/target/linux/rockchip/image/Makefile b/target/linux/rockchip/image/Makefile index 5d90ef8cf835c6..e232166e51ee9b 100644 --- a/target/linux/rockchip/image/Makefile +++ b/target/linux/rockchip/image/Makefile @@ -21,7 +21,7 @@ endef define Build/boot-script # Make an U-boot image and copy it to the boot partition - mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),default).bootscript $@.boot/boot.scr + mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr endef define Build/pine64-img @@ -29,7 +29,7 @@ define Build/pine64-img # combining boot partition, root partition as well as the u-boot bootloader # Generate a new partition table in $@ with 32 MiB of - # alignment padding for the u-boot-rockchip.bin (idbloader + u-boot) to fit: + # alignment padding for the idbloader and u-boot to fit: # http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow # # U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage @@ -39,19 +39,17 @@ define Build/pine64-img $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \ 32768 - # Copy the u-boot-rockchip.bin to the image at sector 0x40 - dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot-rockchip.bin of="$@" seek=64 conv=notrunc + # Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000 + dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-idbloader.img of="$@" seek=64 conv=notrunc + dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc endef ### Devices ### define Device/Default PROFILES := Default KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb - BOOT_SCRIPT := IMAGES := sysupgrade.img.gz - IMAGE/sysupgrade.img.gz = boot-common | boot-script $$(BOOT_SCRIPT) | pine64-img | gzip | append-metadata DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1))) - UBOOT_DEVICE_NAME = $(lastword $(subst _, ,$(1)))-$$(SOC) endef include $(SUBTARGET).mk diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 23519b43ee21e1..e8c183df3f0c88 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -5,43 +5,31 @@ # FIT will be loaded at 0x02080000. Leave 16M for that, align it to 2M and load the kernel after it. KERNEL_LOADADDR := 0x03200000 +define Device/friendlyarm_nanopi-neo3 + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi NEO3 + SOC := rk3328 + UBOOT_DEVICE_NAME := nanopi-r2s-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata +endef +TARGET_DEVICES += friendlyarm_nanopi-neo3 + define Device/firefly_roc-rk3328-cc DEVICE_VENDOR := Firefly DEVICE_MODEL := ROC-RK3328-CC SOC := rk3328 DEVICE_DTS := rockchip/rk3328-roc-cc UBOOT_DEVICE_NAME := roc-cc-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata endef TARGET_DEVICES += firefly_roc-rk3328-cc -define Device/friendlyarm_nanopc-t4 - DEVICE_VENDOR := FriendlyARM - DEVICE_MODEL := NanoPC T4 - SOC := rk3399 - DEVICE_PACKAGES := kmod-brcmfmac brcmfmac-nvram-4356-sdio cypress-firmware-4356-sdio -endef -TARGET_DEVICES += friendlyarm_nanopc-t4 - -define Device/friendlyarm_nanopi-r2c - DEVICE_VENDOR := FriendlyARM - DEVICE_MODEL := NanoPi R2C - SOC := rk3328 - DEVICE_PACKAGES := kmod-usb-net-rtl8152 -endef -TARGET_DEVICES += friendlyarm_nanopi-r2c - -define Device/friendlyarm_nanopi-r2c-plus - DEVICE_VENDOR := FriendlyARM - DEVICE_MODEL := NanoPi R2C Plus - SOC := rk3328 - DEVICE_PACKAGES := kmod-usb-net-rtl8152 -endef -TARGET_DEVICES += friendlyarm_nanopi-r2c-plus - define Device/friendlyarm_nanopi-r2s DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi R2S SOC := rk3328 + UBOOT_DEVICE_NAME := nanopi-r2s-rk3328 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-usb-net-rtl8152 endef TARGET_DEVICES += friendlyarm_nanopi-r2s @@ -51,126 +39,125 @@ define Device/friendlyarm_nanopi-r4s DEVICE_MODEL := NanoPi R4S DEVICE_VARIANT := 4GB LPDDR4 SOC := rk3399 - DEVICE_PACKAGES := kmod-r8169 -endef -TARGET_DEVICES += friendlyarm_nanopi-r4s - -define Device/friendlyarm_nanopi-r4s-enterprise - DEVICE_VENDOR := FriendlyARM - DEVICE_MODEL := NanoPi R4S Enterprise Edition - DEVICE_VARIANT := 4GB LPDDR4 - SOC := rk3399 UBOOT_DEVICE_NAME := nanopi-r4s-rk3399 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-r8169 endef -TARGET_DEVICES += friendlyarm_nanopi-r4s-enterprise +TARGET_DEVICES += friendlyarm_nanopi-r4s -define Device/friendlyarm_nanopi-r5c - DEVICE_VENDOR := FriendlyARM +define Device/friendlyelec_nanopi-r5c + DEVICE_VENDOR := Friendlyelec DEVICE_MODEL := NanoPi R5C SOC := rk3568 - DEVICE_PACKAGES := kmod-r8169 kmod-rtw88-8822ce rtl8822ce-firmware wpad-basic-mbedtls + UBOOT_DEVICE_NAME := nanopi-r5c-rk3568 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-r8169 endef -TARGET_DEVICES += friendlyarm_nanopi-r5c +TARGET_DEVICES += friendlyelec_nanopi-r5c -define Device/friendlyarm_nanopi-r5s - DEVICE_VENDOR := FriendlyARM +define Device/friendlyelec_nanopi-r5s + DEVICE_VENDOR := Friendlyelec DEVICE_MODEL := NanoPi R5S SOC := rk3568 + UBOOT_DEVICE_NAME := nanopi-r5s-rk3568 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata DEVICE_PACKAGES := kmod-r8169 endef -TARGET_DEVICES += friendlyarm_nanopi-r5s +TARGET_DEVICES += friendlyelec_nanopi-r5s -define Device/pine64_rock64 - DEVICE_VENDOR := Pine64 - DEVICE_MODEL := Rock64 - SOC := rk3328 +define Device/friendlyelec_nanopi-r6c + DEVICE_VENDOR := Friendlyelec + DEVICE_MODEL := NanoPi R6C + SOC := rk3588s + UBOOT_DEVICE_NAME := nanopi-r6c-rk3588 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r6c | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += friendlyelec_nanopi-r6c + +define Device/friendlyelec_nanopi-r6c-plus + DEVICE_VENDOR := Friendlyelec + DEVICE_MODEL := NanoPi R6C Plus + SOC := rk3588s + UBOOT_DEVICE_NAME := nanopi-r6c-rk3588 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r6c | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += friendlyelec_nanopi-r6c-plus + +define Device/friendlyelec_nanopi-r6s + DEVICE_VENDOR := Friendlyelec + DEVICE_MODEL := NanoPi R6S + SOC := rk3588s + UBOOT_DEVICE_NAME := nanopi-r6s-rk3588 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r6c | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-r8169 endef -TARGET_DEVICES += pine64_rock64 +TARGET_DEVICES += friendlyelec_nanopi-r6s define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 SOC := rk3399 + UBOOT_DEVICE_NAME := rockpro64-rk3399 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata endef TARGET_DEVICES += pine64_rockpro64 -define Device/radxa_cm3-io - DEVICE_VENDOR := Radxa - DEVICE_MODEL := CM3 IO +define Device/pine64_quartz64-a + DEVICE_VENDOR := Pine64 + DEVICE_MODEL := QUARTZ64 SOC := rk3566 - DEVICE_DTS := rockchip/rk3566-radxa-cm3-io - UBOOT_DEVICE_NAME := radxa-cm3-io-rk3566 + SUPPORTED_DEVICES := pine64,quartz64-a + UBOOT_DEVICE_NAME := quartz64-a-rk3566 + IMAGE/sysupgrade.img.gz := boot-common | boot-script quartz64-a | pine64-img | gzip | append-metadata endef -TARGET_DEVICES += radxa_cm3-io - -define Device/radxa_e25 - DEVICE_VENDOR := Radxa - DEVICE_MODEL := E25 - SOC := rk3568 - DEVICE_DTS := rockchip/rk3568-radxa-e25 - BOOT_SCRIPT := radxa-e25 - UBOOT_DEVICE_NAME := radxa-e25-rk3568 - DEVICE_PACKAGES := kmod-r8169 kmod-ata-ahci-dwc -endef -TARGET_DEVICES += radxa_e25 +TARGET_DEVICES += pine64_quartz64-a define Device/radxa_rock-3a DEVICE_VENDOR := Radxa - DEVICE_MODEL := ROCK 3A + DEVICE_MODEL := ROCK3 Model A SOC := rk3568 - DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis + SUPPORTED_DEVICES := radxa,rock3a + UBOOT_DEVICE_NAME := rock-3a-rk3568 + IMAGE/sysupgrade.img.gz := boot-common | boot-script rock-3a | pine64-img | gzip | append-metadata endef TARGET_DEVICES += radxa_rock-3a -define Device/radxa_rock-pi-4a +define Device/radxa_rock-pi-4 DEVICE_VENDOR := Radxa - DEVICE_MODEL := ROCK Pi 4A + DEVICE_MODEL := ROCK Pi 4 + DEVICE_DTS := rockchip/rk3399-rock-pi-4b SOC := rk3399 - SUPPORTED_DEVICES := radxa,rockpi4a radxa,rockpi4 + SUPPORTED_DEVICES := radxa,rockpi4b UBOOT_DEVICE_NAME := rock-pi-4-rk3399 + IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := \ + brcmfmac-firmware-43456-sdio \ + brcmfmac-firmware-43456-sdio-rockpi-4 \ + kmod-brcmfmac wpad-openssl endef -TARGET_DEVICES += radxa_rock-pi-4a - -define Device/radxa_rock-pi-e - DEVICE_VENDOR := Radxa - DEVICE_MODEL := ROCK Pi E - SOC := rk3328 -endef -TARGET_DEVICES += radxa_rock-pi-e - -define Device/radxa_rock-pi-s - DEVICE_VENDOR := Radxa - DEVICE_MODEL := ROCK Pi S - SOC := rk3308 - DEVICE_DTS := rockchip/rk3308-rock-pi-s - BOOT_SCRIPT := rock-pi-s - UBOOT_DEVICE_NAME := rock-pi-s-rk3308 - DEVICE_PACKAGES := kmod-usb-net-cdc-ncm kmod-usb-net-rndis -endef -TARGET_DEVICES += radxa_rock-pi-s +TARGET_DEVICES += radxa_rock-pi-4 -define Device/sinovoip_bpi-r2-pro - DEVICE_VENDOR := Sinovoip +define Device/rockchip_bpi-r2-pro + DEVICE_VENDOR := Rockchip DEVICE_MODEL := Bananapi-R2 Pro SOC := rk3568 - SUPPORTED_DEVICES := sinovoip,rk3568-bpi-r2pro - DEVICE_PACKAGES := kmod-ata-ahci-dwc -endef -TARGET_DEVICES += sinovoip_bpi-r2-pro - -define Device/xunlong_orangepi-r1-plus - DEVICE_VENDOR := Xunlong - DEVICE_MODEL := Orange Pi R1 Plus - SOC := rk3328 - DEVICE_PACKAGES := kmod-usb-net-rtl8152 -endef -TARGET_DEVICES += xunlong_orangepi-r1-plus - -define Device/xunlong_orangepi-r1-plus-lts - DEVICE_VENDOR := Xunlong - DEVICE_MODEL := Orange Pi R1 Plus LTS - SOC := rk3328 - DEVICE_PACKAGES := kmod-usb-net-rtl8152 -endef -TARGET_DEVICES += xunlong_orangepi-r1-plus-lts + SUPPORTED_DEVICES := \ + sinovoip,rk3568-bpi-r2pro \ + rockchip,rk3568-bpi-r2pro + UBOOT_DEVICE_NAME := bpi-r2-pro-rk3568 + IMAGE/sysupgrade.img.gz := boot-common | boot-script quartz64-a | pine64-img | gzip | append-metadata +endef +TARGET_DEVICES += rockchip_bpi-r2-pro + +define Device/xunlong_orangepi-5-plus + DEVICE_VENDOR := XunLong + DEVICE_MODEL := RK3588 OPi 5 Plus + SOC := rk3588 + UBOOT_DEVICE_NAME := orangepi-5-plus-rk3588 + SUPPORTED_DEVICES := rockchip,rk3588-orangepi-5-plus + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r6c | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-r8169 +endef +TARGET_DEVICES += xunlong_orangepi-5-plus diff --git a/target/linux/rockchip/image/default.bootscript b/target/linux/rockchip/image/default.bootscript index cca0b8d4acff38..5aa7330cffb46c 100644 --- a/target/linux/rockchip/image/default.bootscript +++ b/target/linux/rockchip/image/default.bootscript @@ -1,4 +1,4 @@ -part uuid ${devtype} ${devnum}:2 uuid +part uuid mmc ${devnum}:2 uuid if test $stdout = 'serial@fe660000' ; then serial_addr=',0xfe660000'; @@ -10,6 +10,6 @@ fi; setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32${serial_addr} root=PARTUUID=${uuid} rw rootwait"; -load ${devtype} ${devnum}:1 ${kernel_addr_r} kernel.img +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/mmc.bootscript b/target/linux/rockchip/image/mmc.bootscript new file mode 100644 index 00000000000000..1e53200027adf0 --- /dev/null +++ b/target/linux/rockchip/image/mmc.bootscript @@ -0,0 +1,7 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait" + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/nanopi-r2s.bootscript b/target/linux/rockchip/image/nanopi-r2s.bootscript new file mode 100644 index 00000000000000..8f961d37329095 --- /dev/null +++ b/target/linux/rockchip/image/nanopi-r2s.bootscript @@ -0,0 +1,7 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait" + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/nanopi-r4s.bootscript b/target/linux/rockchip/image/nanopi-r4s.bootscript new file mode 100644 index 00000000000000..1e53200027adf0 --- /dev/null +++ b/target/linux/rockchip/image/nanopi-r4s.bootscript @@ -0,0 +1,7 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait" + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/nanopi-r5s.bootscript b/target/linux/rockchip/image/nanopi-r5s.bootscript new file mode 100644 index 00000000000000..6deafd70c16dab --- /dev/null +++ b/target/linux/rockchip/image/nanopi-r5s.bootscript @@ -0,0 +1,8 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait" + + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/nanopi-r6c.bootscript b/target/linux/rockchip/image/nanopi-r6c.bootscript new file mode 100644 index 00000000000000..17d9b680596eaf --- /dev/null +++ b/target/linux/rockchip/image/nanopi-r6c.bootscript @@ -0,0 +1,8 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfeb50000 root=PARTUUID=${uuid} rw rootwait" + + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/quartz64-a.bootscript b/target/linux/rockchip/image/quartz64-a.bootscript new file mode 100644 index 00000000000000..6deafd70c16dab --- /dev/null +++ b/target/linux/rockchip/image/quartz64-a.bootscript @@ -0,0 +1,8 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait" + + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/image/rock-3a.bootscript b/target/linux/rockchip/image/rock-3a.bootscript new file mode 100644 index 00000000000000..6deafd70c16dab --- /dev/null +++ b/target/linux/rockchip/image/rock-3a.bootscript @@ -0,0 +1,8 @@ +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait" + + +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +bootm ${kernel_addr_r} diff --git a/target/linux/rockchip/patches-6.6/006-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/006-rockchip-use-system-LED-for-OpenWrt.patch new file mode 100644 index 00000000000000..f2b358e40a8127 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/006-rockchip-use-system-LED-for-OpenWrt.patch @@ -0,0 +1,44 @@ +From 52e4a561560b0b4564329dc3771240c8e68ef48f Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Fri, 10 Jul 2020 21:38:20 +0200 +Subject: [PATCH 06/95] rockchip: use system LED for OpenWrt + +Use the SYS LED on the casing for showing system status. + +This patch is kept separate from the NanoPi R2S support patch, as i plan +on submitting the device support upstream. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 5 +++++ + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 5 +++++ + 2 files changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +@@ -16,6 +16,11 @@ + aliases { + ethernet1 = &rtl8153; + mmc0 = &sdmmc; ++ ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; + }; + + chosen { +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -13,6 +13,11 @@ + aliases { + mmc0 = &sdmmc; + mmc1 = &emmc; ++ ++ led-boot = &power_led; ++ led-failsafe = &power_led; ++ led-running = &power_led; ++ led-upgrade = &power_led; + }; + + chosen { diff --git a/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.6/007-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch similarity index 69% rename from target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch rename to target/linux/rockchip/patches-6.6/007-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch index eeef0df014f2d0..644981c5d60eb8 100644 --- a/target/linux/rockchip/patches-6.6/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch +++ b/target/linux/rockchip/patches-6.6/007-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch @@ -1,7 +1,7 @@ -From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001 +From 13cb72fa5bccd8fd4152ffce8d92a12e3c5c36bc Mon Sep 17 00:00:00 2001 From: David Bauer Date: Sun, 26 Jul 2020 13:32:59 +0200 -Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S +Subject: [PATCH 07/95] arm64: rockchip: add OF node for USB eth on NanoPi R2S This adds the OF node for the USB3 ethernet adapter on the FriendlyARM NanoPi R2S. Add the correct value for the RTL8153 LED configuration @@ -9,12 +9,12 @@ register to match the blink behavior of the other port on the device. Signed-off-by: David Bauer --- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++ - 1 file changed, 1 insertions(+) + arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 1 + + 1 file changed, 1 insertion(+) --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -406,6 +406,7 @@ +@@ -402,6 +402,7 @@ rtl8153: device@2 { compatible = "usbbda,8153"; reg = <2>; diff --git a/target/linux/rockchip/patches-6.6/008-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-6.6/008-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch new file mode 100644 index 00000000000000..30dbdfe1ac6a89 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/008-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch @@ -0,0 +1,31 @@ +From 038e5650cdabe7531cd64a5b873c9b02aab3f06c Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Mon, 7 Jun 2021 15:45:37 +0800 +Subject: [PATCH 08/95] arm64: dts: rockchip: add EEPROM node for NanoPi R4S + +NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which +stores the MAC address. + +Signed-off-by: Tianling Shen +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -68,6 +68,15 @@ + status = "disabled"; + }; + ++&i2c2 { ++ eeprom@51 { ++ compatible = "microchip,24c02", "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ read-only; /* This holds our MAC */ ++ }; ++}; ++ + &i2c4 { + status = "disabled"; + }; diff --git a/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.6/009-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch similarity index 65% rename from target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch rename to target/linux/rockchip/patches-6.6/009-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch index b3c941821aaaf8..eb868133e9da6b 100644 --- a/target/linux/rockchip/patches-6.6/105-nanopi-r4s-sd-signalling.patch +++ b/target/linux/rockchip/patches-6.6/009-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch @@ -1,5 +1,7 @@ +From eeb15d6eeed0dc35d10b482b2a857abfb0c8417c Mon Sep 17 00:00:00 2001 From: David Bauer -Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S +Date: Thu, 1 Sep 2022 00:28:11 -0400 +Subject: [PATCH 09/95] arm64: dts: rockchip: disable UHS modes for NanoPi R4S The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting while U-Boot requires the card to be in 3.3V mode. @@ -9,20 +11,13 @@ mode. This reduces transfer speeds but ensures a reboot whether from userspace or following a kernel panic is always working. Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 5 +++++ + 1 file changed, 5 insertions(+) ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -335,7 +335,6 @@ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; -- sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vcc_sdio>; - status = "okay"; --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -112,6 +112,11 @@ +@@ -121,6 +121,11 @@ status = "disabled"; }; diff --git a/target/linux/rockchip/patches-6.6/010-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch b/target/linux/rockchip/patches-6.6/010-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch new file mode 100644 index 00000000000000..8c655571416675 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/010-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch @@ -0,0 +1,398 @@ +From 901cf603c663ad3d52d274d07ecf4411aa93f992 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Wed, 12 May 2021 13:04:20 -0400 +Subject: [PATCH 10/95] rockchip: rk3328: add support for FriendlyARM NanoPi + NEO3 + +This patch adds support for FriendlyARM NanoPi NEO3 + +Soc: RockChip RK3328 +RAM: 1GB/2GB DDR4 +LAN: 10/100/1000M Ethernet with unique MAC +USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header +MicroSD: x 1 for system boot and storage +LED: Power LED x 1, System LED x 1 +Key: User Button x 1 +Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan +GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO +Power: 5V/1A, via Type-C or GPIO + +Signed-off-by: Marty Jones +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 359 ++++++++++++++++++ + 2 files changed, 360 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts +@@ -0,0 +1,359 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 David Bauer ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include "rk3328.dtsi" ++ ++/ { ++ model = "FriendlyElec NanoPi NEO3"; ++ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328"; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ gmac_clk: gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac_clkin"; ++ #clock-cells = <0>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&reset_button_pin>; ++ pinctrl-names = "default"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; ++ linux,code = ; ++ debounce-interval = <50>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&stat_led_pin>; ++ pinctrl-names = "default"; ++ ++ stat_led: led-1 { ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "nanopi-neo3:green:stat"; ++ }; ++ }; ++ ++ vcc_io_sdio: sdmmcio-regulator { ++ compatible = "regulator-gpio"; ++ enable-active-high; ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sdio_vcc_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_io_sdio"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-settling-time-us = <5000>; ++ regulator-type = "voltage"; ++ startup-delay-us = <2000>; ++ states = <1800000 0x1>, ++ <3300000 0x0>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vcc_sd: sdmmc-regulator { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&sdmmc0m1_pin>; ++ pinctrl-names = "default"; ++ regulator-name = "vcc_sd"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_io_33>; ++ }; ++ ++ vdd_5v: vdd-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_5v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_arm>; ++}; ++ ++&display_subsystem { ++ status = "disabled"; ++}; ++ ++&gmac2io { ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; ++ clock_in_out = "input"; ++ phy-handle = <&rtl8211e>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc_io_33>; ++ pinctrl-0 = <&rgmiim1_pins>; ++ pinctrl-names = "default"; ++ rx_delay = <0x18>; ++ snps,aal; ++ tx_delay = <0x24>; ++ status = "okay"; ++ ++ mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtl8211e: ethernet-phy@1 { ++ reg = <1>; ++ pinctrl-0 = <ð_phy_reset_pin>; ++ pinctrl-names = "default"; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <50000>; ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ ++ rk805: pmic@18 { ++ compatible = "rockchip,rk805"; ++ reg = <0x18>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk805-clkout2"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-0 = <&pmic_int_l>; ++ pinctrl-names = "default"; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vdd_5v>; ++ vcc2-supply = <&vdd_5v>; ++ vcc3-supply = <&vdd_5v>; ++ vcc4-supply = <&vdd_5v>; ++ vcc5-supply = <&vcc_io_33>; ++ vcc6-supply = <&vdd_5v>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ ++ vdd_arm: DCDC_REG2 { ++ regulator-name = "vdd_arm"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1450000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <950000>; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_io_33: DCDC_REG4 { ++ regulator-name = "vcc_io_33"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_18: LDO_REG1 { ++ regulator-name = "vcc_18"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc18_emmc: LDO_REG2 { ++ regulator-name = "vcc18_emmc"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_10: LDO_REG3 { ++ regulator-name = "vdd_10"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1000000>; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&io_domains { ++ pmuio-supply = <&vcc_io_33>; ++ vccio1-supply = <&vcc_io_33>; ++ vccio2-supply = <&vcc18_emmc>; ++ vccio3-supply = <&vcc_io_sdio>; ++ vccio4-supply = <&vcc_18>; ++ vccio5-supply = <&vcc_io_33>; ++ vccio6-supply = <&vcc_io_33>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ button { ++ reset_button_pin: reset-button-pin { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gmac2io { ++ eth_phy_reset_pin: eth-phy-reset-pin { ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ leds { ++ stat_led_pin: stat-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sd { ++ sdio_vcc_pin: sdio-vcc-pin { ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_sd>; ++ vqmmc-supply = <&vcc_io_sdio>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <0>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&u2phy { ++ status = "okay"; ++}; ++ ++&u2phy_host { ++ status = "okay"; ++}; ++ ++&u2phy_otg { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb20_otg { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/011-rockchip-add-system-LED-aliases-specific-to-OpenWrt.patch b/target/linux/rockchip/patches-6.6/011-rockchip-add-system-LED-aliases-specific-to-OpenWrt.patch new file mode 100644 index 00000000000000..630aed9a4b5deb --- /dev/null +++ b/target/linux/rockchip/patches-6.6/011-rockchip-add-system-LED-aliases-specific-to-OpenWrt.patch @@ -0,0 +1,29 @@ +From 0926497951d548c81b5b60965f0b0352f3da5e01 Mon Sep 17 00:00:00 2001 +From: David Bauer +Date: Sun, 11 Sep 2022 11:10:20 -0400 +Subject: [PATCH 11/95] rockchip: add system-LED aliases specific to OpenWrt + +Add the aliases sections required to detect LEDs specific to OpenWrt +boot / update indication for the NanoPi R4S. + +Signed-off-by: David Bauer +--- + arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts +@@ -19,6 +19,13 @@ + model = "FriendlyElec NanoPi R4S"; + compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; + ++ aliases { ++ led-boot = &sys_led; ++ led-failsafe = &sys_led; ++ led-running = &sys_led; ++ led-upgrade = &sys_led; ++ }; ++ + /delete-node/ display-subsystem; + + gpio-leds { diff --git a/target/linux/rockchip/patches-6.6/012-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch b/target/linux/rockchip/patches-6.6/012-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch new file mode 100644 index 00000000000000..1c087f7d3bd408 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/012-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch @@ -0,0 +1,106 @@ +From 3a8a66759baf24ece7e8a968a700d6a35876a63d Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 27 Sep 2022 08:00:44 +0000 +Subject: [PATCH 12/95] crypto: rockchip: move kconfig to its dedicated + directory + +Move all rockchip kconfig in its own subdirectory. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/Kconfig | 32 ++------------------------------ + drivers/crypto/Makefile | 2 +- + drivers/crypto/rockchip/Kconfig | 28 ++++++++++++++++++++++++++++ + 3 files changed, 31 insertions(+), 31 deletions(-) + create mode 100644 drivers/crypto/rockchip/Kconfig + +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -609,6 +609,8 @@ config CRYPTO_DEV_QCOM_RNG + To compile this driver as a module, choose M here. The + module will be called qcom-rng. If unsure, say N. + ++source "drivers/crypto/rockchip/Kconfig" ++ + config CRYPTO_DEV_VMX + bool "Support for VMX cryptographic acceleration instructions" + depends on PPC64 && VSX +@@ -629,36 +631,6 @@ config CRYPTO_DEV_IMGTEC_HASH + hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256 + hashing algorithms. + +-config CRYPTO_DEV_ROCKCHIP +- tristate "Rockchip's Cryptographic Engine driver" +- depends on OF && ARCH_ROCKCHIP +- depends on PM +- select CRYPTO_ECB +- select CRYPTO_CBC +- select CRYPTO_DES +- select CRYPTO_AES +- select CRYPTO_ENGINE +- select CRYPTO_LIB_DES +- select CRYPTO_MD5 +- select CRYPTO_SHA1 +- select CRYPTO_SHA256 +- select CRYPTO_HASH +- select CRYPTO_SKCIPHER +- +- help +- This driver interfaces with the hardware crypto accelerator. +- Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. +- +-config CRYPTO_DEV_ROCKCHIP_DEBUG +- bool "Enable Rockchip crypto stats" +- depends on CRYPTO_DEV_ROCKCHIP +- depends on DEBUG_FS +- help +- Say y to enable Rockchip crypto debug stats. +- This will create /sys/kernel/debug/rk3288_crypto/stats for displaying +- the number of requests per algorithm and other internal stats. +- +- + config CRYPTO_DEV_ZYNQMP_AES + tristate "Support for Xilinx ZynqMP AES hw accelerator" + depends on ZYNQMP_FIRMWARE || COMPILE_TEST +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -34,7 +34,7 @@ obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += + obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ + obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ + obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o +-obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ ++obj-y += rockchip/ + obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o + obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o + obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o +--- /dev/null ++++ b/drivers/crypto/rockchip/Kconfig +@@ -0,0 +1,28 @@ ++config CRYPTO_DEV_ROCKCHIP ++ tristate "Rockchip's Cryptographic Engine driver" ++ depends on OF && ARCH_ROCKCHIP ++ depends on PM ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_DES ++ select CRYPTO_AES ++ select CRYPTO_ENGINE ++ select CRYPTO_LIB_DES ++ select CRYPTO_MD5 ++ select CRYPTO_SHA1 ++ select CRYPTO_SHA256 ++ select CRYPTO_HASH ++ select CRYPTO_SKCIPHER ++ ++ help ++ This driver interfaces with the hardware crypto accelerator. ++ Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode. ++ ++config CRYPTO_DEV_ROCKCHIP_DEBUG ++ bool "Enable Rockchip crypto stats" ++ depends on CRYPTO_DEV_ROCKCHIP ++ depends on DEBUG_FS ++ help ++ Say y to enable Rockchip crypto debug stats. ++ This will create /sys/kernel/debug/rk3288_crypto/stats for displaying ++ the number of requests per algorithm and other internal stats. diff --git a/target/linux/rockchip/patches-6.6/013-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch b/target/linux/rockchip/patches-6.6/013-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch new file mode 100644 index 00000000000000..18984fcfb0202d --- /dev/null +++ b/target/linux/rockchip/patches-6.6/013-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch @@ -0,0 +1,89 @@ +From 94327499ba7867ec017abe331446858086ae1f36 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 27 Sep 2022 08:00:45 +0000 +Subject: [PATCH 13/95] dt-bindings: crypto: add support for + rockchip,crypto-rk3588 + +Add device tree binding documentation for the Rockchip cryptographic +offloader V2. + +Signed-off-by: Corentin Labbe +--- + .../crypto/rockchip,rk3588-crypto.yaml | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip cryptographic offloader V2 ++ ++maintainers: ++ - Corentin Labbe ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3568-crypto ++ - rockchip,rk3588-crypto ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 4 ++ ++ clock-names: ++ items: ++ - const: aclk ++ - const: hclk ++ - const: sclk ++ - const: pka ++ ++ resets: ++ minItems: 5 ++ ++ reset-names: ++ items: ++ - const: core ++ - const: a ++ - const: h ++ - const: rng ++ - const: pka ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ crypto@fe380000 { ++ compatible = "rockchip,rk3588-crypto"; ++ reg = <0xfe380000 0x4000>; ++ interrupts = ; ++ clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, ++ <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; ++ clock-names = "aclk", "hclk", "sclk", "pka"; ++ resets = <&cru SRST_CRYPTO_NS_CORE>, <&cru SRST_A_CRYPTO_NS>, ++ <&cru SRST_H_CRYPTO_NS>, <&cru SRST_CRYPTO_NS_RNG>, ++ <&cru SRST_CRYPTO_NS_PKA>; ++ reset-names = "core", "a", "h", "rng", "pka"; ++ }; diff --git a/target/linux/rockchip/patches-6.6/014-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch b/target/linux/rockchip/patches-6.6/014-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch new file mode 100644 index 00000000000000..284e329bc99750 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/014-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch @@ -0,0 +1,22 @@ +From efbbe9089347272d845cf9a8478d6249b0902cf9 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 27 Sep 2022 08:00:46 +0000 +Subject: [PATCH 14/95] MAINTAINERS: add new dt-binding doc to the right entry + +Rockchip crypto driver have a new file to be added. + +Signed-off-by: Corentin Labbe +--- + MAINTAINERS | 1 + + 1 file changed, 1 insertion(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -18512,6 +18512,7 @@ M: Corentin Labbe + L: linux-crypto@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml ++F: Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml + F: drivers/crypto/rockchip/ + + ROCKCHIP I2S TDM DRIVER diff --git a/target/linux/rockchip/patches-6.6/015-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch b/target/linux/rockchip/patches-6.6/015-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch new file mode 100644 index 00000000000000..ef4308e968d790 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/015-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch @@ -0,0 +1,1633 @@ +From e45e7f6cbd32fd3672ce93f6dd880bbddf723b02 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 27 Sep 2022 08:00:47 +0000 +Subject: [PATCH 15/95] crypto: rockchip: support the new crypto IP for + rk3568/rk3588 + +Rockchip rk3568 and rk3588 have a common crypto offloader IP. +This driver adds support for it. + +Signed-off-by: Corentin Labbe +--- + drivers/crypto/rockchip/Kconfig | 28 + + drivers/crypto/rockchip/Makefile | 5 + + drivers/crypto/rockchip/rk3588_crypto.c | 646 ++++++++++++++++++ + drivers/crypto/rockchip/rk3588_crypto.h | 221 ++++++ + drivers/crypto/rockchip/rk3588_crypto_ahash.c | 346 ++++++++++ + .../crypto/rockchip/rk3588_crypto_skcipher.c | 340 +++++++++ + 6 files changed, 1586 insertions(+) + create mode 100644 drivers/crypto/rockchip/rk3588_crypto.c + create mode 100644 drivers/crypto/rockchip/rk3588_crypto.h + create mode 100644 drivers/crypto/rockchip/rk3588_crypto_ahash.c + create mode 100644 drivers/crypto/rockchip/rk3588_crypto_skcipher.c + +--- a/drivers/crypto/rockchip/Kconfig ++++ b/drivers/crypto/rockchip/Kconfig +@@ -26,3 +26,31 @@ config CRYPTO_DEV_ROCKCHIP_DEBUG + Say y to enable Rockchip crypto debug stats. + This will create /sys/kernel/debug/rk3288_crypto/stats for displaying + the number of requests per algorithm and other internal stats. ++ ++config CRYPTO_DEV_ROCKCHIP2 ++ tristate "Rockchip's cryptographic offloader V2" ++ depends on OF && ARCH_ROCKCHIP ++ depends on PM ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_AES ++ select CRYPTO_MD5 ++ select CRYPTO_SHA1 ++ select CRYPTO_SHA256 ++ select CRYPTO_SM3_GENERIC ++ select CRYPTO_HASH ++ select CRYPTO_SKCIPHER ++ select CRYPTO_ENGINE ++ ++ help ++ This driver interfaces with the hardware crypto offloader present ++ on RK3568 and RK3588. ++ ++config CRYPTO_DEV_ROCKCHIP2_DEBUG ++ bool "Enable Rockchip V2 crypto stats" ++ depends on CRYPTO_DEV_ROCKCHIP2 ++ depends on DEBUG_FS ++ help ++ Say y to enable Rockchip crypto debug stats. ++ This will create /sys/kernel/debug/rk3588_crypto/stats for displaying ++ the number of requests per algorithm and other internal stats. +--- a/drivers/crypto/rockchip/Makefile ++++ b/drivers/crypto/rockchip/Makefile +@@ -3,3 +3,8 @@ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rk_ + rk_crypto-objs := rk3288_crypto.o \ + rk3288_crypto_skcipher.o \ + rk3288_crypto_ahash.o ++ ++obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP2) += rk_crypto2.o ++rk_crypto2-objs := rk3588_crypto.o \ ++ rk3588_crypto_skcipher.o \ ++ rk3588_crypto_ahash.o +--- /dev/null ++++ b/drivers/crypto/rockchip/rk3588_crypto.c +@@ -0,0 +1,646 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * hardware cryptographic offloader for rk3568/rk3588 SoC ++ * ++ * Copyright (c) 2022, Corentin Labbe ++ */ ++ ++#include "rk3588_crypto.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static struct rockchip_ip rocklist = { ++ .dev_list = LIST_HEAD_INIT(rocklist.dev_list), ++ .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock), ++}; ++ ++struct rk_crypto_dev *get_rk_crypto(void) ++{ ++ struct rk_crypto_dev *first; ++ ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_dev, list); ++ list_rotate_left(&rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ return first; ++} ++ ++static const struct rk_variant rk3568_variant = { ++ .num_clks = 4, ++}; ++ ++static const struct rk_variant rk3588_variant = { ++ .num_clks = 4, ++}; ++ ++static int rk_crypto_get_clks(struct rk_crypto_dev *dev) ++{ ++ int i, j, err; ++ unsigned long cr; ++ ++ dev->num_clks = devm_clk_bulk_get_all(dev->dev, &dev->clks); ++ if (dev->num_clks < dev->variant->num_clks) { ++ dev_err(dev->dev, "Missing clocks, got %d instead of %d\n", ++ dev->num_clks, dev->variant->num_clks); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < dev->num_clks; i++) { ++ cr = clk_get_rate(dev->clks[i].clk); ++ for (j = 0; j < ARRAY_SIZE(dev->variant->rkclks); j++) { ++ if (dev->variant->rkclks[j].max == 0) ++ continue; ++ if (strcmp(dev->variant->rkclks[j].name, dev->clks[i].id)) ++ continue; ++ if (cr > dev->variant->rkclks[j].max) { ++ err = clk_set_rate(dev->clks[i].clk, ++ dev->variant->rkclks[j].max); ++ if (err) ++ dev_err(dev->dev, "Fail downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ else ++ dev_info(dev->dev, "Downclocking %s from %lu to %lu\n", ++ dev->variant->rkclks[j].name, cr, ++ dev->variant->rkclks[j].max); ++ } ++ } ++ } ++ return 0; ++} ++ ++static int rk_crypto_enable_clk(struct rk_crypto_dev *dev) ++{ ++ int err; ++ ++ err = clk_bulk_prepare_enable(dev->num_clks, dev->clks); ++ if (err) ++ dev_err(dev->dev, "Could not enable clock clks\n"); ++ ++ return err; ++} ++ ++static void rk_crypto_disable_clk(struct rk_crypto_dev *dev) ++{ ++ clk_bulk_disable_unprepare(dev->num_clks, dev->clks); ++} ++ ++/* ++ * Power management strategy: The device is suspended until a request ++ * is handled. For avoiding suspend/resume yoyo, the autosuspend is set to 2s. ++ */ ++static int rk_crypto_pm_suspend(struct device *dev) ++{ ++ struct rk_crypto_dev *rkdev = dev_get_drvdata(dev); ++ ++ rk_crypto_disable_clk(rkdev); ++ reset_control_assert(rkdev->rst); ++ ++ return 0; ++} ++ ++static int rk_crypto_pm_resume(struct device *dev) ++{ ++ struct rk_crypto_dev *rkdev = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = rk_crypto_enable_clk(rkdev); ++ if (ret) ++ return ret; ++ ++ reset_control_deassert(rkdev->rst); ++ return 0; ++} ++ ++static const struct dev_pm_ops rk_crypto_pm_ops = { ++ SET_RUNTIME_PM_OPS(rk_crypto_pm_suspend, rk_crypto_pm_resume, NULL) ++}; ++ ++static int rk_crypto_pm_init(struct rk_crypto_dev *rkdev) ++{ ++ int err; ++ ++ pm_runtime_use_autosuspend(rkdev->dev); ++ pm_runtime_set_autosuspend_delay(rkdev->dev, 2000); ++ ++ err = pm_runtime_set_suspended(rkdev->dev); ++ if (err) ++ return err; ++ pm_runtime_enable(rkdev->dev); ++ return err; ++} ++ ++static void rk_crypto_pm_exit(struct rk_crypto_dev *rkdev) ++{ ++ pm_runtime_disable(rkdev->dev); ++} ++ ++static irqreturn_t rk_crypto_irq_handle(int irq, void *dev_id) ++{ ++ struct rk_crypto_dev *rkc = platform_get_drvdata(dev_id); ++ u32 v; ++ ++ v = readl(rkc->reg + RK_CRYPTO_DMA_INT_ST); ++ writel(v, rkc->reg + RK_CRYPTO_DMA_INT_ST); ++ ++ rkc->status = 1; ++ if (v & 0xF8) { ++ dev_warn(rkc->dev, "DMA Error\n"); ++ rkc->status = 0; ++ } ++ complete(&rkc->complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct rk_crypto_template rk_cipher_algs[] = { ++ { ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, ++ .alg.skcipher = { ++ .base.cra_name = "ecb(aes)", ++ .base.cra_driver_name = "ecb-aes-rk2", ++ .base.cra_priority = 300, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, ++ .base.cra_blocksize = AES_BLOCK_SIZE, ++ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), ++ .base.cra_alignmask = 0x0f, ++ .base.cra_module = THIS_MODULE, ++ ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = rk_aes_setkey, ++ .encrypt = rk_aes_ecb_encrypt, ++ .decrypt = rk_aes_ecb_decrypt, ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_SKCIPHER, ++ .alg.skcipher = { ++ .base.cra_name = "cbc(aes)", ++ .base.cra_driver_name = "cbc-aes-rk2", ++ .base.cra_priority = 300, ++ .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, ++ .base.cra_blocksize = AES_BLOCK_SIZE, ++ .base.cra_ctxsize = sizeof(struct rk_cipher_ctx), ++ .base.cra_alignmask = 0x0f, ++ .base.cra_module = THIS_MODULE, ++ ++ .init = rk_cipher_tfm_init, ++ .exit = rk_cipher_tfm_exit, ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = rk_aes_setkey, ++ .encrypt = rk_aes_cbc_encrypt, ++ .decrypt = rk_aes_cbc_decrypt, ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_MD5, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = MD5_DIGEST_SIZE, ++ .statesize = sizeof(struct md5_state), ++ .base = { ++ .cra_name = "md5", ++ .cra_driver_name = "rk2-md5", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA1_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_SHA1, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = SHA1_DIGEST_SIZE, ++ .statesize = sizeof(struct sha1_state), ++ .base = { ++ .cra_name = "sha1", ++ .cra_driver_name = "rk2-sha1", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA1_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_SHA256, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "rk2-sha256", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_SHA384, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha384", ++ .cra_driver_name = "rk2-sha384", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_SHA512, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha512", ++ .cra_driver_name = "rk2-sha512", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++ { ++ .type = CRYPTO_ALG_TYPE_AHASH, ++ .rk_mode = RK_CRYPTO_SM3_GENERIC, ++ .alg.hash = { ++ .init = rk_ahash_init, ++ .update = rk_ahash_update, ++ .final = rk_ahash_final, ++ .finup = rk_ahash_finup, ++ .export = rk_ahash_export, ++ .import = rk_ahash_import, ++ .digest = rk_ahash_digest, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "sm3", ++ .cra_driver_name = "rk2-sm3", ++ .cra_priority = 300, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct rk_ahash_ctx), ++ .cra_alignmask = 3, ++ .cra_init = rk_cra_hash_init, ++ .cra_exit = rk_cra_hash_exit, ++ .cra_module = THIS_MODULE, ++ } ++ } ++ } ++ }, ++}; ++ ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++static int rk_crypto_debugfs_show(struct seq_file *seq, void *v) ++{ ++ struct rk_crypto_dev *dd; ++ unsigned int i; ++ ++ spin_lock(&rocklist.lock); ++ list_for_each_entry(dd, &rocklist.dev_list, list) { ++ seq_printf(seq, "%s %s requests: %lu\n", ++ dev_driver_string(dd->dev), dev_name(dd->dev), ++ dd->nreq); ++ } ++ spin_unlock(&rocklist.lock); ++ ++ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { ++ if (!rk_cipher_algs[i].dev) ++ continue; ++ switch (rk_cipher_algs[i].type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk_cipher_algs[i].alg.skcipher.base.cra_driver_name, ++ rk_cipher_algs[i].alg.skcipher.base.cra_name, ++ rk_cipher_algs[i].stat_req, rk_cipher_algs[i].stat_fb); ++ seq_printf(seq, "\tfallback due to length: %lu\n", ++ rk_cipher_algs[i].stat_fb_len); ++ seq_printf(seq, "\tfallback due to alignment: %lu\n", ++ rk_cipher_algs[i].stat_fb_align); ++ seq_printf(seq, "\tfallback due to SGs: %lu\n", ++ rk_cipher_algs[i].stat_fb_sgdiff); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", ++ rk_cipher_algs[i].alg.hash.halg.base.cra_driver_name, ++ rk_cipher_algs[i].alg.hash.halg.base.cra_name, ++ rk_cipher_algs[i].stat_req, rk_cipher_algs[i].stat_fb); ++ break; ++ } ++ } ++ return 0; ++} ++ ++DEFINE_SHOW_ATTRIBUTE(rk_crypto_debugfs); ++#endif ++ ++static void register_debugfs(struct rk_crypto_dev *crypto_dev) ++{ ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++ /* Ignore error of debugfs */ ++ rocklist.dbgfs_dir = debugfs_create_dir("rk3588_crypto", NULL); ++ rocklist.dbgfs_stats = debugfs_create_file("stats", 0444, ++ rocklist.dbgfs_dir, ++ &rocklist, ++ &rk_crypto_debugfs_fops); ++#endif ++} ++ ++static int rk_crypto_register(struct rk_crypto_dev *rkc) ++{ ++ unsigned int i, k; ++ int err = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { ++ rk_cipher_algs[i].dev = rkc; ++ switch (rk_cipher_algs[i].type) { ++ case CRYPTO_ALG_TYPE_SKCIPHER: ++ dev_info(rkc->dev, "Register %s as %s\n", ++ rk_cipher_algs[i].alg.skcipher.base.cra_name, ++ rk_cipher_algs[i].alg.skcipher.base.cra_driver_name); ++ err = crypto_register_skcipher(&rk_cipher_algs[i].alg.skcipher); ++ break; ++ case CRYPTO_ALG_TYPE_AHASH: ++ dev_info(rkc->dev, "Register %s as %s\n", ++ rk_cipher_algs[i].alg.hash.halg.base.cra_name, ++ rk_cipher_algs[i].alg.hash.halg.base.cra_driver_name); ++ err = crypto_register_ahash(&rk_cipher_algs[i].alg.hash); ++ break; ++ default: ++ dev_err(rkc->dev, "unknown algorithm\n"); ++ } ++ if (err) ++ goto err_cipher_algs; ++ } ++ return 0; ++ ++err_cipher_algs: ++ for (k = 0; k < i; k++) { ++ if (rk_cipher_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER) ++ crypto_unregister_skcipher(&rk_cipher_algs[k].alg.skcipher); ++ else ++ crypto_unregister_ahash(&rk_cipher_algs[i].alg.hash); ++ } ++ return err; ++} ++ ++static void rk_crypto_unregister(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rk_cipher_algs); i++) { ++ if (rk_cipher_algs[i].type == CRYPTO_ALG_TYPE_SKCIPHER) ++ crypto_unregister_skcipher(&rk_cipher_algs[i].alg.skcipher); ++ else ++ crypto_unregister_ahash(&rk_cipher_algs[i].alg.hash); ++ } ++} ++ ++static const struct of_device_id crypto_of_id_table[] = { ++ { .compatible = "rockchip,rk3568-crypto", ++ .data = &rk3568_variant, ++ }, ++ { .compatible = "rockchip,rk3588-crypto", ++ .data = &rk3588_variant, ++ }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, crypto_of_id_table); ++ ++static int rk_crypto_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rk_crypto_dev *rkc, *first; ++ int err = 0; ++ ++ rkc = devm_kzalloc(&pdev->dev, sizeof(*rkc), GFP_KERNEL); ++ if (!rkc) { ++ err = -ENOMEM; ++ goto err_crypto; ++ } ++ ++ rkc->dev = &pdev->dev; ++ platform_set_drvdata(pdev, rkc); ++ ++ rkc->variant = of_device_get_match_data(&pdev->dev); ++ if (!rkc->variant) { ++ dev_err(&pdev->dev, "Missing variant\n"); ++ return -EINVAL; ++ } ++ ++ rkc->rst = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(rkc->rst)) { ++ err = PTR_ERR(rkc->rst); ++ goto err_crypto; ++ } ++ ++ rkc->tl = dma_alloc_coherent(rkc->dev, ++ sizeof(struct rk_crypto_lli) * MAX_LLI, ++ &rkc->t_phy, GFP_KERNEL); ++ if (!rkc->tl) { ++ dev_err(rkc->dev, "Cannot get DMA memory for task\n"); ++ err = -ENOMEM; ++ goto err_crypto; ++ } ++ ++ reset_control_assert(rkc->rst); ++ usleep_range(10, 20); ++ reset_control_deassert(rkc->rst); ++ ++ rkc->reg = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rkc->reg)) { ++ err = PTR_ERR(rkc->reg); ++ goto err_crypto; ++ } ++ ++ err = rk_crypto_get_clks(rkc); ++ if (err) ++ goto err_crypto; ++ ++ rkc->irq = platform_get_irq(pdev, 0); ++ if (rkc->irq < 0) { ++ dev_err(&pdev->dev, "control Interrupt is not available.\n"); ++ err = rkc->irq; ++ goto err_crypto; ++ } ++ ++ err = devm_request_irq(&pdev->dev, rkc->irq, ++ rk_crypto_irq_handle, IRQF_SHARED, ++ "rk-crypto", pdev); ++ ++ if (err) { ++ dev_err(&pdev->dev, "irq request failed.\n"); ++ goto err_crypto; ++ } ++ ++ rkc->engine = crypto_engine_alloc_init(&pdev->dev, true); ++ crypto_engine_start(rkc->engine); ++ init_completion(&rkc->complete); ++ ++ err = rk_crypto_pm_init(rkc); ++ if (err) ++ goto err_pm; ++ ++ err = pm_runtime_resume_and_get(&pdev->dev); ++ ++ spin_lock(&rocklist.lock); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_dev, list); ++ list_add_tail(&rkc->list, &rocklist.dev_list); ++ spin_unlock(&rocklist.lock); ++ ++ if (!first) { ++ dev_info(dev, "Registers crypto algos\n"); ++ err = rk_crypto_register(rkc); ++ if (err) { ++ dev_err(dev, "Fail to register crypto algorithms"); ++ goto err_register_alg; ++ } ++ ++ register_debugfs(rkc); ++ } ++ ++ return 0; ++ ++err_register_alg: ++ rk_crypto_pm_exit(rkc); ++err_pm: ++ crypto_engine_exit(rkc->engine); ++err_crypto: ++ dev_err(dev, "Crypto Accelerator not successfully registered\n"); ++ return err; ++} ++ ++static int rk_crypto_remove(struct platform_device *pdev) ++{ ++ struct rk_crypto_dev *crypto_tmp = platform_get_drvdata(pdev); ++ struct rk_crypto_dev *first; ++ ++ spin_lock_bh(&rocklist.lock); ++ list_del(&crypto_tmp->list); ++ first = list_first_entry_or_null(&rocklist.dev_list, ++ struct rk_crypto_dev, list); ++ spin_unlock_bh(&rocklist.lock); ++ ++ if (!first) { ++#ifdef CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG ++ debugfs_remove_recursive(rocklist.dbgfs_dir); ++#endif ++ rk_crypto_unregister(); ++ } ++ rk_crypto_pm_exit(crypto_tmp); ++ crypto_engine_exit(crypto_tmp->engine); ++ return 0; ++} ++ ++static struct platform_driver crypto_driver = { ++ .probe = rk_crypto_probe, ++ .remove = rk_crypto_remove, ++ .driver = { ++ .name = "rk3588-crypto", ++ .pm = &rk_crypto_pm_ops, ++ .of_match_table = crypto_of_id_table, ++ }, ++}; ++ ++module_platform_driver(crypto_driver); ++ ++MODULE_DESCRIPTION("Rockchip Crypto Engine cryptographic offloader"); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Corentin Labbe "); +--- /dev/null ++++ b/drivers/crypto/rockchip/rk3588_crypto.h +@@ -0,0 +1,221 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RK_CRYPTO_CLK_CTL 0x0000 ++#define RK_CRYPTO_RST_CTL 0x0004 ++ ++#define RK_CRYPTO_DMA_INT_EN 0x0008 ++/* values for RK_CRYPTO_DMA_INT_EN */ ++#define RK_CRYPTO_DMA_INT_LISTDONE BIT(0) ++ ++#define RK_CRYPTO_DMA_INT_ST 0x000C ++/* values in RK_CRYPTO_DMA_INT_ST are the same than in RK_CRYPTO_DMA_INT_EN */ ++ ++#define RK_CRYPTO_DMA_CTL 0x0010 ++#define RK_CRYPTO_DMA_CTL_START BIT(0) ++ ++#define RK_CRYPTO_DMA_LLI_ADDR 0x0014 ++ ++#define RK_CRYPTO_FIFO_CTL 0x0040 ++ ++#define RK_CRYPTO_BC_CTL 0x0044 ++#define RK_CRYPTO_AES (0 << 8) ++#define RK_CRYPTO_MODE_ECB (0 << 4) ++#define RK_CRYPTO_MODE_CBC (1 << 4) ++ ++#define RK_CRYPTO_HASH_CTL 0x0048 ++#define RK_CRYPTO_HW_PAD BIT(2) ++#define RK_CRYPTO_SHA1 (0 << 4) ++#define RK_CRYPTO_MD5 (1 << 4) ++#define RK_CRYPTO_SHA224 (3 << 4) ++#define RK_CRYPTO_SHA256 (2 << 4) ++#define RK_CRYPTO_SHA384 (9 << 4) ++#define RK_CRYPTO_SHA512 (8 << 4) ++#define RK_CRYPTO_SM3_GENERIC (4 << 4) ++ ++#define RK_CRYPTO_AES_ECB_MODE (RK_CRYPTO_AES | RK_CRYPTO_MODE_ECB) ++#define RK_CRYPTO_AES_CBC_MODE (RK_CRYPTO_AES | RK_CRYPTO_MODE_CBC) ++#define RK_CRYPTO_AES_CTR_MODE 3 ++#define RK_CRYPTO_AES_128BIT_key (0 << 2) ++#define RK_CRYPTO_AES_192BIT_key (1 << 2) ++#define RK_CRYPTO_AES_256BIT_key (2 << 2) ++ ++#define RK_CRYPTO_DEC BIT(1) ++#define RK_CRYPTO_ENABLE BIT(0) ++ ++#define RK_CRYPTO_CH0_IV_0 0x0100 ++ ++#define RK_CRYPTO_KEY0 0x0180 ++#define RK_CRYPTO_KEY1 0x0184 ++#define RK_CRYPTO_KEY2 0x0188 ++#define RK_CRYPTO_KEY3 0x018C ++#define RK_CRYPTO_KEY4 0x0190 ++#define RK_CRYPTO_KEY5 0x0194 ++#define RK_CRYPTO_KEY6 0x0198 ++#define RK_CRYPTO_KEY7 0x019C ++ ++#define RK_CRYPTO_CH0_PC_LEN_0 0x0280 ++ ++#define RK_CRYPTO_CH0_IV_LEN 0x0300 ++ ++#define RK_CRYPTO_HASH_DOUT_0 0x03A0 ++#define RK_CRYPTO_HASH_VALID 0x03E4 ++ ++#define CRYPTO_AES_VERSION 0x0680 ++#define CRYPTO_DES_VERSION 0x0684 ++#define CRYPTO_SM4_VERSION 0x0688 ++#define CRYPTO_HASH_VERSION 0x068C ++#define CRYPTO_HMAC_VERSION 0x0690 ++#define CRYPTO_RNG_VERSION 0x0694 ++#define CRYPTO_PKA_VERSION 0x0698 ++#define CRYPTO_CRYPTO_VERSION 0x06F0 ++ ++#define RK_LLI_DMA_CTRL_SRC_INT BIT(10) ++#define RK_LLI_DMA_CTRL_DST_INT BIT(9) ++#define RK_LLI_DMA_CTRL_LIST_INT BIT(8) ++#define RK_LLI_DMA_CTRL_LAST BIT(0) ++ ++#define RK_LLI_STRING_LAST BIT(2) ++#define RK_LLI_STRING_FIRST BIT(1) ++#define RK_LLI_CIPHER_START BIT(0) ++ ++#define RK_MAX_CLKS 4 ++ ++/* there are no hw limit, but we need to choose a maximum of descriptor to allocate */ ++#define MAX_LLI 20 ++ ++struct rk_crypto_lli { ++ __le32 src_addr; ++ __le32 src_len; ++ __le32 dst_addr; ++ __le32 dst_len; ++ __le32 user; ++ __le32 iv; ++ __le32 dma_ctrl; ++ __le32 next; ++}; ++ ++/* ++ * struct rockchip_ip - struct for managing a list of RK crypto instance ++ * @dev_list: Used for doing a list of rk_crypto_dev ++ * @lock: Control access to dev_list ++ * @dbgfs_dir: Debugfs dentry for statistic directory ++ * @dbgfs_stats: Debugfs dentry for statistic counters ++ */ ++struct rockchip_ip { ++ struct list_head dev_list; ++ spinlock_t lock; /* Control access to dev_list */ ++ struct dentry *dbgfs_dir; ++ struct dentry *dbgfs_stats; ++}; ++ ++struct rk_clks { ++ const char *name; ++ unsigned long max; ++}; ++ ++struct rk_variant { ++ int num_clks; ++ struct rk_clks rkclks[RK_MAX_CLKS]; ++}; ++ ++struct rk_crypto_dev { ++ struct list_head list; ++ struct device *dev; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ struct reset_control *rst; ++ void __iomem *reg; ++ int irq; ++ const struct rk_variant *variant; ++ unsigned long nreq; ++ struct crypto_engine *engine; ++ struct completion complete; ++ int status; ++ struct rk_crypto_lli *tl; ++ dma_addr_t t_phy; ++}; ++ ++/* the private variable of hash */ ++struct rk_ahash_ctx { ++ struct crypto_engine_ctx enginectx; ++ /* for fallback */ ++ struct crypto_ahash *fallback_tfm; ++}; ++ ++/* the private variable of hash for fallback */ ++struct rk_ahash_rctx { ++ struct rk_crypto_dev *dev; ++ struct ahash_request fallback_req; ++ u32 mode; ++ int nrsgs; ++}; ++ ++/* the private variable of cipher */ ++struct rk_cipher_ctx { ++ struct crypto_engine_ctx enginectx; ++ unsigned int keylen; ++ u8 key[AES_MAX_KEY_SIZE]; ++ u8 iv[AES_BLOCK_SIZE]; ++ struct crypto_skcipher *fallback_tfm; ++}; ++ ++struct rk_cipher_rctx { ++ struct rk_crypto_dev *dev; ++ u8 backup_iv[AES_BLOCK_SIZE]; ++ u32 mode; ++ struct skcipher_request fallback_req; // keep at the end ++}; ++ ++struct rk_crypto_template { ++ u32 type; ++ u32 rk_mode; ++ struct rk_crypto_dev *dev; ++ union { ++ struct skcipher_alg skcipher; ++ struct ahash_alg hash; ++ } alg; ++ unsigned long stat_req; ++ unsigned long stat_fb; ++ unsigned long stat_fb_len; ++ unsigned long stat_fb_sglen; ++ unsigned long stat_fb_align; ++ unsigned long stat_fb_sgdiff; ++}; ++ ++struct rk_crypto_dev *get_rk_crypto(void); ++ ++int rk_cipher_tfm_init(struct crypto_skcipher *tfm); ++void rk_cipher_tfm_exit(struct crypto_skcipher *tfm); ++int rk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen); ++int rk_aes_ecb_encrypt(struct skcipher_request *req); ++int rk_aes_ecb_decrypt(struct skcipher_request *req); ++int rk_aes_cbc_encrypt(struct skcipher_request *req); ++int rk_aes_cbc_decrypt(struct skcipher_request *req); ++ ++int rk_ahash_init(struct ahash_request *req); ++int rk_ahash_update(struct ahash_request *req); ++int rk_ahash_final(struct ahash_request *req); ++int rk_ahash_finup(struct ahash_request *req); ++int rk_ahash_import(struct ahash_request *req, const void *in); ++int rk_ahash_export(struct ahash_request *req, void *out); ++int rk_ahash_digest(struct ahash_request *req); ++int rk_cra_hash_init(struct crypto_tfm *tfm); ++void rk_cra_hash_exit(struct crypto_tfm *tfm); +--- /dev/null ++++ b/drivers/crypto/rockchip/rk3588_crypto_ahash.c +@@ -0,0 +1,346 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Crypto acceleration support for Rockchip RK3588 ++ * ++ * Copyright (c) 2022 Corentin Labbe ++ */ ++#include ++#include ++#include "rk3588_crypto.h" ++ ++static bool rk_ahash_need_fallback(struct ahash_request *areq) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.hash); ++ struct scatterlist *sg; ++ ++ sg = areq->src; ++ while (sg) { ++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ if (sg->length % 4) { ++ algt->stat_fb_sglen++; ++ return true; ++ } ++ sg = sg_next(sg); ++ } ++ return false; ++} ++ ++static int rk_ahash_digest_fb(struct ahash_request *areq) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_ctx *tfmctx = crypto_ahash_ctx(tfm); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.hash); ++ ++ algt->stat_fb++; ++ ++ ahash_request_set_tfm(&rctx->fallback_req, tfmctx->fallback_tfm); ++ rctx->fallback_req.base.flags = areq->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ rctx->fallback_req.nbytes = areq->nbytes; ++ rctx->fallback_req.src = areq->src; ++ rctx->fallback_req.result = areq->result; ++ ++ return crypto_ahash_digest(&rctx->fallback_req); ++} ++ ++static int zero_message_process(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.hash); ++ int digestsize = crypto_ahash_digestsize(tfm); ++ ++ switch (algt->rk_mode) { ++ case RK_CRYPTO_SHA1: ++ memcpy(req->result, sha1_zero_message_hash, digestsize); ++ break; ++ case RK_CRYPTO_SHA256: ++ memcpy(req->result, sha256_zero_message_hash, digestsize); ++ break; ++ case RK_CRYPTO_SHA384: ++ memcpy(req->result, sha384_zero_message_hash, digestsize); ++ break; ++ case RK_CRYPTO_SHA512: ++ memcpy(req->result, sha512_zero_message_hash, digestsize); ++ break; ++ case RK_CRYPTO_MD5: ++ memcpy(req->result, md5_zero_message_hash, digestsize); ++ break; ++ case RK_CRYPTO_SM3_GENERIC: ++ memcpy(req->result, sm3_zero_message_hash, digestsize); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int rk_ahash_init(struct ahash_request *req) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_init(&rctx->fallback_req); ++} ++ ++int rk_ahash_update(struct ahash_request *req) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ rctx->fallback_req.nbytes = req->nbytes; ++ rctx->fallback_req.src = req->src; ++ ++ return crypto_ahash_update(&rctx->fallback_req); ++} ++ ++int rk_ahash_final(struct ahash_request *req) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ rctx->fallback_req.result = req->result; ++ ++ return crypto_ahash_final(&rctx->fallback_req); ++} ++ ++int rk_ahash_finup(struct ahash_request *req) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ rctx->fallback_req.nbytes = req->nbytes; ++ rctx->fallback_req.src = req->src; ++ rctx->fallback_req.result = req->result; ++ ++ return crypto_ahash_finup(&rctx->fallback_req); ++} ++ ++int rk_ahash_import(struct ahash_request *req, const void *in) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_import(&rctx->fallback_req, in); ++} ++ ++int rk_ahash_export(struct ahash_request *req, void *out) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct rk_ahash_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); ++ rctx->fallback_req.base.flags = req->base.flags & ++ CRYPTO_TFM_REQ_MAY_SLEEP; ++ ++ return crypto_ahash_export(&rctx->fallback_req, out); ++} ++ ++int rk_ahash_digest(struct ahash_request *req) ++{ ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(req); ++ struct rk_crypto_dev *dev; ++ struct crypto_engine *engine; ++ ++ if (rk_ahash_need_fallback(req)) ++ return rk_ahash_digest_fb(req); ++ ++ if (!req->nbytes) ++ return zero_message_process(req); ++ ++ dev = get_rk_crypto(); ++ ++ rctx->dev = dev; ++ engine = dev->engine; ++ ++ return crypto_transfer_hash_request_to_engine(engine, req); ++} ++ ++static int rk_hash_prepare(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk_crypto_dev *rkc = rctx->dev; ++ int ret; ++ ++ ret = dma_map_sg(rkc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE); ++ if (ret <= 0) ++ return -EINVAL; ++ ++ rctx->nrsgs = ret; ++ ++ return 0; ++} ++ ++static int rk_hash_unprepare(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct rk_crypto_dev *rkc = rctx->dev; ++ ++ dma_unmap_sg(rkc->dev, areq->src, rctx->nrsgs, DMA_TO_DEVICE); ++ return 0; ++} ++ ++static int rk_hash_run(struct crypto_engine *engine, void *breq) ++{ ++ struct ahash_request *areq = container_of(breq, struct ahash_request, base); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); ++ struct rk_ahash_rctx *rctx = ahash_request_ctx(areq); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.hash); ++ struct scatterlist *sgs = areq->src; ++ struct rk_crypto_dev *rkc = rctx->dev; ++ struct rk_crypto_lli *dd = &rkc->tl[0]; ++ int ddi = 0; ++ int err = 0; ++ unsigned int len = areq->nbytes; ++ unsigned int todo; ++ u32 v; ++ int i; ++ ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ ++ dev_dbg(rkc->dev, "%s %s len=%d\n", __func__, ++ crypto_tfm_alg_name(areq->base.tfm), areq->nbytes); ++ ++ algt->stat_req++; ++ rkc->nreq++; ++ ++ rctx->mode = algt->rk_mode; ++ rctx->mode |= 0xffff0000; ++ rctx->mode |= RK_CRYPTO_ENABLE | RK_CRYPTO_HW_PAD; ++ writel(rctx->mode, rkc->reg + RK_CRYPTO_HASH_CTL); ++ ++ while (sgs && len > 0) { ++ dd = &rkc->tl[ddi]; ++ ++ todo = min(sg_dma_len(sgs), len); ++ dd->src_addr = sg_dma_address(sgs); ++ dd->src_len = todo; ++ dd->dst_addr = 0; ++ dd->dst_len = 0; ++ dd->dma_ctrl = ddi << 24; ++ dd->iv = 0; ++ dd->next = rkc->t_phy + sizeof(struct rk_crypto_lli) * (ddi + 1); ++ ++ if (ddi == 0) ++ dd->user = RK_LLI_CIPHER_START | RK_LLI_STRING_FIRST; ++ else ++ dd->user = 0; ++ ++ len -= todo; ++ dd->dma_ctrl |= RK_LLI_DMA_CTRL_SRC_INT; ++ if (len == 0) { ++ dd->user |= RK_LLI_STRING_LAST; ++ dd->dma_ctrl |= RK_LLI_DMA_CTRL_LAST; ++ } ++ dev_dbg(rkc->dev, "HASH SG %d sglen=%d user=%x dma=%x mode=%x len=%d todo=%d phy=%llx\n", ++ ddi, sgs->length, dd->user, dd->dma_ctrl, rctx->mode, len, todo, rkc->t_phy); ++ ++ sgs = sg_next(sgs); ++ ddi++; ++ } ++ dd->next = 1; ++ writel(RK_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK_CRYPTO_DMA_INT_EN); ++ ++ writel(rkc->t_phy, rkc->reg + RK_CRYPTO_DMA_LLI_ADDR); ++ ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; ++ ++ writel(RK_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK_CRYPTO_DMA_CTL); ++ ++ wait_for_completion_interruptible_timeout(&rkc->complete, ++ msecs_to_jiffies(2000)); ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); ++ err = -EFAULT; ++ goto theend; ++ } ++ ++ readl_poll_timeout_atomic(rkc->reg + RK_CRYPTO_HASH_VALID, v, v == 1, ++ 10, 1000); ++ ++ for (i = 0; i < crypto_ahash_digestsize(tfm) / 4; i++) { ++ v = readl(rkc->reg + RK_CRYPTO_HASH_DOUT_0 + i * 4); ++ put_unaligned_le32(be32_to_cpu(v), areq->result + i * 4); ++ } ++ ++theend: ++ pm_runtime_put_autosuspend(rkc->dev); ++ ++ local_bh_disable(); ++ crypto_finalize_hash_request(engine, breq, err); ++ local_bh_enable(); ++ ++ return 0; ++} ++ ++int rk_cra_hash_init(struct crypto_tfm *tfm) ++{ ++ struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); ++ const char *alg_name = crypto_tfm_alg_name(tfm); ++ struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.hash); ++ ++ /* for fallback */ ++ tctx->fallback_tfm = crypto_alloc_ahash(alg_name, 0, ++ CRYPTO_ALG_NEED_FALLBACK); ++ if (IS_ERR(tctx->fallback_tfm)) { ++ dev_err(algt->dev->dev, "Could not load fallback driver.\n"); ++ return PTR_ERR(tctx->fallback_tfm); ++ } ++ ++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), ++ sizeof(struct rk_ahash_rctx) + ++ crypto_ahash_reqsize(tctx->fallback_tfm)); ++ ++ tctx->enginectx.op.do_one_request = rk_hash_run; ++ tctx->enginectx.op.prepare_request = rk_hash_prepare; ++ tctx->enginectx.op.unprepare_request = rk_hash_unprepare; ++ ++ return 0; ++} ++ ++void rk_cra_hash_exit(struct crypto_tfm *tfm) ++{ ++ struct rk_ahash_ctx *tctx = crypto_tfm_ctx(tfm); ++ ++ crypto_free_ahash(tctx->fallback_tfm); ++} +--- /dev/null ++++ b/drivers/crypto/rockchip/rk3588_crypto_skcipher.c +@@ -0,0 +1,340 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * hardware cryptographic offloader for rk3568/rk3588 SoC ++ * ++ * Copyright (c) 2022 Corentin Labbe ++ */ ++#include ++#include "rk3588_crypto.h" ++ ++static int rk_cipher_need_fallback(struct skcipher_request *req) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.skcipher); ++ struct scatterlist *sgs, *sgd; ++ unsigned int stodo, dtodo, len; ++ unsigned int bs = crypto_skcipher_blocksize(tfm); ++ ++ if (!req->cryptlen) ++ return true; ++ ++ len = req->cryptlen; ++ sgs = req->src; ++ sgd = req->dst; ++ while (sgs && sgd) { ++ if (!IS_ALIGNED(sgs->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ if (!IS_ALIGNED(sgd->offset, sizeof(u32))) { ++ algt->stat_fb_align++; ++ return true; ++ } ++ stodo = min(len, sgs->length); ++ if (stodo % bs) { ++ algt->stat_fb_len++; ++ return true; ++ } ++ dtodo = min(len, sgd->length); ++ if (dtodo % bs) { ++ algt->stat_fb_len++; ++ return true; ++ } ++ if (stodo != dtodo) { ++ algt->stat_fb_sgdiff++; ++ return true; ++ } ++ len -= stodo; ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ } ++ return false; ++} ++ ++static int rk_cipher_fallback(struct skcipher_request *areq) ++{ ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); ++ struct rk_cipher_ctx *op = crypto_skcipher_ctx(tfm); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.skcipher); ++ int err; ++ ++ algt->stat_fb++; ++ ++ skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm); ++ skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags, ++ areq->base.complete, areq->base.data); ++ skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst, ++ areq->cryptlen, areq->iv); ++ if (rctx->mode & RK_CRYPTO_DEC) ++ err = crypto_skcipher_decrypt(&rctx->fallback_req); ++ else ++ err = crypto_skcipher_encrypt(&rctx->fallback_req); ++ return err; ++} ++ ++static int rk_cipher_handle_req(struct skcipher_request *req) ++{ ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ struct rk_crypto_dev *rkc; ++ struct crypto_engine *engine; ++ ++ if (rk_cipher_need_fallback(req)) ++ return rk_cipher_fallback(req); ++ ++ rkc = get_rk_crypto(); ++ ++ engine = rkc->engine; ++ rctx->dev = rkc; ++ ++ return crypto_transfer_skcipher_request_to_engine(engine, req); ++} ++ ++int rk_aes_setkey(struct crypto_skcipher *cipher, const u8 *key, ++ unsigned int keylen) ++{ ++ struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); ++ struct rk_cipher_ctx *ctx = crypto_tfm_ctx(tfm); ++ ++ if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && ++ keylen != AES_KEYSIZE_256) ++ return -EINVAL; ++ ctx->keylen = keylen; ++ memcpy(ctx->key, key, keylen); ++ ++ return crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); ++} ++ ++int rk_aes_ecb_encrypt(struct skcipher_request *req) ++{ ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ ++ rctx->mode = RK_CRYPTO_AES_ECB_MODE; ++ return rk_cipher_handle_req(req); ++} ++ ++int rk_aes_ecb_decrypt(struct skcipher_request *req) ++{ ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ ++ rctx->mode = RK_CRYPTO_AES_ECB_MODE | RK_CRYPTO_DEC; ++ return rk_cipher_handle_req(req); ++} ++ ++int rk_aes_cbc_encrypt(struct skcipher_request *req) ++{ ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ ++ rctx->mode = RK_CRYPTO_AES_CBC_MODE; ++ return rk_cipher_handle_req(req); ++} ++ ++int rk_aes_cbc_decrypt(struct skcipher_request *req) ++{ ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(req); ++ ++ rctx->mode = RK_CRYPTO_AES_CBC_MODE | RK_CRYPTO_DEC; ++ return rk_cipher_handle_req(req); ++} ++ ++static int rk_cipher_run(struct crypto_engine *engine, void *async_req) ++{ ++ struct skcipher_request *areq = container_of(async_req, struct skcipher_request, base); ++ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq); ++ struct rk_cipher_rctx *rctx = skcipher_request_ctx(areq); ++ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ struct scatterlist *sgs, *sgd; ++ int err = 0; ++ int ivsize = crypto_skcipher_ivsize(tfm); ++ unsigned int len = areq->cryptlen; ++ unsigned int todo; ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.skcipher); ++ struct rk_crypto_dev *rkc = rctx->dev; ++ struct rk_crypto_lli *dd = &rkc->tl[0]; ++ u32 m, v; ++ u32 *rkey = (u32 *)ctx->key; ++ u32 *riv = (u32 *)areq->iv; ++ int i; ++ unsigned int offset; ++ ++ err = pm_runtime_resume_and_get(rkc->dev); ++ if (err) ++ return err; ++ ++ algt->stat_req++; ++ rkc->nreq++; ++ ++ m = rctx->mode | RK_CRYPTO_ENABLE; ++ switch (ctx->keylen) { ++ case AES_KEYSIZE_128: ++ m |= RK_CRYPTO_AES_128BIT_key; ++ break; ++ case AES_KEYSIZE_192: ++ m |= RK_CRYPTO_AES_192BIT_key; ++ break; ++ case AES_KEYSIZE_256: ++ m |= RK_CRYPTO_AES_256BIT_key; ++ break; ++ } ++ /* the upper bits are a write enable mask, so we need to write 1 to all ++ * upper 16 bits to allow write to the 16 lower bits ++ */ ++ m |= 0xffff0000; ++ ++ dev_dbg(rkc->dev, "%s %s len=%u keylen=%u mode=%x\n", __func__, ++ crypto_tfm_alg_name(areq->base.tfm), ++ areq->cryptlen, ctx->keylen, m); ++ sgs = areq->src; ++ sgd = areq->dst; ++ ++ while (sgs && sgd && len) { ++ ivsize = crypto_skcipher_ivsize(tfm); ++ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) { ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ offset = sgs->length - ivsize; ++ scatterwalk_map_and_copy(rctx->backup_iv, sgs, ++ offset, ivsize, 0); ++ } ++ } ++ ++ if (sgs == sgd) { ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ goto theend; ++ } ++ } else { ++ err = dma_map_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ goto theend; ++ } ++ err = dma_map_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); ++ if (err != 1) { ++ dev_err(rkc->dev, "Invalid sg number %d\n", err); ++ err = -EINVAL; ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ goto theend; ++ } ++ } ++ err = 0; ++ writel(m, rkc->reg + RK_CRYPTO_BC_CTL); ++ ++ for (i = 0; i < ctx->keylen / 4; i++) { ++ v = cpu_to_be32(rkey[i]); ++ writel(v, rkc->reg + RK_CRYPTO_KEY0 + i * 4); ++ } ++ ++ if (ivsize) { ++ for (i = 0; i < ivsize / 4; i++) ++ writel(cpu_to_be32(riv[i]), ++ rkc->reg + RK_CRYPTO_CH0_IV_0 + i * 4); ++ writel(ivsize, rkc->reg + RK_CRYPTO_CH0_IV_LEN); ++ } ++ if (!sgs->length) { ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ continue; ++ } ++ ++ /* The hw support multiple descriptor, so why this driver use ++ * only one descritor ? ++ * Using one descriptor per SG seems the way to do and it works ++ * but only when doing encryption. ++ * With decryption it always fail on second descriptor. ++ * Probably the HW dont know how to use IV. ++ */ ++ todo = min(sg_dma_len(sgs), len); ++ len -= todo; ++ dd->src_addr = sg_dma_address(sgs); ++ dd->src_len = todo; ++ dd->dst_addr = sg_dma_address(sgd); ++ dd->dst_len = todo; ++ dd->iv = 0; ++ dd->next = 1; ++ ++ dd->user = RK_LLI_CIPHER_START | RK_LLI_STRING_FIRST | RK_LLI_STRING_LAST; ++ dd->dma_ctrl |= RK_LLI_DMA_CTRL_DST_INT | RK_LLI_DMA_CTRL_LAST; ++ ++ writel(RK_CRYPTO_DMA_INT_LISTDONE | 0x7F, rkc->reg + RK_CRYPTO_DMA_INT_EN); ++ ++ writel(rkc->t_phy, rkc->reg + RK_CRYPTO_DMA_LLI_ADDR); ++ ++ reinit_completion(&rkc->complete); ++ rkc->status = 0; ++ ++ writel(RK_CRYPTO_DMA_CTL_START | 1 << 16, rkc->reg + RK_CRYPTO_DMA_CTL); ++ ++ wait_for_completion_interruptible_timeout(&rkc->complete, ++ msecs_to_jiffies(10000)); ++ if (sgs == sgd) { ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_BIDIRECTIONAL); ++ } else { ++ dma_unmap_sg(rkc->dev, sgs, 1, DMA_TO_DEVICE); ++ dma_unmap_sg(rkc->dev, sgd, 1, DMA_FROM_DEVICE); ++ } ++ ++ if (!rkc->status) { ++ dev_err(rkc->dev, "DMA timeout\n"); ++ err = -EFAULT; ++ goto theend; ++ } ++ if (areq->iv && ivsize > 0) { ++ offset = sgd->length - ivsize; ++ if (rctx->mode & RK_CRYPTO_DEC) { ++ memcpy(areq->iv, rctx->backup_iv, ivsize); ++ memzero_explicit(rctx->backup_iv, ivsize); ++ } else { ++ scatterwalk_map_and_copy(areq->iv, sgd, offset, ++ ivsize, 0); ++ } ++ } ++ sgs = sg_next(sgs); ++ sgd = sg_next(sgd); ++ } ++theend: ++ writel(0xffff0000, rkc->reg + RK_CRYPTO_BC_CTL); ++ pm_runtime_put_autosuspend(rkc->dev); ++ ++ local_bh_disable(); ++ crypto_finalize_skcipher_request(engine, areq, err); ++ local_bh_enable(); ++ return 0; ++} ++ ++int rk_cipher_tfm_init(struct crypto_skcipher *tfm) ++{ ++ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ const char *name = crypto_tfm_alg_name(&tfm->base); ++ struct skcipher_alg *alg = crypto_skcipher_alg(tfm); ++ struct rk_crypto_template *algt = container_of(alg, struct rk_crypto_template, alg.skcipher); ++ ++ ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK); ++ if (IS_ERR(ctx->fallback_tfm)) { ++ dev_err(algt->dev->dev, "ERROR: Cannot allocate fallback for %s %ld\n", ++ name, PTR_ERR(ctx->fallback_tfm)); ++ return PTR_ERR(ctx->fallback_tfm); ++ } ++ ++ tfm->reqsize = sizeof(struct rk_cipher_rctx) + ++ crypto_skcipher_reqsize(ctx->fallback_tfm); ++ ++ ctx->enginectx.op.do_one_request = rk_cipher_run; ++ ctx->enginectx.op.prepare_request = NULL; ++ ctx->enginectx.op.unprepare_request = NULL; ++ ++ return 0; ++} ++ ++void rk_cipher_tfm_exit(struct crypto_skcipher *tfm) ++{ ++ struct rk_cipher_ctx *ctx = crypto_skcipher_ctx(tfm); ++ ++ memzero_explicit(ctx->key, ctx->keylen); ++ crypto_free_skcipher(ctx->fallback_tfm); ++} diff --git a/target/linux/rockchip/patches-6.6/016-ARM64-dts-rk3568-add-crypto-node.patch b/target/linux/rockchip/patches-6.6/016-ARM64-dts-rk3568-add-crypto-node.patch new file mode 100644 index 00000000000000..6648d687a3ff25 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/016-ARM64-dts-rk3568-add-crypto-node.patch @@ -0,0 +1,36 @@ +From a835ba3fd0d62c735e17bf40bee95e2931e44b84 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe +Date: Tue, 27 Sep 2022 08:00:48 +0000 +Subject: [PATCH 16/95] ARM64: dts: rk3568: add crypto node + +The rk3568 has a crypto IP handled by the rk3588 crypto driver so adds a +node for it. + +Signed-off-by: Corentin Labbe +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -213,6 +213,20 @@ + }; + }; + ++ crypto: crypto@fe380000 { ++ compatible = "rockchip,rk3568-crypto"; ++ reg = <0x0 0xfe380000 0x0 0x2000>; ++ interrupts = ; ++ clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, ++ <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; ++ clock-names = "aclk", "hclk", "sclk", "pka"; ++ resets = <&cru SRST_CRYPTO_NS_CORE>, <&cru SRST_A_CRYPTO_NS>, ++ <&cru SRST_H_CRYPTO_NS>, <&cru SRST_CRYPTO_NS_RNG>, ++ <&cru SRST_CRYPTO_NS_PKA>; ++ reset-names = "core", "a", "h", "rng,", "pka"; ++ status = "okay"; ++ }; ++ + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/017-drivers-crypto-rockchip-fix-openwrt-build.patch b/target/linux/rockchip/patches-6.6/017-drivers-crypto-rockchip-fix-openwrt-build.patch new file mode 100644 index 00000000000000..948a29047ffe8f --- /dev/null +++ b/target/linux/rockchip/patches-6.6/017-drivers-crypto-rockchip-fix-openwrt-build.patch @@ -0,0 +1,31 @@ +From 1dc0e2c75df089cdf1acb78192381f40088bba01 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Thu, 29 Sep 2022 18:44:42 -0400 +Subject: [PATCH 17/95] drivers: crypto-rockchip fix openwrt build + +Signed-off-by: Marty Jones +--- + drivers/crypto/rockchip/rk3288_crypto.c | 12 ------------ + 1 file changed, 12 deletions(-) + +--- a/drivers/crypto/rockchip/rk3288_crypto.c ++++ b/drivers/crypto/rockchip/rk3288_crypto.c +@@ -31,18 +31,6 @@ static struct rockchip_ip rocklist = { + .lock = __SPIN_LOCK_UNLOCKED(rocklist.lock), + }; + +-struct rk_crypto_info *get_rk_crypto(void) +-{ +- struct rk_crypto_info *first; +- +- spin_lock(&rocklist.lock); +- first = list_first_entry_or_null(&rocklist.dev_list, +- struct rk_crypto_info, list); +- list_rotate_left(&rocklist.dev_list); +- spin_unlock(&rocklist.lock); +- return first; +-} +- + static const struct rk_variant rk3288_variant = { + .num_clks = 4, + .rkclks = { diff --git a/target/linux/rockchip/patches-6.6/018-rock3a-fixes.patch b/target/linux/rockchip/patches-6.6/018-rock3a-fixes.patch new file mode 100644 index 00000000000000..a3d2dcc858242e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/018-rock3a-fixes.patch @@ -0,0 +1,109 @@ +From 1b31cbc7f82082266049fadedf822affa49db8f6 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Tue, 30 May 2023 01:56:43 -0400 +Subject: [PATCH 18/95] rock3a fixes + +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 35 +++++++++---------- + 1 file changed, 17 insertions(+), 18 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -32,13 +32,6 @@ + }; + }; + +- gmac1_clkin: external-gmac1-clock { +- compatible = "fixed-clock"; +- clock-frequency = <125000000>; +- clock-output-names = "gmac1_clkin"; +- #clock-cells = <0>; +- }; +- + leds { + compatible = "gpio-leds"; + +@@ -256,18 +249,25 @@ + + &gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; +- clock_in_out = "input"; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; ++ clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; +- phy-mode = "rgmii-id"; +- phy-supply = <&vcc_3v3>; ++ phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk +- &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; ++ ++ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; ++ ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ + status = "okay"; + }; + +@@ -410,6 +410,7 @@ + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; ++ regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + +@@ -446,6 +447,7 @@ + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; ++ regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + +@@ -504,6 +506,7 @@ + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; ++ regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + +@@ -524,6 +527,7 @@ + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; ++ regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; +@@ -585,11 +589,6 @@ + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; +- pinctrl-names = "default"; +- pinctrl-0 = <ð_phy_rst>; +- reset-assert-us = <20000>; +- reset-deassert-us = <100000>; +- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; + }; + +@@ -793,7 +792,7 @@ + }; + + &usb_host0_xhci { +- extcon = <&usb2phy0>; ++ dr_mode = "host"; + status = "okay"; + }; + diff --git a/target/linux/rockchip/patches-6.6/019-rock-pi-4b-fix-wifi.patch b/target/linux/rockchip/patches-6.6/019-rock-pi-4b-fix-wifi.patch new file mode 100644 index 00000000000000..c685f07e5b4f27 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/019-rock-pi-4b-fix-wifi.patch @@ -0,0 +1,20 @@ +From e85254ff587de217555b1eca5f6c5a66ba0df283 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Tue, 30 May 2023 01:58:03 -0400 +Subject: [PATCH 19/95] rock pi 4b fix wifi + +--- + arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +@@ -24,7 +24,7 @@ + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; +- interrupts = ; ++ interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; diff --git a/target/linux/rockchip/patches-6.6/020-nanopi-r5c-r5s-fixes.patch b/target/linux/rockchip/patches-6.6/020-nanopi-r5c-r5s-fixes.patch new file mode 100644 index 00000000000000..bc1118f392b295 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/020-nanopi-r5c-r5s-fixes.patch @@ -0,0 +1,233 @@ +From 4ec87387e211ac6ffb0315c470d52d73cfb2a639 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Sun, 4 Jun 2023 02:29:36 -0400 +Subject: [PATCH] fix r5s r5c + +Signed-off-by: Marty Jones +--- + .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 70 ++++++++++--------- + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 61 ++++++++-------- + 2 files changed, 67 insertions(+), 64 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts +@@ -11,14 +11,14 @@ + + / { + model = "FriendlyElec NanoPi R5C"; +- compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; ++ compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; + +- gpio-keys { ++ gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +- pinctrl-0 = <&reset_button_pin>; ++ pinctrl-0 = <&key1_pin>; + +- button-reset { ++ key-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "reset"; +@@ -28,39 +28,41 @@ + + gpio-leds { + compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; +- +- led-lan { +- color = ; +- function = LED_FUNCTION_LAN; +- gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; +- }; + +- power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; ++ sys_led: led-sys { ++ label = "red:sys"; + linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&sys_led_pin>; + }; + +- led-wan { +- color = ; +- function = LED_FUNCTION_WAN; ++ lan-led { ++ label = "green:lan"; ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan_led_pin>; ++ }; ++ ++ wan-led { ++ label = "green:wan"; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wan_led_pin>; + }; + +- led-wlan { +- color = ; +- function = LED_FUNCTION_WLAN; ++ wlan-led { ++ label = "green:wlan"; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wlan_led_pin>; + }; + }; + }; + + &pcie2x1 { + pinctrl-names = "default"; +- pinctrl-0 = <&pcie20_reset_pin>; ++ pinctrl-0 = <&m2_w_disable_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +@@ -80,15 +82,21 @@ + }; + + &pinctrl { +- gpio-leds { +- lan_led_pin: lan-led-pin { +- rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ gpio-key { ++ key1_pin: key1-pin { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; ++ }; + +- power_led_pin: power-led-pin { ++ gpio-leds { ++ sys_led_pin: power-led-pin { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + ++ lan_led_pin: lan-led-pin { ++ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; +@@ -98,15 +106,9 @@ + }; + }; + +- pcie { +- pcie20_reset_pin: pcie20-reset-pin { ++ m2-pins { ++ m2_w_disable_pin: m2-w-disable-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +- +- rockchip-key { +- reset_button_pin: reset-button-pin { +- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; +- }; +- }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +@@ -11,7 +11,7 @@ + + / { + model = "FriendlyElec NanoPi R5S"; +- compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; ++ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; +@@ -19,34 +19,34 @@ + + gpio-leds { + compatible = "gpio-leds"; +- pinctrl-names = "default"; +- pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + +- led-lan1 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <1>; +- gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ sys_led: led-sys { ++ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ label = "red:power"; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sys_led_pin>; + }; + +- led-lan2 { +- color = ; +- function = LED_FUNCTION_LAN; +- function-enumerator = <2>; +- gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ wan_led: led-wan { ++ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wan_led_pin>; + }; + +- power_led: led-power { +- color = ; +- function = LED_FUNCTION_POWER; +- linux,default-trigger = "heartbeat"; +- gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; ++ lan1_led: led-lan1 { ++ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ label = "green:lan1"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>; + }; + +- led-wan { +- color = ; +- function = LED_FUNCTION_WAN; +- gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; ++ lan2_led: led-lan2 { ++ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; ++ label = "green:lan2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan2_led_pin>; + }; + }; + }; +@@ -117,20 +117,21 @@ + }; + + gpio-leds { +- lan1_led_pin: lan1-led-pin { +- rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +- }; + +- lan2_led_pin: lan2-led-pin { +- rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; +- }; +- +- power_led_pin: power-led-pin { ++ sys_led_pin: sys-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; + }; + }; diff --git a/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch b/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch deleted file mode 100644 index fb5015cf6e0fe4..00000000000000 --- a/target/linux/rockchip/patches-6.6/023-v6.8-arm64-dts-rockchip-Add-ethernet0-alias-to-the-dts-for-RK3566-boards.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 36d9b3ae708e865cdab95692db5a24c5d975383d Mon Sep 17 00:00:00 2001 -From: Dragan Simic -Date: Tue, 12 Dec 2023 09:01:39 +0100 -Subject: [PATCH] arm64: dts: rockchip: Add ethernet0 alias to the dts for - RK3566 boards - -Add ethernet0 alias to the board dts files for a few supported RK3566 boards -that had it missing. Also, remove the ethernet0 alias from one RK3566 SoM -dtsi file, which doesn't enable the GMAC, and add the ethernet0 alias back to -the dependent board dts files, which actually enable the GMAC. - -Signed-off-by: Dragan Simic -Link: https://lore.kernel.org/r/d2a272e0ae0fff0adfab8bb0238243b11d348799.1702368023.git.dsimic@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 1 + - 1 files changed, 1 insertions(+), 0 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -14,6 +14,7 @@ - compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566"; - - aliases { -+ ethernet0 = &gmac1; - mmc1 = &sdmmc0; - }; - diff --git a/target/linux/rockchip/patches-6.6/095-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch b/target/linux/rockchip/patches-6.6/095-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch new file mode 100644 index 00000000000000..31b843efbbcf28 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/095-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch @@ -0,0 +1,17 @@ +From 3e8be25a2ae2141c94bf20c75200e8282605d825 Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Tue, 30 May 2023 02:03:35 -0400 +Subject: [PATCH 95/95] rockchip: add FriendlyElec NanoPi R6C/R6S + +--- + arch/arm64/boot/dts/rockchip/Makefile | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -106,3 +106,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb diff --git a/target/linux/rockchip/patches-6.6/097-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch b/target/linux/rockchip/patches-6.6/097-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch new file mode 100644 index 00000000000000..6961b355099d4a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/097-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch @@ -0,0 +1,144 @@ +From ba70dba1ea8347003c94f0fdad00ff6dd765408c Mon Sep 17 00:00:00 2001 +From: Marty Jones +Date: Tue, 13 Jun 2023 02:40:07 -0400 +Subject: [PATCH] rockchip: add FriendlyElec NanoPi R6C Plus + +Signed-off-by: Marty Jones +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3588s-nanopi-r6c-plus.dts | 121 ++++++++++++++++++ + 2 files changed, 122 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c-plus.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -107,4 +107,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c-plus.dts +@@ -0,0 +1,121 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. ++ * (http://www.friendlyelec.com) ++ * Copyright (c) 2023, Marty Jones ; ++ }; ++ ++ gpio_leds: gpio-leds { ++ compatible = "gpio-leds"; ++ ++ sys_led: led-sys { ++ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ label = "red:sys"; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sys_led_pin>; ++ }; ++ ++ wan_led: led-wan { ++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; ++ label = "green:wan"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wan_led_pin>; ++ }; ++ ++ lan_led: led-lan { ++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; ++ label = "green:lan"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan1_led_pin>; ++ }; ++ ++ lan2_led: led-lan2 { ++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; ++ label = "green:lan1"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lan2_led_pin>; ++ }; ++ }; ++}; ++ ++ ++&pinctrl { ++ gpio-key { ++ key1_pin: key1-pin { ++ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-leds { ++ sys_led_pin: sys-led-pin { ++ rockchip,pins = ++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wan_led_pin: wan-led-pin { ++ rockchip,pins = ++ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan1_led_pin: lan1-led-pin { ++ rockchip,pins = ++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ lan2_led_pin: lan2-led-pin { ++ rockchip,pins = ++ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host20_en: vcc5v0-host20-en { ++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ clock-frequency = <200000>; ++ status = "okay"; ++ ++ eeprom@53 { ++ compatible = "microchip,24c02", "atmel,24c02"; ++ reg = <0x53>; ++ #address-cells = <2>; ++ #size-cells = <0>; ++ pagesize = <16>; ++ size = <256>; ++ ++ eui_48: eui-48@fa { ++ reg = <0xfa 0x06>; ++ }; ++ }; ++}; diff --git a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch deleted file mode 100644 index 683e5347f75b01..00000000000000 --- a/target/linux/rockchip/patches-6.6/100-rockchip-use-system-LED-for-OpenWrt.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001 -From: David Bauer -Date: Fri, 10 Jul 2020 21:38:20 +0200 -Subject: [PATCH] rockchip: use system LED for OpenWrt - -Use the SYS LED on the casing for showing system status. - -This patch is kept separate from the NanoPi R2S support patch, as i plan -on submitting the device support upstream. - -Signed-off-by: David Bauer ---- - arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -6,6 +6,7 @@ - /dts-v1/; - - #include -+#include - #include - #include "rk3328.dtsi" - -@@ -16,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; - }; - - chosen { -@@ -48,19 +54,22 @@ - pinctrl-names = "default"; - - lan_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_LAN; - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:lan"; - }; - - sys_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; - gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:red:sys"; - default-state = "on"; - }; - - wan_led: led-2 { -+ color = ; -+ function = LED_FUNCTION_WAN; - gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; -- label = "nanopi-r2s:green:wan"; - }; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -13,6 +13,11 @@ - aliases { - mmc0 = &sdmmc; - mmc1 = &emmc; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen { diff --git a/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch b/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch deleted file mode 100644 index d7579d61e90ce3..00000000000000 --- a/target/linux/rockchip/patches-6.6/106-r4s-openwrt-leds.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -19,6 +19,13 @@ - model = "FriendlyElec NanoPi R4S"; - compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &sys_led; -+ led-failsafe = &sys_led; -+ led-running = &sys_led; -+ led-upgrade = &sys_led; -+ }; -+ - /delete-node/ display-subsystem; - - gpio-leds { diff --git a/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch b/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch deleted file mode 100644 index 3aff37d0969b01..00000000000000 --- a/target/linux/rockchip/patches-6.6/107-arm64-dts-rockchip-Update-LED-properties-for-Orange-.patch +++ /dev/null @@ -1,40 +0,0 @@ -From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:10:52 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1 - Plus - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Tianling Shen ---- - .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++-------- - 1 file changed, 9 insertions(+), 8 deletions(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -17,6 +17,11 @@ - aliases { - ethernet1 = &rtl8153; - mmc0 = &sdmmc; -+ -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen { -@@ -41,11 +46,10 @@ - gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; - }; - -- led-1 { -+ status_led: led-1 { - function = LED_FUNCTION_STATUS; - color = ; - gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -- linux,default-trigger = "heartbeat"; - }; - - led-2 { diff --git a/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch b/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch deleted file mode 100644 index af8f8b16bada0a..00000000000000 --- a/target/linux/rockchip/patches-6.6/108-arm64-dts-rockchip-add-LED-configuration-to-Orange-P.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Fri, 19 May 2023 12:38:04 +0800 -Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1 - Plus - -Add the correct value for the RTL8153 LED configuration register to -match the blink behavior of the other port on the device. - -Signed-off-by: Tianling Shen ---- - arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts -@@ -365,6 +365,7 @@ - rtl8153: device@2 { - compatible = "usbbda,8153"; - reg = <2>; -+ realtek,led-data = <0x87>; - }; - }; - diff --git a/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch deleted file mode 100644 index 1a80dadd48b93b..00000000000000 --- a/target/linux/rockchip/patches-6.6/109-nanopc-t4-add-led-aliases.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts -@@ -15,6 +15,13 @@ - model = "FriendlyElec NanoPC-T4"; - compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; - -+ aliases { -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; -+ }; -+ - vcc12v0_sys: vcc12v0-sys { - compatible = "regulator-fixed"; - regulator-always-on; diff --git a/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch b/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch deleted file mode 100644 index c22fdd52b8a789..00000000000000 --- a/target/linux/rockchip/patches-6.6/110-arm64-dts-rockchip-Update-LED-properties-for-NanoPi-.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Tianling Shen -Date: Tue Jun 20 16:45:27 2023 +0800 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5 - series - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Tianling Shen ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts -@@ -40,7 +40,6 @@ - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts -@@ -39,7 +39,6 @@ - power_led: led-power { - color = ; - function = LED_FUNCTION_POWER; -- linux,default-trigger = "heartbeat"; - gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; - }; - ---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi -@@ -18,6 +18,11 @@ - aliases { - mmc0 = &sdmmc0; - mmc1 = &sdhci; -+ -+ led-boot = &power_led; -+ led-failsafe = &power_led; -+ led-running = &power_led; -+ led-upgrade = &power_led; - }; - - chosen: chosen { diff --git a/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch b/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch deleted file mode 100644 index c8183a2b8ae9b6..00000000000000 --- a/target/linux/rockchip/patches-6.6/111-radxa-cm3-io-add-led-aliases.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marius Durbaca -Date: Tue Feb 20 15:05:27 2024 +0200 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa -CM3 IO board - -Add OpenWrt's LED aliases for showing system status. - -Suggested-by: Tianling Shen -Signed-off-by: Marius Durbaca ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts -@@ -16,6 +16,10 @@ - aliases { - ethernet0 = &gmac1; - mmc1 = &sdmmc0; -+ led-boot = &status_led; -+ led-failsafe = &status_led; -+ led-running = &status_led; -+ led-upgrade = &status_led; - }; - - chosen: chosen { ---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi -@@ -17,7 +17,7 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ status_led: led-0 { - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_STATUS; diff --git a/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases-and-stop-heartbeat.patch deleted file mode 100644 index 6bcde5b8ebefcd..00000000000000 --- a/target/linux/rockchip/patches-6.6/112-radxa-e25-add-led-aliases-and-stop-heartbeat.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marius Durbaca -Date: Tue Feb 27 16:25:27 2024 +0200 -Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa -E25 - -Add OpenWrt's LED aliases for showing system status. - -Signed-off-by: Marius Durbaca ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts -@@ -9,6 +9,10 @@ - - aliases { - mmc1 = &sdmmc0; -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - pwm-leds { ---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi -@@ -23,7 +23,7 @@ - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - function = LED_FUNCTION_HEARTBEAT; - color = ; -- linux,default-trigger = "heartbeat"; -+ default-state = "on"; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; diff --git a/target/linux/rockchip/patches-6.6/115-rock-3a-add-led-aliases-and-stop-heartbeat.patch b/target/linux/rockchip/patches-6.6/115-rock-3a-add-led-aliases-and-stop-heartbeat.patch deleted file mode 100644 index bdcc96ce83140c..00000000000000 --- a/target/linux/rockchip/patches-6.6/115-rock-3a-add-led-aliases-and-stop-heartbeat.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -15,6 +15,10 @@ - ethernet0 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; -+ led-boot = &led_blue; -+ led-failsafe = &led_blue; -+ led-running = &led_blue; -+ led-upgrade = &led_blue; - }; - - chosen: chosen { -@@ -42,11 +46,11 @@ - leds { - compatible = "gpio-leds"; - -- led_user: led-0 { -- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -- function = LED_FUNCTION_HEARTBEAT; -+ led_blue: led-0 { - color = ; -- linux,default-trigger = "heartbeat"; -+ default-state = "on"; -+ function = LED_FUNCTION_HEARTBEAT; -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&led_user_en>; - }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch b/target/linux/rockchip/patches-6.6/200-v6.7-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch new file mode 100644 index 00000000000000..a91a557b093729 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-01-clk-divider-Fix-divisor-masking-on-64-bit-platforms.patch @@ -0,0 +1,81 @@ +From 122481e9b538979f0ab1b6d2ebbcd3446cec4a33 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 18 May 2023 05:19:48 +0200 +Subject: [PATCH 01/41] clk: divider: Fix divisor masking on 64 bit platforms + +The clock framework handles clock rates as "unsigned long", so u32 on +32-bit architectures and u64 on 64-bit architectures. + +The current code casts the dividend to u64 on 32-bit to avoid a +potential overflow. For example DIV_ROUND_UP(3000000000, 1500000000) += (3.0G + 1.5G - 1) / 1.5G = = OVERFLOW / 1.5G, which has been +introduced in commit 9556f9dad8f5 ("clk: divider: handle integer overflow +when dividing large clock rates"). + +On 64 bit platforms this masks the divisor, so that only the lower +32 bit are used. Thus requesting a frequency >= 4.3GHz results +in incorrect values. For example requesting 4300000000 (4.3 GHz) will +effectively request ca. 5 MHz. Requesting clk_round_rate(clk, ULONG_MAX) +is a bit of a special case, since that still returns correct values as +long as the parent clock is below 8.5 GHz. + +Fix this by introducing a new helper, which avoids the overflow +by using a modulo operation instead of math tricks. This avoids +any requirements on the arguments (except that divisor should not +be 0 obviously). + +Signed-off-by: Sebastian Reichel +--- + drivers/clk/clk-divider.c | 6 +++--- + include/linux/math.h | 11 +++++++++++ + 2 files changed, 14 insertions(+), 3 deletions(-) + +--- a/drivers/clk/clk-divider.c ++++ b/drivers/clk/clk-divider.c +@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl + unsigned long parent_rate, unsigned long rate, + unsigned long flags) + { +- int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ int div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + + if (flags & CLK_DIVIDER_POWER_OF_TWO) + div = __roundup_pow_of_two(div); +@@ -237,7 +237,7 @@ static int _div_round_closest(const stru + int up, down; + unsigned long up_rate, down_rate; + +- up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ up = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + down = parent_rate / rate; + + if (flags & CLK_DIVIDER_POWER_OF_TWO) { +@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate, + { + unsigned int div, value; + +- div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); ++ div = DIV_ROUND_UP_NO_OVERFLOW(parent_rate, rate); + + if (!_is_valid_div(table, div, flags)) + return -EINVAL; +--- a/include/linux/math.h ++++ b/include/linux/math.h +@@ -36,6 +36,17 @@ + + #define DIV_ROUND_UP __KERNEL_DIV_ROUND_UP + ++/** ++ * DIV_ROUND_UP_NO_OVERFLOW - divide two numbers and always round up ++ * @n: numerator / dividend ++ * @d: denominator / divisor ++ * ++ * This functions does the same as DIV_ROUND_UP, but internally uses a ++ * division and a modulo operation instead of math tricks. This way it ++ * avoids overflowing when handling big numbers. ++ */ ++#define DIV_ROUND_UP_NO_OVERFLOW(n, d) (((n) / (d)) + !!((n) % (d))) ++ + #define DIV_ROUND_DOWN_ULL(ll, d) \ + ({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; }) + diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-07-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network-con.patch b/target/linux/rockchip/patches-6.6/200-v6.7-07-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network-con.patch new file mode 100644 index 00000000000000..a9f0b96916e772 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-07-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-network-con.patch @@ -0,0 +1,88 @@ +From 1f538925b863f9b0fdd1c24570565e8e4985b8a0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Mon, 17 Apr 2023 21:13:03 +0200 +Subject: [PATCH 07/41] arm64: dts: rockchip: rk3588-evb1: add PCIe2 network + controller + +The RK3588 EVB1 has a second network card, which is connected +via PCIe2. This adds support for that. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 43 +++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -29,6 +29,26 @@ + pwms = <&pwm2 0 25000 0>; + }; + ++ pcie20_avdd0v85: pcie20-avdd0v85-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie20_avdd0v85"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ vin-supply = <&avdd_0v85_s0>; ++ }; ++ ++ pcie20_avdd1v8: pcie20-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie20_avdd1v8"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&avcc_1v8_s0>; ++ }; ++ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -87,6 +107,10 @@ + status = "okay"; + }; + ++&combphy2_psu { ++ status = "okay"; ++}; ++ + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + }; +@@ -163,7 +187,20 @@ + }; + }; + ++&pcie2x1l1 { ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; ++ status = "okay"; ++}; ++ + &pinctrl { ++ rtl8111 { ++ rtl8111_isolate: rtl8111-isolate { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -177,6 +214,12 @@ + }; + }; + ++ pcie2 { ++ pcie2_1_rst: pcie2-1-rst { ++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-08-arm64-dts-rockchip-rk3588-evb1-add-PCIe3-bus.patch b/target/linux/rockchip/patches-6.6/200-v6.7-08-arm64-dts-rockchip-rk3588-evb1-add-PCIe3-bus.patch new file mode 100644 index 00000000000000..8905c066b28d14 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-08-arm64-dts-rockchip-rk3588-evb1-add-PCIe3-bus.patch @@ -0,0 +1,97 @@ +From b7295c0349ff35a32c37e9429e3359d12f3ecf0b Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 11 Jul 2023 17:20:47 +0200 +Subject: [PATCH 08/41] arm64: dts: rockchip: rk3588-evb1: add PCIe3 bus + +Enable PCIe3 support, which is exposed via a PCIe3 connector. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 55 +++++++++++++++++++ + 1 file changed, 55 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -49,6 +49,26 @@ + vin-supply = <&avcc_1v8_s0>; + }; + ++ pcie30_avdd0v75: pcie30-avdd0v75-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v75"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ vin-supply = <&avdd_0v75_s0>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&avcc_1v8_s0>; ++ }; ++ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -58,6 +78,19 @@ + regulator-max-microvolt = <12000000>; + }; + ++ vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc12v_dcin>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc3v3_pcie30_en>; ++ }; ++ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; +@@ -194,6 +227,18 @@ + status = "okay"; + }; + ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_reset>; ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ + &pinctrl { + rtl8111 { + rtl8111_isolate: rtl8111-isolate { +@@ -220,6 +265,16 @@ + }; + }; + ++ pcie3 { ++ pcie3_reset: pcie3-reset { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc3v3_pcie30_en: vcc3v3-pcie30-en { ++ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-09-arm64-dts-rockchip-rock-5b-add-PCIe-network-controll.patch b/target/linux/rockchip/patches-6.6/200-v6.7-09-arm64-dts-rockchip-rock-5b-add-PCIe-network-controll.patch new file mode 100644 index 00000000000000..4c90bc2da04755 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-09-arm64-dts-rockchip-rock-5b-add-PCIe-network-controll.patch @@ -0,0 +1,71 @@ +From 7d2e3eded0118612014961b6e8c2a3dd2e9daee0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 28 Feb 2023 14:40:59 +0000 +Subject: [PATCH 09/41] arm64: dts: rockchip: rock-5b: add PCIe network + controller + +Enable the RTL8125 network controller, which is connected via +PCIe. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 27 +++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -44,6 +44,15 @@ + #cooling-cells = <2>; + }; + ++ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; +@@ -78,6 +87,10 @@ + }; + }; + ++&combphy0_ps { ++ status = "okay"; ++}; ++ + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + }; +@@ -204,6 +217,14 @@ + }; + }; + ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_2_rst>; ++ status = "okay"; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -217,6 +238,12 @@ + }; + }; + ++ pcie2 { ++ pcie2_2_rst: pcie2-2-rst { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-10-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-M-key.patch b/target/linux/rockchip/patches-6.6/200-v6.7-10-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-M-key.patch new file mode 100644 index 00000000000000..81f43bee0763ef --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-10-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-M-key.patch @@ -0,0 +1,71 @@ +From f979867857a275629d365ca5f4db1148a9879176 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 14 Jul 2023 19:19:29 +0200 +Subject: [PATCH 10/41] arm64: dts: rockchip: rock-5b: add PCIe for M.2 M-key + +The Radxa Rock 5B has PCIe 3x4 routed to its M.2 M-key connector +on the board's back. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -53,6 +53,19 @@ + vin-supply = <&vcc_3v3_s3>; + }; + ++ vcc3v3_pcie30: vcc3v3-pcie30-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie30"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_vcc3v3_en>; ++ }; ++ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; +@@ -225,6 +238,18 @@ + status = "okay"; + }; + ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_rst>; ++ status = "okay"; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -244,6 +269,16 @@ + }; + }; + ++ pcie3 { ++ pcie3_rst: pcie3-rst { ++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie3_vcc3v3_en: pcie3-vcc3v3-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-11-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-E-Key.patch b/target/linux/rockchip/patches-6.6/200-v6.7-11-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-E-Key.patch new file mode 100644 index 00000000000000..7ff8171e5e3ad7 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-11-arm64-dts-rockchip-rock-5b-add-PCIe-for-M.2-E-Key.patch @@ -0,0 +1,78 @@ +From c6b2b27433180b30e0756f228f0cf4b4b9d5ac5a Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 21 Jul 2023 17:43:58 +0200 +Subject: [PATCH 11/41] arm64: dts: rockchip: rock-5b: add PCIe for M.2 E-Key + +Enable PCIe2_0 controller and its voltage supply, which is routed +to the M.2 E-Key on the upper side of the Radxa Rock 5B. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 35 +++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -44,6 +44,21 @@ + #cooling-cells = <2>; + }; + ++ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie2x1l0"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ regulator-boot-on; ++ regulator-always-on; ++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_vcc3v3_en>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; +@@ -104,6 +119,10 @@ + status = "okay"; + }; + ++&combphy1_ps { ++ status = "okay"; ++}; ++ + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + }; +@@ -230,6 +249,14 @@ + }; + }; + ++&pcie2x1l0 { ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ status = "okay"; ++}; ++ + &pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; +@@ -264,6 +291,14 @@ + }; + + pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-12-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch b/target/linux/rockchip/patches-6.6/200-v6.7-12-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch new file mode 100644 index 00000000000000..8bef7eb25fa137 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-12-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch @@ -0,0 +1,61 @@ +From ab9b8789c6e472196230793b207e6ed69aacb156 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Jul 2023 18:05:56 +0200 +Subject: [PATCH 12/41] dt-bindings: usb: add rk3588 compatible to + rockchip,dwc3 + +RK3588 has three DWC3 controllers. Two of them are fully functional in +host, device and OTG mode including USB2 support. They are connected to +dedicated PHYs, that also support USB-C's DisplayPort alternate mode. + +The third controller is connected to one of the combphy's shared +with PCIe and SATA. It can only be used in host mode and does not +support USB2. Compared to the other controllers this one needs +some extra clocks. + +Signed-off-by: Sebastian Reichel +--- + .../devicetree/bindings/usb/rockchip,dwc3.yaml | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml ++++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +@@ -30,6 +30,7 @@ select: + enum: + - rockchip,rk3328-dwc3 + - rockchip,rk3568-dwc3 ++ - rockchip,rk3588-dwc3 + required: + - compatible + +@@ -39,6 +40,7 @@ properties: + - enum: + - rockchip,rk3328-dwc3 + - rockchip,rk3568-dwc3 ++ - rockchip,rk3588-dwc3 + - const: snps,dwc3 + + reg: +@@ -58,7 +60,9 @@ properties: + Master/Core clock, must to be >= 62.5 MHz for SS + operation and >= 30MHz for HS operation + - description: +- Controller grf clock ++ Controller grf clock OR UTMI clock ++ - description: ++ PIPE clock + + clock-names: + minItems: 3 +@@ -66,7 +70,10 @@ properties: + - const: ref_clk + - const: suspend_clk + - const: bus_clk +- - const: grf_clk ++ - enum: ++ - grf_clk ++ - utmi ++ - const: pipe + + power-domains: + maxItems: 1 diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-13-usb-dwc3-add-optional-PHY-interface-clocks.patch b/target/linux/rockchip/patches-6.6/200-v6.7-13-usb-dwc3-add-optional-PHY-interface-clocks.patch new file mode 100644 index 00000000000000..f83c417d322324 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-13-usb-dwc3-add-optional-PHY-interface-clocks.patch @@ -0,0 +1,86 @@ +From 97b72e2d95039c733573459bd15f5a0e96aa3a68 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 20 Jul 2023 18:59:37 +0200 +Subject: [PATCH 13/41] usb: dwc3: add optional PHY interface clocks + +On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and +requires two extra clocks to be enabled. Without these extra clocks +hot-plugging USB devices is broken. + +Signed-off-by: Sebastian Reichel +--- + drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ + drivers/usb/dwc3/core.h | 4 ++++ + 2 files changed, 30 insertions(+) + +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -818,8 +818,20 @@ static int dwc3_clk_enable(struct dwc3 * + if (ret) + goto disable_ref_clk; + ++ ret = clk_prepare_enable(dwc->utmi_clk); ++ if (ret) ++ goto disable_susp_clk; ++ ++ ret = clk_prepare_enable(dwc->pipe_clk); ++ if (ret) ++ goto disable_utmi_clk; ++ + return 0; + ++disable_utmi_clk: ++ clk_disable_unprepare(dwc->utmi_clk); ++disable_susp_clk: ++ clk_disable_unprepare(dwc->susp_clk); + disable_ref_clk: + clk_disable_unprepare(dwc->ref_clk); + disable_bus_clk: +@@ -829,6 +841,8 @@ disable_bus_clk: + + static void dwc3_clk_disable(struct dwc3 *dwc) + { ++ clk_disable_unprepare(dwc->pipe_clk); ++ clk_disable_unprepare(dwc->utmi_clk); + clk_disable_unprepare(dwc->susp_clk); + clk_disable_unprepare(dwc->ref_clk); + clk_disable_unprepare(dwc->bus_clk); +@@ -1842,6 +1856,18 @@ static int dwc3_get_clocks(struct dwc3 * + } + } + ++ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); ++ if (IS_ERR(dwc->utmi_clk)) { ++ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), ++ "could not get utmi clock\n"); ++ } ++ ++ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); ++ if (IS_ERR(dwc->pipe_clk)) { ++ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), ++ "could not get pipe clock\n"); ++ } ++ + return 0; + } + +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -996,6 +996,8 @@ struct dwc3_scratchpad_array { + * @bus_clk: clock for accessing the registers + * @ref_clk: reference clock + * @susp_clk: clock used when the SS phy is in low power (S3) state ++ * @utmi_clk: clock used for USB2 PHY communication ++ * @pipe_clk: clock used for USB3 PHY communication + * @reset: reset control + * @regs: base address for our registers + * @regs_size: address space size +@@ -1166,6 +1168,8 @@ struct dwc3 { + struct clk *bus_clk; + struct clk *ref_clk; + struct clk *susp_clk; ++ struct clk *utmi_clk; ++ struct clk *pipe_clk; + + struct reset_control *reset; + diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-14-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch b/target/linux/rockchip/patches-6.6/200-v6.7-14-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch new file mode 100644 index 00000000000000..582ccee881f173 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-14-arm64-dts-rockchip-rk3588s-Add-USB3-host-controller.patch @@ -0,0 +1,46 @@ +From 4c2162f99fbc0791b85a14ebb2a17c40a18efa7f Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Jul 2023 18:57:15 +0200 +Subject: [PATCH 14/41] arm64: dts: rockchip: rk3588s: Add USB3 host controller + +RK3588 has three USB3 controllers. This adds the host-only controller, +which is using the naneng-combphy shared with PCIe and SATA. + +The other two are dual-role and using a different PHY that is not yet +supported upstream. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -443,6 +443,27 @@ + status = "disabled"; + }; + ++ usb_host2_xhci: usb@fcd00000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfcd00000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, ++ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, ++ <&cru CLK_PIPEPHY2_PIPE_U3_G>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; ++ dr_mode = "host"; ++ phys = <&combphy2_psu PHY_TYPE_USB3>; ++ phy-names = "usb3-phy"; ++ phy_type = "utmi_wide"; ++ resets = <&cru SRST_A_USB3OTG2>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-15-arm64-dts-rockchip-rk3588-rock5b-add-USB3-host.patch b/target/linux/rockchip/patches-6.6/200-v6.7-15-arm64-dts-rockchip-rk3588-rock5b-add-USB3-host.patch new file mode 100644 index 00000000000000..5f36ae7db9b943 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-15-arm64-dts-rockchip-rk3588-rock5b-add-USB3-host.patch @@ -0,0 +1,38 @@ +From 1a67b0d41f4a0b867789cf2503291fc497c6ff81 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 19 Jul 2023 15:56:42 +0200 +Subject: [PATCH 15/41] arm64: dts: rockchip: rk3588-rock5b: add USB3 host + +Enable USB3 host controller for the Radxa ROCK 5 Model B. This adds +USB3 for the upper USB3 port (the one further away from the PCB). + +The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588 +USB TypeC host controller, which use a different PHY that is not yet +supported upstream. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -123,6 +123,10 @@ + status = "okay"; + }; + ++&combphy2_psu { ++ status = "okay"; ++}; ++ + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + }; +@@ -717,3 +721,7 @@ + &usb_host1_ohci { + status = "okay"; + }; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-16-arm64-dts-rockchip-rk3588s-rock5a-add-USB3-host.patch b/target/linux/rockchip/patches-6.6/200-v6.7-16-arm64-dts-rockchip-rk3588s-rock5a-add-USB3-host.patch new file mode 100644 index 00000000000000..682d6c66c8fbf6 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-16-arm64-dts-rockchip-rk3588s-rock5a-add-USB3-host.patch @@ -0,0 +1,37 @@ +From 4933b279c701287de5788581ae5a2f662b700ebb Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 21 Jul 2023 15:19:37 +0200 +Subject: [PATCH 16/41] arm64: dts: rockchip: rk3588s-rock5a: add USB3 host + +Enable USB3 host controller for the Radxa ROCK 5 Model A. This adds +USB3 for the lower USB3 port (the one closer to the PCB). + +The upper USB3 port uses the RK3588 USB TypeC host controller, which +uses a different PHY that is not yet supported upstream. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -114,6 +114,10 @@ + }; + }; + ++&combphy2_psu { ++ status = "okay"; ++}; ++ + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + }; +@@ -735,3 +739,7 @@ + &usb_host1_ohci { + status = "okay"; + }; ++ ++&usb_host2_xhci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-17-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch b/target/linux/rockchip/patches-6.6/200-v6.7-17-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch new file mode 100644 index 00000000000000..feff1d989b27f8 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-17-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch @@ -0,0 +1,185 @@ +From f03ed7758b9e7d08737a026bd9e666ac2746d1d8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Apr 2023 17:38:57 +0200 +Subject: [PATCH 17/41] dt-bindings: phy: add rockchip usbdp combo phy document + +Add device tree binding document for Rockchip USBDP Combo PHY +with Samsung IP block. + +Co-developed-by: Frank Wang +Signed-off-by: Frank Wang +Signed-off-by: Sebastian Reichel +--- + .../bindings/phy/phy-rockchip-usbdp.yaml | 166 ++++++++++++++++++ + 1 file changed, 166 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml +@@ -0,0 +1,166 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip USBDP Combo PHY with Samsung IP block ++ ++maintainers: ++ - Frank Wang ++ - Zhang Yubing ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3588-usbdp-phy ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: refclk ++ - const: immortal ++ - const: pclk ++ - const: utmi ++ ++ resets: ++ maxItems: 5 ++ ++ reset-names: ++ items: ++ - const: init ++ - const: cmn ++ - const: lane ++ - const: pcs_apb ++ - const: pma_apb ++ ++ rockchip,dp-lane-mux: ++ $ref: /schemas/types.yaml#/definitions/uint32-array ++ minItems: 2 ++ maxItems: 4 ++ description: ++ An array of physical Tyep-C lanes indexes. Position of an entry determines ++ the dp lane index, while the value of an entry indicater physical Type-C lane. ++ The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could ++ have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2, ++ dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have ++ "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0, ++ dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C ++ phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need. ++ ++ rockchip,u2phy-grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the syscon managing the 'usb2 phy general register files'. ++ ++ rockchip,usb-grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the syscon managing the 'usb general register files'. ++ ++ rockchip,usbdpphy-grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the syscon managing the 'usbdp phy general register files'. ++ ++ rockchip,vo-grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: ++ Phandle to the syscon managing the 'video output general register files'. ++ When select the dp lane mapping will request its phandle. ++ ++ sbu1-dc-gpios: ++ description: ++ GPIO connected to the SBU1 line of the USB-C connector via a big resistor ++ (~100K) to apply a DC offset for signalling the connector orientation. ++ ++ sbu2-dc-gpios: ++ description: ++ GPIO connected to the SBU2 line of the USB-C connector via a big resistor ++ (~100K) to apply a DC offset for signalling the connector orientation. ++ ++ orientation-switch: ++ description: Flag the port as possible handler of orientation switching ++ type: boolean ++ ++ mode-switch: ++ description: Flag the port as possible handle of altmode switching ++ type: boolean ++ ++ dp-port: ++ type: object ++ additionalProperties: false ++ ++ properties: ++ "#phy-cells": ++ const: 0 ++ ++ required: ++ - "#phy-cells" ++ ++ usb3-port: ++ type: object ++ additionalProperties: false ++ ++ properties: ++ "#phy-cells": ++ const: 0 ++ ++ required: ++ - "#phy-cells" ++ ++ port: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ A port node to link the PHY to a TypeC controller for the purpose of ++ handling orientation switching. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - dp-port ++ - usb3-port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ usbdp_phy0: phy@fed80000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed80000 0x0 0x10000>; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY0_IMMORTAL>, ++ <&cru PCLK_USBDPPHY0>; ++ clock-names = "refclk", "immortal", "pclk"; ++ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY0_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY0_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY0_PCS>, ++ <&cru SRST_P_USBDPPHY0>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ status = "disabled"; ++ ++ usbdp_phy0_dp: dp-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usbdp_phy0_u3: usb3-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-18-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch b/target/linux/rockchip/patches-6.6/200-v6.7-18-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch new file mode 100644 index 00000000000000..d005753c08c7fe --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-18-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch @@ -0,0 +1,57 @@ +From 86af665b81ec23dbefc97f1b481d17536fd84f26 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 30 May 2023 18:49:48 +0200 +Subject: [PATCH 18/41] dt-bindings: soc: rockchip: add rk3588 USB3 syscon + +RK3588 USB3 support requires the GRF for USB, USBDP PHY and VO. + +Signed-off-by: Sebastian Reichel +--- + .../devicetree/bindings/soc/rockchip/grf.yaml | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml ++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +@@ -28,6 +28,9 @@ properties: + - rockchip,rk3588-sys-grf + - rockchip,rk3588-pcie3-phy-grf + - rockchip,rk3588-pcie3-pipe-grf ++ - rockchip,rk3588-usb-grf ++ - rockchip,rk3588-usbdpphy-grf ++ - rockchip,rk3588-vo-grf + - rockchip,rv1108-usbgrf + - const: syscon + - items: +@@ -64,6 +67,9 @@ properties: + reg: + maxItems: 1 + ++ clocks: ++ maxItems: 1 ++ + "#address-cells": + const: 1 + +@@ -246,6 +252,22 @@ allOf: + + unevaluatedProperties: false + ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - rockchip,rk3588-vo-grf ++ ++ then: ++ required: ++ - clocks ++ ++ else: ++ properties: ++ clocks: false ++ ++ + examples: + - | + #include diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-19-phy-rockchip-add-usbdp-combo-phy-driver.patch b/target/linux/rockchip/patches-6.6/200-v6.7-19-phy-rockchip-add-usbdp-combo-phy-driver.patch new file mode 100644 index 00000000000000..6fb1e4d1775b28 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-19-phy-rockchip-add-usbdp-combo-phy-driver.patch @@ -0,0 +1,1782 @@ +From 4c85beb0e132ef647a084987d954e03e9028f661 Mon Sep 17 00:00:00 2001 +From: Frank Wang +Date: Tue, 25 Apr 2023 15:55:54 +0200 +Subject: [PATCH 19/41] phy: rockchip: add usbdp combo phy driver + +This adds a new USBDP combo PHY with Samsung IP block driver. + +The driver get lane mux and mapping info in 2 ways, supporting +DisplayPort alternate mode or parsing from DT. When parsing from DT, +the property "rockchip,dp-lane-mux" provide the DP mux and mapping info. + +When do DP link training, need to set lane number, link rate, swing, and +pre-emphasis via PHY configure interface. + +Co-developed-by: Zhang Yubing +Signed-off-by: Zhang Yubing +Co-developed-by: Frank Wang +Signed-off-by: Frank Wang +Signed-off-by: Sebastian Reichel +--- + drivers/phy/rockchip/Kconfig | 12 + + drivers/phy/rockchip/Makefile | 1 + + drivers/phy/rockchip/phy-rockchip-usbdp.c | 1728 +++++++++++++++++++++ + 3 files changed, 1741 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -107,3 +107,15 @@ config PHY_ROCKCHIP_USB + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. ++ ++config PHY_ROCKCHIP_USBDP ++ tristate "Rockchip USBDP COMBO PHY Driver" ++ depends on ARCH_ROCKCHIP && OF ++ select GENERIC_PHY ++ select TYPEC ++ help ++ Enable this to support the Rockchip USB3.0/DP combo PHY with ++ Samsung IP block. This is required for USB3 support on RK3588. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called phy-rockchip-usbdp +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy- + obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o ++obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c +@@ -0,0 +1,1728 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Rockchip USBDP Combo PHY with Samsung IP block driver ++ * ++ * Copyright (C) 2021 Rockchip Electronics Co., Ltd ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* RK3588 USBDP PHY Register Definitions */ ++ ++#define UDPHY_PCS 0x4000 ++#define UDPHY_PMA 0x8000 ++ ++/* VO0 GRF Registers */ ++#define RK3588_GRF_VO0_CON0 0x0000 ++#define RK3588_GRF_VO0_CON2 0x0008 ++#define DP_SINK_HPD_CFG BIT(11) ++#define DP_SINK_HPD_SEL BIT(10) ++#define DP_AUX_DIN_SEL BIT(9) ++#define DP_AUX_DOUT_SEL BIT(8) ++#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) ++#define DP_LANE_SEL_ALL GENMASK(7, 0) ++#define PHY_AUX_DP_DATA_POL_NORMAL 0 ++#define PHY_AUX_DP_DATA_POL_INVERT 1 ++ ++/* PMA CMN Registers */ ++#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ ++#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) ++#define CMN_DP_LANE_EN_N(n) BIT(n) ++#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) ++#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) ++#define PHY_LANE_MUX_USB 0 ++#define PHY_LANE_MUX_DP 1 ++ ++#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ ++#define CMN_DP_TX_LINK_BW GENMASK(6, 5) ++#define CMN_DP_TX_LANE_SWAP_EN BIT(2) ++ ++#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ ++#define CMN_ROPLL_SSC_EN BIT(1) ++#define CMN_LCPLL_SSC_EN BIT(0) ++ ++#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ ++#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) ++#define CMN_ANA_LCPLL_AFC_DONE BIT(6) ++ ++#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ ++#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) ++#define CMN_ANA_ROPLL_AFC_DONE BIT(0) ++ ++#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ ++#define CMN_DP_INIT_RSTN BIT(3) ++#define CMN_DP_CMN_RSTN BIT(2) ++#define CMN_CDR_WTCHDG_EN BIT(1) ++#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) ++ ++#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ ++#define LN_ANA_TX_SER_TXCLK_INV BIT(1) ++ ++#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ ++#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) ++ ++#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ ++#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) ++ ++ ++#define BIT_WRITEABLE_SHIFT 16 ++ ++enum { ++ DP_BW_RBR, ++ DP_BW_HBR, ++ DP_BW_HBR2, ++ DP_BW_HBR3, ++}; ++ ++enum { ++ UDPHY_MODE_NONE = 0, ++ UDPHY_MODE_USB = BIT(0), ++ UDPHY_MODE_DP = BIT(1), ++ UDPHY_MODE_DP_USB = BIT(1) | BIT(0), ++}; ++ ++struct udphy_grf_reg { ++ unsigned int offset; ++ unsigned int bitend; ++ unsigned int bitstart; ++ unsigned int disable; ++ unsigned int enable; ++}; ++ ++struct udphy_grf_cfg { ++ /* u2phy-grf */ ++ struct udphy_grf_reg bvalid_phy_con; ++ struct udphy_grf_reg bvalid_grf_con; ++ ++ /* usb-grf */ ++ struct udphy_grf_reg usb3otg0_cfg; ++ struct udphy_grf_reg usb3otg1_cfg; ++ ++ /* usbdpphy-grf */ ++ struct udphy_grf_reg low_pwrn; ++ struct udphy_grf_reg rx_lfps; ++}; ++ ++struct udphy_vogrf_cfg { ++ /* vo-grf */ ++ struct udphy_grf_reg hpd_trigger; ++}; ++ ++struct dp_tx_drv_ctrl { ++ u32 trsv_reg0204; ++ u32 trsv_reg0205; ++ u32 trsv_reg0206; ++ u32 trsv_reg0207; ++}; ++ ++struct rockchip_udphy; ++ ++struct rockchip_udphy_cfg { ++ /* resets to be requested */ ++ const char * const *rst_list; ++ int num_rsts; ++ ++ struct udphy_grf_cfg grfcfg; ++ struct udphy_vogrf_cfg vogrfcfg[2]; ++ const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; ++ const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; ++ int (*combophy_init)(struct rockchip_udphy *udphy); ++ int (*dp_phy_set_rate)(struct rockchip_udphy *udphy, ++ struct phy_configure_opts_dp *dp); ++ int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy, ++ struct phy_configure_opts_dp *dp); ++ int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd); ++ int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes); ++ int (*dplane_select)(struct rockchip_udphy *udphy); ++}; ++ ++struct rockchip_udphy { ++ struct device *dev; ++ struct regmap *pma_regmap; ++ struct regmap *u2phygrf; ++ struct regmap *udphygrf; ++ struct regmap *usbgrf; ++ struct regmap *vogrf; ++ struct typec_switch_dev *sw; ++ struct typec_mux_dev *mux; ++ struct mutex mutex; /* mutex to protect access to individual PHYs */ ++ ++ /* clocks and rests */ ++ int num_clks; ++ struct clk_bulk_data *clks; ++ struct clk *refclk; ++ struct reset_control **rsts; ++ ++ /* PHY status management */ ++ bool flip; ++ bool mode_change; ++ u8 mode; ++ u8 status; ++ ++ /* utilized for USB */ ++ bool hs; /* flag for high-speed */ ++ ++ /* utilized for DP */ ++ struct gpio_desc *sbu1_dc_gpio; ++ struct gpio_desc *sbu2_dc_gpio; ++ u32 lane_mux_sel[4]; ++ u32 dp_lane_sel[4]; ++ u32 dp_aux_dout_sel; ++ u32 dp_aux_din_sel; ++ bool dp_sink_hpd_sel; ++ bool dp_sink_hpd_cfg; ++ u8 bw; ++ int id; ++ ++ /* PHY const config */ ++ const struct rockchip_udphy_cfg *cfgs; ++}; ++ ++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x20, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x29, 0x18, 0x42, 0xe5 }, ++ { 0x2b, 0x1c, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x23, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x29, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x20, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x29, 0x18, 0x42, 0xe5 }, ++ { 0x2b, 0x1c, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x23, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x43, 0x67 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x29, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x21, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x26, 0x16, 0x43, 0xe5 }, ++ { 0x2a, 0x19, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x24, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x17, 0x43, 0xe7 }, ++ { 0x2b, 0x1a, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x28, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x17, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x28, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { ++ /* voltage swing 0, pre-emphasis 0->3 */ ++ { ++ { 0x21, 0x10, 0x42, 0xe5 }, ++ { 0x26, 0x14, 0x42, 0xe5 }, ++ { 0x26, 0x16, 0x43, 0xe5 }, ++ { 0x29, 0x18, 0x43, 0xe7 }, ++ }, ++ ++ /* voltage swing 1, pre-emphasis 0->2 */ ++ { ++ { 0x24, 0x10, 0x42, 0xe7 }, ++ { 0x2a, 0x18, 0x43, 0xe7 }, ++ { 0x2b, 0x1b, 0x43, 0xe7 } ++ }, ++ ++ /* voltage swing 2, pre-emphasis 0->1 */ ++ { ++ { 0x27, 0x10, 0x42, 0xe7 }, ++ { 0x2b, 0x18, 0x43, 0xe7 } ++ }, ++ ++ /* voltage swing 3, pre-emphasis 0 */ ++ { ++ { 0x28, 0x10, 0x43, 0xe7 }, ++ }, ++}; ++ ++static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { ++ {0x0090, 0x68}, {0x0094, 0x68}, ++ {0x0128, 0x24}, {0x012c, 0x44}, ++ {0x0130, 0x3f}, {0x0134, 0x44}, ++ {0x015c, 0xa9}, {0x0160, 0x71}, ++ {0x0164, 0x71}, {0x0168, 0xa9}, ++ {0x0174, 0xa9}, {0x0178, 0x71}, ++ {0x017c, 0x71}, {0x0180, 0xa9}, ++ {0x018c, 0x41}, {0x0190, 0x00}, ++ {0x0194, 0x05}, {0x01ac, 0x2a}, ++ {0x01b0, 0x17}, {0x01b4, 0x17}, ++ {0x01b8, 0x2a}, {0x01c8, 0x04}, ++ {0x01cc, 0x08}, {0x01d0, 0x08}, ++ {0x01d4, 0x04}, {0x01d8, 0x20}, ++ {0x01dc, 0x01}, {0x01e0, 0x09}, ++ {0x01e4, 0x03}, {0x01f0, 0x29}, ++ {0x01f4, 0x02}, {0x01f8, 0x02}, ++ {0x01fc, 0x29}, {0x0208, 0x2a}, ++ {0x020c, 0x17}, {0x0210, 0x17}, ++ {0x0214, 0x2a}, {0x0224, 0x20}, ++ {0x03f0, 0x0a}, {0x03f4, 0x07}, ++ {0x03f8, 0x07}, {0x03fc, 0x0c}, ++ {0x0404, 0x12}, {0x0408, 0x1a}, ++ {0x040c, 0x1a}, {0x0410, 0x3f}, ++ {0x0ce0, 0x68}, {0x0ce8, 0xd0}, ++ {0x0cf0, 0x87}, {0x0cf8, 0x70}, ++ {0x0d00, 0x70}, {0x0d08, 0xa9}, ++ {0x1ce0, 0x68}, {0x1ce8, 0xd0}, ++ {0x1cf0, 0x87}, {0x1cf8, 0x70}, ++ {0x1d00, 0x70}, {0x1d08, 0xa9}, ++ {0x0a3c, 0xd0}, {0x0a44, 0xd0}, ++ {0x0a48, 0x01}, {0x0a4c, 0x0d}, ++ {0x0a54, 0xe0}, {0x0a5c, 0xe0}, ++ {0x0a64, 0xa8}, {0x1a3c, 0xd0}, ++ {0x1a44, 0xd0}, {0x1a48, 0x01}, ++ {0x1a4c, 0x0d}, {0x1a54, 0xe0}, ++ {0x1a5c, 0xe0}, {0x1a64, 0xa8} ++}; ++ ++static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = { ++ {0x0830, 0x07}, {0x085c, 0x80}, ++ {0x1030, 0x07}, {0x105c, 0x80}, ++ {0x1830, 0x07}, {0x185c, 0x80}, ++ {0x2030, 0x07}, {0x205c, 0x80}, ++ {0x0228, 0x38}, {0x0104, 0x44}, ++ {0x0248, 0x44}, {0x038C, 0x02}, ++ {0x0878, 0x04}, {0x1878, 0x04}, ++ {0x0898, 0x77}, {0x1898, 0x77}, ++ {0x0054, 0x01}, {0x00e0, 0x38}, ++ {0x0060, 0x24}, {0x0064, 0x77}, ++ {0x0070, 0x76}, {0x0234, 0xE8}, ++ {0x0AF4, 0x15}, {0x1AF4, 0x15}, ++ {0x081C, 0xE5}, {0x181C, 0xE5}, ++ {0x099C, 0x48}, {0x199C, 0x48}, ++ {0x09A4, 0x07}, {0x09A8, 0x22}, ++ {0x19A4, 0x07}, {0x19A8, 0x22}, ++ {0x09B8, 0x3E}, {0x19B8, 0x3E}, ++ {0x09E4, 0x02}, {0x19E4, 0x02}, ++ {0x0A34, 0x1E}, {0x1A34, 0x1E}, ++ {0x0A98, 0x2F}, {0x1A98, 0x2F}, ++ {0x0c30, 0x0E}, {0x0C48, 0x06}, ++ {0x1C30, 0x0E}, {0x1C48, 0x06}, ++ {0x028C, 0x18}, {0x0AF0, 0x00}, ++ {0x1AF0, 0x00} ++}; ++ ++static const struct reg_sequence rk3588_udphy_init_sequence[] = { ++ {0x0104, 0x44}, {0x0234, 0xE8}, ++ {0x0248, 0x44}, {0x028C, 0x18}, ++ {0x081C, 0xE5}, {0x0878, 0x00}, ++ {0x0994, 0x1C}, {0x0AF0, 0x00}, ++ {0x181C, 0xE5}, {0x1878, 0x00}, ++ {0x1994, 0x1C}, {0x1AF0, 0x00}, ++ {0x0428, 0x60}, {0x0D58, 0x33}, ++ {0x1D58, 0x33}, {0x0990, 0x74}, ++ {0x0D64, 0x17}, {0x08C8, 0x13}, ++ {0x1990, 0x74}, {0x1D64, 0x17}, ++ {0x18C8, 0x13}, {0x0D90, 0x40}, ++ {0x0DA8, 0x40}, {0x0DC0, 0x40}, ++ {0x0DD8, 0x40}, {0x1D90, 0x40}, ++ {0x1DA8, 0x40}, {0x1DC0, 0x40}, ++ {0x1DD8, 0x40}, {0x03C0, 0x30}, ++ {0x03C4, 0x06}, {0x0E10, 0x00}, ++ {0x1E10, 0x00}, {0x043C, 0x0F}, ++ {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, ++ {0x0D34, 0x0F}, {0x1D34, 0x0F}, ++ {0x08FC, 0x2A}, {0x0914, 0x28}, ++ {0x0A30, 0x03}, {0x0E38, 0x05}, ++ {0x0ECC, 0x27}, {0x0ED0, 0x22}, ++ {0x0ED4, 0x26}, {0x18FC, 0x2A}, ++ {0x1914, 0x28}, {0x1A30, 0x03}, ++ {0x1E38, 0x05}, {0x1ECC, 0x27}, ++ {0x1ED0, 0x22}, {0x1ED4, 0x26}, ++ {0x0048, 0x0F}, {0x0060, 0x3C}, ++ {0x0064, 0xF7}, {0x006C, 0x20}, ++ {0x0070, 0x7D}, {0x0074, 0x68}, ++ {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, ++ {0x0440, 0x3F}, {0x10D4, 0x08}, ++ {0x20D4, 0x08}, {0x00D4, 0x30}, ++ {0x0024, 0x6e}, ++}; ++ ++static inline int grfreg_write(struct regmap *base, ++ const struct udphy_grf_reg *reg, bool en) ++{ ++ u32 val, mask, tmp; ++ ++ tmp = en ? reg->enable : reg->disable; ++ mask = GENMASK(reg->bitend, reg->bitstart); ++ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); ++ ++ return regmap_write(base, reg->offset, val); ++} ++ ++static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev) ++{ ++ int i; ++ ++ udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); ++ if (udphy->num_clks < 1) ++ return -ENODEV; ++ ++ /* used for configure phy reference clock frequency */ ++ for (i = 0; i < udphy->num_clks; i++) { ++ if (!strncmp(udphy->clks[i].id, "refclk", 6)) { ++ udphy->refclk = udphy->clks[i].clk; ++ break; ++ } ++ } ++ ++ if (!udphy->refclk) ++ dev_warn(udphy->dev, "no refclk found\n"); ++ ++ return 0; ++} ++ ++static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int idx; ++ ++ udphy->rsts = devm_kcalloc(dev, cfg->num_rsts, ++ sizeof(*udphy->rsts), GFP_KERNEL); ++ if (!udphy->rsts) ++ return -ENOMEM; ++ ++ for (idx = 0; idx < cfg->num_rsts; idx++) { ++ struct reset_control *rst; ++ const char *name = cfg->rst_list[idx]; ++ ++ rst = devm_reset_control_get(dev, name); ++ if (IS_ERR(rst)) { ++ dev_err(dev, "failed to get %s reset\n", name); ++ devm_kfree(dev, (void *)udphy->rsts); ++ return PTR_ERR(rst); ++ } ++ ++ udphy->rsts[idx] = rst; ++ } ++ ++ return 0; ++} ++ ++static int udphy_get_rst_idx(const char * const *list, int num, char *name) ++{ ++ int idx; ++ ++ for (idx = 0; idx < num; idx++) { ++ if (!strcmp(list[idx], name)) ++ return idx; ++ } ++ ++ return -EINVAL; ++} ++ ++static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int idx; ++ ++ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); ++ if (idx < 0) ++ return idx; ++ ++ return reset_control_assert(udphy->rsts[idx]); ++} ++ ++static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int idx; ++ ++ idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name); ++ if (idx < 0) ++ return idx; ++ ++ return reset_control_deassert(udphy->rsts[idx]); ++} ++ ++static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ const struct udphy_grf_reg *preg; ++ ++ preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; ++ grfreg_write(udphy->usbgrf, preg, disable); ++} ++ ++static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ ++ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); ++ grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); ++} ++ ++/* ++ * In usb/dp combo phy driver, here are 2 ways to mapping lanes. ++ * ++ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) ++ * --------------------------------------------------------------------------- ++ * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 ++ * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * C/E(Normal) dpln3 dpln2 dpln0 dpln1 ++ * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 ++ * D/F(Normal) usbrx usbtx dpln0 dpln1 ++ * D/F(Flip ) dpln0 dpln1 usbrx usbtx ++ * A(Normal ) dpln3 dpln1 dpln2 dpln0 ++ * A(Flip ) dpln2 dpln0 dpln3 dpln1 ++ * B(Normal ) usbrx usbtx dpln1 dpln0 ++ * B(Flip ) dpln1 dpln0 usbrx usbtx ++ * --------------------------------------------------------------------------- ++ * ++ * 2 Mapping the lanes in dtsi ++ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = ; ++ * sample as follow: ++ * --------------------------------------------------------------------------- ++ * B11-B10 A2-A3 A11-A10 B2-B3 ++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 ++ * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 ++ * --------------------------------------------------------------------------- ++ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = ; ++ * sample as follow: ++ * --------------------------------------------------------------------------- ++ * B11-B10 A2-A3 A11-A10 B2-B3 ++ * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) ++ * <0 1> dpln0 dpln1 usbrx usbtx ++ * <2 3> usbrx usbtx dpln0 dpln1 ++ * --------------------------------------------------------------------------- ++ */ ++ ++static int udphy_dplane_select(struct rockchip_udphy *udphy) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ ++ if (cfg->dplane_select) ++ return cfg->dplane_select(udphy); ++ ++ return 0; ++} ++ ++static int udphy_dplane_get(struct rockchip_udphy *udphy) ++{ ++ int dp_lanes; ++ ++ switch (udphy->mode) { ++ case UDPHY_MODE_DP: ++ dp_lanes = 4; ++ break; ++ case UDPHY_MODE_DP_USB: ++ dp_lanes = 2; ++ break; ++ case UDPHY_MODE_USB: ++ fallthrough; ++ default: ++ dp_lanes = 0; ++ break; ++ } ++ ++ return dp_lanes; ++} ++ ++static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int ret = 0; ++ ++ if (cfg->dplane_enable) ++ ret = cfg->dplane_enable(udphy, dp_lanes); ++ ++ return ret; ++} ++ ++static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) ++{ ++ if (udphy->flip) { ++ udphy->dp_lane_sel[0] = 0; ++ udphy->dp_lane_sel[1] = 1; ++ udphy->dp_lane_sel[2] = 3; ++ udphy->dp_lane_sel[3] = 2; ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; ++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; ++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); ++ } else { ++ udphy->dp_lane_sel[0] = 2; ++ udphy->dp_lane_sel[1] = 3; ++ udphy->dp_lane_sel[2] = 1; ++ udphy->dp_lane_sel[3] = 0; ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; ++ udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); ++ } ++ ++ udphy->mode = UDPHY_MODE_DP_USB; ++ ++ return 0; ++} ++ ++static int udphy_orien_sw_set(struct typec_switch_dev *sw, ++ enum typec_orientation orien) ++{ ++ struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw); ++ ++ mutex_lock(&udphy->mutex); ++ ++ if (orien == TYPEC_ORIENTATION_NONE) { ++ gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); ++ gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); ++ /* unattached */ ++ udphy_usb_bvalid_enable(udphy, false); ++ goto unlock_ret; ++ } ++ ++ udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false; ++ upphy_set_typec_default_mapping(udphy); ++ udphy_usb_bvalid_enable(udphy, true); ++ ++unlock_ret: ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static int udphy_setup_orien_switch(struct rockchip_udphy *udphy) ++{ ++ struct typec_switch_desc sw_desc = { }; ++ ++ sw_desc.drvdata = udphy; ++ sw_desc.fwnode = dev_fwnode(udphy->dev); ++ sw_desc.set = udphy_orien_sw_set; ++ ++ udphy->sw = typec_switch_register(udphy->dev, &sw_desc); ++ if (IS_ERR(udphy->sw)) { ++ dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", ++ PTR_ERR(udphy->sw)); ++ return PTR_ERR(udphy->sw); ++ } ++ ++ return 0; ++} ++ ++static void udphy_orien_switch_unregister(void *data) ++{ ++ struct rockchip_udphy *udphy = data; ++ ++ typec_switch_unregister(udphy->sw); ++} ++ ++static int udphy_setup(struct rockchip_udphy *udphy) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int ret = 0; ++ ++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); ++ if (ret) { ++ dev_err(udphy->dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ if (cfg->combophy_init) { ++ ret = cfg->combophy_init(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "failed to init combophy\n"); ++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int udphy_disable(struct rockchip_udphy *udphy) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int i; ++ ++ clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); ++ ++ for (i = 0; i < cfg->num_rsts; i++) ++ reset_control_assert(udphy->rsts[i]); ++ ++ return 0; ++} ++ ++static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np) ++{ ++ struct property *prop; ++ int ret, i, len, num_lanes; ++ ++ prop = of_find_property(np, "rockchip,dp-lane-mux", &len); ++ if (!prop) { ++ dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n"); ++ udphy->mode = UDPHY_MODE_USB; ++ return 0; ++ } ++ ++ num_lanes = len / sizeof(u32); ++ ++ if (num_lanes != 2 && num_lanes != 4) { ++ dev_err(udphy->dev, "invalid number of lane mux\n"); ++ return -EINVAL; ++ } ++ ++ ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes); ++ if (ret) { ++ dev_err(udphy->dev, "get dp lane mux failed\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < num_lanes; i++) { ++ int j; ++ ++ if (udphy->dp_lane_sel[i] > 3) { ++ dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n"); ++ return -EINVAL; ++ } ++ ++ udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; ++ ++ for (j = i + 1; j < num_lanes; j++) { ++ if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { ++ dev_err(udphy->dev, "set repeat lane mux value\n"); ++ return -EINVAL; ++ } ++ } ++ } ++ ++ udphy->mode = UDPHY_MODE_DP; ++ if (num_lanes == 2) ++ udphy->mode |= UDPHY_MODE_USB; ++ ++ return 0; ++} ++ ++static int udphy_get_initial_status(struct rockchip_udphy *udphy) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int ret, i; ++ u32 value; ++ ++ ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); ++ if (ret) { ++ dev_err(udphy->dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < cfg->num_rsts; i++) ++ reset_control_deassert(udphy->rsts[i]); ++ ++ regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); ++ if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) ++ udphy->status = UDPHY_MODE_DP; ++ else ++ udphy_disable(udphy); ++ ++ return 0; ++} ++ ++static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev) ++{ ++ struct device_node *np = dev->of_node; ++ enum usb_device_speed maximum_speed; ++ int ret; ++ ++ udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); ++ if (IS_ERR(udphy->u2phygrf)) { ++ if (PTR_ERR(udphy->u2phygrf) == -ENODEV) { ++ dev_warn(dev, "missing u2phy-grf dt node\n"); ++ udphy->u2phygrf = NULL; ++ } else { ++ return PTR_ERR(udphy->u2phygrf); ++ } ++ } ++ ++ udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); ++ if (IS_ERR(udphy->udphygrf)) { ++ if (PTR_ERR(udphy->udphygrf) == -ENODEV) { ++ dev_warn(dev, "missing usbdpphy-grf dt node\n"); ++ udphy->udphygrf = NULL; ++ } else { ++ return PTR_ERR(udphy->udphygrf); ++ } ++ } ++ ++ udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); ++ if (IS_ERR(udphy->usbgrf)) { ++ if (PTR_ERR(udphy->usbgrf) == -ENODEV) { ++ dev_warn(dev, "missing usb-grf dt node\n"); ++ udphy->usbgrf = NULL; ++ } else { ++ return PTR_ERR(udphy->usbgrf); ++ } ++ } ++ ++ udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); ++ if (IS_ERR(udphy->vogrf)) { ++ if (PTR_ERR(udphy->vogrf) == -ENODEV) { ++ dev_warn(dev, "missing vo-grf dt node\n"); ++ udphy->vogrf = NULL; ++ } else { ++ return PTR_ERR(udphy->vogrf); ++ } ++ } ++ ++ ret = udphy_parse_lane_mux_data(udphy, np); ++ if (ret) ++ return ret; ++ ++ udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); ++ if (IS_ERR(udphy->sbu1_dc_gpio)) ++ return PTR_ERR(udphy->sbu1_dc_gpio); ++ ++ udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); ++ if (IS_ERR(udphy->sbu2_dc_gpio)) ++ return PTR_ERR(udphy->sbu2_dc_gpio); ++ ++ if (device_property_present(dev, "maximum-speed")) { ++ maximum_speed = usb_get_maximum_speed(dev); ++ udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false; ++ } ++ ++ ret = udphy_clk_init(udphy, dev); ++ if (ret) ++ return ret; ++ ++ ret = udphy_reset_init(udphy, dev); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) ++{ ++ int ret; ++ ++ if (!(udphy->mode & mode)) { ++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); ++ return 0; ++ } ++ ++ if (udphy->status == UDPHY_MODE_NONE) { ++ udphy->mode_change = false; ++ ret = udphy_setup(udphy); ++ if (ret) ++ return ret; ++ ++ if (udphy->mode & UDPHY_MODE_USB) ++ udphy_u3_port_disable(udphy, false); ++ } else if (udphy->mode_change) { ++ udphy->mode_change = false; ++ udphy->status = UDPHY_MODE_NONE; ++ if (udphy->mode == UDPHY_MODE_DP) ++ udphy_u3_port_disable(udphy, true); ++ ++ ret = udphy_disable(udphy); ++ if (ret) ++ return ret; ++ ret = udphy_setup(udphy); ++ if (ret) ++ return ret; ++ } ++ ++ udphy->status |= mode; ++ ++ return 0; ++} ++ ++static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) ++{ ++ int ret; ++ ++ if (!(udphy->mode & mode)) { ++ dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); ++ return 0; ++ } ++ ++ if (!udphy->status) ++ return 0; ++ ++ udphy->status &= ~mode; ++ ++ if (udphy->status == UDPHY_MODE_NONE) { ++ ret = udphy_disable(udphy); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int rockchip_dp_phy_power_on(struct phy *phy) ++{ ++ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ int ret, dp_lanes; ++ ++ mutex_lock(&udphy->mutex); ++ ++ dp_lanes = udphy_dplane_get(udphy); ++ phy_set_bus_width(phy, dp_lanes); ++ ++ ret = udphy_power_on(udphy, UDPHY_MODE_DP); ++ if (ret) ++ goto unlock; ++ ++ ret = udphy_dplane_enable(udphy, dp_lanes); ++ if (ret) ++ goto unlock; ++ ++ ret = udphy_dplane_select(udphy); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ /* ++ * If data send by aux channel too fast after phy power on, ++ * the aux may be not ready which will cause aux error. Adding ++ * delay to avoid this issue. ++ */ ++ usleep_range(10000, 11000); ++ return ret; ++} ++ ++static int rockchip_dp_phy_power_off(struct phy *phy) ++{ ++ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ int ret; ++ ++ mutex_lock(&udphy->mutex); ++ ret = udphy_dplane_enable(udphy, 0); ++ if (ret) ++ goto unlock; ++ ++ ret = udphy_power_off(udphy, UDPHY_MODE_DP); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ return ret; ++} ++ ++static int rockchip_dp_phy_verify_link_rate(unsigned int link_rate) ++{ ++ switch (link_rate) { ++ case 1620: ++ case 2700: ++ case 5400: ++ case 8100: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy, ++ struct phy_configure_opts_dp *dp) ++{ ++ int i, ret; ++ ++ /* If changing link rate was required, verify it's supported. */ ++ ret = rockchip_dp_phy_verify_link_rate(dp->link_rate); ++ if (ret) ++ return ret; ++ ++ /* Verify lane count. */ ++ switch (dp->lanes) { ++ case 1: ++ case 2: ++ case 4: ++ /* valid lane count. */ ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* ++ * If changing voltages is required, check swing and pre-emphasis ++ * levels, per-lane. ++ */ ++ if (dp->set_voltages) { ++ /* Lane count verified previously. */ ++ for (i = 0; i < dp->lanes; i++) { ++ if (dp->voltage[i] > 3 || dp->pre[i] > 3) ++ return -EINVAL; ++ ++ /* ++ * Sum of voltage swing and pre-emphasis levels cannot ++ * exceed 3. ++ */ ++ if (dp->voltage[i] + dp->pre[i] > 3) ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static int rockchip_dp_phy_configure(struct phy *phy, ++ union phy_configure_opts *opts) ++{ ++ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int ret; ++ ++ ret = rockchip_dp_phy_verify_config(udphy, &opts->dp); ++ if (ret) ++ return ret; ++ ++ if (opts->dp.set_rate && cfg->dp_phy_set_rate) { ++ ret = cfg->dp_phy_set_rate(udphy, &opts->dp); ++ if (ret) { ++ dev_err(udphy->dev, ++ "rockchip_hdptx_phy_set_rate failed\n"); ++ return ret; ++ } ++ } ++ ++ if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) { ++ ret = cfg->dp_phy_set_voltages(udphy, &opts->dp); ++ if (ret) { ++ dev_err(udphy->dev, ++ "rockchip_dp_phy_set_voltages failed\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct phy_ops rockchip_dp_phy_ops = { ++ .power_on = rockchip_dp_phy_power_on, ++ .power_off = rockchip_dp_phy_power_off, ++ .configure = rockchip_dp_phy_configure, ++ .owner = THIS_MODULE, ++}; ++ ++static int rockchip_u3phy_init(struct phy *phy) ++{ ++ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ int ret = 0; ++ ++ mutex_lock(&udphy->mutex); ++ /* DP only or high-speed, disable U3 port */ ++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { ++ udphy_u3_port_disable(udphy, true); ++ goto unlock; ++ } ++ ++ ret = udphy_power_on(udphy, UDPHY_MODE_USB); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ return ret; ++} ++ ++static int rockchip_u3phy_exit(struct phy *phy) ++{ ++ struct rockchip_udphy *udphy = phy_get_drvdata(phy); ++ int ret = 0; ++ ++ mutex_lock(&udphy->mutex); ++ /* DP only or high-speed */ ++ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) ++ goto unlock; ++ ++ ret = udphy_power_off(udphy, UDPHY_MODE_USB); ++ ++unlock: ++ mutex_unlock(&udphy->mutex); ++ return ret; ++} ++ ++static const struct phy_ops rockchip_u3phy_ops = { ++ .init = rockchip_u3phy_init, ++ .exit = rockchip_u3phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int usbdp_typec_mux_set(struct typec_mux_dev *mux, ++ struct typec_mux_state *state) ++{ ++ struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux); ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ u8 mode; ++ ++ mutex_lock(&udphy->mutex); ++ ++ switch (state->mode) { ++ case TYPEC_DP_STATE_C: ++ fallthrough; ++ case TYPEC_DP_STATE_E: ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ mode = UDPHY_MODE_DP; ++ break; ++ case TYPEC_DP_STATE_D: ++ fallthrough; ++ default: ++ if (udphy->flip) { ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; ++ } else { ++ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; ++ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; ++ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; ++ } ++ mode = UDPHY_MODE_DP_USB; ++ break; ++ } ++ ++ if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { ++ struct typec_displayport_data *data = state->data; ++ ++ if (!data) { ++ if (cfg->hpd_event_trigger) ++ cfg->hpd_event_trigger(udphy, false); ++ } else if (data->status & DP_STATUS_IRQ_HPD) { ++ if (cfg->hpd_event_trigger) { ++ cfg->hpd_event_trigger(udphy, false); ++ usleep_range(750, 800); ++ cfg->hpd_event_trigger(udphy, true); ++ } ++ } else if (data->status & DP_STATUS_HPD_STATE) { ++ if (udphy->mode != mode) { ++ udphy->mode = mode; ++ udphy->mode_change = true; ++ } ++ if (cfg->hpd_event_trigger) ++ cfg->hpd_event_trigger(udphy, true); ++ } else { ++ if (cfg->hpd_event_trigger) ++ cfg->hpd_event_trigger(udphy, false); ++ } ++ } ++ ++ mutex_unlock(&udphy->mutex); ++ return 0; ++} ++ ++static int udphy_setup_typec_mux(struct rockchip_udphy *udphy) ++{ ++ struct typec_mux_desc mux_desc = {}; ++ ++ mux_desc.drvdata = udphy; ++ mux_desc.fwnode = dev_fwnode(udphy->dev); ++ mux_desc.set = usbdp_typec_mux_set; ++ ++ udphy->mux = typec_mux_register(udphy->dev, &mux_desc); ++ if (IS_ERR(udphy->mux)) { ++ dev_err(udphy->dev, "Error register typec mux: %ld\n", ++ PTR_ERR(udphy->mux)); ++ return PTR_ERR(udphy->mux); ++ } ++ ++ return 0; ++} ++ ++static void udphy_typec_mux_unregister(void *data) ++{ ++ struct rockchip_udphy *udphy = data; ++ ++ typec_mux_unregister(udphy->mux); ++} ++ ++static u32 udphy_dp_get_max_link_rate(struct rockchip_udphy *udphy, struct device_node *np) ++{ ++ u32 max_link_rate; ++ int ret; ++ ++ ret = of_property_read_u32(np, "max-link-rate", &max_link_rate); ++ if (ret) ++ return 8100; ++ ++ ret = rockchip_dp_phy_verify_link_rate(max_link_rate); ++ if (ret) { ++ dev_warn(udphy->dev, "invalid max-link-rate value:%d\n", max_link_rate); ++ max_link_rate = 8100; ++ } ++ ++ return max_link_rate; ++} ++ ++static const struct regmap_config rockchip_udphy_pma_regmap_cfg = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .fast_io = true, ++ .max_register = 0x20dc, ++}; ++ ++static int rockchip_udphy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ struct device_node *child_np; ++ struct phy_provider *phy_provider; ++ struct resource *res; ++ struct rockchip_udphy *udphy; ++ const struct rockchip_udphy_cfg *phy_cfgs; ++ void __iomem *base; ++ int id, ret; ++ ++ udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); ++ if (!udphy) ++ return -ENOMEM; ++ ++ id = of_alias_get_id(dev->of_node, "usbdp"); ++ if (id < 0) ++ id = 0; ++ udphy->id = id; ++ ++ phy_cfgs = device_get_match_data(dev); ++ if (!phy_cfgs) { ++ dev_err(dev, "no OF data can be matched with %p node\n", np); ++ return -EINVAL; ++ } ++ ++ udphy->cfgs = phy_cfgs; ++ ++ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, ++ &rockchip_udphy_pma_regmap_cfg); ++ if (IS_ERR(udphy->pma_regmap)) ++ return PTR_ERR(udphy->pma_regmap); ++ ++ ret = udphy_parse_dt(udphy, dev); ++ if (ret) ++ return ret; ++ ++ ret = udphy_get_initial_status(udphy); ++ if (ret) ++ return ret; ++ ++ mutex_init(&udphy->mutex); ++ udphy->dev = dev; ++ platform_set_drvdata(pdev, udphy); ++ ++ if (device_property_present(dev, "orientation-switch")) { ++ ret = udphy_setup_orien_switch(udphy); ++ if (ret) ++ return ret; ++ ++ ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy); ++ if (ret) ++ return ret; ++ } ++ ++ if (device_property_present(dev, "mode-switch")) { ++ ret = udphy_setup_typec_mux(udphy); ++ if (ret) ++ return ret; ++ ++ ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy); ++ if (ret) ++ return ret; ++ } ++ ++ for_each_available_child_of_node(np, child_np) { ++ struct phy *phy; ++ ++ if (of_node_name_eq(child_np, "dp-port")) { ++ phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops); ++ if (IS_ERR(phy)) { ++ dev_err(dev, "failed to create dp phy: %pOFn\n", child_np); ++ goto put_child; ++ } ++ ++ phy_set_bus_width(phy, udphy_dplane_get(udphy)); ++ phy->attrs.max_link_rate = udphy_dp_get_max_link_rate(udphy, child_np); ++ } else if (of_node_name_eq(child_np, "usb3-port")) { ++ phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops); ++ if (IS_ERR(phy)) { ++ dev_err(dev, "failed to create usb phy: %pOFn\n", child_np); ++ goto put_child; ++ } ++ } else ++ continue; ++ ++ phy_set_drvdata(phy, udphy); ++ } ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (IS_ERR(phy_provider)) { ++ dev_err(dev, "failed to register phy provider\n"); ++ goto put_child; ++ } ++ ++ return 0; ++ ++put_child: ++ of_node_put(child_np); ++ return ret; ++} ++ ++static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) ++{ ++ unsigned long rate; ++ int ret; ++ ++ /* configure phy reference clock */ ++ rate = clk_get_rate(udphy->refclk); ++ dev_dbg(udphy->dev, "refclk freq %ld\n", rate); ++ ++ switch (rate) { ++ case 24000000: ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg, ++ ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ case 26000000: ++ /* register default is 26MHz */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg, ++ ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg)); ++ if (ret) ++ return ret; ++ break; ++ default: ++ dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) ++{ ++ unsigned int val; ++ int ret; ++ ++ /* LCPLL check */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, ++ val, (val & CMN_ANA_LCPLL_AFC_DONE) && ++ (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); ++ if (ret) { ++ dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); ++ return ret; ++ } ++ } ++ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ if (!udphy->flip) { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); ++ } else { ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, ++ TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, ++ val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, ++ 200, 100000); ++ if (ret) ++ dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int rk3588_udphy_init(struct rockchip_udphy *udphy) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ int ret; ++ ++ /* enable rx lfps for usb */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); ++ ++ /* Step 1: power on pma and deassert apb rstn */ ++ grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); ++ ++ udphy_reset_deassert(udphy, "pma_apb"); ++ udphy_reset_deassert(udphy, "pcs_apb"); ++ ++ /* Step 2: set init sequence and phy refclk */ ++ ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence, ++ ARRAY_SIZE(rk3588_udphy_init_sequence)); ++ if (ret) { ++ dev_err(udphy->dev, "init sequence set error %d\n", ret); ++ goto assert_apb; ++ } ++ ++ ret = rk3588_udphy_refclk_set(udphy); ++ if (ret) { ++ dev_err(udphy->dev, "refclk set error %d\n", ret); ++ goto assert_apb; ++ } ++ ++ /* Step 3: configure lane mux */ ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, ++ CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | ++ FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); ++ ++ /* Step 4: deassert init rstn and wait for 200ns from datasheet */ ++ if (udphy->mode & UDPHY_MODE_USB) ++ udphy_reset_deassert(udphy, "init"); ++ ++ if (udphy->mode & UDPHY_MODE_DP) { ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_INIT_RSTN, ++ FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); ++ } ++ ++ udelay(1); ++ ++ /* Step 5: deassert cmn/lane rstn */ ++ if (udphy->mode & UDPHY_MODE_USB) { ++ udphy_reset_deassert(udphy, "cmn"); ++ udphy_reset_deassert(udphy, "lane"); ++ } ++ ++ /* Step 6: wait for lock done of pll */ ++ ret = rk3588_udphy_status_check(udphy); ++ if (ret) ++ goto assert_phy; ++ ++ return 0; ++ ++assert_phy: ++ udphy_reset_assert(udphy, "init"); ++ udphy_reset_assert(udphy, "cmn"); ++ udphy_reset_assert(udphy, "lane"); ++ ++assert_apb: ++ udphy_reset_assert(udphy, "pma_apb"); ++ udphy_reset_assert(udphy, "pcs_apb"); ++ return ret; ++} ++ ++static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd) ++{ ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ ++ udphy->dp_sink_hpd_sel = true; ++ udphy->dp_sink_hpd_cfg = hpd; ++ ++ grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); ++ ++ return 0; ++} ++ ++static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) ++{ ++ int i; ++ u32 val = 0; ++ ++ for (i = 0; i < dp_lanes; i++) ++ val |= BIT(udphy->dp_lane_sel[i]); ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, ++ FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); ++ ++ if (!dp_lanes) ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); ++ ++ return 0; ++} ++ ++static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy) ++{ ++ u32 value = 0; ++ ++ switch (udphy->mode) { ++ case UDPHY_MODE_DP: ++ value |= 2 << udphy->dp_lane_sel[2] * 2; ++ value |= 3 << udphy->dp_lane_sel[3] * 2; ++ fallthrough; ++ case UDPHY_MODE_DP_USB: ++ value |= 0 << udphy->dp_lane_sel[0] * 2; ++ value |= 1 << udphy->dp_lane_sel[1] * 2; ++ break; ++ case UDPHY_MODE_USB: ++ break; ++ default: ++ break; ++ } ++ ++ regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, ++ ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | ++ FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | ++ FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); ++ ++ return 0; ++} ++ ++static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy, ++ struct phy_configure_opts_dp *dp) ++{ ++ u32 val; ++ int ret; ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, ++ CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); ++ ++ switch (dp->link_rate) { ++ case 1620: ++ udphy->bw = DP_BW_RBR; ++ break; ++ case 2700: ++ udphy->bw = DP_BW_HBR; ++ break; ++ case 5400: ++ udphy->bw = DP_BW_HBR2; ++ break; ++ case 8100: ++ udphy->bw = DP_BW_HBR3; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, ++ FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); ++ regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, ++ FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); ++ regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, ++ FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); ++ ++ ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, ++ FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && ++ FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), ++ 0, 1000); ++ if (ret) { ++ dev_err(udphy->dev, "ROPLL is not lock\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, ++ u32 voltage, u32 pre, u32 lane) ++{ ++ u32 offset = 0x800 * lane; ++ u32 val; ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ const struct dp_tx_drv_ctrl (*dp_ctrl)[4]; ++ ++ dp_ctrl = udphy->mux ? cfg->dp_tx_ctrl_cfg_typec[bw] : cfg->dp_tx_ctrl_cfg[bw]; ++ val = dp_ctrl[voltage][pre].trsv_reg0204; ++ regmap_write(udphy->pma_regmap, 0x0810 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0205; ++ regmap_write(udphy->pma_regmap, 0x0814 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0206; ++ regmap_write(udphy->pma_regmap, 0x0818 + offset, val); ++ ++ val = dp_ctrl[voltage][pre].trsv_reg0207; ++ regmap_write(udphy->pma_regmap, 0x081c + offset, val); ++} ++ ++static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy, ++ struct phy_configure_opts_dp *dp) ++{ ++ u32 i, lane; ++ ++ for (i = 0; i < dp->lanes; i++) { ++ lane = udphy->dp_lane_sel[i]; ++ switch (dp->link_rate) { ++ case 1620: ++ case 2700: ++ regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, ++ udphy->lane_mux_sel[lane])); ++ break; ++ case 5400: ++ case 8100: ++ regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), ++ LN_ANA_TX_SER_TXCLK_INV, ++ FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); ++ break; ++ } ++ ++ rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane); ++ } ++ ++ return 0; ++} ++ ++static int __maybe_unused udphy_resume(struct device *dev) ++{ ++ struct rockchip_udphy *udphy = dev_get_drvdata(dev); ++ const struct rockchip_udphy_cfg *cfg = udphy->cfgs; ++ ++ if (udphy->dp_sink_hpd_sel) ++ cfg->hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops udphy_pm_ops = { ++ SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, udphy_resume) ++}; ++ ++static const char * const rk3588_udphy_rst_l[] = { ++ "init", "cmn", "lane", "pcs_apb", "pma_apb" ++}; ++ ++static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { ++ .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), ++ .rst_list = rk3588_udphy_rst_l, ++ .grfcfg = { ++ /* u2phy-grf */ ++ .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, ++ .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, ++ ++ /* usb-grf */ ++ .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, ++ .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, ++ ++ /* usbdpphy-grf */ ++ .low_pwrn = { 0x0004, 13, 13, 0, 1 }, ++ .rx_lfps = { 0x0004, 14, 14, 0, 1 }, ++ }, ++ .vogrfcfg = { ++ { ++ .hpd_trigger = { 0x0000, 11, 10, 1, 3 }, ++ }, ++ { ++ .hpd_trigger = { 0x0008, 11, 10, 1, 3 }, ++ }, ++ }, ++ .dp_tx_ctrl_cfg = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++ .dp_tx_ctrl_cfg_typec = { ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, ++ rk3588_dp_tx_drv_ctrl_hbr2, ++ rk3588_dp_tx_drv_ctrl_hbr3, ++ }, ++ .combophy_init = rk3588_udphy_init, ++ .dp_phy_set_rate = rk3588_dp_phy_set_rate, ++ .dp_phy_set_voltages = rk3588_dp_phy_set_voltages, ++ .hpd_event_trigger = rk3588_udphy_hpd_event_trigger, ++ .dplane_enable = rk3588_udphy_dplane_enable, ++ .dplane_select = rk3588_udphy_dplane_select, ++}; ++ ++static const struct of_device_id rockchip_udphy_dt_match[] = { ++ { ++ .compatible = "rockchip,rk3588-usbdp-phy", ++ .data = &rk3588_udphy_cfgs ++ }, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match); ++ ++static struct platform_driver rockchip_udphy_driver = { ++ .probe = rockchip_udphy_probe, ++ .driver = { ++ .name = "rockchip-usbdp-phy", ++ .of_match_table = rockchip_udphy_dt_match, ++ .pm = &udphy_pm_ops, ++ }, ++}; ++ ++module_platform_driver(rockchip_udphy_driver); ++ ++MODULE_AUTHOR("Frank Wang "); ++MODULE_AUTHOR("Zhang Yubing "); ++MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-20-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch b/target/linux/rockchip/patches-6.6/200-v6.7-20-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch new file mode 100644 index 00000000000000..73cbf4e7c58c02 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-20-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch @@ -0,0 +1,187 @@ +From c7fe71f2048da9ca0e51aa163c3cbce99b4304b3 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Apr 2023 17:49:04 +0200 +Subject: [PATCH 20/41] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes + +Add both USB3-Displayport PHYs from RK3588. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 62 +++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 73 +++++++++++++++++++++++ + 2 files changed, 135 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -17,6 +17,37 @@ + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + ++ usbdpphy1_grf: syscon@fd5cc000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5cc000 0x0 0x4000>; ++ }; ++ ++ usb2phy1_grf: syscon@fd5d4000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", ++ "simple-mfd"; ++ reg = <0x0 0xfd5d4000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy1: usb2-phy@4000 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x4000 0x10>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; ++ reset-names = "phy", "apb"; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy1"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ u2phy1_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -310,6 +341,37 @@ + }; + }; + ++ usbdp_phy1: phy@fed90000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed90000 0x0 0x10000>; ++ rockchip,u2phy-grf = <&usb2phy1_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy1_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY1_IMMORTAL>, ++ <&cru PCLK_USBDPPHY1>, ++ <&u2phy1>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY1_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY1_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY1_PCS>, ++ <&cru SRST_P_USBDPPHY1>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ status = "disabled"; ++ ++ usbdp_phy1_dp: dp-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usbdp_phy1_u3: usb3-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -484,6 +484,37 @@ + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + ++ usbdpphy0_grf: syscon@fd5c8000 { ++ compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; ++ reg = <0x0 0xfd5c8000 0x0 0x4000>; ++ }; ++ ++ usb2phy0_grf: syscon@fd5d0000 { ++ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", ++ "simple-mfd"; ++ reg = <0x0 0xfd5d0000 0x0 0x4000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u2phy0: usb2-phy@0 { ++ compatible = "rockchip,rk3588-usb2phy"; ++ reg = <0x0 0x10>; ++ interrupts = ; ++ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; ++ reset-names = "phy", "apb"; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "usb480m_phy0"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ u2phy0_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; +@@ -509,6 +540,17 @@ + }; + }; + ++ vo0_grf: syscon@fd5a6000 { ++ compatible = "rockchip,rk3588-vo-grf", "syscon"; ++ reg = <0x0 0xfd5a6000 0x0 0x2000>; ++ clocks = <&cru PCLK_VO0GRF>; ++ }; ++ ++ usb_grf: syscon@fd5ac000 { ++ compatible = "rockchip,rk3588-usb-grf", "syscon"; ++ reg = <0x0 0xfd5ac000 0x0 0x4000>; ++ }; ++ + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; +@@ -2217,6 +2259,37 @@ + #dma-cells = <1>; + }; + ++ usbdp_phy0: phy@fed80000 { ++ compatible = "rockchip,rk3588-usbdp-phy"; ++ reg = <0x0 0xfed80000 0x0 0x10000>; ++ rockchip,u2phy-grf = <&usb2phy0_grf>; ++ rockchip,usb-grf = <&usb_grf>; ++ rockchip,usbdpphy-grf = <&usbdpphy0_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, ++ <&cru CLK_USBDP_PHY0_IMMORTAL>, ++ <&cru PCLK_USBDPPHY0>, ++ <&u2phy0>; ++ clock-names = "refclk", "immortal", "pclk", "utmi"; ++ resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, ++ <&cru SRST_USBDP_COMBO_PHY0_CMN>, ++ <&cru SRST_USBDP_COMBO_PHY0_LANE>, ++ <&cru SRST_USBDP_COMBO_PHY0_PCS>, ++ <&cru SRST_P_USBDPPHY0>; ++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; ++ status = "disabled"; ++ ++ usbdp_phy0_dp: dp-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usbdp_phy0_u3: usb3-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-21-arm64-dts-rockchip-rk3588s-Add-USB3-DRD-controllers.patch b/target/linux/rockchip/patches-6.6/200-v6.7-21-arm64-dts-rockchip-rk3588s-Add-USB3-DRD-controllers.patch new file mode 100644 index 00000000000000..f8103709b3730e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-21-arm64-dts-rockchip-rk3588s-Add-USB3-DRD-controllers.patch @@ -0,0 +1,73 @@ +From f4240c7c1db6d246bf84aa736e3cf13ea39429e9 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 18 Jul 2023 19:05:38 +0200 +Subject: [PATCH 21/41] arm64: dts: rockchip: rk3588s: Add USB3 DRD controllers + +Add both USB3 dual-role controllers to the RK3588 devicetree. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ + 2 files changed, 42 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -7,6 +7,26 @@ + #include "rk3588-pinctrl.dtsi" + + / { ++ usb_host1_xhci: usb@fc400000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc400000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "host"; ++ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG1>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -399,6 +399,28 @@ + }; + }; + ++ usb_host0_xhci: usb@fc000000 { ++ compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfc000000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref_clk", "suspend_clk", "bus_clk"; ++ dr_mode = "otg"; ++ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG0>; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-22-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch b/target/linux/rockchip/patches-6.6/200-v6.7-22-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch new file mode 100644 index 00000000000000..96c16f6afd0bcf --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-22-arm64-dts-rockchip-rk3588-evb1-add-USB3.patch @@ -0,0 +1,198 @@ +From 8760a05d818baa73e49ef7c7c142f9d0fdb28256 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 26 Apr 2023 21:18:43 +0200 +Subject: [PATCH 22/41] arm64: dts: rockchip: rk3588-evb1: add USB3 + +Add support for the boards USB3 type A, as well as its Type-C +connector. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 144 ++++++++++++++++++ + 1 file changed, 144 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -8,6 +8,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -134,6 +135,18 @@ + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; ++ ++ vbus5v0_typec: vbus5v0-typec { ++ compatible = "regulator-fixed"; ++ regulator-name = "vbus5v0_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ enable-active-high; ++ gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; ++ vin-supply = <&vcc5v0_usb>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ }; + }; + + &combphy0_ps { +@@ -194,6 +207,56 @@ + &i2c2 { + status = "okay"; + ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vbus5v0_typec>; ++ status = "okay"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "dual"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ++ ; ++ source-pdos = ++ ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_orien_sw: endpoint { ++ remote-endpoint = <&usbdp_phy0_orientation_switch>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_role_sw: endpoint { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ dp_altmode_mux: endpoint { ++ remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; +@@ -280,6 +343,16 @@ + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ usb-typec { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &pwm2 { +@@ -906,6 +979,22 @@ + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -944,3 +1033,58 @@ + &usb_host1_ohci { + status = "okay"; + }; ++ ++&usbdp_phy0 { ++ orientation-switch; ++ mode-switch; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_orientation_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_orien_sw>; ++ }; ++ ++ usbdp_phy0_dp_altmode_mux: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&dp_altmode_mux>; ++ }; ++ }; ++}; ++ ++&usbdp_phy0_u3 { ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ rockchip,dp-lane-mux = <2 3>; ++ status = "okay"; ++}; ++ ++&usbdp_phy1_u3 { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "otg"; ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dwc3_0_role_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-23-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.6/200-v6.7-23-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch new file mode 100644 index 00000000000000..58526fd824760e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-23-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch @@ -0,0 +1,72 @@ +From f394bee6ec7436619ded028c7892016a3a05f16d Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 13 Jun 2023 16:45:05 +0200 +Subject: [PATCH 23/41] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf + +Currently pclk_vo1grf is not exposed, but it should be referenced +from the vo1_grf syscon, which needs it enabled. That syscon will +be required for HDMI-RX functionality among other things. + +Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates +and need the VO's hclk enabled in addition to their parent clock. + +No Fixes tag has been added, since the logic requiring these clocks +is not yet upstream anyways. + +Signed-off-by: Sebastian Reichel +--- + drivers/clk/rockchip/clk-rk3588.c | 11 +++++------ + include/dt-bindings/clock/rockchip,rk3588-cru.h | 3 ++- + 2 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/clk/rockchip/clk-rk3588.c ++++ b/drivers/clk/rockchip/clk-rk3588.c +@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(56), 0, GFLAGS), + GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0, + RK3588_CLKGATE_CON(56), 1, GFLAGS), +- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(55), 10, GFLAGS), + COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0, + RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3588_CLKGATE_CON(56), 11, GFLAGS), +@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588 + RK3588_CLKGATE_CON(60), 9, GFLAGS), + GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0, + RK3588_CLKGATE_CON(60), 10, GFLAGS), +- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED, +- RK3588_CLKGATE_CON(59), 12, GFLAGS), + GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0, + RK3588_CLKGATE_CON(59), 14, GFLAGS), + GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0, +@@ -2447,12 +2443,15 @@ static struct rockchip_clk_branch rk3588 + GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), + GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), + GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), +- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), ++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), + GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), +- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), ++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), + GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), + GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), + GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS), ++ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS), ++ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS), ++ + }; + + static void __init rk3588_clk_init(struct device_node *np) +--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h ++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h +@@ -733,8 +733,9 @@ + #define ACLK_AV1_PRE 718 + #define PCLK_AV1_PRE 719 + #define HCLK_SDIO_PRE 720 ++#define PCLK_VO1GRF 721 + +-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1) ++#define CLK_NR_CLKS (PCLK_VO1GRF + 1) + + /* scmi-clocks indices */ + diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-24-arm64-dts-rockchip-rk3588is-Add-AV1-decoder-node.patch b/target/linux/rockchip/patches-6.6/200-v6.7-24-arm64-dts-rockchip-rk3588is-Add-AV1-decoder-node.patch new file mode 100644 index 00000000000000..87f6863edbae49 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-24-arm64-dts-rockchip-rk3588is-Add-AV1-decoder-node.patch @@ -0,0 +1,36 @@ +From a99f60696caea55f45ba4e288d7c50a4fc95183e Mon Sep 17 00:00:00 2001 +From: Benjamin Gaignard +Date: Wed, 2 Nov 2022 14:31:56 +0100 +Subject: [PATCH 24/41] arm64: dts: rockchip: rk3588is: Add AV1 decoder node + +Add node for AV1 video decoder. + +Signed-off-by: Benjamin Gaignard +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2419,6 +2419,20 @@ + #interrupt-cells = <2>; + }; + }; ++ ++ av1d: av1d@fdc70000 { ++ compatible = "rockchip,rk3588-av1-vpu"; ++ reg = <0x0 0xfdc70000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "vdpu"; ++ clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ clock-names = "aclk", "hclk"; ++ assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; ++ assigned-clock-rates = <400000000>, <400000000>; ++ resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; ++ power-domains = <&power RK3588_PD_AV1>; ++ status = "okay"; ++ }; + }; + + #include "rk3588s-pinctrl.dtsi" diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-26-dt-bindings-media-rockchip-Add-resets-property-into-.patch b/target/linux/rockchip/patches-6.6/200-v6.7-26-dt-bindings-media-rockchip-Add-resets-property-into-.patch new file mode 100644 index 00000000000000..b2e3c9a6a7b895 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-26-dt-bindings-media-rockchip-Add-resets-property-into-.patch @@ -0,0 +1,27 @@ +From 87e0a8bd8a089128bb8097939ccb15812b308f65 Mon Sep 17 00:00:00 2001 +From: Benjamin Gaignard +Date: Mon, 12 Jun 2023 14:57:58 +0200 +Subject: [PATCH 26/41] dt-bindings: media: rockchip: Add resets property into + decoder node + +RK3588 AV1 decoder hardware block have resets lines and driver code +already suppport it. +Update yaml file to be aligned with this feature. + +Signed-off-by: Benjamin Gaignard +--- + Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml +@@ -68,6 +68,9 @@ properties: + iommus: + maxItems: 1 + ++ resets: ++ maxItems: 4 ++ + required: + - compatible + - reg diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-27-cpufreq-rockchip-Introduce-driver-for-rk3588.patch b/target/linux/rockchip/patches-6.6/200-v6.7-27-cpufreq-rockchip-Introduce-driver-for-rk3588.patch new file mode 100644 index 00000000000000..d50988fa7b4f0b --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-27-cpufreq-rockchip-Introduce-driver-for-rk3588.patch @@ -0,0 +1,712 @@ +From 060e1a8aa7a81f974058806882e1620ef5c694b8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 18 Aug 2022 14:21:30 +0200 +Subject: [PATCH 27/41] cpufreq: rockchip: Introduce driver for rk3588 + +This is a heavily modified port from the downstream driver. +Downstream used it for multiple rockchip generations, while +upstream just used the generic cpufreq-dt driver so far. For +rk3588 this is no longer good enough, since two regulators +need to be controlled. + +Also during shutdown the correct frequency needs to be configured +for the big CPU cores to avoid a system hang when firmware tries +to bring them up at reboot time. + +Signed-off-by: Sebastian Reichel +--- + drivers/cpufreq/Kconfig.arm | 10 + + drivers/cpufreq/Makefile | 1 + + drivers/cpufreq/cpufreq-dt-platdev.c | 2 + + drivers/cpufreq/rockchip-cpufreq.c | 645 +++++++++++++++++++++++++++ + 4 files changed, 658 insertions(+) + create mode 100644 drivers/cpufreq/rockchip-cpufreq.c + +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -190,6 +190,16 @@ config ARM_RASPBERRYPI_CPUFREQ + + If in doubt, say N. + ++config ARM_ROCKCHIP_CPUFREQ ++ tristate "Rockchip CPUfreq driver" ++ depends on ARCH_ROCKCHIP && CPUFREQ_DT ++ select PM_OPP ++ help ++ This adds the CPUFreq driver support for Rockchip SoCs, ++ based on cpufreq-dt. ++ ++ If in doubt, say N. ++ + config ARM_S3C64XX_CPUFREQ + bool "Samsung S3C64XX" + depends on CPU_S3C6410 +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -71,6 +71,7 @@ obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq + obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o + obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o + obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o ++obj-$(CONFIG_ARM_ROCKCHIP_CPUFREQ) += rockchip-cpufreq.o + obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o + obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o + obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -166,6 +166,8 @@ static const struct of_device_id blockli + { .compatible = "qcom,sm8450", }, + { .compatible = "qcom,sm8550", }, + ++ { .compatible = "rockchip,rk3588", }, ++ + { .compatible = "st,stih407", }, + { .compatible = "st,stih410", }, + { .compatible = "st,stih418", }, +--- /dev/null ++++ b/drivers/cpufreq/rockchip-cpufreq.c +@@ -0,0 +1,645 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip CPUFreq Driver. This is similar to the generic DT ++ * cpufreq driver, but handles the following platform specific ++ * quirks: ++ * ++ * * support for two regulators - one for the CPU core and one ++ * for the memory interface ++ * * reboot handler to setup the reboot frequency ++ * * handling of read margin registers ++ * ++ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (C) 2023 Collabora Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cpufreq-dt.h" ++ ++#define RK3588_MEMCFG_HSSPRF_LOW 0x20 ++#define RK3588_MEMCFG_HSDPRF_LOW 0x28 ++#define RK3588_MEMCFG_HSDPRF_HIGH 0x2c ++#define RK3588_CPU_CTRL 0x30 ++ ++#define VOLT_RM_TABLE_END ~1 ++ ++static struct platform_device *cpufreq_pdev; ++static LIST_HEAD(priv_list); ++ ++struct volt_rm_table { ++ uint32_t volt; ++ uint32_t rm; ++}; ++ ++struct rockchip_opp_info { ++ const struct rockchip_opp_data *data; ++ struct volt_rm_table *volt_rm_tbl; ++ struct regmap *grf; ++ u32 current_rm; ++ u32 reboot_freq; ++}; ++ ++struct private_data { ++ struct list_head node; ++ ++ cpumask_var_t cpus; ++ struct device *cpu_dev; ++ struct cpufreq_frequency_table *freq_table; ++}; ++ ++struct rockchip_opp_data { ++ int (*set_read_margin)(struct device *dev, struct rockchip_opp_info *opp_info, ++ unsigned long volt); ++}; ++ ++struct cluster_info { ++ struct list_head list_head; ++ struct rockchip_opp_info opp_info; ++ cpumask_t cpus; ++}; ++static LIST_HEAD(cluster_info_list); ++ ++static int rk3588_cpu_set_read_margin(struct device *dev, struct rockchip_opp_info *opp_info, ++ unsigned long volt) ++{ ++ bool is_found = false; ++ u32 rm; ++ int i; ++ ++ if (!opp_info->volt_rm_tbl) ++ return 0; ++ ++ for (i = 0; opp_info->volt_rm_tbl[i].rm != VOLT_RM_TABLE_END; i++) { ++ if (volt >= opp_info->volt_rm_tbl[i].volt) { ++ rm = opp_info->volt_rm_tbl[i].rm; ++ is_found = true; ++ break; ++ } ++ } ++ ++ if (!is_found) ++ return 0; ++ if (rm == opp_info->current_rm) ++ return 0; ++ if (!opp_info->grf) ++ return 0; ++ ++ dev_dbg(dev, "set rm to %d\n", rm); ++ regmap_write(opp_info->grf, RK3588_MEMCFG_HSSPRF_LOW, 0x001c0000 | (rm << 2)); ++ regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_LOW, 0x003c0000 | (rm << 2)); ++ regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_HIGH, 0x003c0000 | (rm << 2)); ++ regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200020); ++ udelay(1); ++ regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200000); ++ ++ opp_info->current_rm = rm; ++ ++ return 0; ++} ++ ++static const struct rockchip_opp_data rk3588_cpu_opp_data = { ++ .set_read_margin = rk3588_cpu_set_read_margin, ++}; ++ ++static const struct of_device_id rockchip_cpufreq_of_match[] = { ++ { ++ .compatible = "rockchip,rk3588", ++ .data = (void *)&rk3588_cpu_opp_data, ++ }, ++ {}, ++}; ++ ++static struct cluster_info *rockchip_cluster_info_lookup(int cpu) ++{ ++ struct cluster_info *cluster; ++ ++ list_for_each_entry(cluster, &cluster_info_list, list_head) { ++ if (cpumask_test_cpu(cpu, &cluster->cpus)) ++ return cluster; ++ } ++ ++ return NULL; ++} ++ ++static int rockchip_cpufreq_set_volt(struct device *dev, ++ struct regulator *reg, ++ struct dev_pm_opp_supply *supply) ++{ ++ int ret; ++ ++ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, ++ supply->u_volt, supply->u_volt_max); ++ if (ret) ++ dev_err(dev, "%s: failed to set voltage (%lu %lu %lu uV): %d\n", ++ __func__, supply->u_volt_min, supply->u_volt, ++ supply->u_volt_max, ret); ++ ++ return ret; ++} ++ ++static int rockchip_cpufreq_set_read_margin(struct device *dev, ++ struct rockchip_opp_info *opp_info, ++ unsigned long volt) ++{ ++ if (opp_info->data && opp_info->data->set_read_margin) { ++ opp_info->data->set_read_margin(dev, opp_info, volt); ++ } ++ ++ return 0; ++} ++ ++static int rk_opp_config_regulators(struct device *dev, ++ struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp, ++ struct regulator **regulators, unsigned int count) ++{ ++ struct dev_pm_opp_supply old_supplies[2]; ++ struct dev_pm_opp_supply new_supplies[2]; ++ struct regulator *vdd_reg = regulators[0]; ++ struct regulator *mem_reg = regulators[1]; ++ struct rockchip_opp_info *opp_info; ++ struct cluster_info *cluster; ++ int ret = 0; ++ unsigned long old_freq = dev_pm_opp_get_freq(old_opp); ++ unsigned long new_freq = dev_pm_opp_get_freq(new_opp); ++ ++ /* We must have two regulators here */ ++ WARN_ON(count != 2); ++ ++ ret = dev_pm_opp_get_supplies(old_opp, old_supplies); ++ if (ret) ++ return ret; ++ ++ ret = dev_pm_opp_get_supplies(new_opp, new_supplies); ++ if (ret) ++ return ret; ++ ++ cluster = rockchip_cluster_info_lookup(dev->id); ++ if (!cluster) ++ return -EINVAL; ++ opp_info = &cluster->opp_info; ++ ++ if (new_freq >= old_freq) { ++ ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]); ++ if (ret) ++ goto error; ++ ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]); ++ if (ret) ++ goto error; ++ rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt); ++ } else { ++ rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt); ++ ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]); ++ if (ret) ++ goto error; ++ ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]); ++ if (ret) ++ goto error; ++ } ++ ++ return 0; ++ ++error: ++ rockchip_cpufreq_set_read_margin(dev, opp_info, old_supplies[0].u_volt); ++ rockchip_cpufreq_set_volt(dev, mem_reg, &old_supplies[1]); ++ rockchip_cpufreq_set_volt(dev, vdd_reg, &old_supplies[0]); ++ return ret; ++} ++ ++static void rockchip_get_opp_data(const struct of_device_id *matches, ++ struct rockchip_opp_info *info) ++{ ++ const struct of_device_id *match; ++ struct device_node *node; ++ ++ node = of_find_node_by_path("/"); ++ match = of_match_node(matches, node); ++ if (match && match->data) ++ info->data = match->data; ++ of_node_put(node); ++} ++ ++static int rockchip_get_volt_rm_table(struct device *dev, struct device_node *np, ++ char *porp_name, struct volt_rm_table **table) ++{ ++ struct volt_rm_table *rm_table; ++ const struct property *prop; ++ int count, i; ++ ++ prop = of_find_property(np, porp_name, NULL); ++ if (!prop) ++ return -EINVAL; ++ ++ if (!prop->value) ++ return -ENODATA; ++ ++ count = of_property_count_u32_elems(np, porp_name); ++ if (count < 0) ++ return -EINVAL; ++ ++ if (count % 2) ++ return -EINVAL; ++ ++ rm_table = devm_kzalloc(dev, sizeof(*rm_table) * (count / 2 + 1), ++ GFP_KERNEL); ++ if (!rm_table) ++ return -ENOMEM; ++ ++ for (i = 0; i < count / 2; i++) { ++ of_property_read_u32_index(np, porp_name, 2 * i, ++ &rm_table[i].volt); ++ of_property_read_u32_index(np, porp_name, 2 * i + 1, ++ &rm_table[i].rm); ++ } ++ ++ rm_table[i].volt = 0; ++ rm_table[i].rm = VOLT_RM_TABLE_END; ++ ++ *table = rm_table; ++ ++ return 0; ++} ++ ++static int rockchip_cpufreq_reboot(struct notifier_block *notifier, unsigned long event, void *cmd) ++{ ++ struct cluster_info *cluster; ++ struct device *dev; ++ int freq, ret, cpu; ++ ++ if (event != SYS_RESTART) ++ return NOTIFY_DONE; ++ ++ for_each_possible_cpu(cpu) { ++ cluster = rockchip_cluster_info_lookup(cpu); ++ if (!cluster) ++ continue; ++ ++ dev = get_cpu_device(cpu); ++ if (!dev) ++ continue; ++ ++ freq = cluster->opp_info.reboot_freq; ++ ++ if (freq) { ++ ret = dev_pm_opp_set_rate(dev, freq); ++ if (ret) ++ dev_err(dev, "Failed setting reboot freq for cpu %d to %d: %d\n", ++ cpu, freq, ret); ++ dev_pm_opp_remove_table(dev); ++ } ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster) ++{ ++ struct rockchip_opp_info *opp_info = &cluster->opp_info; ++ int reg_table_token = -EINVAL; ++ int opp_table_token = -EINVAL; ++ struct device_node *np; ++ struct device *dev; ++ const char * const reg_names[] = { "cpu", "mem", NULL }; ++ int ret = 0; ++ ++ dev = get_cpu_device(cpu); ++ if (!dev) ++ return -ENODEV; ++ ++ if (!of_find_property(dev->of_node, "cpu-supply", NULL)) ++ return -ENOENT; ++ ++ np = of_parse_phandle(dev->of_node, "operating-points-v2", 0); ++ if (!np) { ++ dev_warn(dev, "OPP-v2 not supported\n"); ++ return -ENOENT; ++ } ++ ++ reg_table_token = dev_pm_opp_set_regulators(dev, reg_names); ++ if (reg_table_token < 0) { ++ ret = reg_table_token; ++ dev_err_probe(dev, ret, "Failed to set opp regulators\n"); ++ goto np_err; ++ } ++ ++ ret = dev_pm_opp_of_get_sharing_cpus(dev, &cluster->cpus); ++ if (ret) { ++ dev_err_probe(dev, ret, "Failed to get sharing cpus\n"); ++ goto np_err; ++ } ++ ++ rockchip_get_opp_data(rockchip_cpufreq_of_match, opp_info); ++ if (opp_info->data && opp_info->data->set_read_margin) { ++ opp_info->current_rm = UINT_MAX; ++ opp_info->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); ++ if (IS_ERR(opp_info->grf)) ++ opp_info->grf = NULL; ++ rockchip_get_volt_rm_table(dev, np, "rockchip,volt-mem-read-margin", &opp_info->volt_rm_tbl); ++ ++ of_property_read_u32(np, "rockchip,reboot-freq", &opp_info->reboot_freq); ++ } ++ ++ opp_table_token = dev_pm_opp_set_config_regulators(dev, rk_opp_config_regulators); ++ if (opp_table_token < 0) { ++ ret = opp_table_token; ++ dev_err(dev, "Failed to set opp config regulators\n"); ++ goto reg_opp_table; ++ } ++ ++ of_node_put(np); ++ ++ return 0; ++ ++reg_opp_table: ++ if (reg_table_token >= 0) ++ dev_pm_opp_put_regulators(reg_table_token); ++np_err: ++ of_node_put(np); ++ ++ return ret; ++} ++ ++static struct notifier_block rockchip_cpufreq_reboot_notifier = { ++ .notifier_call = rockchip_cpufreq_reboot, ++ .priority = 0, ++}; ++ ++static struct freq_attr *cpufreq_rockchip_attr[] = { ++ &cpufreq_freq_attr_scaling_available_freqs, ++ NULL, ++}; ++ ++static int cpufreq_online(struct cpufreq_policy *policy) ++{ ++ /* We did light-weight tear down earlier, nothing to do here */ ++ return 0; ++} ++ ++static int cpufreq_offline(struct cpufreq_policy *policy) ++{ ++ /* ++ * Preserve policy->driver_data and don't free resources on light-weight ++ * tear down. ++ */ ++ return 0; ++} ++ ++static struct private_data *rockchip_cpufreq_find_data(int cpu) ++{ ++ struct private_data *priv; ++ ++ list_for_each_entry(priv, &priv_list, node) { ++ if (cpumask_test_cpu(cpu, priv->cpus)) ++ return priv; ++ } ++ ++ return NULL; ++} ++ ++static int cpufreq_init(struct cpufreq_policy *policy) ++{ ++ struct private_data *priv; ++ struct device *cpu_dev; ++ struct clk *cpu_clk; ++ unsigned int transition_latency; ++ int ret; ++ ++ priv = rockchip_cpufreq_find_data(policy->cpu); ++ if (!priv) { ++ pr_err("failed to find data for cpu%d\n", policy->cpu); ++ return -ENODEV; ++ } ++ cpu_dev = priv->cpu_dev; ++ ++ cpu_clk = clk_get(cpu_dev, NULL); ++ if (IS_ERR(cpu_clk)) { ++ ret = PTR_ERR(cpu_clk); ++ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); ++ if (!transition_latency) ++ transition_latency = CPUFREQ_ETERNAL; ++ ++ cpumask_copy(policy->cpus, priv->cpus); ++ policy->driver_data = priv; ++ policy->clk = cpu_clk; ++ policy->freq_table = priv->freq_table; ++ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000; ++ policy->cpuinfo.transition_latency = transition_latency; ++ policy->dvfs_possible_from_any_cpu = true; ++ ++ return 0; ++} ++ ++static int cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ clk_put(policy->clk); ++ return 0; ++} ++ ++static int set_target(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct private_data *priv = policy->driver_data; ++ unsigned long freq = policy->freq_table[index].frequency; ++ ++ return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); ++} ++ ++static struct cpufreq_driver rockchip_cpufreq_driver = { ++ .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | ++ CPUFREQ_IS_COOLING_DEV | ++ CPUFREQ_HAVE_GOVERNOR_PER_POLICY, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = set_target, ++ .get = cpufreq_generic_get, ++ .init = cpufreq_init, ++ .exit = cpufreq_exit, ++ .online = cpufreq_online, ++ .offline = cpufreq_offline, ++ .register_em = cpufreq_register_em_with_opp, ++ .name = "rockchip-cpufreq", ++ .attr = cpufreq_rockchip_attr, ++ .suspend = cpufreq_generic_suspend, ++}; ++ ++static int rockchip_cpufreq_init(struct device *dev, int cpu) ++{ ++ struct private_data *priv; ++ struct device *cpu_dev; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ if (!alloc_cpumask_var(&priv->cpus, GFP_KERNEL)) ++ return -ENOMEM; ++ ++ cpumask_set_cpu(cpu, priv->cpus); ++ ++ cpu_dev = get_cpu_device(cpu); ++ if (!cpu_dev) ++ return -EPROBE_DEFER; ++ priv->cpu_dev = cpu_dev; ++ ++ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, priv->cpus); ++ if (ret) ++ return ret; ++ ++ ret = dev_pm_opp_of_cpumask_add_table(priv->cpus); ++ if (ret) ++ return ret; ++ ++ ret = dev_pm_opp_get_opp_count(cpu_dev); ++ if (ret <= 0) ++ return dev_err_probe(cpu_dev, -ENODEV, "OPP table can't be empty\n"); ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &priv->freq_table); ++ if (ret) ++ return dev_err_probe(cpu_dev, ret, "failed to init cpufreq table\n"); ++ ++ list_add(&priv->node, &priv_list); ++ ++ return 0; ++} ++ ++static void rockchip_cpufreq_free_list(void *data) ++{ ++ struct cluster_info *cluster, *pos; ++ ++ list_for_each_entry_safe(cluster, pos, &cluster_info_list, list_head) { ++ list_del(&cluster->list_head); ++ } ++} ++ ++static int rockchip_cpufreq_init_list(struct device *dev) ++{ ++ struct cluster_info *cluster; ++ int cpu, ret; ++ ++ for_each_possible_cpu(cpu) { ++ cluster = rockchip_cluster_info_lookup(cpu); ++ if (cluster) ++ continue; ++ ++ cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL); ++ if (!cluster) { ++ ret = -ENOMEM; ++ goto release_cluster_info; ++ } ++ ++ ret = rockchip_cpufreq_cluster_init(cpu, cluster); ++ if (ret) { ++ dev_err_probe(dev, ret, "Failed to initialize dvfs info cpu%d\n", cpu); ++ goto release_cluster_info; ++ } ++ list_add(&cluster->list_head, &cluster_info_list); ++ } ++ ++ return 0; ++ ++release_cluster_info: ++ rockchip_cpufreq_free_list(NULL); ++ return ret; ++} ++ ++static void rockchip_cpufreq_unregister(void *data) ++{ ++ cpufreq_unregister_driver(&rockchip_cpufreq_driver); ++} ++ ++static int rockchip_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret, cpu; ++ ++ ret = rockchip_cpufreq_init_list(&pdev->dev); ++ if (ret) ++ return ret; ++ ++ ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_free_list, NULL); ++ if (ret) ++ return ret; ++ ++ ret = devm_register_reboot_notifier(&pdev->dev, &rockchip_cpufreq_reboot_notifier); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "Failed to register reboot handler\n"); ++ ++ for_each_possible_cpu(cpu) { ++ ret = rockchip_cpufreq_init(&pdev->dev, cpu); ++ if (ret) ++ return ret; ++ } ++ ++ ret = cpufreq_register_driver(&rockchip_cpufreq_driver); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "failed register driver\n"); ++ ++ ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_unregister, NULL); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static struct platform_driver rockchip_cpufreq_platdrv = { ++ .driver = { ++ .name = "rockchip-cpufreq", ++ }, ++ .probe = rockchip_cpufreq_probe, ++}; ++ ++static int __init rockchip_cpufreq_driver_init(void) ++{ ++ int ret; ++ ++ if (!of_machine_is_compatible("rockchip,rk3588") && ++ !of_machine_is_compatible("rockchip,rk3588s")) { ++ return -ENODEV; ++ } ++ ++ ret = platform_driver_register(&rockchip_cpufreq_platdrv); ++ if (ret) ++ return ret; ++ ++ cpufreq_pdev = platform_device_register_data(NULL, "rockchip-cpufreq", -1, ++ NULL, 0); ++ if (IS_ERR(cpufreq_pdev)) { ++ pr_err("failed to register rockchip-cpufreq platform device\n"); ++ ret = PTR_ERR(cpufreq_pdev); ++ goto unregister_platform_driver; ++ } ++ ++ return 0; ++ ++unregister_platform_driver: ++ platform_driver_unregister(&rockchip_cpufreq_platdrv); ++ return ret; ++} ++module_init(rockchip_cpufreq_driver_init); ++ ++static void __exit rockchip_cpufreq_driver_exit(void) ++{ ++ platform_device_unregister(cpufreq_pdev); ++ platform_driver_unregister(&rockchip_cpufreq_platdrv); ++} ++module_exit(rockchip_cpufreq_driver_exit) ++ ++MODULE_AUTHOR("Finley Xiao "); ++MODULE_DESCRIPTION("Rockchip cpufreq driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-28-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch b/target/linux/rockchip/patches-6.6/200-v6.7-28-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch new file mode 100644 index 00000000000000..9ece098af9a0bd --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-28-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch @@ -0,0 +1,555 @@ +From cc2a0371626a00d8c2778594f8302c7836900be0 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 4 Apr 2023 17:30:46 +0200 +Subject: [PATCH 28/41] arm64: dts: rockchip: rk3588: add cpu frequency scaling + support + +Add required bits for CPU frequency scaling to the Rockchip 3588 +devicetree. This is missing the 2.4 GHz operating point for the +big cpu clusters, since that does not work well on all SoCs. +Downstream has a driver for PVTM, which reduces the requested +frequencies based on (among other things) silicon quality. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 452 ++++++++++++++++++++++ + 1 file changed, 452 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + / { + compatible = "rockchip,rk3588"; +@@ -18,6 +19,215 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ cluster0_opp_table: opp-table-cluster0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <750000 750000 950000>, ++ <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <750000 750000 950000>, ++ <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <750000 750000 950000>, ++ <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <750000 750000 950000>, ++ <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <775000 775000 950000>, ++ <775000 775000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <825000 825000 950000>, ++ <825000 825000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <875000 875000 950000>, ++ <875000 875000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <950000 950000 950000>, ++ <950000 950000 950000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp_table: opp-table-cluster1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ rockchip,grf = <&bigcore0_grf>; ++ rockchip,volt-mem-read-margin = < ++ 855000 1 ++ 765000 2 ++ 675000 3 ++ 495000 4 ++ >; ++ ++ rockchip,reboot-freq = <1800000000>; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <625000 625000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <650000 650000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <675000 675000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <700000 700000 1000000>, ++ <700000 700000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <775000 775000 1000000>, ++ <775000 775000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <850000 850000 1000000>, ++ <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <925000 925000 1000000>, ++ <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster2_opp_table: opp-table-cluster2 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ rockchip,grf = <&bigcore1_grf>; ++ rockchip,volt-mem-read-margin = < ++ 855000 1 ++ 765000 2 ++ 675000 3 ++ 495000 4 ++ >; ++ ++ rockchip,reboot-freq = <1800000000>; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <600000 600000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <625000 625000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <650000 650000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <675000 675000 1000000>, ++ <675000 675000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <700000 700000 1000000>, ++ <700000 700000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <775000 775000 1000000>, ++ <775000 775000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <850000 850000 1000000>, ++ <850000 850000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <925000 925000 1000000>, ++ <925000 925000 1000000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -64,6 +274,7 @@ + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -83,6 +294,7 @@ + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -102,6 +314,7 @@ + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -121,6 +334,7 @@ + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; ++ operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; +@@ -142,6 +356,7 @@ + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -161,6 +376,7 @@ + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; ++ operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -182,6 +398,7 @@ + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; ++ operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -201,6 +418,7 @@ + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; ++ operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; +@@ -362,6 +580,230 @@ + #clock-cells = <0>; + }; + ++ thermal_zones: thermal-zones { ++ soc_thermal: soc-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ sustainable-power = <2100>; /* milliwatts */ ++ ++ thermal-sensors = <&tsadc 0>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ soc_target: trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&soc_target>; ++ cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <1024>; ++ }; ++ }; ++ }; ++ ++ bigcore0_thermal: bigcore0-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 1>; ++ ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ b0_target: trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&b0_target>; ++ cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <1024>; ++ }; ++ }; ++ }; ++ ++ bigcore1_thermal: bigcore1-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 2>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ b1_target: trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&b1_target>; ++ cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <1024>; ++ }; ++ }; ++ }; ++ ++ little_core_thermal: littlecore-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 3>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ l0_target: trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&l0_target>; ++ cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <1024>; ++ }; ++ }; ++ }; ++ ++ center_thermal: center-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 4>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 5>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ ++ npu_thermal: npu-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ thermal-sensors = <&tsadc 6>; ++ trips { ++ trip-point-0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-1 { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ trip-point-2 { ++ /* millicelsius */ ++ temperature = <115000>; ++ /* millicelsius */ ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -491,6 +933,16 @@ + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + ++ bigcore0_grf: syscon@fd590000 { ++ compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; ++ reg = <0x0 0xfd590000 0x0 0x100>; ++ }; ++ ++ bigcore1_grf: syscon@fd592000 { ++ compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; ++ reg = <0x0 0xfd592000 0x0 0x100>; ++ }; ++ + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-29-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch b/target/linux/rockchip/patches-6.6/200-v6.7-29-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch new file mode 100644 index 00000000000000..59c388d917615a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-29-arm64-dts-rockchip-enable-RK3588-tsadc-by-default.patch @@ -0,0 +1,22 @@ +From e0afda8017b1b504c7925f45ef0200e80df8e44b Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 25 May 2023 19:45:02 +0200 +Subject: [PATCH 29/41] arm64: dts: rockchip: enable RK3588 tsadc by default + +Enable the thermal ADC for all boards. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2598,7 +2598,6 @@ + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; +- status = "disabled"; + }; + + saradc: adc@fec10000 { diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-30-arm64-dts-rockchip-rk3588-evb1-add-cpu-mem-regulator.patch b/target/linux/rockchip/patches-6.6/200-v6.7-30-arm64-dts-rockchip-rk3588-evb1-add-cpu-mem-regulator.patch new file mode 100644 index 00000000000000..26e3aceba4d325 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-30-arm64-dts-rockchip-rk3588-evb1-add-cpu-mem-regulator.patch @@ -0,0 +1,59 @@ +From 68c46abeacb0587ed74044291f0aeca2be5b0683 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Thu, 25 May 2023 19:48:49 +0200 +Subject: [PATCH 30/41] arm64: dts: rockchip: rk3588-evb1: add cpu mem + regulator info + +Add the second supply regulator for the CPU cores, which is used +for supplying the memory interface. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -159,34 +159,42 @@ + + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_mem_s0>; + }; + + &cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_mem_s0>; + }; + + &cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_mem_s0>; + }; + + &cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_mem_s0>; + }; + + &cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &gmac0 { diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-31-arm64-dts-rockchip-rock5a-add-cpu-mem-regulator-info.patch b/target/linux/rockchip/patches-6.6/200-v6.7-31-arm64-dts-rockchip-rock5a-add-cpu-mem-regulator-info.patch new file mode 100644 index 00000000000000..3d322ae5eefbea --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-31-arm64-dts-rockchip-rock5a-add-cpu-mem-regulator-info.patch @@ -0,0 +1,59 @@ +From 977ddbb94890f5afa2daa8726ab05c6afd71c472 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Mon, 24 Jul 2023 15:18:39 +0200 +Subject: [PATCH 31/41] arm64: dts: rockchip: rock5a: add cpu mem regulator + info + +Add the second supply regulator for the CPU cores, which is used +for supplying the memory interface. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -120,34 +120,42 @@ + + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_s0>; + }; + + &cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_s0>; + }; + + &cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_s0>; + }; + + &cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_s0>; + }; + + &cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &i2c0 { diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-32-arm64-dts-rockchip-rock5b-add-cpu-mem-regulator-info.patch b/target/linux/rockchip/patches-6.6/200-v6.7-32-arm64-dts-rockchip-rock5b-add-cpu-mem-regulator-info.patch new file mode 100644 index 00000000000000..bb6e78a7e5c11a --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-32-arm64-dts-rockchip-rock5b-add-cpu-mem-regulator-info.patch @@ -0,0 +1,59 @@ +From 379715d7c42f5103a6b8de741b090d2e51344826 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Mon, 24 Jul 2023 15:07:49 +0200 +Subject: [PATCH 32/41] arm64: dts: rockchip: rock5b: add cpu mem regulator + info + +Add the second supply regulator for the CPU cores, which is used +for supplying the memory interface. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -129,34 +129,42 @@ + + &cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_s0>; + }; + + &cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; ++ mem-supply = <&vdd_cpu_big0_s0>; + }; + + &cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_s0>; + }; + + &cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; ++ mem-supply = <&vdd_cpu_big1_s0>; + }; + + &cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; ++ mem-supply = <&vdd_cpu_lit_mem_s0>; + }; + + &i2c0 { diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-33-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch b/target/linux/rockchip/patches-6.6/200-v6.7-33-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch new file mode 100644 index 00000000000000..a96a8f4a484045 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-33-arm64-dts-rockchip-add-status-LED-to-rock-5b.patch @@ -0,0 +1,55 @@ +From dc551c258ec6bcb550f6d06df6a34b3455bacdc5 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 21 Jul 2023 15:34:28 +0200 +Subject: [PATCH 33/41] arm64: dts: rockchip: add status LED to rock-5b + +Describe the Rock 5B status LED in its device tree. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -3,6 +3,7 @@ + /dts-v1/; + + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -36,6 +37,19 @@ + pinctrl-0 = <&hp_detect>; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_rgb_b>; ++ ++ led_rgb_b { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; +@@ -296,6 +310,12 @@ + }; + }; + ++ leds { ++ led_rgb_b: led-rgb-b { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-34-arm64-dts-rockchip-rk3588-evb1-add-ADC-buttons.patch b/target/linux/rockchip/patches-6.6/200-v6.7-34-arm64-dts-rockchip-rk3588-evb1-add-ADC-buttons.patch new file mode 100644 index 00000000000000..fee0b16dd04c15 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-34-arm64-dts-rockchip-rk3588-evb1-add-ADC-buttons.patch @@ -0,0 +1,74 @@ +From ef797eb4e048d16933591802500295a3612b60f8 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 21 Jul 2023 15:47:00 +0200 +Subject: [PATCH 34/41] arm64: dts: rockchip: rk3588-evb1: add ADC buttons + +The Rockchip EVB1 has a couple of buttons connected via an ADC +line. Let's add them to its devicetree. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -7,6 +7,7 @@ + /dts-v1/; + + #include ++#include + #include + #include + #include "rk3588.dtsi" +@@ -24,6 +25,38 @@ + stdout-path = "serial2:1500000n8"; + }; + ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-vol-up { ++ label = "Volume Up"; ++ linux,code = ; ++ press-threshold-microvolt = <17000>; ++ }; ++ ++ button-vol-down { ++ label = "Volume Down"; ++ linux,code = ; ++ press-threshold-microvolt = <417000>; ++ }; ++ ++ button-menu { ++ label = "Menu"; ++ linux,code = ; ++ press-threshold-microvolt = <890000>; ++ }; ++ ++ button-escape { ++ label = "Escape"; ++ linux,code = ; ++ press-threshold-microvolt = <1235000>; ++ }; ++ }; ++ + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; +@@ -367,6 +400,11 @@ + status = "okay"; + }; + ++&saradc { ++ vref-supply = <&vcc_1v8_s0>; ++ status = "okay"; ++}; ++ + &sdhci { + bus-width = <8>; + no-sdio; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-35-usb-typec-tcpm-avoid-graph-warning.patch b/target/linux/rockchip/patches-6.6/200-v6.7-35-usb-typec-tcpm-avoid-graph-warning.patch new file mode 100644 index 00000000000000..693dd80514c927 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-35-usb-typec-tcpm-avoid-graph-warning.patch @@ -0,0 +1,42 @@ +From d49623b5cd3b29f946a95521fbb2a44eda0aea9c Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 28 Jul 2023 16:43:16 +0200 +Subject: [PATCH 35/41] usb: typec: tcpm: avoid graph warning + +When using a devicetree as described in commit d56de8c9a17d ("usb: +typec: tcpm: try to get role switch from tcpc fwnode"), the kernel +will print an error when probing the TCPM driver, which looks +similar to this: + +OF: graph: no port node found in /i2c@feac0000/usb-typec@22 + +This is a false positive, since the code first tries to find a ports +node for the device and only then checks the fwnode. Fix this by +swapping the order. + +Note, that this will now generate a error message for devicetrees with +a role-switch ports node directly in the TCPM node instead of in the +connectors sub-node, before falling back to the legacy behaviour. These +devicetrees generate warnings when being checked against the bindings, +and should be fixed. + +Fixes: d56de8c9a17d ("usb: typec: tcpm: try to get role switch from tcpc fwnode") +Signed-off-by: Sebastian Reichel +--- + drivers/usb/typec/tcpm/tcpm.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/usb/typec/tcpm/tcpm.c ++++ b/drivers/usb/typec/tcpm/tcpm.c +@@ -6621,9 +6621,9 @@ struct tcpm_port *tcpm_register_port(str + port->partner_desc.identity = &port->partner_ident; + port->port_type = port->typec_caps.type; + +- port->role_sw = usb_role_switch_get(port->dev); ++ port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode); + if (!port->role_sw) +- port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode); ++ port->role_sw = usb_role_switch_get(port->dev); + if (IS_ERR(port->role_sw)) { + err = PTR_ERR(port->role_sw); + goto out_destroy_wq; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-36-arm64-dts-rockchip-rk3588s-rock5a-add-upper-USB3-por.patch b/target/linux/rockchip/patches-6.6/200-v6.7-36-arm64-dts-rockchip-rk3588s-rock5a-add-upper-USB3-por.patch new file mode 100644 index 00000000000000..0aab66cb68f217 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-36-arm64-dts-rockchip-rk3588s-rock5a-add-upper-USB3-por.patch @@ -0,0 +1,59 @@ +From 8d7efd46755f22f6a2927e9815a4d5823db5f3b2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Jul 2023 16:30:46 +0200 +Subject: [PATCH 36/41] arm64: dts: rockchip: rk3588s-rock5a: add upper USB3 + port + +Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from +Radxa Rock 5 Model A. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588s-rock-5a.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +@@ -707,6 +707,14 @@ + }; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -730,6 +738,15 @@ + status = "okay"; + }; + ++&usbdp_phy0 { ++ status = "okay"; ++ rockchip,dp-lane-mux = <2 3>; ++}; ++ ++&usbdp_phy0_u3 { ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + pinctrl-names = "default"; +@@ -740,6 +757,11 @@ + status = "okay"; + }; + ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-37-arm64-dts-rockchip-rk3588-rock5b-add-lower-USB3-port.patch b/target/linux/rockchip/patches-6.6/200-v6.7-37-arm64-dts-rockchip-rk3588-rock5b-add-lower-USB3-port.patch new file mode 100644 index 00000000000000..23019abb8bd719 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-37-arm64-dts-rockchip-rk3588-rock5b-add-lower-USB3-port.patch @@ -0,0 +1,57 @@ +From e0b50dce22908bf995eedfbffde7b7b39a9190bd Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Jul 2023 17:18:17 +0200 +Subject: [PATCH 37/41] arm64: dts: rockchip: rk3588-rock5b: add lower USB3 + port + +Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from +Radxa Rock 5 Model B. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -715,6 +715,14 @@ + status = "okay"; + }; + ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -734,6 +742,14 @@ + status = "okay"; + }; + ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usbdp_phy1_u3 { ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -750,6 +766,10 @@ + status = "okay"; + }; + ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ + &usb_host2_xhci { + status = "okay"; + }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-38-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch b/target/linux/rockchip/patches-6.6/200-v6.7-38-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch new file mode 100644 index 00000000000000..bc613f9d02da0c --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-38-arm64-dts-rockchip-rk3588-rock5b-add-USB-C-support.patch @@ -0,0 +1,190 @@ +From 1583cee0fdadc3bf16bb8903761a82bf92b62320 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Jul 2023 18:35:56 +0200 +Subject: [PATCH 38/41] arm64: dts: rockchip: rk3588-rock5b: add USB-C support + +Add support for using the Radxa Rock 5 Model B USB-C port for USB in +OHCI, EHCI or XHCI mode. Displayport AltMode is not yet supported. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-rock-5b.dts | 119 ++++++++++++++++++ + 1 file changed, 119 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -58,6 +59,15 @@ + #cooling-cells = <2>; + }; + ++ vcc12v_dcin: vcc12v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; +@@ -116,6 +126,7 @@ + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { +@@ -221,6 +232,61 @@ + }; + }; + ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "okay"; ++ ++ usbc0: usb-typec@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio3>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usbc0_int>; ++ vbus-supply = <&vcc12v_dcin>; ++ status = "okay"; ++ ++ usb_con: connector { ++ compatible = "usb-c-connector"; ++ label = "USB-C"; ++ data-role = "dual"; ++ power-role = "sink"; ++ try-power-role = "sink"; ++ op-sink-microwatt = <1000000>; ++ sink-pdos = ++ , ++ ; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_hs: endpoint { ++ remote-endpoint = <&usb_host0_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ usbc0_ss: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ usbc0_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ + &i2c6 { + status = "okay"; + +@@ -350,6 +416,10 @@ + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ ++ usbc0_int: usbc0-int { ++ rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; + }; + }; + +@@ -715,6 +785,14 @@ + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ + &u2phy1 { + status = "okay"; + }; +@@ -750,6 +828,33 @@ + status = "okay"; + }; + ++&usbdp_phy0 { ++ orientation-switch; ++ mode-switch; ++ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; ++ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_ss>; ++ }; ++ ++ usbdp_phy0_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc0_sbu>; ++ }; ++ }; ++}; ++ ++&usbdp_phy0_u3 { ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -758,6 +863,20 @@ + status = "okay"; + }; + ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb_host0_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc0_hs>; ++ }; ++ }; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-39-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-WLAN-contro.patch b/target/linux/rockchip/patches-6.6/200-v6.7-39-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-WLAN-contro.patch new file mode 100644 index 00000000000000..da68d2e92f7192 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-39-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-WLAN-contro.patch @@ -0,0 +1,86 @@ +From 049b5480e1b96ecffcb2e0fac72abc658c148d0c Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 14 Jul 2023 17:38:24 +0200 +Subject: [PATCH 39/41] arm64: dts: rockchip: rk3588-evb1: add PCIe2 WLAN + controller + +Enable PCIe bus used by on-board PCIe Broadcom WLAN controller. + +TODO: The WLAN controller is not detected. + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -63,6 +63,15 @@ + pwms = <&pwm2 0 25000 0>; + }; + ++ wlan-rfkill { ++ compatible = "rfkill-gpio"; ++ label = "rfkill-pcie-wlan"; ++ radio-type = "wlan"; ++ shutdown-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_pwren>, <&wifi_host_wake_irq>; ++ }; ++ + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; +@@ -186,6 +195,10 @@ + status = "okay"; + }; + ++&combphy1_ps { ++ status = "okay"; ++}; ++ + &combphy2_psu { + status = "okay"; + }; +@@ -324,6 +337,13 @@ + }; + }; + ++&pcie2x1l0 { ++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ pinctrl-0 = <&pcie2_0_rst>; ++ status = "okay"; ++}; ++ + &pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; +@@ -364,6 +384,10 @@ + }; + + pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; +@@ -394,6 +418,16 @@ + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ wlan { ++ wifi_host_wake_irq: wifi-host-wake-irq { ++ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ wifi_pwren: wifi-pwren { ++ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; + }; + + &pwm2 { diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-40-dt-bindings-es8328-convert-to-DT-schema-format.patch b/target/linux/rockchip/patches-6.6/200-v6.7-40-dt-bindings-es8328-convert-to-DT-schema-format.patch new file mode 100644 index 00000000000000..aab7e2b77a2e5e --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-40-dt-bindings-es8328-convert-to-DT-schema-format.patch @@ -0,0 +1,136 @@ +From dbfa3907a8cebfb47e5d11e64702e961508f16b7 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Jul 2023 18:49:43 +0200 +Subject: [PATCH 40/41] dt-bindings: es8328: convert to DT schema format + +Convert the binding to DT schema format. + +Signed-off-by: Sebastian Reichel +--- + .../devicetree/bindings/sound/es8328.txt | 38 --------- + .../bindings/sound/everest,es8328.yaml | 77 +++++++++++++++++++ + 2 files changed, 77 insertions(+), 38 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/sound/es8328.txt + create mode 100644 Documentation/devicetree/bindings/sound/everest,es8328.yaml + +--- a/Documentation/devicetree/bindings/sound/es8328.txt ++++ /dev/null +@@ -1,38 +0,0 @@ +-Everest ES8328 audio CODEC +- +-This device supports both I2C and SPI. +- +-Required properties: +- +- - compatible : Should be "everest,es8328" or "everest,es8388" +- - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V +- - AVDD-supply : Regulator providing analog supply voltage 3.3V +- - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V +- - IPVDD-supply : Regulator providing analog output voltage 3.3V +- - clocks : A 22.5792 or 11.2896 MHz clock +- - reg : the I2C address of the device for I2C, the chip select number for SPI +- +-Pins on the device (for linking into audio routes): +- +- * LOUT1 +- * LOUT2 +- * ROUT1 +- * ROUT2 +- * LINPUT1 +- * RINPUT1 +- * LINPUT2 +- * RINPUT2 +- * Mic Bias +- +- +-Example: +- +-codec: es8328@11 { +- compatible = "everest,es8328"; +- DVDD-supply = <®_3p3v>; +- AVDD-supply = <®_3p3v>; +- PVDD-supply = <®_3p3v>; +- HPVDD-supply = <®_3p3v>; +- clocks = <&clks 169>; +- reg = <0x11>; +-}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/everest,es8328.yaml +@@ -0,0 +1,77 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/everest,es8328.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Everest ES8328 audio CODEC ++ ++description: ++ Everest Audio Codec, which can be connected via I2C or SPI. ++ Pins on the device (for linking into audio routes) are ++ * LOUT1 ++ * LOUT2 ++ * ROUT1 ++ * ROUT2 ++ * LINPUT1 ++ * RINPUT1 ++ * LINPUT2 ++ * RINPUT2 ++ * Mic Bias ++ ++maintainers: ++ - David Yang ++ ++properties: ++ compatible: ++ enum: ++ - everest,es8328 ++ - everest,es8388 ++ ++ reg: ++ maxItems: 1 ++ ++ "#sound-dai-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: A 22.5792 or 11.2896 MHz clock ++ ++ DVDD-supply: ++ description: Regulator providing digital core supply voltage 1.8 - 3.6V ++ ++ AVDD-supply: ++ description: Regulator providing analog supply voltage 3.3V ++ ++ PVDD-supply: ++ description: Regulator providing digital IO supply voltage 1.8 - 3.6V ++ ++ IPVDD-supply: ++ description: Regulator providing analog output voltage 3.3V ++ ++required: ++ - compatible ++ - clocks ++ - DVDD-supply ++ - AVDD-supply ++ - PVDD-supply ++ - IPVDD-supply ++ ++additionalProperties: false ++ ++examples: ++ - | ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ es8328: codec@11 { ++ compatible = "everest,es8328"; ++ reg = <0x11>; ++ AVDD-supply = <®_3p3v>; ++ DVDD-supply = <®_3p3v>; ++ HPVDD-supply = <®_3p3v>; ++ PVDD-supply = <®_3p3v>; ++ clocks = <&clks 169>; ++ }; ++ }; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-41-arm64-dts-rockchip-rk3588-evb1-add-analog-audio.patch b/target/linux/rockchip/patches-6.6/200-v6.7-41-arm64-dts-rockchip-rk3588-evb1-add-analog-audio.patch new file mode 100644 index 00000000000000..8acfafa879328b --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-41-arm64-dts-rockchip-rk3588-evb1-add-analog-audio.patch @@ -0,0 +1,136 @@ +From fe23f2bcf3dc650be3a0f25afa4a645200ff3878 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Fri, 21 Jul 2023 16:59:40 +0200 +Subject: [PATCH 41/41] arm64: dts: rockchip: rk3588-evb1: add analog audio + +Add support for the EVB1 analog audio to its devicetree. + +TODO: fails like this: + +es8328 1-0011: ASoC: error at snd_soc_dai_set_sysclk on es8328-hifi-analog: -22 +es8328 1-0011: simple-card: set_sysclk error + fe470000.i2s-es8328-hifi-analog: ASoC: error at snd_soc_link_init on fe470000.i2s-es8328-hifi-analog: -22 + +Signed-off-by: Sebastian Reichel +--- + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 95 +++++++++++++++++++ + 1 file changed, 95 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +@@ -57,6 +57,65 @@ + }; + }; + ++ analog-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_detect>; ++ simple-audio-card,name = "RK3588 EVB1 Audio"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,bitclock-master = <&masterdai>; ++ simple-audio-card,frame-master = <&masterdai>; ++ ++ ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Microphone", "Onboard Mic", ++ "Headphone", "Headphones", ++ "Speaker", "Speaker"; ++ simple-audio-card,routing = ++ "Speaker Amplifier INL", "LOUT2", ++ "Speaker Amplifier INR", "ROUT2", ++ "Speaker", "Speaker Amplifier OUTL", ++ "Speaker", "Speaker Amplifier OUTR", ++ "Headphone Amplifier INL", "LOUT1", ++ "Headphone Amplifier INR", "ROUT1", ++ "Headphones", "Headphone Amplifier OUTL", ++ "Headphones", "Headphone Amplifier OUTR", ++ "LINPUT1", "Onboard Mic", ++ "LINPUT2", "Onboard Mic", ++ "RINPUT1", "Mic Jack", ++ "RINPUT2", "Mic Jack"; ++ ++ simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; ++ simple-audio-card,aux-devs = <&_headphone>, <&_speaker>; ++ simple-audio-card,pin-switches = "Headphone", "Speaker"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s0_8ch>; ++ }; ++ ++ masterdai: simple-audio-card,codec { ++ sound-dai = <&es8388>; ++ }; ++ }; ++ ++ amp_headphone: headphone-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&headphone_amplifier_en>; ++ sound-name-prefix = "Headphone Amplifier"; ++ }; ++ ++ amp_speaker: speaker-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&speaker_amplifier_en>; ++ sound-name-prefix = "Speaker Amplifier"; ++ }; ++ + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; +@@ -324,6 +383,28 @@ + }; + }; + ++&i2c7 { ++ status = "okay"; ++ ++ es8388: audio-codec@11 { ++ compatible = "everest,es8388"; ++ reg = <0x11>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++&i2s0_8ch { ++ pinctrl-0 = <&i2s0_lrck ++ &i2s0_mclk ++ &i2s0_sclk ++ &i2s0_sdi0 ++ &i2s0_sdo0>; ++ status = "okay"; ++}; ++ + &mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ +@@ -364,6 +445,20 @@ + }; + + &pinctrl { ++ audio { ++ hp_detect: headphone-detect { ++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ headphone_amplifier_en: headphone-amplifier-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ speaker_amplifier_en: speaker-amplifier-en { ++ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/target/linux/rockchip/patches-6.6/200-v6.7-42-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch b/target/linux/rockchip/patches-6.6/200-v6.7-42-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch new file mode 100644 index 00000000000000..088395769ace28 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/200-v6.7-42-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch @@ -0,0 +1,129 @@ +From 10ec0a7f1a6950be2af070d71ffbc713426e6dd2 Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Tue, 25 Apr 2023 18:17:19 +0200 +Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add USB3 controllers + +Add all USB3 controllers. + +Signed-off-by: Sebastian Reichel +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 29 +++++++++++ + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 62 +++++++++++++++++++++++ + 2 files changed, 91 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -7,6 +7,35 @@ + #include "rk3588-pinctrl.dtsi" + + / { ++ usbdrd3_1: usbdrd3_1 { ++ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; ++ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref", "suspend", "bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ usbdrd_dwc3_1: usb@fc400000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0xfc400000 0x0 0x400000>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG1>; ++ reset-names = "usb3-otg"; ++ dr_mode = "host"; ++ phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -841,6 +841,38 @@ + }; + }; + ++ usbdrd3_0: usbdrd3_0 { ++ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; ++ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref", "suspend", "bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ usbdrd_dwc3_0: usb@fc000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0xfc000000 0x0 0x400000>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_USB>; ++ resets = <&cru SRST_A_USB3OTG0>; ++ reset-names = "usb3-otg"; ++ dr_mode = "otg"; ++ phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ quirk-skip-phy-init; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; +@@ -928,6 +960,36 @@ + status = "disabled"; + }; + ++ usbhost3_0: usbhost3_0 { ++ compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; ++ clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, ++ <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, ++ <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>; ++ clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ usbhost_dwc3_0: usb@fcd00000 { ++ compatible = "snps,dwc3"; ++ reg = <0x0 0xfcd00000 0x0 0x400000>; ++ interrupts = ; ++ resets = <&cru SRST_A_USB3OTG2>; ++ reset-names = "usb3-host"; ++ dr_mode = "host"; ++ phys = <&combphy2_psu PHY_TYPE_USB3>; ++ phy-names = "usb3-phy"; ++ phy_type = "utmi_wide"; ++ snps,dis_enblslpm_quirk; ++ snps,dis-u2-freeclk-exists-quirk; ++ snps,dis-del-phy-power-chg-quirk; ++ snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ status = "disabled"; ++ }; ++ }; ++ + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; diff --git a/target/linux/rockchip/patches-6.6/201-fix-USB3-do-not-disable-sub-nodes.patch b/target/linux/rockchip/patches-6.6/201-fix-USB3-do-not-disable-sub-nodes.patch new file mode 100644 index 00000000000000..b1c4a8f9d0ac86 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/201-fix-USB3-do-not-disable-sub-nodes.patch @@ -0,0 +1,38 @@ +From bd03124217afbe108ebf0a5bd23ab8db1f2ae2bf Mon Sep 17 00:00:00 2001 +From: Sebastian Reichel +Date: Wed, 26 Apr 2023 15:01:10 +0200 +Subject: [PATCH 84/95] fix USB3: do not disable sub-nodes + +--- + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 - + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 -- + 2 files changed, 3 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi +@@ -32,7 +32,6 @@ + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; +- status = "disabled"; + }; + }; + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -869,7 +869,6 @@ + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + quirk-skip-phy-init; +- status = "disabled"; + }; + }; + +@@ -986,7 +985,6 @@ + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; +- status = "disabled"; + }; + }; + diff --git a/target/linux/rockchip/patches-6.6/202-orangepi-5-plus.patch b/target/linux/rockchip/patches-6.6/202-orangepi-5-plus.patch new file mode 100644 index 00000000000000..1f6ac683967dee --- /dev/null +++ b/target/linux/rockchip/patches-6.6/202-orangepi-5-plus.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb diff --git a/target/linux/rockchip/patches-6.6/203-cpu-rk3588-add-more-operating-points.patch b/target/linux/rockchip/patches-6.6/203-cpu-rk3588-add-more-operating-points.patch new file mode 100644 index 00000000000000..d8df45a70fee84 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/203-cpu-rk3588-add-more-operating-points.patch @@ -0,0 +1,28 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -149,6 +149,12 @@ + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>, ++ <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; + }; + + cluster2_opp_table: opp-table-cluster2 { +@@ -226,6 +232,12 @@ + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; ++ opp-2400000000 { ++ opp-hz = /bits/ 64 <2400000000>; ++ opp-microvolt = <1000000 1000000 1000000>, ++ <1000000 1000000 1000000>; ++ clock-latency-ns = <40000>; ++ }; + }; + + cpus { diff --git a/target/linux/rockchip/patches-6.6/204-irqchip-fix-its-timeout-issue.patch b/target/linux/rockchip/patches-6.6/204-irqchip-fix-its-timeout-issue.patch new file mode 100644 index 00000000000000..c1983c19bbff57 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/204-irqchip-fix-its-timeout-issue.patch @@ -0,0 +1,208 @@ +From d441305416aa91190df5865bbc0e3c684ec183b0 Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Fri, 11 Aug 2023 17:56:00 +0300 +Subject: [PATCH 1/1] irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx + boards + +--- + drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++++++++++++++++++++++--- + 1 file changed, 72 insertions(+), 7 deletions(-) + +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -163,6 +163,7 @@ struct its_device { + struct its_node *its; + struct event_lpi_map event_map; + void *itt; ++ u32 itt_sz; + u32 nr_ites; + u32 device_id; + bool shared; +@@ -2186,6 +2187,9 @@ static struct page *its_allocate_prop_ta + { + struct page *prop_page; + ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ + prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); + if (!prop_page) + return NULL; +@@ -2309,6 +2313,7 @@ static int its_setup_baser(struct its_no + u32 alloc_pages, psz; + struct page *page; + void *base; ++ gfp_t gfp_flags; + + psz = baser->psz; + alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz); +@@ -2320,7 +2325,11 @@ static int its_setup_baser(struct its_no + order = get_order(GITS_BASER_PAGES_MAX * psz); + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ ++ page = alloc_pages_node(its->numa_node, gfp_flags, order); + if (!page) + return -ENOMEM; + +@@ -2370,6 +2379,15 @@ retry_baser: + its_write_baser(its, baser, val); + tmp = baser->val; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) { ++ if (tmp & GITS_BASER_SHAREABILITY_MASK) ++ tmp &= ~GITS_BASER_SHAREABILITY_MASK; ++ else ++ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order)); ++ } ++ + if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { + /* + * Shareability didn't stick. Just use +@@ -2960,6 +2978,8 @@ static struct page *its_allocate_pending + { + struct page *pend_page; + ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; + pend_page = alloc_pages(gfp_flags | __GFP_ZERO, + get_order(LPI_PENDBASE_SZ)); + if (!pend_page) +@@ -3118,6 +3138,11 @@ static void its_cpu_init_lpis(void) + if (!rdists_support_shareable()) + tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; ++ + if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { + if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) { + /* +@@ -3145,6 +3170,11 @@ static void its_cpu_init_lpis(void) + if (!rdists_support_shareable()) + tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; ++ + if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { + /* + * The HW reports non-shareable, we must remove the +@@ -3308,7 +3338,11 @@ static bool its_alloc_table_entry(struct + + /* Allocate memory for 2nd level table */ + if (!table[idx]) { +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(baser->psz)); + if (!page) + return false; +@@ -3397,6 +3431,7 @@ static struct its_device *its_create_dev + int nr_lpis; + int nr_ites; + int sz; ++ gfp_t gfp_flags; + + if (!its_alloc_device_table(its, dev_id)) + return NULL; +@@ -3412,7 +3447,15 @@ static struct its_device *its_create_dev + nr_ites = max(2, nvecs); + sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); + sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; +- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); ++ gfp_flags = GFP_KERNEL; ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) { ++ gfp_flags |= GFP_DMA32; ++ itt = (void *)__get_free_pages(gfp_flags, get_order(sz)); ++ } else { ++ itt = kzalloc_node(sz, gfp_flags, its->numa_node); ++ } ++ + if (alloc_lpis) { + lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); + if (lpi_map) +@@ -3426,7 +3469,13 @@ static struct its_device *its_create_dev + + if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) { + kfree(dev); +- kfree(itt); ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ free_pages((unsigned long)itt, get_order(sz)); ++ else ++ kfree(itt); ++ + bitmap_free(lpi_map); + kfree(col_map); + return NULL; +@@ -3436,6 +3485,7 @@ static struct its_device *its_create_dev + + dev->its = its; + dev->itt = itt; ++ dev->itt_sz = sz; + dev->nr_ites = nr_ites; + dev->event_map.lpi_map = lpi_map; + dev->event_map.col_map = col_map; +@@ -3463,7 +3513,13 @@ static void its_free_device(struct its_d + list_del(&its_dev->entry); + raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); + kfree(its_dev->event_map.col_map); +- kfree(its_dev->itt); ++ ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); ++ else ++ kfree(its_dev->itt); ++ + kfree(its_dev); + } + +@@ -5069,6 +5125,7 @@ static int __init its_probe_one(struct i + struct page *page; + u32 ctlr; + int err; ++ gfp_t gfp_flags; + + its_enable_quirks(its); + +@@ -5102,7 +5159,10 @@ static int __init its_probe_one(struct i + } + } + +- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, ++ gfp_flags = GFP_KERNEL | __GFP_ZERO; ++ if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) ++ gfp_flags |= GFP_DMA32; ++ page = alloc_pages_node(its->numa_node, gfp_flags, + get_order(ITS_CMD_QUEUE_SZ)); + if (!page) { + err = -ENOMEM; +@@ -5131,6 +5191,11 @@ static int __init its_probe_one(struct i + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + tmp &= ~GITS_CBASER_SHAREABILITY_MASK; + ++ if (of_machine_is_compatible("rockchip,rk3568") || ++ of_machine_is_compatible("rockchip,rk3566") || ++ of_machine_is_compatible("rockchip,rk3588")) ++ tmp &= ~GITS_CBASER_SHAREABILITY_MASK; ++ + if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { + if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) { + /* diff --git a/target/linux/rockchip/patches-6.6/205-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.6/205-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch new file mode 100644 index 00000000000000..23357dfae75f99 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/205-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch @@ -0,0 +1,35 @@ +From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 9 Oct 2023 22:27:26 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s + +Add SFC (SPI Flash) to RK3588S SOC. + +Reviewed-by: Dhruva Gole +Signed-off-by: Muhammed Efe Cetin +Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +@@ -2034,6 +2034,17 @@ + }; + }; + ++ sfc: spi@fe2b0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xfe2b0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-6.6/206-arm64-dts-rockchip-Add-Orange-Pi-5.patch b/target/linux/rockchip/patches-6.6/206-arm64-dts-rockchip-Add-Orange-Pi-5.patch new file mode 100644 index 00000000000000..63edf0bb673138 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/206-arm64-dts-rockchip-Add-Orange-Pi-5.patch @@ -0,0 +1,693 @@ +From b6bc755d806eac3fbddb7ea278fc7d2eb57dba4a Mon Sep 17 00:00:00 2001 +From: Muhammed Efe Cetin +Date: Mon, 9 Oct 2023 22:27:27 +0300 +Subject: [PATCH] arm64: dts: rockchip: Add Orange Pi 5 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add initial support for OPi5 that includes support for USB2, PCIe2, Sata, +Sdmmc, SPI Flash, PMIC. + +Signed-off-by: Muhammed Efe Cetin +Reviewed-by: Ondřej Jirman +Link: https://lore.kernel.org/r/4212da199c9c532b60d380bf1dfa83490e16bc13.1696878787.git.efectn@6tel.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 662 ++++++++++++++++++ + 2 files changed, 663 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts + +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -110,3 +110,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-r + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +@@ -0,0 +1,662 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include "rk3588s.dtsi" ++ ++/ { ++ model = "Xunlong Orange Pi 5"; ++ compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; ++ ++ aliases { ++ mmc0 = &sdmmc; ++ serial2 = &uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 1>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <100>; ++ ++ button-recovery { ++ label = "Recovery"; ++ linux,code = ; ++ press-threshold-microvolt = <1800>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 =<&leds_gpio>; ++ ++ led-1 { ++ gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; ++ label = "status_led"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ vbus_typec: vbus-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec5v_pwren>; ++ regulator-name = "vbus_typec"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-low; ++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; ++ regulator-name = "vcc_3v3_sd_s0"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3_s3>; ++ }; ++ ++ vcc3v3_pcie20: vcc3v3-pcie20-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vcc3v3_pcie20"; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&combphy2_psu { ++ status = "okay"; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&gmac1 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii-rxid"; ++ pinctrl-0 = <&gmac1_miim ++ &gmac1_tx_bus2 ++ &gmac1_rx_bus2 ++ &gmac1_rgmii_clk ++ &gmac1_rgmii_bus>; ++ pinctrl-names = "default"; ++ tx_delay = <0x42>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c2 { ++ status = "okay"; ++ ++ vdd_npu_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c6 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m3_xfer>; ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ #clock-cells = <0>; ++ clock-output-names = "hym8563"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ wakeup-source; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x1>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pcie2x1l2 { ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie20>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ gpio-func { ++ leds_gpio: leds-gpio { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb-typec { ++ usbc0_int: usbc0-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ typec5v_pwren: typec5v-pwren { ++ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ max-frequency = <150000000>; ++ no-mmc; ++ no-sdio; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3_sd_s0>; ++ vqmmc-supply = <&vccio_sd_s0>; ++ status = "okay"; ++}; ++ ++&sfc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fspim0_pins>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <100000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ ++&spi2 { ++ status = "okay"; ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ reg = <0x0>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ spi-max-frequency = <1000000>; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: dcdc-reg1 { ++ regulator-name = "vdd_gpu_s0"; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: dcdc-reg2 { ++ regulator-name = "vdd_cpu_lit_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-name = "vdd_log_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: dcdc-reg4 { ++ regulator-name = "vdd_vdenc_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-name = "vdd_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <900000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 { ++ regulator-name = "vdd2_ddr_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-max-microvolt = <1100000>; ++ regulator-min-microvolt = <1100000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-name = "vdd_2v0_pldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-name = "vcc_3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-name = "vddq_ddr_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-name = "vcc_1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-name = "avcc_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-name = "vcc_1v8_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-name = "avdd_1v2_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-name = "vcc_3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-name = "vccio_sd_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <12500>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-name = "pldo6_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-name = "vdd_0v75_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-name = "vdd_ddr_pll_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-name = "avdd_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-name = "vdd_0v85_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-name = "vdd_0v75_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; diff --git a/target/linux/rockchip/patches-6.6/207-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch b/target/linux/rockchip/patches-6.6/207-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch new file mode 100644 index 00000000000000..25526ba23ccce9 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/207-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch @@ -0,0 +1,58 @@ +From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 8 Oct 2023 15:04:59 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s + +This is used on Orange Pi 5 Plus. + +Signed-off-by: Ondrej Jirman +Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 35 +++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -1350,6 +1350,41 @@ + + i2s2 { + /omit-if-no-ref/ ++ i2s2m0_lrck: i2s2m0-lrck { ++ rockchip,pins = ++ /* i2s2m0_lrck */ ++ <2 RK_PC0 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_mclk: i2s2m0-mclk { ++ rockchip,pins = ++ /* i2s2m0_mclk */ ++ <2 RK_PB6 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sclk: i2s2m0-sclk { ++ rockchip,pins = ++ /* i2s2m0_sclk */ ++ <2 RK_PB7 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdi: i2s2m0-sdi { ++ rockchip,pins = ++ /* i2s2m0_sdi */ ++ <2 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ i2s2m0_sdo: i2s2m0-sdo { ++ rockchip,pins = ++ /* i2s2m0_sdo */ ++ <4 RK_PC3 2 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ diff --git a/target/linux/rockchip/patches-6.6/208-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch b/target/linux/rockchip/patches-6.6/208-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch new file mode 100644 index 00000000000000..4a9cb6ea395228 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/208-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch @@ -0,0 +1,32 @@ +From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 8 Oct 2023 15:05:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s + +This is used on Orange Pi 5 Plus. + +Signed-off-by: Ondrej Jirman +Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -3343,6 +3343,15 @@ + + uart9 { + /omit-if-no-ref/ ++ uart9m0_xfer: uart9m0-xfer { ++ rockchip,pins = ++ /* uart9_rx_m0 */ ++ <2 RK_PC4 10 &pcfg_pull_up>, ++ /* uart9_tx_m0 */ ++ <2 RK_PC2 10 &pcfg_pull_up>; ++ }; ++ ++ /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ diff --git a/target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch b/target/linux/rockchip/patches-6.6/209-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch similarity index 100% rename from target/linux/rockchip/patches-6.6/030-v6.9-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch rename to target/linux/rockchip/patches-6.6/209-arm64-dts-rockchip-adjust-vendor-on-Banana-Pi-R2-Pro.patch diff --git a/target/linux/rockchip/patches-6.6/302-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-r.patch b/target/linux/rockchip/patches-6.6/302-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-r.patch new file mode 100644 index 00000000000000..4f0d67ec778934 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/302-arm64-dts-rockchip-Add-missing-sdmmc2-SDR-rates-to-r.patch @@ -0,0 +1,39 @@ +From 0597d85859e48c4366862a6252479698590ae39c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Tam=C3=A1s=20Sz=C5=B1cs?= +Date: Wed, 11 Oct 2023 19:14:56 +0000 +Subject: [PATCH] arm64: dts: rockchip: Add missing sdmmc2 SDR rates to rock-3a +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add missing UHS-I SDR rates to sdmmc2. Add explicit alias as mmc2 while at it. +It would be good to have matching timings enabled in case slower SDIO devices +are encountered. + +Signed-off-by: Tamás Szűcs +Link: https://lore.kernel.org/r/20231011191448.58936-1-tszucs@protonmail.ch +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -15,6 +15,7 @@ + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; ++ mmc2 = &sdmmc2; + }; + + chosen: chosen { +@@ -746,6 +747,9 @@ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; ++ sd-uhs-sdr12; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>;