From fc7849a401cb9e3d1680b055b9cd868e6876d452 Mon Sep 17 00:00:00 2001 From: NakanoMiku Date: Tue, 29 Oct 2024 14:32:45 +0800 Subject: [PATCH] Add support for loong64 --- include/atomic_queue/defs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/atomic_queue/defs.h b/include/atomic_queue/defs.h index 4601b1d..053f8e1 100644 --- a/include/atomic_queue/defs.h +++ b/include/atomic_queue/defs.h @@ -56,6 +56,14 @@ static inline void spin_loop_pause() noexcept { asm volatile (".insn i 0x0F, 0, x0, x0, 0x010"); } } // namespace atomic_queue +#elif defined(__loongarch__) +namespace atomic_queue { +constexpr int CACHE_LINE_SIZE = 64; +static inline void spin_loop_pause() noexcept +{ + asm volatile("nop \n nop \n nop \n nop \n nop \n nop \n nop \n nop"); +} +} // namespace atomic_queue #else #ifdef _MSC_VER #pragma message("Unknown CPU architecture. Using L1 cache line size of 64 bytes and no spinloop pause instruction.")