diff --git a/ChangeLog b/ChangeLog
index 6250d27..b0a8e6e 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,11 @@
+R2307:
+======
+- added/enhanced support for HDC1000 and HDC1080
+- update to IDF version 5.1 for S3 dual-core support
+- ILI9341 update
+- added support for ESP32-C6
+- fixes
+
 R2306:
 ======
 - fix: enable/disable at-jobs not working as expected
diff --git a/bin/flash-atrium.sh b/bin/flash-atrium.sh
index f5b4223..dd2121d 100755
--- a/bin/flash-atrium.sh
+++ b/bin/flash-atrium.sh
@@ -57,7 +57,7 @@ esp32_4m | esp32-s2_4m)
 	esptool.py --chip $chip erase_flash
 	esptool.py --baud 1000000 --chip $chip write_flash 0x1000 $1/boot@0x1000.bin 0x8000 $1/ptable@0x8000.bin 0x100000 $1/atrium.bin
 ;;
-esp32-c3_4m | esp32-s3_4m )
+esp32-c3_4m | esp32-c6_4m | esp32-s3_4m )
 	esptool.py --chip $chip erase_flash
 	esptool.py --baud 1000000 --chip $chip write_flash 0x0000 $1/boot@0x0000.bin 0x8000 $1/ptable@0x8000.bin 0x100000 $1/atrium.bin
 ;;
diff --git a/components/cyclic/cyclic.cpp b/components/cyclic/cyclic.cpp
index 3e47aaf..05a9baa 100644
--- a/components/cyclic/cyclic.cpp
+++ b/components/cyclic/cyclic.cpp
@@ -88,7 +88,7 @@ static StaticTask_t CyclicTask;
 
 static SubTask *SubTasks = 0;
 static SemaphoreHandle_t Mtx = 0;
-static volatile uint64_t TimeSpent = 0;
+static uint64_t TimeSpent = 0;
 
 #ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB
 #define busy_set(...)
@@ -144,6 +144,7 @@ int cyclic_rm_task(const char *name)
 }
 
 
+// called from event task, if no dedicated cyclic task is created
 unsigned cyclic_execute()
 {
 	MLock lock(Mtx,__FUNCTION__);
diff --git a/components/event/event.cpp b/components/event/event.cpp
index 6fde613..b466f44 100644
--- a/components/event/event.cpp
+++ b/components/event/event.cpp
@@ -330,6 +330,7 @@ void event_trigger(event_t id)
 		++Invalid;
 	} else if (EventHandlers[id].callbacks.empty()) {
 		++Discarded;
+		++EventHandlers[id].occur;
 	} else {
 		Event e(id);
 		BaseType_t r = xQueueSend(EventsQ,&e,1000);
@@ -356,13 +357,15 @@ void event_trigger_arg(event_t id, void *arg)
 	if ((id != 0) && (id < EventHandlers.size())) {
 		if (!EventHandlers[id].callbacks.empty()) {
 			Event e(id,arg);
-			log_dbug(TAG,"trigger %d %p",id,arg);
 			BaseType_t r = xQueueSend(EventsQ,&e,1000);
 			if (r != pdTRUE)
 				++Lost;
+			else
+				log_dbug(TAG,"trigger %d %p",id,arg);
 			return;
 		}
 		++Discarded;
+		++EventHandlers[id].occur;
 	} else {
 		++Invalid;
 	}
diff --git a/components/logging/CMakeLists.txt b/components/logging/CMakeLists.txt
index 1de1e39..a299c22 100644
--- a/components/logging/CMakeLists.txt
+++ b/components/logging/CMakeLists.txt
@@ -3,6 +3,6 @@
 #register_component()
 idf_component_register(
 	SRCS logging.c modules.c profiling.cpp xlog.cpp
-	REQUIRES netsvc streams term main esp_timer tinyusb
+	REQUIRES netsvc streams term main esp_timer #tinyusb
 	INCLUDE_DIRS .
 )
diff --git a/components/logging/logging.c b/components/logging/logging.c
index 7a640ba..43852c4 100644
--- a/components/logging/logging.c
+++ b/components/logging/logging.c
@@ -274,7 +274,7 @@ void log_common(log_level_t l, logmod_t m, const char *f, va_list val)
 #else
 		struct timespec ts;
 		clock_gettime(CLOCK_REALTIME,&ts);
-		p += sprintf(at," (%lu.%03u) %s: ",ts.tv_sec,(unsigned)(ts.tv_nsec/1E6),a);
+		p += sprintf(at," (%llu.%03u) %s: ",ts.tv_sec,(unsigned)(ts.tv_nsec/1E6),a);
 #endif
 	} else {
 		struct tm tm;
@@ -405,10 +405,10 @@ void abort_on_mutex(SemaphoreHandle_t mtx, const char *usage)
 	uart_print(__FUNCTION__);
 	TaskHandle_t h = xSemaphoreGetMutexHolder(mtx);
 #if defined ESP32
-	const char *n = pcTaskGetTaskName(0);
+	const char *n = pcTaskGetName(0);
 	if (n)
 		uart_print(n);
-	n = pcTaskGetTaskName(h);
+	n = pcTaskGetName(h);
 	if (n)
 		uart_print(n);
 #else
diff --git a/components/netsvc/tcpio.h b/components/netsvc/tcpio.h
index 8001a22..31dbe89 100644
--- a/components/netsvc/tcpio.h
+++ b/components/netsvc/tcpio.h
@@ -28,7 +28,7 @@ typedef struct tcpout_arg {
 	struct tcp_pcb *pcb;
 	const char *name;
 	err_t err;
-	xSemaphoreHandle sem;
+	SemaphoreHandle_t sem;
 } tcpout_arg_t;
 
 typedef struct tcpwrite_arg {
@@ -37,12 +37,12 @@ typedef struct tcpwrite_arg {
 	const char *data;
 	size_t size;
 	err_t err;
-	xSemaphoreHandle sem;
+	SemaphoreHandle_t sem;
 } tcpwrite_arg_t;
 
 typedef struct tcp_pbuf_arg {
 	struct pbuf *pbuf;
-	xSemaphoreHandle sem;
+	SemaphoreHandle_t sem;
 } tcp_pbuf_arg_t;
 
 #ifdef __cplusplus
diff --git a/components/netsvc/udns.cpp b/components/netsvc/udns.cpp
index d5ccb29..ad76e95 100644
--- a/components/netsvc/udns.cpp
+++ b/components/netsvc/udns.cpp
@@ -152,7 +152,7 @@ struct DnsEntry
 {
 	DnsEntry *next;
 	ip_addr_t ip;
-	portTickType ttl;
+	TickType_t ttl;
 	uint8_t len;
 	char host[];
 };
@@ -161,7 +161,7 @@ struct DnsEntry
 struct Query
 {
 	Query *next;
-	portTickType ts;
+	TickType_t ts;
 	uint8_t *buf;
 	void *arg;
 	void (*cb)(const char *, const ip_addr_t *, void *);
@@ -463,7 +463,7 @@ static int parseAnswer(struct pbuf *p, size_t off, const ip_addr_t *sender)
 			return -off;
 		}
 		log_devel(TAG,"IPv4 %s",ip2str_r(&ip,ipstr,sizeof(ipstr)));
-#if defined CONFIG_LWIP_IPV6 || defined ESP32
+#if defined CONFIG_LWIP_IPV6 //|| defined ESP32
 	// why mask bit 15?
 //	} else if (((a.rr_class & 0x7fff) == TYPE_ADDR) && (a.rdlen == 16)) {
 	} else if ((a.rr_class == TYPE_ADDR) && (a.rdlen == 16)) {
@@ -1087,7 +1087,7 @@ static void udns_cyclic_fn(void *arg)
 	if (Queries) {
 		Lock lock(Mtx,__FUNCTION__);
 		log_dbug(TAG,"locked");
-		portTickType ts = xTaskGetTickCount();
+		TickType_t ts = xTaskGetTickCount();
 		Query *q = Queries;
 		while (q) {
 			log_dbug(TAG,"%s: q->ts=%u, ts=%u",q->hostname,q->ts,ts);
@@ -1139,7 +1139,7 @@ static unsigned udns_cyclic(void *arg)
 		abort();
 	}
 	Lock lock(Mtx,__FUNCTION__);
-	portTickType ts = xTaskGetTickCount();
+	TickType_t ts = xTaskGetTickCount();
 	Query *q = Queries;
 	while (q) {
 		if ((q->ts + configTICK_RATE_HZ < ts) && (!q->local)) {
@@ -1165,12 +1165,14 @@ static void wifi_down(void *)
 
 static inline void mdns_init_fn(void *)
 {
+#if 0
 	tcpip_adapter_ip_info_t ipconfig;
 	assert(Mtx);
 	if (ESP_OK == tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ipconfig)) {
 		if (0 != ipconfig.ip.addr)
 			IP4 = ipconfig.ip;
 	}
+#endif
 #if LWIP_IPV6
 	if (MPCB6 == 0) {
 		ip_addr_t mdns_ip6;
@@ -1195,10 +1197,12 @@ static inline void mdns_init_fn(void *)
 		IP_ADDR4(&mdns,224,0,0,251);
 		if (err_t e = udp_connect(MPCB,&mdns,MDNS_PORT))
 			log_warn(TAG,"connect 224.0.0.251: %s",strlwiperr(e));
+#if 0
 		if (err_t e = igmp_joingroup(&ipconfig.ip,ip_2_ip4(&mdns)))
 			log_warn(TAG,"unable to join MDNS group: %d",e);
 		else
 			log_dbug(TAG,"initialized MDNS");
+#endif
 	}
 #endif
 	State = mdns_wifiup;
diff --git a/components/streams/stream.h b/components/streams/stream.h
index 8af5312..c8a84e7 100644
--- a/components/streams/stream.h
+++ b/components/streams/stream.h
@@ -60,13 +60,18 @@ class stream
 	stream &operator << (uint32_t v)
 	{ return operator << ((uint64_t) v); }
 
-#if defined CONFIG_IDF_TARGET_ESP32C3
+#if defined ESP32 && IDF_VERSION < 50
+	stream &operator << (size_t v)
+	{ return operator << ((uint64_t) v); }
+#endif
+
+#if IDF_VERSION >= 50
 	stream &operator << (int v)
 	{ return operator << ((int64_t) v); }
 
 	stream &operator << (unsigned v)
 	{ return operator << ((uint64_t) v); }
-#endif 
+#endif
 
 	stream &operator << (double);
 
diff --git a/components/term/CMakeLists.txt b/components/term/CMakeLists.txt
index c4735c8..1476c76 100644
--- a/components/term/CMakeLists.txt
+++ b/components/term/CMakeLists.txt
@@ -5,5 +5,5 @@ idf_component_register(
 
 	INCLUDE_DIRS .
 
-	REQUIRES logging netsvc streams tinyusb
+	REQUIRES logging netsvc streams #tinyusb
 )
diff --git a/components/term/uart_terminal.cpp b/components/term/uart_terminal.cpp
index 3b4a670..f3daf4a 100644
--- a/components/term/uart_terminal.cpp
+++ b/components/term/uart_terminal.cpp
@@ -82,11 +82,11 @@ void UartTerminal::init(uint8_t uart)
 {
 	m_uart_rx = uart;
 	m_uart_tx = uart;
-#if CONFIG_UART_CONSOLE_NONE != 1
+#if CONFIG_UART_CONSOLE_NONE != 1 && CONFIG_CONSOLE_UART_NUM != -1
 	if ((int)uart != CONFIG_CONSOLE_UART_NUM)
 #endif
 		uart_driver_install((uart_port_t)uart,UART_FIFO_LEN*2,UART_FIFO_LEN*2,0,DRIVER_ARG);
-	sprintf(m_name,"uart@%d",uart);
+	snprintf(m_name,sizeof(m_name),"uart@%d",uart);
 }
 
 
@@ -94,8 +94,8 @@ void UartTerminal::init(uint8_t rx, uint8_t tx)
 {
 	m_uart_rx = rx;
 	m_uart_tx = tx;
-	sprintf(m_name,"uart@%d,%d",rx,tx);
-#if CONFIG_UART_CONSOLE_NONE != 1
+	snprintf(m_name,sizeof(m_name),"uart@%d,%d",rx,tx);
+#if CONFIG_UART_CONSOLE_NONE != 1 && CONFIG_CONSOLE_UART_NUM != -1
 	if ((int)rx != CONFIG_CONSOLE_UART_NUM)
 #endif
 		uart_driver_install((uart_port_t)rx,UART_FIFO_LEN*2,UART_FIFO_LEN*2,0,DRIVER_ARG);
diff --git a/components/term/uart_terminal.h b/components/term/uart_terminal.h
index 6a60ea2..4fcdf88 100644
--- a/components/term/uart_terminal.h
+++ b/components/term/uart_terminal.h
@@ -40,7 +40,11 @@ class UartTerminal : public Terminal
 
 	private:
 	int8_t m_uart_rx, m_uart_tx;
+#if IDF_VERSION >= 50
+	char m_name[14];
+#else
 	char m_name[10];
+#endif
 };
 
 extern "C"
diff --git a/components/wfc/hwcfg_esp32.cpp b/components/wfc/hwcfg_esp32.cpp
index 9d4d3fc..b092fc2 100644
--- a/components/wfc/hwcfg_esp32.cpp
+++ b/components/wfc/hwcfg_esp32.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -500,6 +500,7 @@ const char *disp_t_str(disp_t e)
 static const char *spidrv_t_names[] = {
 	"spidrv_ili9341",
 	"spidrv_invalid",
+	"spidrv_sdcard",
 	"spidrv_ssd1309",
 	"spidrv_sx1276",
 	"spidrv_xpt2046",
@@ -508,6 +509,7 @@ static const char *spidrv_t_names[] = {
 static spidrv_t spidrv_t_values[] = {
 	spidrv_ili9341,
 	spidrv_invalid,
+	spidrv_sdcard,
 	spidrv_ssd1309,
 	spidrv_sx1276,
 	spidrv_xpt2046,
@@ -520,6 +522,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *v, const char *s)
 	static std::map<const char *,spidrv_t, cstr_less> namesmap = {
 		{ "spidrv_ili9341", spidrv_ili9341},
 		{ "spidrv_invalid", spidrv_invalid},
+		{ "spidrv_sdcard", spidrv_sdcard},
 		{ "spidrv_ssd1309", spidrv_ssd1309},
 		{ "spidrv_sx1276", spidrv_sx1276},
 		{ "spidrv_xpt2046", spidrv_xpt2046},
@@ -564,6 +567,8 @@ const char *spidrv_t_str(spidrv_t e)
 		return "spidrv_ili9341";
 	case spidrv_xpt2046:
 		return "spidrv_xpt2046";
+	case spidrv_sdcard:
+		return "spidrv_sdcard";
 	}
 	#endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB
 	#ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB
@@ -3704,6 +3709,10 @@ void I2CConfig::toASCII(stream &o, size_t indent) const
 		o << ".drv = " ;
 		o << i2cdrv_t_str(devices_drv(i));
 		o << ';';
+		ascii_indent(o,indent);
+		o << ".intr = " ;
+		o << (unsigned) devices_intr(i);
+		o << ';';
 		--indent;
 	}
 	--indent;
@@ -4108,6 +4117,12 @@ int I2CConfig::setByName(const char *name, const char *value)
 					}
 				}
 			}
+			if (!strcmp("intr",idxe)) {
+				if (eptr != value) {
+					set_devices_intr(x,(uint8_t)ull);
+					return 0;
+				}
+			}
 			return -199;
 		}
 	}
diff --git a/components/wfc/hwcfg_esp32.h b/components/wfc/hwcfg_esp32.h
index 7c3f422..27a8de1 100644
--- a/components/wfc/hwcfg_esp32.h
+++ b/components/wfc/hwcfg_esp32.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -201,6 +201,7 @@ typedef enum {
 	spidrv_ssd1309 = 2,
 	spidrv_ili9341 = 3,
 	spidrv_xpt2046 = 4,
+	spidrv_sdcard = 5,
 } spidrv_t;
 //! Function to get an ASCII string from a value of a spidrv_t.
 const char *spidrv_t_str(spidrv_t e);
@@ -209,7 +210,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *, const char *);
 
 typedef uint8_t pull_mode_t;
 typedef uint8_t relay_cfg_t;
-typedef uint16_t i2cdev_t;
+typedef uint32_t i2cdev_t;
 typedef uint8_t ledcfg_t;
 typedef uint16_t gpiocfg_t;
 typedef uint8_t spiopt_t;
@@ -2137,6 +2138,10 @@ class I2CConfig : public Message
 	i2cdrv_t devices_drv(unsigned x) const;
 	//! Function to set the drv part of bitset devices.
 	void set_devices_drv(unsigned x, i2cdrv_t);
+	//! Function to get the intr part of bitset devices.
+	uint8_t devices_intr(unsigned x) const;
+	//! Function to set the intr part of bitset devices.
+	void set_devices_intr(unsigned x, uint8_t);
 	//! Set devices using a constant reference
 	void set_devices(unsigned x, i2cdev_t v);
 	/*!
@@ -7264,6 +7269,11 @@ inline i2cdrv_t I2CConfig::devices_drv(unsigned x) const
 	return (i2cdrv_t)((m_devices[x] >> 8) & 0xff);
 }
 
+inline uint8_t I2CConfig::devices_intr(unsigned x) const
+{
+	return (uint8_t)((m_devices[x] >> 16) & 0x3f);
+}
+
 /*!
  * Function for clearing the associated member variable.
  * It will reset the value to the default value.
@@ -7288,13 +7298,19 @@ inline std::vector<i2cdev_t> *I2CConfig::mutable_devices()
 inline void I2CConfig::set_devices_addr(unsigned x, uint8_t v)
 {
 	m_devices[x] &= ~(0x7fULL << 0);
-	m_devices[x] |= ((uint16_t) v << 0);
+	m_devices[x] |= ((uint32_t) v << 0);
 }
 
 inline void I2CConfig::set_devices_drv(unsigned x, i2cdrv_t v)
 {
 	m_devices[x] &= ~(0xffULL << 8);
-	m_devices[x] |= ((uint16_t) v << 8);
+	m_devices[x] |= ((uint32_t) v << 8);
+}
+
+inline void I2CConfig::set_devices_intr(unsigned x, uint8_t v)
+{
+	m_devices[x] &= ~(0x3fULL << 16);
+	m_devices[x] |= ((uint32_t) v << 16);
 }
 
 inline void I2CConfig::add_devices(i2cdev_t v)
diff --git a/components/wfc/hwcfg_esp8266.cpp b/components/wfc/hwcfg_esp8266.cpp
index e1f950b..b6e9b13 100644
--- a/components/wfc/hwcfg_esp8266.cpp
+++ b/components/wfc/hwcfg_esp8266.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -500,6 +500,7 @@ const char *disp_t_str(disp_t e)
 static const char *spidrv_t_names[] = {
 	"spidrv_ili9341",
 	"spidrv_invalid",
+	"spidrv_sdcard",
 	"spidrv_ssd1309",
 	"spidrv_sx1276",
 	"spidrv_xpt2046",
@@ -508,6 +509,7 @@ static const char *spidrv_t_names[] = {
 static spidrv_t spidrv_t_values[] = {
 	spidrv_ili9341,
 	spidrv_invalid,
+	spidrv_sdcard,
 	spidrv_ssd1309,
 	spidrv_sx1276,
 	spidrv_xpt2046,
@@ -520,6 +522,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *v, const char *s)
 	static std::map<const char *,spidrv_t, cstr_less> namesmap = {
 		{ "spidrv_ili9341", spidrv_ili9341},
 		{ "spidrv_invalid", spidrv_invalid},
+		{ "spidrv_sdcard", spidrv_sdcard},
 		{ "spidrv_ssd1309", spidrv_ssd1309},
 		{ "spidrv_sx1276", spidrv_sx1276},
 		{ "spidrv_xpt2046", spidrv_xpt2046},
@@ -564,6 +567,8 @@ const char *spidrv_t_str(spidrv_t e)
 		return "spidrv_ili9341";
 	case spidrv_xpt2046:
 		return "spidrv_xpt2046";
+	case spidrv_sdcard:
+		return "spidrv_sdcard";
 	}
 	#endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB
 	#ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB
@@ -3239,6 +3244,10 @@ void I2CConfig::toASCII(stream &o, size_t indent) const
 		o << ".drv = " ;
 		o << i2cdrv_t_str(devices_drv(i));
 		o << ';';
+		ascii_indent(o,indent);
+		o << ".intr = " ;
+		o << (unsigned) devices_intr(i);
+		o << ';';
 		--indent;
 	}
 	--indent;
@@ -3571,6 +3580,12 @@ int I2CConfig::setByName(const char *name, const char *value)
 					}
 				}
 			}
+			if (!strcmp("intr",idxe)) {
+				if (eptr != value) {
+					set_devices_intr(x,(uint8_t)ull);
+					return 0;
+				}
+			}
 			return -151;
 		}
 	}
diff --git a/components/wfc/hwcfg_esp8266.h b/components/wfc/hwcfg_esp8266.h
index dee79db..fb372e2 100644
--- a/components/wfc/hwcfg_esp8266.h
+++ b/components/wfc/hwcfg_esp8266.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -202,6 +202,7 @@ typedef enum {
 	spidrv_ssd1309 = 2,
 	spidrv_ili9341 = 3,
 	spidrv_xpt2046 = 4,
+	spidrv_sdcard = 5,
 } spidrv_t;
 //! Function to get an ASCII string from a value of a spidrv_t.
 const char *spidrv_t_str(spidrv_t e);
@@ -210,7 +211,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *, const char *);
 
 typedef uint8_t pull_mode_t;
 typedef uint8_t relay_cfg_t;
-typedef uint16_t i2cdev_t;
+typedef uint32_t i2cdev_t;
 typedef uint8_t ledcfg_t;
 typedef uint16_t gpiocfg_t;
 typedef uint8_t spiopt_t;
@@ -2044,6 +2045,10 @@ class I2CConfig : public Message
 	i2cdrv_t devices_drv(unsigned x) const;
 	//! Function to set the drv part of bitset devices.
 	void set_devices_drv(unsigned x, i2cdrv_t);
+	//! Function to get the intr part of bitset devices.
+	uint8_t devices_intr(unsigned x) const;
+	//! Function to set the intr part of bitset devices.
+	void set_devices_intr(unsigned x, uint8_t);
 	//! Set devices using a constant reference
 	void set_devices(unsigned x, i2cdev_t v);
 	/*!
@@ -6811,6 +6816,11 @@ inline i2cdrv_t I2CConfig::devices_drv(unsigned x) const
 	return (i2cdrv_t)((m_devices[x] >> 8) & 0xff);
 }
 
+inline uint8_t I2CConfig::devices_intr(unsigned x) const
+{
+	return (uint8_t)((m_devices[x] >> 16) & 0x3f);
+}
+
 /*!
  * Function for clearing the associated member variable.
  * It will reset the value to the default value.
@@ -6835,13 +6845,19 @@ inline std::vector<i2cdev_t> *I2CConfig::mutable_devices()
 inline void I2CConfig::set_devices_addr(unsigned x, uint8_t v)
 {
 	m_devices[x] &= ~(0x7fULL << 0);
-	m_devices[x] |= ((uint16_t) v << 0);
+	m_devices[x] |= ((uint32_t) v << 0);
 }
 
 inline void I2CConfig::set_devices_drv(unsigned x, i2cdrv_t v)
 {
 	m_devices[x] &= ~(0xffULL << 8);
-	m_devices[x] |= ((uint16_t) v << 8);
+	m_devices[x] |= ((uint32_t) v << 8);
+}
+
+inline void I2CConfig::set_devices_intr(unsigned x, uint8_t v)
+{
+	m_devices[x] &= ~(0x3fULL << 16);
+	m_devices[x] |= ((uint32_t) v << 16);
 }
 
 inline void I2CConfig::add_devices(i2cdev_t v)
diff --git a/components/wfc/hwcfg_esp8285.cpp b/components/wfc/hwcfg_esp8285.cpp
index 9778ae3..a1ec5a2 100644
--- a/components/wfc/hwcfg_esp8285.cpp
+++ b/components/wfc/hwcfg_esp8285.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -502,6 +502,7 @@ const char *disp_t_str(disp_t e)
 static const char *spidrv_t_names[] = {
 	"spidrv_ili9341",
 	"spidrv_invalid",
+	"spidrv_sdcard",
 	"spidrv_ssd1309",
 	"spidrv_sx1276",
 	"spidrv_xpt2046",
@@ -510,6 +511,7 @@ static const char *spidrv_t_names[] = {
 static spidrv_t spidrv_t_values[] = {
 	spidrv_ili9341,
 	spidrv_invalid,
+	spidrv_sdcard,
 	spidrv_ssd1309,
 	spidrv_sx1276,
 	spidrv_xpt2046,
@@ -522,6 +524,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *v, const char *s)
 	static std::map<const char *,spidrv_t, cstr_less> namesmap = {
 		{ "spidrv_ili9341", spidrv_ili9341},
 		{ "spidrv_invalid", spidrv_invalid},
+		{ "spidrv_sdcard", spidrv_sdcard},
 		{ "spidrv_ssd1309", spidrv_ssd1309},
 		{ "spidrv_sx1276", spidrv_sx1276},
 		{ "spidrv_xpt2046", spidrv_xpt2046},
@@ -566,6 +569,8 @@ const char *spidrv_t_str(spidrv_t e)
 		return "spidrv_ili9341";
 	case spidrv_xpt2046:
 		return "spidrv_xpt2046";
+	case spidrv_sdcard:
+		return "spidrv_sdcard";
 	}
 	#endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB
 	#ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB
@@ -3241,6 +3246,10 @@ void I2CConfig::toASCII(stream &o, size_t indent) const
 		o << ".drv = " ;
 		o << i2cdrv_t_str(devices_drv(i));
 		o << ';';
+		ascii_indent(o,indent);
+		o << ".intr = " ;
+		o << (unsigned) devices_intr(i);
+		o << ';';
 		--indent;
 	}
 	--indent;
@@ -3573,6 +3582,12 @@ int I2CConfig::setByName(const char *name, const char *value)
 					}
 				}
 			}
+			if (!strcmp("intr",idxe)) {
+				if (eptr != value) {
+					set_devices_intr(x,(uint8_t)ull);
+					return 0;
+				}
+			}
 			return -151;
 		}
 	}
diff --git a/components/wfc/hwcfg_esp8285.h b/components/wfc/hwcfg_esp8285.h
index 405ba39..2aac1b4 100644
--- a/components/wfc/hwcfg_esp8285.h
+++ b/components/wfc/hwcfg_esp8285.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -203,6 +203,7 @@ typedef enum {
 	spidrv_ssd1309 = 2,
 	spidrv_ili9341 = 3,
 	spidrv_xpt2046 = 4,
+	spidrv_sdcard = 5,
 } spidrv_t;
 //! Function to get an ASCII string from a value of a spidrv_t.
 const char *spidrv_t_str(spidrv_t e);
@@ -211,7 +212,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *, const char *);
 
 typedef uint8_t pull_mode_t;
 typedef uint8_t relay_cfg_t;
-typedef uint16_t i2cdev_t;
+typedef uint32_t i2cdev_t;
 typedef uint8_t ledcfg_t;
 typedef uint16_t gpiocfg_t;
 typedef uint8_t spiopt_t;
@@ -2045,6 +2046,10 @@ class I2CConfig
 	i2cdrv_t devices_drv(unsigned x) const;
 	//! Function to set the drv part of bitset devices.
 	void set_devices_drv(unsigned x, i2cdrv_t);
+	//! Function to get the intr part of bitset devices.
+	uint8_t devices_intr(unsigned x) const;
+	//! Function to set the intr part of bitset devices.
+	void set_devices_intr(unsigned x, uint8_t);
 	//! Set devices using a constant reference
 	void set_devices(unsigned x, i2cdev_t v);
 	/*!
@@ -6809,6 +6814,11 @@ inline i2cdrv_t I2CConfig::devices_drv(unsigned x) const
 	return (i2cdrv_t)((m_devices[x] >> 8) & 0xff);
 }
 
+inline uint8_t I2CConfig::devices_intr(unsigned x) const
+{
+	return (uint8_t)((m_devices[x] >> 16) & 0x3f);
+}
+
 /*!
  * Function for clearing the associated member variable.
  * It will reset the value to the default value.
@@ -6833,13 +6843,19 @@ inline std::vector<i2cdev_t> *I2CConfig::mutable_devices()
 inline void I2CConfig::set_devices_addr(unsigned x, uint8_t v)
 {
 	m_devices[x] &= ~(0x7fULL << 0);
-	m_devices[x] |= ((uint16_t) v << 0);
+	m_devices[x] |= ((uint32_t) v << 0);
 }
 
 inline void I2CConfig::set_devices_drv(unsigned x, i2cdrv_t v)
 {
 	m_devices[x] &= ~(0xffULL << 8);
-	m_devices[x] |= ((uint16_t) v << 8);
+	m_devices[x] |= ((uint32_t) v << 8);
+}
+
+inline void I2CConfig::set_devices_intr(unsigned x, uint8_t v)
+{
+	m_devices[x] &= ~(0x3fULL << 16);
+	m_devices[x] |= ((uint32_t) v << 16);
 }
 
 inline void I2CConfig::add_devices(i2cdev_t v)
diff --git a/components/wfc/hwcfg_pc.cpp b/components/wfc/hwcfg_pc.cpp
index 32bcde1..ec30aa6 100644
--- a/components/wfc/hwcfg_pc.cpp
+++ b/components/wfc/hwcfg_pc.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -302,6 +302,7 @@ const char *disp_t_str(disp_t e)
 static const char *spidrv_t_names[] = {
 	"spidrv_ili9341",
 	"spidrv_invalid",
+	"spidrv_sdcard",
 	"spidrv_ssd1309",
 	"spidrv_sx1276",
 	"spidrv_xpt2046",
@@ -310,6 +311,7 @@ static const char *spidrv_t_names[] = {
 static spidrv_t spidrv_t_values[] = {
 	spidrv_ili9341,
 	spidrv_invalid,
+	spidrv_sdcard,
 	spidrv_ssd1309,
 	spidrv_sx1276,
 	spidrv_xpt2046,
@@ -4016,6 +4018,10 @@ void I2CConfig::toASCII(std::ostream &o, size_t indent) const
 		o << ".drv = " ;
 		o << i2cdrv_t_str(devices_drv(i));
 		o << ';';
+		ascii_indent(o,indent);
+		o << ".intr = " ;
+		o << (unsigned) devices_intr(i);
+		o << ';';
 		--indent;
 	}
 	--indent;
@@ -4495,6 +4501,12 @@ int I2CConfig::setByName(const char *name, const char *value)
 					return 0;
 				}
 			}
+			if (!strcmp("intr",idxe)) {
+				if (eptr != value) {
+					set_devices_intr(x,(uint8_t)ull);
+					return 0;
+				}
+			}
 			return -199;
 		}
 	}
diff --git a/components/wfc/hwcfg_pc.h b/components/wfc/hwcfg_pc.h
index 0675a54..53aabb5 100644
--- a/components/wfc/hwcfg_pc.h
+++ b/components/wfc/hwcfg_pc.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -203,6 +203,7 @@ typedef enum {
 	spidrv_ssd1309 = 2,
 	spidrv_ili9341 = 3,
 	spidrv_xpt2046 = 4,
+	spidrv_sdcard = 5,
 } spidrv_t;
 //! Function to get an ASCII string from a value of a spidrv_t.
 const char *spidrv_t_str(spidrv_t e);
@@ -211,7 +212,7 @@ size_t parse_ascii_spidrv_t(spidrv_t *, const char *);
 
 typedef uint8_t pull_mode_t;
 typedef uint8_t relay_cfg_t;
-typedef uint16_t i2cdev_t;
+typedef uint32_t i2cdev_t;
 typedef uint8_t ledcfg_t;
 typedef uint16_t gpiocfg_t;
 typedef uint8_t spiopt_t;
@@ -2229,6 +2230,10 @@ class I2CConfig : public Message
 	i2cdrv_t devices_drv(unsigned x) const;
 	//! Function to set the drv part of bitset devices.
 	void set_devices_drv(unsigned x, i2cdrv_t);
+	//! Function to get the intr part of bitset devices.
+	uint8_t devices_intr(unsigned x) const;
+	//! Function to set the intr part of bitset devices.
+	void set_devices_intr(unsigned x, uint8_t);
 	//! Set devices using a constant reference
 	void set_devices(unsigned x, i2cdev_t v);
 	/*!
@@ -7520,6 +7525,11 @@ inline i2cdrv_t I2CConfig::devices_drv(unsigned x) const
 	return (i2cdrv_t)((m_devices[x] >> 8) & 0xff);
 }
 
+inline uint8_t I2CConfig::devices_intr(unsigned x) const
+{
+	return (uint8_t)((m_devices[x] >> 16) & 0x3f);
+}
+
 /*!
  * Function for clearing the associated member variable.
  * It will reset the value to the default value.
@@ -7544,13 +7554,19 @@ inline std::vector<i2cdev_t> *I2CConfig::mutable_devices()
 inline void I2CConfig::set_devices_addr(unsigned x, uint8_t v)
 {
 	m_devices[x] &= ~(0x7fULL << 0);
-	m_devices[x] |= ((uint16_t) v << 0);
+	m_devices[x] |= ((uint32_t) v << 0);
 }
 
 inline void I2CConfig::set_devices_drv(unsigned x, i2cdrv_t v)
 {
 	m_devices[x] &= ~(0xffULL << 8);
-	m_devices[x] |= ((uint16_t) v << 8);
+	m_devices[x] |= ((uint32_t) v << 8);
+}
+
+inline void I2CConfig::set_devices_intr(unsigned x, uint8_t v)
+{
+	m_devices[x] &= ~(0x3fULL << 16);
+	m_devices[x] |= ((uint32_t) v << 16);
 }
 
 inline void I2CConfig::add_devices(i2cdev_t v)
diff --git a/components/wfc/swcfg_esp32.cpp b/components/wfc/swcfg_esp32.cpp
index 4174a57..a5a1216 100644
--- a/components/wfc/swcfg_esp32.cpp
+++ b/components/wfc/swcfg_esp32.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2292,8 +2292,8 @@ Message *Influx::p_getMember(const char *s, unsigned n, unsigned x)
 
 void UartSettings::clear()
 {
-	m_port = 0;
-	m_baudrate = 0;
+	m_port = -1;
+	m_baudrate = 115200;
 	m_config = 5;
 	m_rx_thresh = 0;
 	m_tx_bufsize = 0;
@@ -2305,7 +2305,7 @@ void UartSettings::toASCII(stream &o, size_t indent) const
 {
 	o << "UartSettings {";
 	++indent;
-	ascii_numeric(o, indent, "port", (unsigned) m_port);
+	ascii_numeric(o, indent, "port", (signed) m_port);
 	ascii_numeric(o, indent, "baudrate", m_baudrate);
 	ascii_numeric(o, indent, "config", m_config);
 	++indent;
@@ -2350,14 +2350,14 @@ ssize_t UartSettings::fromMemory(const void *b, ssize_t s)
 			return -95;
 		a += fn;
 		switch (fid) {
-		case 0x8:	// port id 1, type uint8_t, coding varint
+		case 0x8:	// port id 1, type int8_t, coding signed varint
 			{
 				varint_t v;
 				int n = read_varint(a,e-a,&v);
 				if (n <= 0)
 					return -96;
 				a += n;
-				set_port(v);
+				set_port(varint_sint(v));
 			}
 			break;
 		case 0x10:	// baudrate id 2, type uint32_t, coding varint
@@ -2424,18 +2424,18 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 	uint8_t *a = b, *e = b + s;
 	signed n;
 	// has port?
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		if (a >= e)
 			return -104;
 		*a++ = 0x8;
-		n = write_varint(a,e-a,m_port);
+		n = write_varint(a,e-a,sint_varint(m_port));
 		if (n <= 0)
 			return -105;
 		a += n;
 	}
 	// has baudrate?
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		if (a >= e)
 			return -106;
@@ -2446,7 +2446,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has config?
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		if (a >= e)
 			return -108;
@@ -2463,7 +2463,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		*a++ = m_rx_thresh;
 	}
 	// has tx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		if (a >= e)
 			return -110;
@@ -2474,7 +2474,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has rx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		if (a >= e)
 			return -112;
@@ -2494,7 +2494,7 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 	++indLvl;
 	if (has_port()) {
 		fsep = json_indent(json,indLvl,fsep,"port");
-		json << (unsigned) m_port;
+		json << (int) m_port;
 	}
 	if (has_baudrate()) {
 		fsep = json_indent(json,indLvl,fsep,"baudrate");
@@ -2529,16 +2529,16 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 size_t UartSettings::calcSize() const
 {
 	size_t r = 0;	// required size, default is fixed length
-	// optional uint8 port, id 1
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
-		r += wiresize((varint_t)m_port) + 1 /* tag(port) 0x8 */;
+	// optional sint8 port, id 1
+	if (m_port != -1) {
+		r += wiresize_s((varint_t)m_port) + 1 /* tag(port) 0x8 */;
 	}
 	// optional unsigned baudrate, id 2
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		r += wiresize((varint_t)m_baudrate) + 1 /* tag(baudrate) 0x10 */;
 	}
 	// optional uartcfg_t config, id 3
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		r += wiresize((varint_t)m_config) + 1 /* tag(config) 0x18 */;
 	}
 	// optional fixed8 rx_thresh, id 4
@@ -2546,11 +2546,11 @@ size_t UartSettings::calcSize() const
 		r += 2;
 	}
 	// optional unsigned tx_bufsize, id 6
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		r += wiresize((varint_t)m_tx_bufsize) + 1 /* tag(tx_bufsize) 0x30 */;
 	}
 	// optional unsigned rx_bufsize, id 7
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		r += wiresize((varint_t)m_rx_bufsize) + 1 /* tag(rx_bufsize) 0x38 */;
 	}
 	return r;
@@ -2596,9 +2596,7 @@ int UartSettings::setByName(const char *name, const char *value)
 			clear_port();
 			return 0;
 		}
-		int r = parse_ascii_u8(&m_port,value);
-		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 0);
+		int r = parse_ascii_s8(&m_port,value);
 		return r;
 	}
 	if (0 == strcmp(name,"baudrate")) {
@@ -2608,7 +2606,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_baudrate,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 1);
+			p_validbits |= ((uint8_t)1U << 0);
 		return r;
 	}
 	if ((0 == memcmp(name,"config",6)) && ((name[6] == 0) || name[6] == '.')) {
@@ -2689,7 +2687,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_tx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 3);
+			p_validbits |= ((uint8_t)1U << 2);
 		return r;
 	}
 	if (0 == strcmp(name,"rx_bufsize")) {
@@ -2699,7 +2697,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_rx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 4);
+			p_validbits |= ((uint8_t)1U << 3);
 		return r;
 	}
 	return -115;
diff --git a/components/wfc/swcfg_esp32.h b/components/wfc/swcfg_esp32.h
index 0a12329..d375cce 100644
--- a/components/wfc/swcfg_esp32.h
+++ b/components/wfc/swcfg_esp32.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -1280,7 +1280,7 @@ class UartSettings : public Message
 	//! @return number of bytes parsed from value or negative value if an error occurs
 	int setByName(const char *param, const char *value);
 	
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	/*!
 	* Function for querying if port has been set.
 	* @return true if port is set.
@@ -1289,14 +1289,14 @@ class UartSettings : public Message
 	//! Function to reset port to its default/unset value.
 	void clear_port();
 	//! Get value of port.
-	uint8_t port() const;
+	int8_t port() const;
 	//! Set port using a constant reference
-	void set_port(uint8_t v);
+	void set_port(int8_t v);
 	/*!
 	* Provide mutable access to port.
 	* @return pointer to member variable of port.
 	*/
-	uint8_t *mutable_port();
+	int8_t *mutable_port();
 	
 	// optional unsigned baudrate, id 2
 	/*!
@@ -1417,15 +1417,15 @@ class UartSettings : public Message
 	Message *p_getMember(const char *s, unsigned n);
 	Message *p_getMember(const char *s, unsigned n, unsigned i);
 	//! unsigned baudrate, id 2
-	uint32_t m_baudrate = 0;
+	uint32_t m_baudrate = 115200;
 	//! unsigned tx_bufsize, id 6
 	uint32_t m_tx_bufsize = 0;
 	//! unsigned rx_bufsize, id 7
 	uint32_t m_rx_bufsize = 0;
 	//! uartcfg_t config, id 3
 	uartcfg_t m_config = 5;
-	//! uint8 port, id 1
-	uint8_t m_port = 0;
+	//! sint8 port, id 1
+	int8_t m_port = -1;
 	//! fixed8 rx_thresh, id 4
 	uint8_t m_rx_thresh = 0;
 	
@@ -5308,7 +5308,7 @@ inline void Influx::set_database(const estring &v)
 
 inline size_t UartSettings::getMaxSize()
 {
-	// optional uint8 port, id 1 has maximum size 3
+	// optional sint8 port, id 1 has maximum size 3
 	// optional unsigned baudrate, id 2 has maximum size 6
 	// optional uartcfg_t config, id 3 has maximum size 3
 	// optional fixed8 rx_thresh, id 4 has maximum size 2
@@ -5317,14 +5317,14 @@ inline size_t UartSettings::getMaxSize()
 	return 26;
 }
 
-inline uint8_t UartSettings::port() const
+inline int8_t UartSettings::port() const
 {
 	return m_port;
 }
 
 inline bool UartSettings::has_port() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 0));
+	return m_port != -1;
 }
 
 /*!
@@ -5333,23 +5333,17 @@ inline bool UartSettings::has_port() const
  */
 inline void UartSettings::clear_port()
 {
-	p_validbits &= ~((uint8_t)1U << 0);
-	m_port = 0;
+	m_port = -1;
 }
 
-inline uint8_t *UartSettings::mutable_port()
+inline int8_t *UartSettings::mutable_port()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
-		p_validbits |= ((uint8_t)1U << 0);
-		m_port = 0;
-	}
 	return &m_port;
 }
 
-inline void UartSettings::set_port(uint8_t v)
+inline void UartSettings::set_port(int8_t v)
 {
 	m_port = v;
-	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5361,7 +5355,7 @@ inline uint32_t UartSettings::baudrate() const
 
 inline bool UartSettings::has_baudrate() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 1));
+	return 0 != (p_validbits & ((uint8_t)1U << 0));
 }
 
 /*!
@@ -5370,15 +5364,15 @@ inline bool UartSettings::has_baudrate() const
  */
 inline void UartSettings::clear_baudrate()
 {
-	p_validbits &= ~((uint8_t)1U << 1);
-	m_baudrate = 0;
+	p_validbits &= ~((uint8_t)1U << 0);
+	m_baudrate = 115200;
 }
 
 inline uint32_t *UartSettings::mutable_baudrate()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
-		p_validbits |= ((uint8_t)1U << 1);
-		m_baudrate = 0;
+	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
+		p_validbits |= ((uint8_t)1U << 0);
+		m_baudrate = 115200;
 	}
 	return &m_baudrate;
 }
@@ -5386,7 +5380,7 @@ inline uint32_t *UartSettings::mutable_baudrate()
 inline void UartSettings::set_baudrate(uint32_t v)
 {
 	m_baudrate = v;
-	p_validbits |= ((uint8_t)1U << 1);
+	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5428,7 +5422,7 @@ inline bool UartSettings::config_ref_tick() const
 
 inline bool UartSettings::has_config() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 2));
+	return 0 != (p_validbits & ((uint8_t)1U << 1));
 }
 
 /*!
@@ -5437,14 +5431,14 @@ inline bool UartSettings::has_config() const
  */
 inline void UartSettings::clear_config()
 {
-	p_validbits &= ~((uint8_t)1U << 2);
+	p_validbits &= ~((uint8_t)1U << 1);
 	m_config = 5;
 }
 
 inline uartcfg_t *UartSettings::mutable_config()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
-		p_validbits |= ((uint8_t)1U << 2);
+	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
+		p_validbits |= ((uint8_t)1U << 1);
 		m_config = 5;
 	}
 	return &m_config;
@@ -5454,48 +5448,48 @@ inline void UartSettings::set_config_wl(uart_wl_t v)
 {
 	m_config &= ~(0x3ULL << 0);
 	m_config |= ((uint16_t) v << 0);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_sb(uart_sb_t v)
 {
 	m_config &= ~(0x3ULL << 2);
 	m_config |= ((uint16_t) v << 2);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_rts(bool v)
 {
 	m_config &= ~(0x1ULL << 4);
 	m_config |= ((uint16_t) v << 4);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_cts(bool v)
 {
 	m_config &= ~(0x1ULL << 5);
 	m_config |= ((uint16_t) v << 5);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_p(uart_p_t v)
 {
 	m_config &= ~(0x3ULL << 6);
 	m_config |= ((uint16_t) v << 6);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_ref_tick(bool v)
 {
 	m_config &= ~(0x1ULL << 10);
 	m_config |= ((uint16_t) v << 10);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config(uartcfg_t v)
 {
 	m_config = v;
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 
@@ -5538,7 +5532,7 @@ inline uint32_t UartSettings::tx_bufsize() const
 
 inline bool UartSettings::has_tx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 3));
+	return 0 != (p_validbits & ((uint8_t)1U << 2));
 }
 
 /*!
@@ -5547,14 +5541,14 @@ inline bool UartSettings::has_tx_bufsize() const
  */
 inline void UartSettings::clear_tx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 3);
+	p_validbits &= ~((uint8_t)1U << 2);
 	m_tx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_tx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
-		p_validbits |= ((uint8_t)1U << 3);
+	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
+		p_validbits |= ((uint8_t)1U << 2);
 		m_tx_bufsize = 0;
 	}
 	return &m_tx_bufsize;
@@ -5563,7 +5557,7 @@ inline uint32_t *UartSettings::mutable_tx_bufsize()
 inline void UartSettings::set_tx_bufsize(uint32_t v)
 {
 	m_tx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 3);
+	p_validbits |= ((uint8_t)1U << 2);
 }
 
 
@@ -5575,7 +5569,7 @@ inline uint32_t UartSettings::rx_bufsize() const
 
 inline bool UartSettings::has_rx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 4));
+	return 0 != (p_validbits & ((uint8_t)1U << 3));
 }
 
 /*!
@@ -5584,14 +5578,14 @@ inline bool UartSettings::has_rx_bufsize() const
  */
 inline void UartSettings::clear_rx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 4);
+	p_validbits &= ~((uint8_t)1U << 3);
 	m_rx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_rx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 4))) {
-		p_validbits |= ((uint8_t)1U << 4);
+	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
+		p_validbits |= ((uint8_t)1U << 3);
 		m_rx_bufsize = 0;
 	}
 	return &m_rx_bufsize;
@@ -5600,7 +5594,7 @@ inline uint32_t *UartSettings::mutable_rx_bufsize()
 inline void UartSettings::set_rx_bufsize(uint32_t v)
 {
 	m_rx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 4);
+	p_validbits |= ((uint8_t)1U << 3);
 }
 
 
diff --git a/components/wfc/swcfg_esp8266.cpp b/components/wfc/swcfg_esp8266.cpp
index c64c992..16ae018 100644
--- a/components/wfc/swcfg_esp8266.cpp
+++ b/components/wfc/swcfg_esp8266.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2094,8 +2094,8 @@ UartSettings::UartSettings()
 
 void UartSettings::clear()
 {
-	m_port = 0;
-	m_baudrate = 0;
+	m_port = -1;
+	m_baudrate = 115200;
 	m_config = 5;
 	m_rx_thresh = 0;
 	m_tx_bufsize = 0;
@@ -2107,7 +2107,7 @@ void UartSettings::toASCII(stream &o, size_t indent) const
 {
 	o << "UartSettings {";
 	++indent;
-	ascii_numeric(o, indent, "port", (unsigned) m_port);
+	ascii_numeric(o, indent, "port", (signed) m_port);
 	ascii_numeric(o, indent, "baudrate", m_baudrate);
 	ascii_numeric(o, indent, "config", m_config);
 	++indent;
@@ -2153,8 +2153,8 @@ ssize_t UartSettings::fromMemory(const void *b, ssize_t s)
 			return -79;
 		a += x;
 		switch (fid) {
-		case 0x8:	// port id 1, type uint8_t, coding varint
-			set_port((uint8_t)ud.u32);
+		case 0x8:	// port id 1, type int8_t, coding signed varint
+			set_port(varint_sint(ud.u8));
 			break;
 		case 0x10:	// baudrate id 2, type uint32_t, coding varint
 			set_baudrate((uint32_t)ud.u32);
@@ -2192,18 +2192,18 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 	uint8_t *a = b, *e = b + s;
 	signed n;
 	// has port?
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		if (a >= e)
 			return -82;
 		*a++ = 0x8;
-		n = write_varint(a,e-a,m_port);
+		n = write_varint(a,e-a,sint_varint(m_port));
 		if (n <= 0)
 			return -83;
 		a += n;
 	}
 	// has baudrate?
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		if (a >= e)
 			return -84;
@@ -2214,7 +2214,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has config?
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		if (a >= e)
 			return -86;
@@ -2231,7 +2231,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		*a++ = m_rx_thresh;
 	}
 	// has tx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		if (a >= e)
 			return -88;
@@ -2242,7 +2242,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has rx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		if (a >= e)
 			return -90;
@@ -2262,7 +2262,7 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 	++indLvl;
 	if (has_port()) {
 		fsep = json_indent(json,indLvl,fsep,"port");
-		to_decstr(json,(unsigned) m_port);
+		to_decstr(json,(int) m_port);
 	}
 	if (has_baudrate()) {
 		fsep = json_indent(json,indLvl,fsep,"baudrate");
@@ -2297,9 +2297,9 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 size_t UartSettings::calcSize() const
 {
 	size_t r = 0;	// required size, default is fixed length
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	if (has_port()) {
-		r += wiresize((varint_t)m_port) + 1 /* tag(port) 0x8 */;
+		r += wiresize_s((varint_t)m_port) + 1 /* tag(port) 0x8 */;
 	}
 	// optional unsigned baudrate, id 2
 	if (has_baudrate()) {
@@ -2358,9 +2358,7 @@ int UartSettings::setByName(const char *name, const char *value)
 			clear_port();
 			return 0;
 		}
-		int r = parse_ascii_u8(&m_port,value);
-		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 0);
+		int r = parse_ascii_s8(&m_port,value);
 		return r;
 	}
 	if (0 == strcmp(name,"baudrate")) {
@@ -2370,7 +2368,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_baudrate,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 1);
+			p_validbits |= ((uint8_t)1U << 0);
 		return r;
 	}
 	if ((0 == memcmp(name,"config",6)) && ((name[6] == 0) || name[6] == '.')) {
@@ -2451,7 +2449,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_tx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 3);
+			p_validbits |= ((uint8_t)1U << 2);
 		return r;
 	}
 	if (0 == strcmp(name,"rx_bufsize")) {
@@ -2461,7 +2459,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_rx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 4);
+			p_validbits |= ((uint8_t)1U << 3);
 		return r;
 	}
 	return -93;
diff --git a/components/wfc/swcfg_esp8266.h b/components/wfc/swcfg_esp8266.h
index fb10026..ae8f5ee 100644
--- a/components/wfc/swcfg_esp8266.h
+++ b/components/wfc/swcfg_esp8266.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -1247,7 +1247,7 @@ class UartSettings : public Message
 	//! @return number of bytes parsed from value or negative value if an error occurs
 	int setByName(const char *param, const char *value);
 	
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	/*!
 	* Function for querying if port has been set.
 	* @return true if port is set.
@@ -1256,14 +1256,14 @@ class UartSettings : public Message
 	//! Function to reset port to its default/unset value.
 	void clear_port();
 	//! Get value of port.
-	uint8_t port() const;
+	int8_t port() const;
 	//! Set port using a constant reference
-	void set_port(uint8_t v);
+	void set_port(int8_t v);
 	/*!
 	* Provide mutable access to port.
 	* @return pointer to member variable of port.
 	*/
-	uint8_t *mutable_port();
+	int8_t *mutable_port();
 	
 	// optional unsigned baudrate, id 2
 	/*!
@@ -1382,15 +1382,15 @@ class UartSettings : public Message
 	
 	protected:
 	//! unsigned baudrate, id 2
-	uint32_t m_baudrate = 0;
+	uint32_t m_baudrate = 115200;
 	//! unsigned tx_bufsize, id 6
 	uint32_t m_tx_bufsize = 0;
 	//! unsigned rx_bufsize, id 7
 	uint32_t m_rx_bufsize = 0;
 	//! uartcfg_t config, id 3
 	uartcfg_t m_config = 5;
-	//! uint8 port, id 1
-	uint8_t m_port = 0;
+	//! sint8 port, id 1
+	int8_t m_port = -1;
 	//! fixed8 rx_thresh, id 4
 	uint8_t m_rx_thresh = 0;
 	
@@ -5199,7 +5199,7 @@ inline void Influx::set_database(const estring &v)
 
 inline size_t UartSettings::getMaxSize()
 {
-	// optional uint8 port, id 1 has maximum size 3
+	// optional sint8 port, id 1 has maximum size 3
 	// optional unsigned baudrate, id 2 has maximum size 6
 	// optional uartcfg_t config, id 3 has maximum size 3
 	// optional fixed8 rx_thresh, id 4 has maximum size 2
@@ -5208,14 +5208,14 @@ inline size_t UartSettings::getMaxSize()
 	return 26;
 }
 
-inline uint8_t UartSettings::port() const
+inline int8_t UartSettings::port() const
 {
 	return m_port;
 }
 
 inline bool UartSettings::has_port() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 0));
+	return m_port != -1;
 }
 
 /*!
@@ -5224,23 +5224,17 @@ inline bool UartSettings::has_port() const
  */
 inline void UartSettings::clear_port()
 {
-	p_validbits &= ~((uint8_t)1U << 0);
-	m_port = 0;
+	m_port = -1;
 }
 
-inline uint8_t *UartSettings::mutable_port()
+inline int8_t *UartSettings::mutable_port()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
-		p_validbits |= ((uint8_t)1U << 0);
-		m_port = 0;
-	}
 	return &m_port;
 }
 
-inline void UartSettings::set_port(uint8_t v)
+inline void UartSettings::set_port(int8_t v)
 {
 	m_port = v;
-	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5252,7 +5246,7 @@ inline uint32_t UartSettings::baudrate() const
 
 inline bool UartSettings::has_baudrate() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 1));
+	return 0 != (p_validbits & ((uint8_t)1U << 0));
 }
 
 /*!
@@ -5261,15 +5255,15 @@ inline bool UartSettings::has_baudrate() const
  */
 inline void UartSettings::clear_baudrate()
 {
-	p_validbits &= ~((uint8_t)1U << 1);
-	m_baudrate = 0;
+	p_validbits &= ~((uint8_t)1U << 0);
+	m_baudrate = 115200;
 }
 
 inline uint32_t *UartSettings::mutable_baudrate()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
-		p_validbits |= ((uint8_t)1U << 1);
-		m_baudrate = 0;
+	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
+		p_validbits |= ((uint8_t)1U << 0);
+		m_baudrate = 115200;
 	}
 	return &m_baudrate;
 }
@@ -5277,7 +5271,7 @@ inline uint32_t *UartSettings::mutable_baudrate()
 inline void UartSettings::set_baudrate(uint32_t v)
 {
 	m_baudrate = v;
-	p_validbits |= ((uint8_t)1U << 1);
+	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5319,7 +5313,7 @@ inline bool UartSettings::config_ref_tick() const
 
 inline bool UartSettings::has_config() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 2));
+	return 0 != (p_validbits & ((uint8_t)1U << 1));
 }
 
 /*!
@@ -5328,14 +5322,14 @@ inline bool UartSettings::has_config() const
  */
 inline void UartSettings::clear_config()
 {
-	p_validbits &= ~((uint8_t)1U << 2);
+	p_validbits &= ~((uint8_t)1U << 1);
 	m_config = 5;
 }
 
 inline uartcfg_t *UartSettings::mutable_config()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
-		p_validbits |= ((uint8_t)1U << 2);
+	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
+		p_validbits |= ((uint8_t)1U << 1);
 		m_config = 5;
 	}
 	return &m_config;
@@ -5345,48 +5339,48 @@ inline void UartSettings::set_config_wl(uart_wl_t v)
 {
 	m_config &= ~(0x3ULL << 0);
 	m_config |= ((uint16_t) v << 0);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_sb(uart_sb_t v)
 {
 	m_config &= ~(0x3ULL << 2);
 	m_config |= ((uint16_t) v << 2);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_rts(bool v)
 {
 	m_config &= ~(0x1ULL << 4);
 	m_config |= ((uint16_t) v << 4);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_cts(bool v)
 {
 	m_config &= ~(0x1ULL << 5);
 	m_config |= ((uint16_t) v << 5);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_p(uart_p_t v)
 {
 	m_config &= ~(0x3ULL << 6);
 	m_config |= ((uint16_t) v << 6);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_ref_tick(bool v)
 {
 	m_config &= ~(0x1ULL << 10);
 	m_config |= ((uint16_t) v << 10);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config(uartcfg_t v)
 {
 	m_config = v;
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 
@@ -5429,7 +5423,7 @@ inline uint32_t UartSettings::tx_bufsize() const
 
 inline bool UartSettings::has_tx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 3));
+	return 0 != (p_validbits & ((uint8_t)1U << 2));
 }
 
 /*!
@@ -5438,14 +5432,14 @@ inline bool UartSettings::has_tx_bufsize() const
  */
 inline void UartSettings::clear_tx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 3);
+	p_validbits &= ~((uint8_t)1U << 2);
 	m_tx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_tx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
-		p_validbits |= ((uint8_t)1U << 3);
+	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
+		p_validbits |= ((uint8_t)1U << 2);
 		m_tx_bufsize = 0;
 	}
 	return &m_tx_bufsize;
@@ -5454,7 +5448,7 @@ inline uint32_t *UartSettings::mutable_tx_bufsize()
 inline void UartSettings::set_tx_bufsize(uint32_t v)
 {
 	m_tx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 3);
+	p_validbits |= ((uint8_t)1U << 2);
 }
 
 
@@ -5466,7 +5460,7 @@ inline uint32_t UartSettings::rx_bufsize() const
 
 inline bool UartSettings::has_rx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 4));
+	return 0 != (p_validbits & ((uint8_t)1U << 3));
 }
 
 /*!
@@ -5475,14 +5469,14 @@ inline bool UartSettings::has_rx_bufsize() const
  */
 inline void UartSettings::clear_rx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 4);
+	p_validbits &= ~((uint8_t)1U << 3);
 	m_rx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_rx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 4))) {
-		p_validbits |= ((uint8_t)1U << 4);
+	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
+		p_validbits |= ((uint8_t)1U << 3);
 		m_rx_bufsize = 0;
 	}
 	return &m_rx_bufsize;
@@ -5491,7 +5485,7 @@ inline uint32_t *UartSettings::mutable_rx_bufsize()
 inline void UartSettings::set_rx_bufsize(uint32_t v)
 {
 	m_rx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 4);
+	p_validbits |= ((uint8_t)1U << 3);
 }
 
 
diff --git a/components/wfc/swcfg_esp8285.cpp b/components/wfc/swcfg_esp8285.cpp
index 7789a2a..bf78dff 100644
--- a/components/wfc/swcfg_esp8285.cpp
+++ b/components/wfc/swcfg_esp8285.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2059,8 +2059,8 @@ UartSettings::UartSettings()
 
 void UartSettings::clear()
 {
-	m_port = 0;
-	m_baudrate = 0;
+	m_port = -1;
+	m_baudrate = 115200;
 	m_config = 5;
 	m_rx_thresh = 0;
 	m_tx_bufsize = 0;
@@ -2072,7 +2072,7 @@ void UartSettings::toASCII(stream &o, size_t indent) const
 {
 	o << "UartSettings {";
 	++indent;
-	ascii_numeric(o, indent, "port", (unsigned) m_port);
+	ascii_numeric(o, indent, "port", (signed) m_port);
 	ascii_numeric(o, indent, "baudrate", m_baudrate);
 	ascii_numeric(o, indent, "config", m_config);
 	++indent;
@@ -2118,8 +2118,8 @@ ssize_t UartSettings::fromMemory(const void *b, ssize_t s)
 			return -77;
 		a += x;
 		switch (fid) {
-		case 0x8:	// port id 1, type uint8_t, coding varint
-			set_port((uint8_t)ud.u32);
+		case 0x8:	// port id 1, type int8_t, coding signed varint
+			set_port(varint_sint(ud.u8));
 			break;
 		case 0x10:	// baudrate id 2, type uint32_t, coding varint
 			set_baudrate((uint32_t)ud.u32);
@@ -2157,18 +2157,18 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 	uint8_t *a = b, *e = b + s;
 	signed n;
 	// has port?
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		if (a >= e)
 			return -80;
 		*a++ = 0x8;
-		n = write_varint(a,e-a,m_port);
+		n = write_varint(a,e-a,sint_varint(m_port));
 		if (n <= 0)
 			return -81;
 		a += n;
 	}
 	// has baudrate?
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		if (a >= e)
 			return -82;
@@ -2179,7 +2179,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has config?
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		if (a >= e)
 			return -84;
@@ -2196,7 +2196,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		*a++ = m_rx_thresh;
 	}
 	// has tx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		if (a >= e)
 			return -86;
@@ -2207,7 +2207,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has rx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		if (a >= e)
 			return -88;
@@ -2227,7 +2227,7 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 	++indLvl;
 	if (has_port()) {
 		fsep = json_indent(json,indLvl,fsep,"port");
-		to_decstr(json,(unsigned) m_port);
+		to_decstr(json,(int) m_port);
 	}
 	if (has_baudrate()) {
 		fsep = json_indent(json,indLvl,fsep,"baudrate");
@@ -2262,9 +2262,9 @@ void UartSettings::toJSON(stream &json, unsigned indLvl) const
 size_t UartSettings::calcSize() const
 {
 	size_t r = 0;	// required size, default is fixed length
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	if (has_port()) {
-		r += wiresize((varint_t)m_port) + 1 /* tag(port) 0x8 */;
+		r += wiresize_s((varint_t)m_port) + 1 /* tag(port) 0x8 */;
 	}
 	// optional unsigned baudrate, id 2
 	if (has_baudrate()) {
@@ -2323,9 +2323,7 @@ int UartSettings::setByName(const char *name, const char *value)
 			clear_port();
 			return 0;
 		}
-		int r = parse_ascii_u8(&m_port,value);
-		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 0);
+		int r = parse_ascii_s8(&m_port,value);
 		return r;
 	}
 	if (0 == strcmp(name,"baudrate")) {
@@ -2335,7 +2333,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_baudrate,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 1);
+			p_validbits |= ((uint8_t)1U << 0);
 		return r;
 	}
 	if ((0 == memcmp(name,"config",6)) && ((name[6] == 0) || name[6] == '.')) {
@@ -2416,7 +2414,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_tx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 3);
+			p_validbits |= ((uint8_t)1U << 2);
 		return r;
 	}
 	if (0 == strcmp(name,"rx_bufsize")) {
@@ -2426,7 +2424,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u32(&m_rx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 4);
+			p_validbits |= ((uint8_t)1U << 3);
 		return r;
 	}
 	return -91;
diff --git a/components/wfc/swcfg_esp8285.h b/components/wfc/swcfg_esp8285.h
index 7716e37..f602572 100644
--- a/components/wfc/swcfg_esp8285.h
+++ b/components/wfc/swcfg_esp8285.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -1226,7 +1226,7 @@ class UartSettings
 	//! @return number of bytes parsed from value or negative value if an error occurs
 	int setByName(const char *param, const char *value);
 	
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	/*!
 	* Function for querying if port has been set.
 	* @return true if port is set.
@@ -1235,14 +1235,14 @@ class UartSettings
 	//! Function to reset port to its default/unset value.
 	void clear_port();
 	//! Get value of port.
-	uint8_t port() const;
+	int8_t port() const;
 	//! Set port using a constant reference
-	void set_port(uint8_t v);
+	void set_port(int8_t v);
 	/*!
 	* Provide mutable access to port.
 	* @return pointer to member variable of port.
 	*/
-	uint8_t *mutable_port();
+	int8_t *mutable_port();
 	
 	// optional unsigned baudrate, id 2
 	/*!
@@ -1361,15 +1361,15 @@ class UartSettings
 	
 	protected:
 	//! unsigned baudrate, id 2
-	uint32_t m_baudrate = 0;
+	uint32_t m_baudrate = 115200;
 	//! unsigned tx_bufsize, id 6
 	uint32_t m_tx_bufsize = 0;
 	//! unsigned rx_bufsize, id 7
 	uint32_t m_rx_bufsize = 0;
 	//! uartcfg_t config, id 3
 	uartcfg_t m_config = 5;
-	//! uint8 port, id 1
-	uint8_t m_port = 0;
+	//! sint8 port, id 1
+	int8_t m_port = -1;
 	//! fixed8 rx_thresh, id 4
 	uint8_t m_rx_thresh = 0;
 	
@@ -5137,7 +5137,7 @@ inline void Influx::set_database(const estring &v)
 
 inline size_t UartSettings::getMaxSize()
 {
-	// optional uint8 port, id 1 has maximum size 3
+	// optional sint8 port, id 1 has maximum size 3
 	// optional unsigned baudrate, id 2 has maximum size 6
 	// optional uartcfg_t config, id 3 has maximum size 3
 	// optional fixed8 rx_thresh, id 4 has maximum size 2
@@ -5146,14 +5146,14 @@ inline size_t UartSettings::getMaxSize()
 	return 26;
 }
 
-inline uint8_t UartSettings::port() const
+inline int8_t UartSettings::port() const
 {
 	return m_port;
 }
 
 inline bool UartSettings::has_port() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 0));
+	return m_port != -1;
 }
 
 /*!
@@ -5162,23 +5162,17 @@ inline bool UartSettings::has_port() const
  */
 inline void UartSettings::clear_port()
 {
-	p_validbits &= ~((uint8_t)1U << 0);
-	m_port = 0;
+	m_port = -1;
 }
 
-inline uint8_t *UartSettings::mutable_port()
+inline int8_t *UartSettings::mutable_port()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
-		p_validbits |= ((uint8_t)1U << 0);
-		m_port = 0;
-	}
 	return &m_port;
 }
 
-inline void UartSettings::set_port(uint8_t v)
+inline void UartSettings::set_port(int8_t v)
 {
 	m_port = v;
-	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5190,7 +5184,7 @@ inline uint32_t UartSettings::baudrate() const
 
 inline bool UartSettings::has_baudrate() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 1));
+	return 0 != (p_validbits & ((uint8_t)1U << 0));
 }
 
 /*!
@@ -5199,15 +5193,15 @@ inline bool UartSettings::has_baudrate() const
  */
 inline void UartSettings::clear_baudrate()
 {
-	p_validbits &= ~((uint8_t)1U << 1);
-	m_baudrate = 0;
+	p_validbits &= ~((uint8_t)1U << 0);
+	m_baudrate = 115200;
 }
 
 inline uint32_t *UartSettings::mutable_baudrate()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
-		p_validbits |= ((uint8_t)1U << 1);
-		m_baudrate = 0;
+	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
+		p_validbits |= ((uint8_t)1U << 0);
+		m_baudrate = 115200;
 	}
 	return &m_baudrate;
 }
@@ -5215,7 +5209,7 @@ inline uint32_t *UartSettings::mutable_baudrate()
 inline void UartSettings::set_baudrate(uint32_t v)
 {
 	m_baudrate = v;
-	p_validbits |= ((uint8_t)1U << 1);
+	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5257,7 +5251,7 @@ inline bool UartSettings::config_ref_tick() const
 
 inline bool UartSettings::has_config() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 2));
+	return 0 != (p_validbits & ((uint8_t)1U << 1));
 }
 
 /*!
@@ -5266,14 +5260,14 @@ inline bool UartSettings::has_config() const
  */
 inline void UartSettings::clear_config()
 {
-	p_validbits &= ~((uint8_t)1U << 2);
+	p_validbits &= ~((uint8_t)1U << 1);
 	m_config = 5;
 }
 
 inline uartcfg_t *UartSettings::mutable_config()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
-		p_validbits |= ((uint8_t)1U << 2);
+	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
+		p_validbits |= ((uint8_t)1U << 1);
 		m_config = 5;
 	}
 	return &m_config;
@@ -5283,48 +5277,48 @@ inline void UartSettings::set_config_wl(uart_wl_t v)
 {
 	m_config &= ~(0x3ULL << 0);
 	m_config |= ((uint16_t) v << 0);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_sb(uart_sb_t v)
 {
 	m_config &= ~(0x3ULL << 2);
 	m_config |= ((uint16_t) v << 2);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_rts(bool v)
 {
 	m_config &= ~(0x1ULL << 4);
 	m_config |= ((uint16_t) v << 4);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_cts(bool v)
 {
 	m_config &= ~(0x1ULL << 5);
 	m_config |= ((uint16_t) v << 5);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_p(uart_p_t v)
 {
 	m_config &= ~(0x3ULL << 6);
 	m_config |= ((uint16_t) v << 6);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_ref_tick(bool v)
 {
 	m_config &= ~(0x1ULL << 10);
 	m_config |= ((uint16_t) v << 10);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config(uartcfg_t v)
 {
 	m_config = v;
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 
@@ -5367,7 +5361,7 @@ inline uint32_t UartSettings::tx_bufsize() const
 
 inline bool UartSettings::has_tx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 3));
+	return 0 != (p_validbits & ((uint8_t)1U << 2));
 }
 
 /*!
@@ -5376,14 +5370,14 @@ inline bool UartSettings::has_tx_bufsize() const
  */
 inline void UartSettings::clear_tx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 3);
+	p_validbits &= ~((uint8_t)1U << 2);
 	m_tx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_tx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
-		p_validbits |= ((uint8_t)1U << 3);
+	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
+		p_validbits |= ((uint8_t)1U << 2);
 		m_tx_bufsize = 0;
 	}
 	return &m_tx_bufsize;
@@ -5392,7 +5386,7 @@ inline uint32_t *UartSettings::mutable_tx_bufsize()
 inline void UartSettings::set_tx_bufsize(uint32_t v)
 {
 	m_tx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 3);
+	p_validbits |= ((uint8_t)1U << 2);
 }
 
 
@@ -5404,7 +5398,7 @@ inline uint32_t UartSettings::rx_bufsize() const
 
 inline bool UartSettings::has_rx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 4));
+	return 0 != (p_validbits & ((uint8_t)1U << 3));
 }
 
 /*!
@@ -5413,14 +5407,14 @@ inline bool UartSettings::has_rx_bufsize() const
  */
 inline void UartSettings::clear_rx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 4);
+	p_validbits &= ~((uint8_t)1U << 3);
 	m_rx_bufsize = 0;
 }
 
 inline uint32_t *UartSettings::mutable_rx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 4))) {
-		p_validbits |= ((uint8_t)1U << 4);
+	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
+		p_validbits |= ((uint8_t)1U << 3);
 		m_rx_bufsize = 0;
 	}
 	return &m_rx_bufsize;
@@ -5429,7 +5423,7 @@ inline uint32_t *UartSettings::mutable_rx_bufsize()
 inline void UartSettings::set_rx_bufsize(uint32_t v)
 {
 	m_rx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 4);
+	p_validbits |= ((uint8_t)1U << 3);
 }
 
 
diff --git a/components/wfc/swcfg_pc.cpp b/components/wfc/swcfg_pc.cpp
index 0780f88..7d7440d 100644
--- a/components/wfc/swcfg_pc.cpp
+++ b/components/wfc/swcfg_pc.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -2389,8 +2389,8 @@ Message *Influx::p_getMember(const char *s, unsigned n, unsigned x)
 
 void UartSettings::clear()
 {
-	m_port = 0;
-	m_baudrate = 0;
+	m_port = -1;
+	m_baudrate = 115200;
 	m_config = 5;
 	m_rx_thresh = 0;
 	m_tx_bufsize = 0;
@@ -2402,7 +2402,7 @@ void UartSettings::toASCII(std::ostream &o, size_t indent) const
 {
 	o << "UartSettings {";
 	++indent;
-	ascii_numeric(o, indent, "port", (unsigned) m_port);
+	ascii_numeric(o, indent, "port", (signed) m_port);
 	ascii_numeric(o, indent, "baudrate", m_baudrate);
 	ascii_numeric(o, indent, "config", m_config);
 	++indent;
@@ -2447,14 +2447,14 @@ ssize_t UartSettings::fromMemory(const void *b, ssize_t s)
 			return -95;
 		a += fn;
 		switch (fid) {
-		case 0x8:	// port id 1, type uint8_t, coding varint
+		case 0x8:	// port id 1, type int8_t, coding signed varint
 			{
 				varint_t v;
 				int n = read_varint(a,e-a,&v);
 				if (n <= 0)
 					return -96;
 				a += n;
-				set_port(v);
+				set_port(varint_sint(v));
 			}
 			break;
 		case 0x10:	// baudrate id 2, type uint64_t, coding varint
@@ -2521,18 +2521,18 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 	uint8_t *a = b, *e = b + s;
 	signed n;
 	// has port?
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		if (a >= e)
 			return -104;
 		*a++ = 0x8;
-		n = write_varint(a,e-a,m_port);
+		n = write_varint(a,e-a,sint_varint(m_port));
 		if (n <= 0)
 			return -105;
 		a += n;
 	}
 	// has baudrate?
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		if (a >= e)
 			return -106;
@@ -2543,7 +2543,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has config?
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		if (a >= e)
 			return -108;
@@ -2560,7 +2560,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		*a++ = m_rx_thresh;
 	}
 	// has tx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		if (a >= e)
 			return -110;
@@ -2571,7 +2571,7 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 		a += n;
 	}
 	// has rx_bufsize?
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		if (a >= e)
 			return -112;
@@ -2587,17 +2587,17 @@ ssize_t UartSettings::toMemory(uint8_t *b, ssize_t s) const
 
 void UartSettings::toWire(void (*put)(uint8_t)) const
 {
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		put(0x8);	// 'port': id=1
-		send_varint(put,m_port);
+		send_varint(put,sint_varint(m_port));
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		put(0x10);	// 'baudrate': id=2
 		send_varint(put,m_baudrate);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		put(0x1c);	// 'config': id=3
 		send_u16(put,m_config);
@@ -2607,12 +2607,12 @@ void UartSettings::toWire(void (*put)(uint8_t)) const
 		put(0x23);	// 'rx_thresh': id=4
 		put(m_rx_thresh);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		put(0x30);	// 'tx_bufsize': id=6
 		send_varint(put,m_tx_bufsize);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		put(0x38);	// 'rx_bufsize': id=7
 		send_varint(put,m_rx_bufsize);
@@ -2621,17 +2621,17 @@ void UartSettings::toWire(void (*put)(uint8_t)) const
 
 void UartSettings::toString(std::string &put) const
 {
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
+	if (m_port != -1) {
 		// 'port': id=1, encoding=varint, tag=0x8
 		put.push_back(0x8);	// 'port': id=1
-		send_varint(put,m_port);
+		send_varint(put,sint_varint(m_port));
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		// 'baudrate': id=2, encoding=varint, tag=0x10
 		put.push_back(0x10);	// 'baudrate': id=2
 		send_varint(put,m_baudrate);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		// 'config': id=3, encoding=16bit, tag=0x1c
 		put.push_back(0x1c);	// 'config': id=3
 		send_u16(put,m_config);
@@ -2641,12 +2641,12 @@ void UartSettings::toString(std::string &put) const
 		put.push_back(0x23);	// 'rx_thresh': id=4
 		put.push_back(m_rx_thresh);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		// 'tx_bufsize': id=6, encoding=varint, tag=0x30
 		put.push_back(0x30);	// 'tx_bufsize': id=6
 		send_varint(put,m_tx_bufsize);
 	}
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		// 'rx_bufsize': id=7, encoding=varint, tag=0x38
 		put.push_back(0x38);	// 'rx_bufsize': id=7
 		send_varint(put,m_rx_bufsize);
@@ -2659,7 +2659,7 @@ void UartSettings::toJSON(std::ostream &json, unsigned indLvl) const
 	++indLvl;
 	if (has_port()) {
 		fsep = json_indent(json,indLvl,fsep,"port");
-		json << (unsigned) m_port;
+		json << (int) m_port;
 	}
 	if (has_baudrate()) {
 		fsep = json_indent(json,indLvl,fsep,"baudrate");
@@ -2694,16 +2694,16 @@ void UartSettings::toJSON(std::ostream &json, unsigned indLvl) const
 size_t UartSettings::calcSize() const
 {
 	size_t r = 0;	// required size, default is fixed length
-	// optional uint8 port, id 1
-	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
-		r += wiresize((varint_t)m_port) + 1 /* tag(port) 0x8 */;
+	// optional sint8 port, id 1
+	if (m_port != -1) {
+		r += wiresize_s((varint_t)m_port) + 1 /* tag(port) 0x8 */;
 	}
 	// optional unsigned baudrate, id 2
-	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 0))) {
 		r += wiresize((varint_t)m_baudrate) + 1 /* tag(baudrate) 0x10 */;
 	}
 	// optional uartcfg_t config, id 3
-	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 1))) {
 		r += wiresize((varint_t)m_config) + 1 /* tag(config) 0x18 */;
 	}
 	// optional fixed8 rx_thresh, id 4
@@ -2711,11 +2711,11 @@ size_t UartSettings::calcSize() const
 		r += 2;
 	}
 	// optional unsigned tx_bufsize, id 6
-	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 2))) {
 		r += wiresize((varint_t)m_tx_bufsize) + 1 /* tag(tx_bufsize) 0x30 */;
 	}
 	// optional unsigned rx_bufsize, id 7
-	if (0 != (p_validbits & ((uint8_t)1U << 4))) {
+	if (0 != (p_validbits & ((uint8_t)1U << 3))) {
 		r += wiresize((varint_t)m_rx_bufsize) + 1 /* tag(rx_bufsize) 0x38 */;
 	}
 	return r;
@@ -2761,9 +2761,7 @@ int UartSettings::setByName(const char *name, const char *value)
 			clear_port();
 			return 0;
 		}
-		int r = parse_ascii_u8(&m_port,value);
-		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 0);
+		int r = parse_ascii_s8(&m_port,value);
 		return r;
 	}
 	if (0 == strcmp(name,"baudrate")) {
@@ -2773,7 +2771,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u64(&m_baudrate,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 1);
+			p_validbits |= ((uint8_t)1U << 0);
 		return r;
 	}
 	if ((0 == memcmp(name,"config",6)) && ((name[6] == 0) || name[6] == '.')) {
@@ -2815,7 +2813,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u64(&m_tx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 3);
+			p_validbits |= ((uint8_t)1U << 2);
 		return r;
 	}
 	if (0 == strcmp(name,"rx_bufsize")) {
@@ -2825,7 +2823,7 @@ int UartSettings::setByName(const char *name, const char *value)
 		}
 		int r = parse_ascii_u64(&m_rx_bufsize,value);
 		if (r > 0)
-			p_validbits |= ((uint8_t)1U << 4);
+			p_validbits |= ((uint8_t)1U << 3);
 		return r;
 	}
 	return -115;
diff --git a/components/wfc/swcfg_pc.h b/components/wfc/swcfg_pc.h
index e42c465..fa38bdc 100644
--- a/components/wfc/swcfg_pc.h
+++ b/components/wfc/swcfg_pc.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -1335,7 +1335,7 @@ class UartSettings : public Message
 	//! @return number of bytes parsed from value or negative value if an error occurs
 	int setByName(const char *param, const char *value);
 	
-	// optional uint8 port, id 1
+	// optional sint8 port, id 1
 	/*!
 	* Function for querying if port has been set.
 	* @return true if port is set.
@@ -1344,14 +1344,14 @@ class UartSettings : public Message
 	//! Function to reset port to its default/unset value.
 	void clear_port();
 	//! Get value of port.
-	uint8_t port() const;
+	int8_t port() const;
 	//! Set port using a constant reference
-	void set_port(uint8_t v);
+	void set_port(int8_t v);
 	/*!
 	* Provide mutable access to port.
 	* @return pointer to member variable of port.
 	*/
-	uint8_t *mutable_port();
+	int8_t *mutable_port();
 	
 	// optional unsigned baudrate, id 2
 	/*!
@@ -1472,15 +1472,15 @@ class UartSettings : public Message
 	Message *p_getMember(const char *s, unsigned n);
 	Message *p_getMember(const char *s, unsigned n, unsigned i);
 	//! unsigned baudrate, id 2
-	uint64_t m_baudrate = 0;
+	uint64_t m_baudrate = 115200;
 	//! unsigned tx_bufsize, id 6
 	uint64_t m_tx_bufsize = 0;
 	//! unsigned rx_bufsize, id 7
 	uint64_t m_rx_bufsize = 0;
 	//! uartcfg_t config, id 3
 	uartcfg_t m_config = 5;
-	//! uint8 port, id 1
-	uint8_t m_port = 0;
+	//! sint8 port, id 1
+	int8_t m_port = -1;
 	//! fixed8 rx_thresh, id 4
 	uint8_t m_rx_thresh = 0;
 	
@@ -5480,7 +5480,7 @@ inline void Influx::set_database(const std::string &v)
 
 inline size_t UartSettings::getMaxSize()
 {
-	// optional uint8 port, id 1 has maximum size 3
+	// optional sint8 port, id 1 has maximum size 3
 	// optional unsigned baudrate, id 2 has maximum size 11
 	// optional uartcfg_t config, id 3 has maximum size 3
 	// optional fixed8 rx_thresh, id 4 has maximum size 2
@@ -5489,14 +5489,14 @@ inline size_t UartSettings::getMaxSize()
 	return 41;
 }
 
-inline uint8_t UartSettings::port() const
+inline int8_t UartSettings::port() const
 {
 	return m_port;
 }
 
 inline bool UartSettings::has_port() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 0));
+	return m_port != -1;
 }
 
 /*!
@@ -5505,23 +5505,17 @@ inline bool UartSettings::has_port() const
  */
 inline void UartSettings::clear_port()
 {
-	p_validbits &= ~((uint8_t)1U << 0);
-	m_port = 0;
+	m_port = -1;
 }
 
-inline uint8_t *UartSettings::mutable_port()
+inline int8_t *UartSettings::mutable_port()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
-		p_validbits |= ((uint8_t)1U << 0);
-		m_port = 0;
-	}
 	return &m_port;
 }
 
-inline void UartSettings::set_port(uint8_t v)
+inline void UartSettings::set_port(int8_t v)
 {
 	m_port = v;
-	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5533,7 +5527,7 @@ inline uint64_t UartSettings::baudrate() const
 
 inline bool UartSettings::has_baudrate() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 1));
+	return 0 != (p_validbits & ((uint8_t)1U << 0));
 }
 
 /*!
@@ -5542,15 +5536,15 @@ inline bool UartSettings::has_baudrate() const
  */
 inline void UartSettings::clear_baudrate()
 {
-	p_validbits &= ~((uint8_t)1U << 1);
-	m_baudrate = 0;
+	p_validbits &= ~((uint8_t)1U << 0);
+	m_baudrate = 115200;
 }
 
 inline uint64_t *UartSettings::mutable_baudrate()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
-		p_validbits |= ((uint8_t)1U << 1);
-		m_baudrate = 0;
+	if (0 == (p_validbits & ((uint8_t)1U << 0))) {
+		p_validbits |= ((uint8_t)1U << 0);
+		m_baudrate = 115200;
 	}
 	return &m_baudrate;
 }
@@ -5558,7 +5552,7 @@ inline uint64_t *UartSettings::mutable_baudrate()
 inline void UartSettings::set_baudrate(uint64_t v)
 {
 	m_baudrate = v;
-	p_validbits |= ((uint8_t)1U << 1);
+	p_validbits |= ((uint8_t)1U << 0);
 }
 
 
@@ -5600,7 +5594,7 @@ inline bool UartSettings::config_ref_tick() const
 
 inline bool UartSettings::has_config() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 2));
+	return 0 != (p_validbits & ((uint8_t)1U << 1));
 }
 
 /*!
@@ -5609,14 +5603,14 @@ inline bool UartSettings::has_config() const
  */
 inline void UartSettings::clear_config()
 {
-	p_validbits &= ~((uint8_t)1U << 2);
+	p_validbits &= ~((uint8_t)1U << 1);
 	m_config = 5;
 }
 
 inline uartcfg_t *UartSettings::mutable_config()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
-		p_validbits |= ((uint8_t)1U << 2);
+	if (0 == (p_validbits & ((uint8_t)1U << 1))) {
+		p_validbits |= ((uint8_t)1U << 1);
 		m_config = 5;
 	}
 	return &m_config;
@@ -5626,48 +5620,48 @@ inline void UartSettings::set_config_wl(uart_wl_t v)
 {
 	m_config &= ~(0x3ULL << 0);
 	m_config |= ((uint16_t) v << 0);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_sb(uart_sb_t v)
 {
 	m_config &= ~(0x3ULL << 2);
 	m_config |= ((uint16_t) v << 2);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_rts(bool v)
 {
 	m_config &= ~(0x1ULL << 4);
 	m_config |= ((uint16_t) v << 4);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_cts(bool v)
 {
 	m_config &= ~(0x1ULL << 5);
 	m_config |= ((uint16_t) v << 5);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_p(uart_p_t v)
 {
 	m_config &= ~(0x3ULL << 6);
 	m_config |= ((uint16_t) v << 6);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config_ref_tick(bool v)
 {
 	m_config &= ~(0x1ULL << 10);
 	m_config |= ((uint16_t) v << 10);
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 inline void UartSettings::set_config(uartcfg_t v)
 {
 	m_config = v;
-	p_validbits |= ((uint8_t)1U << 2);
+	p_validbits |= ((uint8_t)1U << 1);
 }
 
 
@@ -5710,7 +5704,7 @@ inline uint64_t UartSettings::tx_bufsize() const
 
 inline bool UartSettings::has_tx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 3));
+	return 0 != (p_validbits & ((uint8_t)1U << 2));
 }
 
 /*!
@@ -5719,14 +5713,14 @@ inline bool UartSettings::has_tx_bufsize() const
  */
 inline void UartSettings::clear_tx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 3);
+	p_validbits &= ~((uint8_t)1U << 2);
 	m_tx_bufsize = 0;
 }
 
 inline uint64_t *UartSettings::mutable_tx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
-		p_validbits |= ((uint8_t)1U << 3);
+	if (0 == (p_validbits & ((uint8_t)1U << 2))) {
+		p_validbits |= ((uint8_t)1U << 2);
 		m_tx_bufsize = 0;
 	}
 	return &m_tx_bufsize;
@@ -5735,7 +5729,7 @@ inline uint64_t *UartSettings::mutable_tx_bufsize()
 inline void UartSettings::set_tx_bufsize(uint64_t v)
 {
 	m_tx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 3);
+	p_validbits |= ((uint8_t)1U << 2);
 }
 
 
@@ -5747,7 +5741,7 @@ inline uint64_t UartSettings::rx_bufsize() const
 
 inline bool UartSettings::has_rx_bufsize() const
 {
-	return 0 != (p_validbits & ((uint8_t)1U << 4));
+	return 0 != (p_validbits & ((uint8_t)1U << 3));
 }
 
 /*!
@@ -5756,14 +5750,14 @@ inline bool UartSettings::has_rx_bufsize() const
  */
 inline void UartSettings::clear_rx_bufsize()
 {
-	p_validbits &= ~((uint8_t)1U << 4);
+	p_validbits &= ~((uint8_t)1U << 3);
 	m_rx_bufsize = 0;
 }
 
 inline uint64_t *UartSettings::mutable_rx_bufsize()
 {
-	if (0 == (p_validbits & ((uint8_t)1U << 4))) {
-		p_validbits |= ((uint8_t)1U << 4);
+	if (0 == (p_validbits & ((uint8_t)1U << 3))) {
+		p_validbits |= ((uint8_t)1U << 3);
 		m_rx_bufsize = 0;
 	}
 	return &m_rx_bufsize;
@@ -5772,7 +5766,7 @@ inline uint64_t *UartSettings::mutable_rx_bufsize()
 inline void UartSettings::set_rx_bufsize(uint64_t v)
 {
 	m_rx_bufsize = v;
-	p_validbits |= ((uint8_t)1U << 4);
+	p_validbits |= ((uint8_t)1U << 3);
 }
 
 
diff --git a/components/wfc/wfccore_esp32.cpp b/components/wfc/wfccore_esp32.cpp
index 4078ebb..c04d6f1 100644
--- a/components/wfc/wfccore_esp32.cpp
+++ b/components/wfc/wfccore_esp32.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_esp32.h b/components/wfc/wfccore_esp32.h
index a9e5ee4..4a66d1f 100644
--- a/components/wfc/wfccore_esp32.h
+++ b/components/wfc/wfccore_esp32.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_esp8266.cpp b/components/wfc/wfccore_esp8266.cpp
index 1102862..1085453 100644
--- a/components/wfc/wfccore_esp8266.cpp
+++ b/components/wfc/wfccore_esp8266.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_esp8266.h b/components/wfc/wfccore_esp8266.h
index 302a51c..d3a8f97 100644
--- a/components/wfc/wfccore_esp8266.h
+++ b/components/wfc/wfccore_esp8266.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_esp8285.cpp b/components/wfc/wfccore_esp8285.cpp
index 41188d3..7f2ce1c 100644
--- a/components/wfc/wfccore_esp8285.cpp
+++ b/components/wfc/wfccore_esp8285.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_esp8285.h b/components/wfc/wfccore_esp8285.h
index 098791d..07d5c3c 100644
--- a/components/wfc/wfccore_esp8285.h
+++ b/components/wfc/wfccore_esp8285.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_pc.cpp b/components/wfc/wfccore_pc.cpp
index 59ca23e..855d43a 100644
--- a/components/wfc/wfccore_pc.cpp
+++ b/components/wfc/wfccore_pc.cpp
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/components/wfc/wfccore_pc.h b/components/wfc/wfccore_pc.h
index 57529f6..ce30c37 100644
--- a/components/wfc/wfccore_pc.h
+++ b/components/wfc/wfccore_pc.h
@@ -10,7 +10,7 @@
  * Copyright: 2018-2023
  * Author   : Thomas Maier-Komor
  * 
- * Code generated on 2023-07-01, 22:37:39 (CET).
+ * Code generated on 2023-07-31, 21:35:41 (CET).
  * 
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/drv/dht/dhtdrv.cpp b/drv/dht/dhtdrv.cpp
index f678ac6..9743d28 100644
--- a/drv/dht/dhtdrv.cpp
+++ b/drv/dht/dhtdrv.cpp
@@ -34,12 +34,11 @@
 #include <rom/gpio.h>
 #include <esp8266/timer_register.h>
 #include <rom/ets_sys.h>
-#elif defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined ESP32
 #if IDF_VERSION >= 40
-#include <esp32/rom/ets_sys.h>
+//#include <esp32/rom/ets_sys.h>
 #include <esp32/rom/gpio.h>
 #else
-//| defined CONFIG_IDF_TARGET_ESP32S3 |
 #include <rom/ets_sys.h>
 #endif
 #endif
@@ -53,7 +52,7 @@
 #define ets_delay_us esp_rom_delay_us
 #endif
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#if defined ESP32
 #define ENTER_CRITICAL() portDISABLE_INTERRUPTS()
 #define EXIT_CRITICAL() portENABLE_INTERRUPTS()
 #elif defined CONFIG_IDF_TARGET_ESP8266
@@ -62,7 +61,7 @@
 #endif
 
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#ifdef ESP32
 #define gettime() esp_timer_get_time()
 #elif defined ESP8266
 static inline uint64_t gettime()
diff --git a/drv/display/CMakeLists.txt b/drv/display/CMakeLists.txt
index 625c77e..8ae3170 100644
--- a/drv/display/CMakeLists.txt
+++ b/drv/display/CMakeLists.txt
@@ -1,5 +1,5 @@
 idf_component_register(
-	SRCS display.cpp hd44780u.cpp ledcluster.cpp ssd130x.cpp fonts_generic.c fonts_ssd1306.c font6x8_ssd130x.c
+	SRCS display.cpp hd44780u.cpp ledcluster.cpp ssd130x.cpp fonts_row_major.c fonts_byte_column_major.c font6x8_ssd130x.c glyphs.c
 	INCLUDE_DIRS .
 	REQUIRES i2c logging
 )
diff --git a/drv/display/display.cpp b/drv/display/display.cpp
index 61f2cf7..8275cbc 100644
--- a/drv/display/display.cpp
+++ b/drv/display/display.cpp
@@ -435,8 +435,7 @@ void SegmentDisplay::write(const char *s, int n)
 
 uint16_t MatrixDisplay::fontHeight() const
 {
-	const Font *font = Fonts+(int)m_font;
-	return font->yAdvance;
+	return m_font->yAdvance;
 }
 
 
@@ -527,11 +526,15 @@ uint16_t MatrixDisplay::charWidth(char c) const
 	c = charToGlyph(c);
 	if (c == 0)
 		return 0;
+	/*
 	const Font *font = Fonts+(int)m_font;
 	if ((c < font->first) || (c > font->last))
 		return 0;
-	uint8_t ch = c - font->first;
-	return font->glyph[ch].xAdvance;
+	*/
+	uint8_t ch = c - m_font->first;
+	if (m_font->glyph == 0)
+		return 6;
+	return m_font->glyph[ch].xAdvance;
 }
 
 
@@ -548,25 +551,24 @@ unsigned MatrixDisplay::drawChar(uint16_t x, uint16_t y, char c, int32_t fg, int
 {
 	PROFILE_FUNCTION();
 	c = charToGlyph(c);
-	const Font *font = Fonts+(int)m_font;
-	if ((c < font->first) || (c > font->last))
+	if ((c < m_font->first) || (c > m_font->last))
 		return 0;
 	if (fg == -1)
 		fg = m_colfg;
 	if (bg == -1)
 		bg = m_colbg;
-	uint8_t ch = c - font->first;
-	const uint8_t *data = font->bitmap + font->glyph[ch].bitmapOffset;
-	uint8_t w = font->glyph[ch].width;
-	uint8_t h = font->glyph[ch].height;
-	int8_t dx = font->glyph[ch].xOffset;
-	int8_t dy = font->glyph[ch].yOffset;
-	uint8_t a = font->glyph[ch].xAdvance;
+	uint8_t ch = c - m_font->first;
+	const uint8_t *data = m_font->bitmap + m_font->glyph[ch].bitmapOffset;
+	uint8_t w = m_font->glyph[ch].width;
+	uint8_t h = m_font->glyph[ch].height;
+	int8_t dx = m_font->glyph[ch].xOffset;
+	int8_t dy = m_font->glyph[ch].yOffset;
+	uint8_t a = m_font->glyph[ch].xAdvance;
 	log_dbug(TAG,"drawChar(%d,%d,'%c') = %u",x,y,c,a);
 //	log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l);
 	if (bg != -1)
 		fillRect(x,y,dx,a,bg);
-	drawBitmap(x+dx,y+dy+font->yAdvance-1,w,h,data,fg,bg);
+	drawBitmap(x+dx,y+dy+m_font->yAdvance-1,w,h,data,fg,bg);
 	return a;
 }
 
@@ -576,7 +578,6 @@ unsigned MatrixDisplay::drawText(uint16_t x, uint16_t y, const char *txt, int n,
 	log_dbug(TAG,"drawText(%d,%d,'%s')",x,y,txt);
 	if (n < 0)
 		n = strlen(txt);
-	const Font *font = Fonts+(int)m_font;
 	uint16_t a = 0, amax = 0;
 	const char *e = txt + n;
 	while (txt != e) {
@@ -585,8 +586,8 @@ unsigned MatrixDisplay::drawText(uint16_t x, uint16_t y, const char *txt, int n,
 			break;
 		if (c == '\n') {
 			x = 0;
-			y += font->yAdvance;
-			if (y+font->yAdvance > m_height)
+			y += m_font->yAdvance;
+			if (y+m_font->yAdvance > m_height)
 				break;
 			if (a > amax)
 				amax = a;
@@ -836,8 +837,8 @@ int32_t MatrixDisplay::setBgColor(color_t c)
 
 int MatrixDisplay::setFont(unsigned f)
 {
-	if (f < font_numfonts) {
-		m_font = (fontid_t)f;
+	if (f < NumFontsRM) {
+		m_font = FontsRM+f;
 		return 0;
 	}
 	return -1;
@@ -846,6 +847,7 @@ int MatrixDisplay::setFont(unsigned f)
 
 int MatrixDisplay::setFont(const char *fn)
 {
+	/*
 	if (0 == strcasecmp(fn,"native")) {
 		m_font = (fontid_t)-1;
 		return 0;
@@ -854,9 +856,10 @@ int MatrixDisplay::setFont(const char *fn)
 		m_font = (fontid_t)-2;
 		return 0;
 	}
-	for (int i = 0; i < font_numfonts; ++i) {
-		if (0 == strcasecmp(Fonts[i].name,fn)) {
-			m_font = (fontid_t)i;
+	*/
+	for (int i = 0; i < NumFontsRM; ++i) {
+		if (0 == strcasecmp(FontsRM[i].name,fn)) {
+			m_font = FontsRM+i;
 			return 0;
 		}
 	}
@@ -887,8 +890,7 @@ void MatrixDisplay::write(const char *txt, int n)
 			}
 		}
 		if (c == '\n') {
-			const Font *font = Fonts+(int)m_font;
-			uint16_t fh = font->yAdvance;
+			uint16_t fh = m_font->yAdvance;
 			m_posx = 0;
 			if (m_posy + fh >= m_height) {
 				m_posy = m_height -1;
diff --git a/drv/display/display.h b/drv/display/display.h
index a0e1c0d..a3a9f4d 100644
--- a/drv/display/display.h
+++ b/drv/display/display.h
@@ -20,7 +20,7 @@
 #define DISPLAY_H
 
 #include "ledcluster.h"
-#include "fonts_generic.h"
+#include "fonts.h"
 
 class MatrixDisplay;
 class SegmentDisplay;
@@ -234,7 +234,7 @@ struct MatrixDisplay : public TextDisplay
 	// clip x/y-low/high
 	uint16_t m_clxl = 0, m_clxh = 0xffff, m_clyl = 0, m_clyh = 0xffff;
 #endif
-	fontid_t m_font = font_native;
+	const Font *m_font = 0;
 	colorspace_t m_colorspace;
 	int32_t m_colfg, m_colbg;
 };
diff --git a/drv/display/font.h b/drv/display/font.h
index c7f324b..e002f93 100644
--- a/drv/display/font.h
+++ b/drv/display/font.h
@@ -29,4 +29,22 @@ typedef struct {
   uint8_t yAdvance; ///< Newline distance (y axis)
 } Font;
 
+typedef enum {
+//	font_nativedbl = -2,
+//	font_native = -1,
+	font_mono9 = 0,
+	font_mono12,
+	font_mono18,
+	font_mono24,
+	font_tomthumb,
+	font_sans9,
+	font_sans12,
+	font_sanslight10,
+	font_sanslight12,
+	font_sanslight14,
+	font_sanslight16,
+	font_org01,
+	font_numfonts
+} fontid_t;
+
 #endif // _GFXFONT_H_
diff --git a/drv/display/font6x8_ssd130x.c b/drv/display/font6x8_ssd130x.c
index 7d358ea..5449f78 100644
--- a/drv/display/font6x8_ssd130x.c
+++ b/drv/display/font6x8_ssd130x.c
@@ -1,4 +1,4 @@
-#include "fonts_ssd1306.h"
+#include <stdint.h>
 
 const unsigned char Font6x8[] = {
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ' '
diff --git a/drv/display/fonts.h b/drv/display/fonts.h
new file mode 100644
index 0000000..4903975
--- /dev/null
+++ b/drv/display/fonts.h
@@ -0,0 +1,16 @@
+#ifndef FONTS_H
+#define FONTS_H
+
+#include "font.h"
+
+// row-major definitions (standard layout)
+extern const Font FontsRM[];
+extern uint8_t NumFontsRM;
+extern const uint8_t Font6x8[];
+extern const uint16_t SizeofFont6x8;
+
+// byte-column-major definitions for SSD130x family
+extern const Font FontsBCM[];
+extern uint8_t NumFontsBCM;
+
+#endif
diff --git a/drv/display/fonts_ssd1306.c b/drv/display/fonts_byte_column_major.c
similarity index 99%
rename from drv/display/fonts_ssd1306.c
rename to drv/display/fonts_byte_column_major.c
index 82faf9b..9b5da1f 100644
--- a/drv/display/fonts_ssd1306.c
+++ b/drv/display/fonts_byte_column_major.c
@@ -1,6 +1,8 @@
 #include <stdint.h>
 #include "font.h"
+#include "glyphs.h"
 
+/*
 #include "FreeSans9pt7b.h"
 #include "FreeSans12pt7b.h"
 #include "FreeMono9pt7b.h"
@@ -13,10 +15,11 @@
 #include "opensanslight-12.h"
 #include "opensanslight-14.h"
 #include "opensanslight-16.h"
+*/
 
 
 
-static const uint8_t FreeSans9pt7b_ssd1306[] = {
+static const uint8_t FreeSans9pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -685,7 +688,7 @@ static const uint8_t FreeSans9pt7b_ssd1306[] = {
 //	0xc0,
 };
 
-static const uint8_t FreeSans12pt7b_ssd1306[] = {
+static const uint8_t FreeSans12pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -1546,7 +1549,7 @@ static const uint8_t FreeSans12pt7b_ssd1306[] = {
 //	0x31, 0x8c, 0x63, 0x18,  0xc6, 0x73, 0x00,
 };
 
-static const uint8_t FreeMono9pt7b_ssd1306[] = {
+static const uint8_t FreeMono9pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -2143,7 +2146,7 @@ static const uint8_t FreeMono9pt7b_ssd1306[] = {
 //	0x89, 0x24, 0x8a, 0x49,  0x2c,
 };
 
-static const uint8_t FreeMono12pt7b_ssd1306[] = {
+static const uint8_t FreeMono12pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -2884,7 +2887,7 @@ static const uint8_t FreeMono12pt7b_ssd1306[] = {
 //	0x10, 0x84, 0x26, 0x00,
 };
 
-static const uint8_t FreeMono18pt7b_ssd1306[] = {
+static const uint8_t FreeMono18pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -4011,7 +4014,7 @@ static const uint8_t FreeMono18pt7b_ssd1306[] = {
 //	0xe0,
 };
 
-static const uint8_t FreeMono24pt7b_ssd1306[] = {
+static const uint8_t FreeMono24pt7b_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -5782,7 +5785,7 @@ static const uint8_t FreeMono24pt7b_ssd1306[] = {
 //	0x18, 0x03, 0x00, 0xc0,  0xf8, 0x1c, 0x00,
 };
 
-static const uint8_t TomThumb_ssd1306[] = {
+static const uint8_t TomThumb_BCM[] = {
 
 	// ' ' (0x20) 8x1, offset 0-1, at +0/-5
 	0x00,
@@ -6255,7 +6258,7 @@ static const uint8_t TomThumb_ssd1306[] = {
 //	0xc0, 0x40, 0x20, 0x40,  0xc0,
 };
 
-static const uint8_t Org_01_ssd1306[] = {
+static const uint8_t Org_01_BCM[] = {
 
 	// ' ' (0x20) 0x0, offset 0-0, at +0/+1
 	// in regular row-major format
@@ -6726,7 +6729,7 @@ static const uint8_t Org_01_ssd1306[] = {
 //	0x89, 0xa8,
 };
 
-static const uint8_t OpenSansLight10_ssd1306[] = {
+static const uint8_t OpenSansLight10_BCM[] = {
 
 	// ' ' (0x20) 1x1, offset 0-1, at +0/+0
 	0x00,
@@ -7196,7 +7199,7 @@ static const uint8_t OpenSansLight10_ssd1306[] = {
 //	0xaa, 0xaa, 0x80,
 };
 
-static const uint8_t OpenSansLight12_ssd1306[] = {
+static const uint8_t OpenSansLight12_BCM[] = {
 
 	// ' ' (0x20) 1x1, offset 0-1, at +0/+0
 	0x00,
@@ -7696,7 +7699,7 @@ static const uint8_t OpenSansLight12_ssd1306[] = {
 //	0xaa, 0xaa, 0xaa,
 };
 
-static const uint8_t OpenSansLight14_ssd1306[] = {
+static const uint8_t OpenSansLight14_BCM[] = {
 
 	// ' ' (0x20) 1x1, offset 0-1, at +0/+0
 	0x00,
@@ -8266,7 +8269,7 @@ static const uint8_t OpenSansLight14_ssd1306[] = {
 //	0x92, 0x49, 0x24, 0x92,  0x49, 0x00,
 };
 
-static const uint8_t OpenSansLight16_ssd1306[] = {
+static const uint8_t OpenSansLight16_BCM[] = {
 
 	// ' ' (0x20) 1x1, offset 0-1, at +0/+0
 	0x00,
@@ -8879,79 +8882,80 @@ static const uint8_t OpenSansLight16_ssd1306[] = {
 };
 
 
-const Font Fonts[] =  {
+const Font FontsBCM[] = {
 	{
 		"Mono9",
-		(uint8_t *)FreeMono9pt7b_ssd1306,
+		(uint8_t *)FreeMono9pt7b_BCM,
 		(GFXglyph *)FreeMono9pt7bGlyphs,
 		0x20, 0x7e, 18
 	},
 	{
 		"Mono12",
-		(uint8_t *)FreeMono12pt7b_ssd1306,
+		(uint8_t *)FreeMono12pt7b_BCM,
 		(GFXglyph *)FreeMono12pt7bGlyphs,
 		0x20, 0x7e, 24
 	},
 	{
 		"Mono18",
-		(uint8_t *)FreeMono18pt7b_ssd1306,
+		(uint8_t *)FreeMono18pt7b_BCM,
 		(GFXglyph *)FreeMono18pt7bGlyphs,
 		0x20, 0x7e, 35
 	},
 	{
 		"Mono24",
-		(uint8_t *)FreeMono24pt7b_ssd1306,
+		(uint8_t *)FreeMono24pt7b_BCM,
 		(GFXglyph *)FreeMono24pt7bGlyphs,
 		0x20, 0x7e, 47
 	},
 	{
 		"TomThumb",
-		(uint8_t *)TomThumb_ssd1306,
+		(uint8_t *)TomThumb_BCM,
 		(GFXglyph *)TomThumbGlyphs,
 		0x20, 0x7e, 6
 	},
 	{
 		"Sans9",
-		(uint8_t *)FreeSans9pt7b_ssd1306,
+		(uint8_t *)FreeSans9pt7b_BCM,
 		(GFXglyph *)FreeSans9pt7bGlyphs,
 		0x20, 0x7e, 22
 	},
 	{
 		"Sans12",
-		(uint8_t *)FreeSans12pt7b_ssd1306,
+		(uint8_t *)FreeSans12pt7b_BCM,
 		(GFXglyph *)FreeSans12pt7bGlyphs,
 		0x20, 0x7e, 22
 	},
 	{
 		"SansLight10",
-		(uint8_t *)OpenSansLight10_ssd1306,
+		(uint8_t *)OpenSansLight10_BCM,
 		(GFXglyph *)OpenSansLight10Glyphs,
 		0x20, 0x7d, 14
 	},
 	{
 		"SansLight12",
-		(uint8_t *)OpenSansLight12_ssd1306,
+		(uint8_t *)OpenSansLight12_BCM,
 		(GFXglyph *)OpenSansLight12Glyphs,
 		0x20, 0x7d, 17
 	},
 	{
 		"SansLight14",
-		(uint8_t *)OpenSansLight14_ssd1306,
+		(uint8_t *)OpenSansLight14_BCM,
 		(GFXglyph *)OpenSansLight14Glyphs,
 		0x20, 0x7d, 20
 	},
 	{
 		"SansLight16",
-		(uint8_t *)OpenSansLight16_ssd1306,
+		(uint8_t *)OpenSansLight16_BCM,
 		(GFXglyph *)OpenSansLight16Glyphs,
 		0x20, 0x7d, 23
 	},
 	{
 		"Org01",
-		(uint8_t *)Org_01_ssd1306,
+		(uint8_t *)Org_01_BCM,
 		(GFXglyph *)Org_01Glyphs,
 		0x20, 0x7e, 7
 	},
 };
 
 
+uint8_t NumFontsBCM = sizeof(FontsBCM)/sizeof(FontsBCM[0]);
diff --git a/drv/display/fonts_generic.h b/drv/display/fonts_generic.h
deleted file mode 100644
index 266150e..0000000
--- a/drv/display/fonts_generic.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef FONTS_SSD1306_H
-#define FONTS_SSD1306_H
-
-#include "font.h"
-
-typedef enum {
-	font_nativedbl = -2,
-	font_native = -1,
-	font_mono9 = 0,
-	font_mono12,
-	font_mono18,
-	font_mono24,
-	font_tomthumb,
-	font_sans9,
-	font_sans12,
-	font_sanslight10,
-	font_sanslight12,
-	font_sanslight14,
-	font_sanslight16,
-	font_org01,
-	font_numfonts
-} fontid_t;
-
-extern const Font Fonts[];
-extern const uint8_t Font6x8[];
-extern const uint16_t SizeofFont6x8;
-#endif
diff --git a/drv/display/fonts_generic.c b/drv/display/fonts_row_major.c
similarity index 99%
rename from drv/display/fonts_generic.c
rename to drv/display/fonts_row_major.c
index 95b2b30..13b046c 100644
--- a/drv/display/fonts_generic.c
+++ b/drv/display/fonts_row_major.c
@@ -1,5 +1,8 @@
 #include <stdint.h>
 #include "font.h"
+#include "glyphs.h"
+
+/*
 #include "FreeSans9pt7b.h"
 #include "FreeSans12pt7b.h"
 #include "FreeMono9pt7b.h"
@@ -12,6 +15,7 @@
 #include "opensanslight-12.h"
 #include "opensanslight-14.h"
 #include "opensanslight-16.h"
+*/
 
 
 static const uint8_t FreeSans9pt7b_generic[] = {
@@ -5037,7 +5041,7 @@ static const uint8_t OpenSansLight16_generic[] = {
 };
 
 
-const Font Fonts[] =  {
+const Font FontsRM[] =  {
 	{
 		"Mono9",
 		(uint8_t *)FreeMono9pt7b_generic,
@@ -5111,3 +5115,6 @@ const Font Fonts[] =  {
 		0x20, 0x7e, 7
 	},
 };
+
+
+uint8_t NumFontsRM = sizeof(FontsRM)/sizeof(FontsRM[0]);
diff --git a/drv/display/fonts_ssd1306.h b/drv/display/fonts_ssd1306.h
deleted file mode 100644
index 266150e..0000000
--- a/drv/display/fonts_ssd1306.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef FONTS_SSD1306_H
-#define FONTS_SSD1306_H
-
-#include "font.h"
-
-typedef enum {
-	font_nativedbl = -2,
-	font_native = -1,
-	font_mono9 = 0,
-	font_mono12,
-	font_mono18,
-	font_mono24,
-	font_tomthumb,
-	font_sans9,
-	font_sans12,
-	font_sanslight10,
-	font_sanslight12,
-	font_sanslight14,
-	font_sanslight16,
-	font_org01,
-	font_numfonts
-} fontid_t;
-
-extern const Font Fonts[];
-extern const uint8_t Font6x8[];
-extern const uint16_t SizeofFont6x8;
-#endif
diff --git a/drv/display/glyphs.c b/drv/display/glyphs.c
new file mode 100644
index 0000000..69b3708
--- /dev/null
+++ b/drv/display/glyphs.c
@@ -0,0 +1,1290 @@
+#include "font.h"
+
+const GFXglyph FreeMono12pt7bGlyphs[] = {
+    {0, 0, 0, 14, 0, 1},        // 0x20 ' '
+    {0, 3, 15, 14, 6, -14},     // 0x21 '!'
+    {6, 8, 7, 14, 3, -14},      // 0x22 '"'
+    {13, 10, 16, 14, 2, -14},   // 0x23 '#'
+    {33, 10, 17, 14, 2, -14},   // 0x24 '$'
+    {55, 10, 15, 14, 2, -14},   // 0x25 '%'
+    {74, 9, 12, 14, 3, -11},    // 0x26 '&'
+    {88, 3, 7, 14, 5, -14},     // 0x27 '''
+    {91, 3, 18, 14, 7, -14},    // 0x28 '('
+    {98, 3, 18, 14, 4, -14},    // 0x29 ')'
+    {105, 9, 9, 14, 3, -14},    // 0x2A '*'
+    {116, 9, 11, 14, 3, -11},   // 0x2B '+'
+    {129, 5, 7, 14, 3, -3},     // 0x2C ','
+    {134, 11, 1, 14, 2, -6},    // 0x2D '-'
+    {136, 3, 3, 14, 5, -2},     // 0x2E '.'
+    {138, 9, 18, 14, 3, -15},   // 0x2F '/'
+    {159, 9, 15, 14, 3, -14},   // 0x30 '0'
+    {176, 7, 14, 14, 4, -13},   // 0x31 '1'
+    {189, 9, 15, 14, 2, -14},   // 0x32 '2'
+    {206, 10, 15, 14, 2, -14},  // 0x33 '3'
+    {225, 8, 15, 14, 3, -14},   // 0x34 '4'
+    {240, 9, 15, 14, 3, -14},   // 0x35 '5'
+    {257, 9, 15, 14, 3, -14},   // 0x36 '6'
+    {274, 8, 15, 14, 3, -14},   // 0x37 '7'
+    {289, 9, 15, 14, 3, -14},   // 0x38 '8'
+    {306, 9, 15, 14, 3, -14},   // 0x39 '9'
+    {323, 3, 10, 14, 5, -9},    // 0x3A ':'
+    {327, 5, 13, 14, 3, -9},    // 0x3B ';'
+    {336, 11, 11, 14, 2, -11},  // 0x3C '<'
+    {352, 12, 4, 14, 1, -8},    // 0x3D '='
+    {358, 11, 11, 14, 2, -11},  // 0x3E '>'
+    {374, 9, 14, 14, 3, -13},   // 0x3F '?'
+    {390, 9, 16, 14, 3, -14},   // 0x40 '@'
+    {408, 14, 14, 14, 0, -13},  // 0x41 'A'
+    {433, 11, 14, 14, 2, -13},  // 0x42 'B'
+    {453, 10, 14, 14, 2, -13},  // 0x43 'C'
+    {471, 10, 14, 14, 2, -13},  // 0x44 'D'
+    {489, 11, 14, 14, 2, -13},  // 0x45 'E'
+    {509, 11, 14, 14, 2, -13},  // 0x46 'F'
+    {529, 11, 14, 14, 2, -13},  // 0x47 'G'
+    {549, 10, 14, 14, 2, -13},  // 0x48 'H'
+    {567, 7, 14, 14, 4, -13},   // 0x49 'I'
+    {580, 11, 14, 14, 2, -13},  // 0x4A 'J'
+    {600, 12, 14, 14, 2, -13},  // 0x4B 'K'
+    {621, 11, 14, 14, 2, -13},  // 0x4C 'L'
+    {641, 13, 14, 14, 1, -13},  // 0x4D 'M'
+    {664, 12, 14, 14, 1, -13},  // 0x4E 'N'
+    {685, 12, 14, 14, 1, -13},  // 0x4F 'O'
+    {706, 10, 14, 14, 2, -13},  // 0x50 'P'
+    {724, 12, 17, 14, 1, -13},  // 0x51 'Q'
+    {750, 12, 14, 14, 2, -13},  // 0x52 'R'
+    {771, 10, 14, 14, 2, -13},  // 0x53 'S'
+    {789, 11, 14, 14, 2, -13},  // 0x54 'T'
+    {809, 12, 14, 14, 1, -13},  // 0x55 'U'
+    {830, 14, 14, 14, 0, -13},  // 0x56 'V'
+    {855, 14, 14, 14, 0, -13},  // 0x57 'W'
+    {880, 12, 14, 14, 1, -13},  // 0x58 'X'
+    {901, 12, 14, 14, 1, -13},  // 0x59 'Y'
+    {922, 9, 14, 14, 3, -13},   // 0x5A 'Z'
+    {938, 3, 18, 14, 7, -14},   // 0x5B '['
+    {945, 9, 18, 14, 3, -15},   // 0x5C '\'
+    {966, 3, 18, 14, 5, -14},   // 0x5D ']'
+    {973, 9, 6, 14, 3, -14},    // 0x5E '^'
+    {980, 14, 1, 14, 0, 3},     // 0x5F '_'
+    {982, 4, 4, 14, 4, -15},    // 0x60 '`'
+    {984, 10, 10, 14, 2, -9},   // 0x61 'a'
+    {997, 13, 15, 14, 0, -14},  // 0x62 'b'
+    {1022, 11, 10, 14, 2, -9},  // 0x63 'c'
+    {1036, 11, 15, 14, 2, -14}, // 0x64 'd'
+    {1057, 10, 10, 14, 2, -9},  // 0x65 'e'
+    {1070, 9, 15, 14, 4, -14},  // 0x66 'f'
+    {1087, 11, 14, 14, 2, -9},  // 0x67 'g'
+    {1107, 10, 15, 14, 2, -14}, // 0x68 'h'
+    {1126, 9, 15, 14, 3, -14},  // 0x69 'i'
+    {1143, 7, 19, 14, 3, -14},  // 0x6A 'j'
+    {1160, 12, 15, 14, 1, -14}, // 0x6B 'k'
+    {1183, 9, 15, 14, 3, -14},  // 0x6C 'l'
+    {1200, 13, 10, 14, 1, -9},  // 0x6D 'm'
+    {1217, 12, 10, 14, 1, -9},  // 0x6E 'n'
+    {1232, 11, 10, 14, 2, -9},  // 0x6F 'o'
+    {1246, 12, 14, 14, 1, -9},  // 0x70 'p'
+    {1267, 11, 14, 14, 2, -9},  // 0x71 'q'
+    {1287, 10, 10, 14, 3, -9},  // 0x72 'r'
+    {1300, 10, 10, 14, 2, -9},  // 0x73 's'
+    {1313, 11, 14, 14, 1, -13}, // 0x74 't'
+    {1333, 11, 10, 14, 2, -9},  // 0x75 'u'
+    {1347, 13, 10, 14, 1, -9},  // 0x76 'v'
+    {1364, 13, 10, 14, 1, -9},  // 0x77 'w'
+    {1381, 12, 10, 14, 1, -9},  // 0x78 'x'
+    {1396, 12, 14, 14, 1, -9},  // 0x79 'y'
+    {1417, 9, 10, 14, 3, -9},   // 0x7A 'z'
+    {1429, 5, 18, 14, 5, -14},  // 0x7B '{'
+    {1441, 1, 18, 14, 7, -14},  // 0x7C '|'
+    {1444, 5, 18, 14, 5, -14},  // 0x7D '}'
+    {1456, 10, 3, 14, 2, -7}};  // 0x7E '~'
+
+
+const GFXglyph FreeMono18pt7bGlyphs[] = {
+    {0, 0, 0, 21, 0, 1},        // 0x20 ' '
+    {0, 4, 22, 21, 8, -21},     // 0x21 '!'
+    {11, 11, 10, 21, 5, -20},   // 0x22 '"'
+    {25, 14, 24, 21, 3, -21},   // 0x23 '#'
+    {67, 13, 26, 21, 4, -22},   // 0x24 '$'
+    {110, 15, 21, 21, 3, -20},  // 0x25 '%'
+    {150, 12, 18, 21, 4, -17},  // 0x26 '&'
+    {177, 4, 10, 21, 8, -20},   // 0x27 '''
+    {182, 5, 25, 21, 10, -20},  // 0x28 '('
+    {198, 5, 25, 21, 6, -20},   // 0x29 ')'
+    {214, 13, 12, 21, 4, -20},  // 0x2A '*'
+    {234, 15, 17, 21, 3, -17},  // 0x2B '+'
+    {266, 7, 10, 21, 5, -4},    // 0x2C ','
+    {275, 15, 1, 21, 3, -9},    // 0x2D '-'
+    {277, 5, 5, 21, 8, -4},     // 0x2E '.'
+    {281, 13, 26, 21, 4, -22},  // 0x2F '/'
+    {324, 13, 21, 21, 4, -20},  // 0x30 '0'
+    {359, 13, 21, 21, 4, -20},  // 0x31 '1'
+    {394, 13, 21, 21, 3, -20},  // 0x32 '2'
+    {429, 14, 21, 21, 3, -20},  // 0x33 '3'
+    {466, 12, 21, 21, 4, -20},  // 0x34 '4'
+    {498, 14, 21, 21, 3, -20},  // 0x35 '5'
+    {535, 12, 21, 21, 5, -20},  // 0x36 '6'
+    {567, 12, 21, 21, 4, -20},  // 0x37 '7'
+    {599, 13, 21, 21, 4, -20},  // 0x38 '8'
+    {634, 12, 21, 21, 5, -20},  // 0x39 '9'
+    {666, 5, 15, 21, 8, -14},   // 0x3A ':'
+    {676, 7, 20, 21, 5, -14},   // 0x3B ';'
+    {694, 15, 16, 21, 3, -17},  // 0x3C '<'
+    {724, 17, 6, 21, 2, -12},   // 0x3D '='
+    {737, 15, 16, 21, 3, -17},  // 0x3E '>'
+    {767, 12, 20, 21, 5, -19},  // 0x3F '?'
+    {797, 13, 23, 21, 4, -20},  // 0x40 '@'
+    {835, 21, 20, 21, 0, -19},  // 0x41 'A'
+    {888, 18, 20, 21, 1, -19},  // 0x42 'B'
+    {933, 17, 20, 21, 2, -19},  // 0x43 'C'
+    {976, 16, 20, 21, 2, -19},  // 0x44 'D'
+    {1016, 17, 20, 21, 1, -19}, // 0x45 'E'
+    {1059, 17, 20, 21, 1, -19}, // 0x46 'F'
+    {1102, 17, 20, 21, 2, -19}, // 0x47 'G'
+    {1145, 16, 20, 21, 2, -19}, // 0x48 'H'
+    {1185, 13, 20, 21, 4, -19}, // 0x49 'I'
+    {1218, 17, 20, 21, 3, -19}, // 0x4A 'J'
+    {1261, 18, 20, 21, 1, -19}, // 0x4B 'K'
+    {1306, 15, 20, 21, 3, -19}, // 0x4C 'L'
+    {1344, 19, 20, 21, 1, -19}, // 0x4D 'M'
+    {1392, 18, 20, 21, 1, -19}, // 0x4E 'N'
+    {1437, 17, 20, 21, 2, -19}, // 0x4F 'O'
+    {1480, 16, 20, 21, 1, -19}, // 0x50 'P'
+    {1520, 17, 24, 21, 2, -19}, // 0x51 'Q'
+    {1571, 19, 20, 21, 1, -19}, // 0x52 'R'
+    {1619, 14, 20, 21, 3, -19}, // 0x53 'S'
+    {1654, 15, 20, 21, 3, -19}, // 0x54 'T'
+    {1692, 17, 20, 21, 2, -19}, // 0x55 'U'
+    {1735, 21, 20, 21, 0, -19}, // 0x56 'V'
+    {1788, 19, 20, 21, 1, -19}, // 0x57 'W'
+    {1836, 19, 20, 21, 1, -19}, // 0x58 'X'
+    {1884, 17, 20, 21, 2, -19}, // 0x59 'Y'
+    {1927, 13, 20, 21, 4, -19}, // 0x5A 'Z'
+    {1960, 5, 25, 21, 10, -20}, // 0x5B '['
+    {1976, 13, 26, 21, 4, -22}, // 0x5C '\'
+    {2019, 5, 25, 21, 6, -20},  // 0x5D ']'
+    {2035, 13, 9, 21, 4, -20},  // 0x5E '^'
+    {2050, 21, 1, 21, 0, 4},    // 0x5F '_'
+    {2053, 6, 5, 21, 5, -21},   // 0x60 '`'
+    {2057, 16, 15, 21, 3, -14}, // 0x61 'a'
+    {2087, 18, 21, 21, 1, -20}, // 0x62 'b'
+    {2135, 15, 15, 21, 3, -14}, // 0x63 'c'
+    {2164, 18, 21, 21, 2, -20}, // 0x64 'd'
+    {2212, 16, 15, 21, 2, -14}, // 0x65 'e'
+    {2242, 14, 21, 21, 4, -20}, // 0x66 'f'
+    {2279, 17, 22, 21, 2, -14}, // 0x67 'g'
+    {2326, 17, 21, 21, 1, -20}, // 0x68 'h'
+    {2371, 14, 22, 21, 4, -21}, // 0x69 'i'
+    {2410, 10, 29, 21, 5, -21}, // 0x6A 'j'
+    {2447, 16, 21, 21, 2, -20}, // 0x6B 'k'
+    {2489, 14, 21, 21, 4, -20}, // 0x6C 'l'
+    {2526, 19, 15, 21, 1, -14}, // 0x6D 'm'
+    {2562, 17, 15, 21, 1, -14}, // 0x6E 'n'
+    {2594, 15, 15, 21, 3, -14}, // 0x6F 'o'
+    {2623, 18, 22, 21, 1, -14}, // 0x70 'p'
+    {2673, 18, 22, 21, 2, -14}, // 0x71 'q'
+    {2723, 15, 15, 21, 3, -14}, // 0x72 'r'
+    {2752, 13, 15, 21, 4, -14}, // 0x73 's'
+    {2777, 16, 20, 21, 1, -19}, // 0x74 't'
+    {2817, 17, 15, 21, 1, -14}, // 0x75 'u'
+    {2849, 19, 15, 21, 1, -14}, // 0x76 'v'
+    {2885, 19, 15, 21, 1, -14}, // 0x77 'w'
+    {2921, 17, 15, 21, 2, -14}, // 0x78 'x'
+    {2953, 17, 22, 21, 2, -14}, // 0x79 'y'
+    {3000, 13, 15, 21, 4, -14}, // 0x7A 'z'
+    {3025, 8, 25, 21, 6, -20},  // 0x7B '{'
+    {3050, 1, 25, 21, 10, -20}, // 0x7C '|'
+    {3054, 8, 25, 21, 7, -20},  // 0x7D '}'
+    {3079, 15, 5, 21, 3, -11}}; // 0x7E '~'
+
+
+const GFXglyph FreeMono24pt7bGlyphs[] = {
+    {0, 0, 0, 28, 0, 1},        // 0x20 ' '
+    {0, 5, 30, 28, 11, -28},    // 0x21 '!'
+    {19, 16, 14, 28, 6, -28},   // 0x22 '"'
+    {47, 19, 32, 28, 4, -29},   // 0x23 '#'
+    {123, 18, 33, 28, 5, -29},  // 0x24 '$'
+    {198, 20, 29, 28, 4, -27},  // 0x25 '%'
+    {271, 18, 25, 28, 5, -23},  // 0x26 '&'
+    {328, 7, 14, 28, 11, -28},  // 0x27 '''
+    {341, 7, 34, 28, 14, -27},  // 0x28 '('
+    {371, 7, 34, 28, 8, -27},   // 0x29 ')'
+    {401, 18, 16, 28, 5, -27},  // 0x2A '*'
+    {437, 20, 22, 28, 4, -23},  // 0x2B '+'
+    {492, 9, 14, 28, 6, -6},    // 0x2C ','
+    {508, 22, 2, 28, 3, -13},   // 0x2D '-'
+    {514, 7, 6, 28, 11, -4},    // 0x2E '.'
+    {520, 18, 35, 28, 5, -30},  // 0x2F '/'
+    {599, 18, 30, 28, 5, -28},  // 0x30 '0'
+    {667, 16, 29, 28, 6, -28},  // 0x31 '1'
+    {725, 18, 29, 28, 5, -28},  // 0x32 '2'
+    {791, 19, 30, 28, 5, -28},  // 0x33 '3'
+    {863, 16, 28, 28, 6, -27},  // 0x34 '4'
+    {919, 19, 29, 28, 5, -27},  // 0x35 '5'
+    {988, 18, 30, 28, 6, -28},  // 0x36 '6'
+    {1056, 18, 28, 28, 5, -27}, // 0x37 '7'
+    {1119, 18, 30, 28, 5, -28}, // 0x38 '8'
+    {1187, 18, 30, 28, 6, -28}, // 0x39 '9'
+    {1255, 7, 21, 28, 11, -19}, // 0x3A ':'
+    {1274, 10, 27, 28, 7, -19}, // 0x3B ';'
+    {1308, 22, 22, 28, 3, -23}, // 0x3C '<'
+    {1369, 24, 9, 28, 2, -17},  // 0x3D '='
+    {1396, 21, 22, 28, 4, -23}, // 0x3E '>'
+    {1454, 17, 28, 28, 6, -26}, // 0x3F '?'
+    {1514, 18, 32, 28, 5, -28}, // 0x40 '@'
+    {1586, 28, 26, 28, 0, -25}, // 0x41 'A'
+    {1677, 22, 26, 28, 3, -25}, // 0x42 'B'
+    {1749, 22, 28, 28, 3, -26}, // 0x43 'C'
+    {1826, 22, 26, 28, 3, -25}, // 0x44 'D'
+    {1898, 22, 26, 28, 3, -25}, // 0x45 'E'
+    {1970, 22, 26, 28, 3, -25}, // 0x46 'F'
+    {2042, 23, 28, 28, 3, -26}, // 0x47 'G'
+    {2123, 23, 26, 28, 3, -25}, // 0x48 'H'
+    {2198, 16, 26, 28, 6, -25}, // 0x49 'I'
+    {2250, 23, 27, 28, 4, -25}, // 0x4A 'J'
+    {2328, 24, 26, 28, 3, -25}, // 0x4B 'K'
+    {2406, 21, 26, 28, 4, -25}, // 0x4C 'L'
+    {2475, 26, 26, 28, 1, -25}, // 0x4D 'M'
+    {2560, 24, 26, 28, 2, -25}, // 0x4E 'N'
+    {2638, 24, 28, 28, 2, -26}, // 0x4F 'O'
+    {2722, 21, 26, 28, 3, -25}, // 0x50 'P'
+    {2791, 24, 32, 28, 2, -26}, // 0x51 'Q'
+    {2887, 24, 26, 28, 3, -25}, // 0x52 'R'
+    {2965, 20, 28, 28, 4, -26}, // 0x53 'S'
+    {3035, 22, 26, 28, 3, -25}, // 0x54 'T'
+    {3107, 23, 27, 28, 3, -25}, // 0x55 'U'
+    {3185, 28, 26, 28, 0, -25}, // 0x56 'V'
+    {3276, 26, 26, 28, 1, -25}, // 0x57 'W'
+    {3361, 24, 26, 28, 2, -25}, // 0x58 'X'
+    {3439, 24, 26, 28, 2, -25}, // 0x59 'Y'
+    {3517, 18, 26, 28, 5, -25}, // 0x5A 'Z'
+    {3576, 7, 34, 28, 13, -27}, // 0x5B '['
+    {3606, 18, 35, 28, 5, -30}, // 0x5C '\'
+    {3685, 7, 34, 28, 8, -27},  // 0x5D ']'
+    {3715, 18, 12, 28, 5, -28}, // 0x5E '^'
+    {3742, 28, 2, 28, 0, 5},    // 0x5F '_'
+    {3749, 8, 7, 28, 7, -29},   // 0x60 '`'
+    {3756, 22, 22, 28, 3, -20}, // 0x61 'a'
+    {3817, 23, 29, 28, 2, -27}, // 0x62 'b'
+    {3901, 21, 22, 28, 4, -20}, // 0x63 'c'
+    {3959, 24, 29, 28, 3, -27}, // 0x64 'd'
+    {4046, 21, 22, 28, 3, -20}, // 0x65 'e'
+    {4104, 19, 28, 28, 6, -27}, // 0x66 'f'
+    {4171, 23, 30, 28, 3, -20}, // 0x67 'g'
+    {4258, 23, 28, 28, 3, -27}, // 0x68 'h'
+    {4339, 18, 29, 28, 5, -28}, // 0x69 'i'
+    {4405, 14, 38, 28, 6, -28}, // 0x6A 'j'
+    {4472, 22, 28, 28, 4, -27}, // 0x6B 'k'
+    {4549, 18, 28, 28, 5, -27}, // 0x6C 'l'
+    {4612, 28, 21, 28, 0, -20}, // 0x6D 'm'
+    {4686, 23, 21, 28, 2, -20}, // 0x6E 'n'
+    {4747, 22, 22, 28, 3, -20}, // 0x6F 'o'
+    {4808, 23, 30, 28, 2, -20}, // 0x70 'p'
+    {4895, 24, 30, 28, 3, -20}, // 0x71 'q'
+    {4985, 21, 20, 28, 5, -19}, // 0x72 'r'
+    {5038, 18, 22, 28, 5, -20}, // 0x73 's'
+    {5088, 21, 27, 28, 3, -25}, // 0x74 't'
+    {5159, 23, 21, 28, 3, -19}, // 0x75 'u'
+    {5220, 26, 20, 28, 1, -19}, // 0x76 'v'
+    {5285, 26, 20, 28, 1, -19}, // 0x77 'w'
+    {5350, 24, 20, 28, 2, -19}, // 0x78 'x'
+    {5410, 24, 29, 28, 2, -19}, // 0x79 'y'
+    {5497, 17, 20, 28, 6, -19}, // 0x7A 'z'
+    {5540, 11, 34, 28, 8, -27}, // 0x7B '{'
+    {5587, 2, 34, 28, 13, -27}, // 0x7C '|'
+    {5596, 11, 34, 28, 9, -27}, // 0x7D '}'
+    {5643, 20, 6, 28, 4, -15}}; // 0x7E '~'
+
+
+const GFXglyph FreeMono9pt7bGlyphs[] = {
+    {0, 0, 0, 11, 0, 1},      // 0x20 ' '
+    {0, 2, 11, 11, 4, -10},   // 0x21 '!'
+    {3, 6, 5, 11, 2, -10},    // 0x22 '"'
+    {7, 7, 12, 11, 2, -10},   // 0x23 '#'
+    {18, 8, 12, 11, 1, -10},  // 0x24 '$'
+    {30, 7, 11, 11, 2, -10},  // 0x25 '%'
+    {40, 7, 10, 11, 2, -9},   // 0x26 '&'
+    {49, 3, 5, 11, 4, -10},   // 0x27 '''
+    {51, 2, 13, 11, 5, -10},  // 0x28 '('
+    {55, 2, 13, 11, 4, -10},  // 0x29 ')'
+    {59, 7, 7, 11, 2, -10},   // 0x2A '*'
+    {66, 7, 7, 11, 2, -8},    // 0x2B '+'
+    {73, 3, 5, 11, 2, -1},    // 0x2C ','
+    {75, 9, 1, 11, 1, -5},    // 0x2D '-'
+    {77, 2, 2, 11, 4, -1},    // 0x2E '.'
+    {78, 7, 13, 11, 2, -11},  // 0x2F '/'
+    {90, 7, 11, 11, 2, -10},  // 0x30 '0'
+    {100, 5, 11, 11, 3, -10}, // 0x31 '1'
+    {107, 7, 11, 11, 2, -10}, // 0x32 '2'
+    {117, 8, 11, 11, 1, -10}, // 0x33 '3'
+    {128, 6, 11, 11, 3, -10}, // 0x34 '4'
+    {137, 7, 11, 11, 2, -10}, // 0x35 '5'
+    {147, 7, 11, 11, 2, -10}, // 0x36 '6'
+    {157, 7, 11, 11, 2, -10}, // 0x37 '7'
+    {167, 7, 11, 11, 2, -10}, // 0x38 '8'
+    {177, 7, 11, 11, 2, -10}, // 0x39 '9'
+    {187, 2, 8, 11, 4, -7},   // 0x3A ':'
+    {189, 3, 11, 11, 3, -7},  // 0x3B ';'
+    {194, 8, 8, 11, 1, -8},   // 0x3C '<'
+    {202, 9, 4, 11, 1, -6},   // 0x3D '='
+    {207, 9, 8, 11, 1, -8},   // 0x3E '>'
+    {216, 7, 10, 11, 2, -9},  // 0x3F '?'
+    {225, 8, 12, 11, 2, -10}, // 0x40 '@'
+    {237, 11, 10, 11, 0, -9}, // 0x41 'A'
+    {251, 9, 10, 11, 1, -9},  // 0x42 'B'
+    {263, 9, 10, 11, 1, -9},  // 0x43 'C'
+    {275, 9, 10, 11, 1, -9},  // 0x44 'D'
+    {287, 9, 10, 11, 1, -9},  // 0x45 'E'
+    {299, 9, 10, 11, 1, -9},  // 0x46 'F'
+    {311, 10, 10, 11, 1, -9}, // 0x47 'G'
+    {324, 9, 10, 11, 1, -9},  // 0x48 'H'
+    {336, 5, 10, 11, 3, -9},  // 0x49 'I'
+    {343, 8, 10, 11, 2, -9},  // 0x4A 'J'
+    {353, 9, 10, 11, 1, -9},  // 0x4B 'K'
+    {365, 8, 10, 11, 2, -9},  // 0x4C 'L'
+    {375, 11, 10, 11, 0, -9}, // 0x4D 'M'
+    {389, 9, 10, 11, 1, -9},  // 0x4E 'N'
+    {401, 9, 10, 11, 1, -9},  // 0x4F 'O'
+    {413, 8, 10, 11, 1, -9},  // 0x50 'P'
+    {423, 9, 13, 11, 1, -9},  // 0x51 'Q'
+    {438, 9, 10, 11, 1, -9},  // 0x52 'R'
+    {450, 7, 10, 11, 2, -9},  // 0x53 'S'
+    {459, 9, 10, 11, 1, -9},  // 0x54 'T'
+    {471, 9, 10, 11, 1, -9},  // 0x55 'U'
+    {483, 11, 10, 11, 0, -9}, // 0x56 'V'
+    {497, 11, 10, 11, 0, -9}, // 0x57 'W'
+    {511, 9, 10, 11, 1, -9},  // 0x58 'X'
+    {523, 9, 10, 11, 1, -9},  // 0x59 'Y'
+    {535, 7, 10, 11, 2, -9},  // 0x5A 'Z'
+    {544, 2, 13, 11, 5, -10}, // 0x5B '['
+    {548, 7, 13, 11, 2, -11}, // 0x5C '\'
+    {560, 2, 13, 11, 4, -10}, // 0x5D ']'
+    {564, 7, 5, 11, 2, -10},  // 0x5E '^'
+    {569, 11, 1, 11, 0, 2},   // 0x5F '_'
+    {571, 3, 3, 11, 3, -11},  // 0x60 '`'
+    {573, 9, 8, 11, 1, -7},   // 0x61 'a'
+    {582, 9, 11, 11, 1, -10}, // 0x62 'b'
+    {595, 7, 8, 11, 2, -7},   // 0x63 'c'
+    {602, 9, 11, 11, 1, -10}, // 0x64 'd'
+    {615, 8, 8, 11, 1, -7},   // 0x65 'e'
+    {623, 6, 11, 11, 3, -10}, // 0x66 'f'
+    {632, 9, 11, 11, 1, -7},  // 0x67 'g'
+    {645, 9, 11, 11, 1, -10}, // 0x68 'h'
+    {658, 7, 10, 11, 2, -9},  // 0x69 'i'
+    {667, 5, 13, 11, 3, -9},  // 0x6A 'j'
+    {676, 8, 11, 11, 2, -10}, // 0x6B 'k'
+    {687, 7, 11, 11, 2, -10}, // 0x6C 'l'
+    {697, 9, 8, 11, 1, -7},   // 0x6D 'm'
+    {706, 9, 8, 11, 1, -7},   // 0x6E 'n'
+    {715, 9, 8, 11, 1, -7},   // 0x6F 'o'
+    {724, 9, 11, 11, 1, -7},  // 0x70 'p'
+    {737, 9, 11, 11, 1, -7},  // 0x71 'q'
+    {750, 7, 8, 11, 3, -7},   // 0x72 'r'
+    {757, 7, 8, 11, 2, -7},   // 0x73 's'
+    {764, 8, 10, 11, 2, -9},  // 0x74 't'
+    {774, 8, 8, 11, 1, -7},   // 0x75 'u'
+    {782, 9, 8, 11, 1, -7},   // 0x76 'v'
+    {791, 9, 8, 11, 1, -7},   // 0x77 'w'
+    {800, 9, 8, 11, 1, -7},   // 0x78 'x'
+    {809, 9, 11, 11, 1, -7},  // 0x79 'y'
+    {822, 7, 8, 11, 2, -7},   // 0x7A 'z'
+    {829, 3, 13, 11, 4, -10}, // 0x7B '{'
+    {834, 1, 13, 11, 5, -10}, // 0x7C '|'
+    {836, 3, 13, 11, 4, -10}, // 0x7D '}'
+    {841, 7, 3, 11, 2, -6}};  // 0x7E '~'
+
+
+const GFXglyph FreeSans12pt7bGlyphs[] = {
+    {0, 0, 0, 6, 0, 1},         // 0x20 ' '
+    {0, 2, 18, 8, 3, -17},      // 0x21 '!'
+    {5, 6, 6, 8, 1, -16},       // 0x22 '"'
+    {10, 13, 16, 13, 0, -15},   // 0x23 '#'
+    {36, 11, 20, 13, 1, -17},   // 0x24 '$'
+    {64, 20, 17, 21, 1, -16},   // 0x25 '%'
+    {107, 14, 17, 16, 1, -16},  // 0x26 '&'
+    {137, 2, 6, 5, 1, -16},     // 0x27 '''
+    {139, 5, 23, 8, 2, -17},    // 0x28 '('
+    {154, 5, 23, 8, 1, -17},    // 0x29 ')'
+    {169, 7, 7, 9, 1, -17},     // 0x2A '*'
+    {176, 10, 11, 14, 2, -10},  // 0x2B '+'
+    {190, 2, 6, 7, 2, -1},      // 0x2C ','
+    {192, 6, 2, 8, 1, -7},      // 0x2D '-'
+    {194, 2, 2, 6, 2, -1},      // 0x2E '.'
+    {195, 7, 18, 7, 0, -17},    // 0x2F '/'
+    {211, 11, 17, 13, 1, -16},  // 0x30 '0'
+    {235, 5, 17, 13, 3, -16},   // 0x31 '1'
+    {246, 11, 17, 13, 1, -16},  // 0x32 '2'
+    {270, 11, 17, 13, 1, -16},  // 0x33 '3'
+    {294, 11, 17, 13, 1, -16},  // 0x34 '4'
+    {318, 11, 17, 13, 1, -16},  // 0x35 '5'
+    {342, 11, 17, 13, 1, -16},  // 0x36 '6'
+    {366, 11, 17, 13, 1, -16},  // 0x37 '7'
+    {390, 11, 17, 13, 1, -16},  // 0x38 '8'
+    {414, 11, 17, 13, 1, -16},  // 0x39 '9'
+    {438, 2, 13, 6, 2, -12},    // 0x3A ':'
+    {442, 2, 16, 6, 2, -11},    // 0x3B ';'
+    {446, 12, 12, 14, 1, -11},  // 0x3C '<'
+    {464, 12, 6, 14, 1, -8},    // 0x3D '='
+    {473, 12, 12, 14, 1, -11},  // 0x3E '>'
+    {491, 10, 18, 13, 2, -17},  // 0x3F '?'
+    {514, 22, 21, 24, 1, -17},  // 0x40 '@'
+    {572, 16, 18, 16, 0, -17},  // 0x41 'A'
+    {608, 13, 18, 16, 2, -17},  // 0x42 'B'
+    {638, 15, 18, 17, 1, -17},  // 0x43 'C'
+    {672, 14, 18, 17, 2, -17},  // 0x44 'D'
+    {704, 12, 18, 15, 2, -17},  // 0x45 'E'
+    {731, 11, 18, 14, 2, -17},  // 0x46 'F'
+    {756, 16, 18, 18, 1, -17},  // 0x47 'G'
+    {792, 13, 18, 17, 2, -17},  // 0x48 'H'
+    {822, 2, 18, 7, 2, -17},    // 0x49 'I'
+    {827, 9, 18, 13, 1, -17},   // 0x4A 'J'
+    {848, 14, 18, 16, 2, -17},  // 0x4B 'K'
+    {880, 10, 18, 14, 2, -17},  // 0x4C 'L'
+    {903, 16, 18, 20, 2, -17},  // 0x4D 'M'
+    {939, 13, 18, 18, 2, -17},  // 0x4E 'N'
+    {969, 17, 18, 19, 1, -17},  // 0x4F 'O'
+    {1008, 12, 18, 16, 2, -17}, // 0x50 'P'
+    {1035, 17, 19, 19, 1, -17}, // 0x51 'Q'
+    {1076, 14, 18, 17, 2, -17}, // 0x52 'R'
+    {1108, 14, 18, 16, 1, -17}, // 0x53 'S'
+    {1140, 12, 18, 15, 1, -17}, // 0x54 'T'
+    {1167, 13, 18, 17, 2, -17}, // 0x55 'U'
+    {1197, 15, 18, 15, 0, -17}, // 0x56 'V'
+    {1231, 22, 18, 22, 0, -17}, // 0x57 'W'
+    {1281, 15, 18, 16, 0, -17}, // 0x58 'X'
+    {1315, 16, 18, 16, 0, -17}, // 0x59 'Y'
+    {1351, 13, 18, 15, 1, -17}, // 0x5A 'Z'
+    {1381, 4, 23, 7, 2, -17},   // 0x5B '['
+    {1393, 7, 18, 7, 0, -17},   // 0x5C '\'
+    {1409, 4, 23, 7, 1, -17},   // 0x5D ']'
+    {1421, 9, 9, 11, 1, -16},   // 0x5E '^'
+    {1432, 15, 1, 13, -1, 4},   // 0x5F '_'
+    {1434, 5, 4, 6, 1, -17},    // 0x60 '`'
+    {1437, 12, 13, 13, 1, -12}, // 0x61 'a'
+    {1457, 12, 18, 13, 1, -17}, // 0x62 'b'
+    {1484, 10, 13, 12, 1, -12}, // 0x63 'c'
+    {1501, 11, 18, 13, 1, -17}, // 0x64 'd'
+    {1526, 11, 13, 13, 1, -12}, // 0x65 'e'
+    {1544, 5, 18, 7, 1, -17},   // 0x66 'f'
+    {1556, 11, 18, 13, 1, -12}, // 0x67 'g'
+    {1581, 10, 18, 13, 1, -17}, // 0x68 'h'
+    {1604, 2, 18, 5, 2, -17},   // 0x69 'i'
+    {1609, 4, 23, 6, 0, -17},   // 0x6A 'j'
+    {1621, 11, 18, 12, 1, -17}, // 0x6B 'k'
+    {1646, 2, 18, 5, 1, -17},   // 0x6C 'l'
+    {1651, 17, 13, 19, 1, -12}, // 0x6D 'm'
+    {1679, 10, 13, 13, 1, -12}, // 0x6E 'n'
+    {1696, 11, 13, 13, 1, -12}, // 0x6F 'o'
+    {1714, 12, 17, 13, 1, -12}, // 0x70 'p'
+    {1740, 11, 17, 13, 1, -12}, // 0x71 'q'
+    {1764, 6, 13, 8, 1, -12},   // 0x72 'r'
+    {1774, 10, 13, 12, 1, -12}, // 0x73 's'
+    {1791, 5, 16, 7, 1, -15},   // 0x74 't'
+    {1801, 10, 13, 13, 1, -12}, // 0x75 'u'
+    {1818, 12, 13, 12, 0, -12}, // 0x76 'v'
+    {1838, 17, 13, 17, 0, -12}, // 0x77 'w'
+    {1866, 11, 13, 11, 0, -12}, // 0x78 'x'
+    {1884, 11, 18, 11, 0, -12}, // 0x79 'y'
+    {1909, 10, 13, 12, 1, -12}, // 0x7A 'z'
+    {1926, 5, 23, 8, 1, -17},   // 0x7B '{'
+    {1941, 2, 23, 6, 2, -17},   // 0x7C '|'
+    {1947, 5, 23, 8, 2, -17},   // 0x7D '}'
+    {1962, 10, 5, 12, 1, -10}}; // 0x7E '~'
+
+
+const GFXglyph FreeSans9pt7bGlyphs[] = {
+    {0, 0, 0, 5, 0, 1},        // 0x20 ' '
+    {0, 2, 13, 6, 2, -12},     // 0x21 '!'
+    {4, 5, 4, 6, 1, -12},      // 0x22 '"'
+    {7, 10, 12, 10, 0, -11},   // 0x23 '#'
+    {22, 9, 16, 10, 1, -13},   // 0x24 '$'
+    {40, 16, 13, 16, 1, -12},  // 0x25 '%'
+    {66, 11, 13, 12, 1, -12},  // 0x26 '&'
+    {84, 2, 4, 4, 1, -12},     // 0x27 '''
+    {85, 4, 17, 6, 1, -12},    // 0x28 '('
+    {94, 4, 17, 6, 1, -12},    // 0x29 ')'
+    {103, 5, 5, 7, 1, -12},    // 0x2A '*'
+    {107, 6, 8, 11, 3, -7},    // 0x2B '+'
+    {113, 2, 4, 5, 2, 0},      // 0x2C ','
+    {114, 4, 1, 6, 1, -4},     // 0x2D '-'
+    {115, 2, 1, 5, 1, 0},      // 0x2E '.'
+    {116, 5, 13, 5, 0, -12},   // 0x2F '/'
+    {125, 8, 13, 10, 1, -12},  // 0x30 '0'
+    {138, 4, 13, 10, 3, -12},  // 0x31 '1'
+    {145, 9, 13, 10, 1, -12},  // 0x32 '2'
+    {160, 8, 13, 10, 1, -12},  // 0x33 '3'
+    {173, 7, 13, 10, 2, -12},  // 0x34 '4'
+    {185, 9, 13, 10, 1, -12},  // 0x35 '5'
+    {200, 9, 13, 10, 1, -12},  // 0x36 '6'
+    {215, 8, 13, 10, 0, -12},  // 0x37 '7'
+    {228, 9, 13, 10, 1, -12},  // 0x38 '8'
+    {243, 8, 13, 10, 1, -12},  // 0x39 '9'
+    {256, 2, 10, 5, 1, -9},    // 0x3A ':'
+    {259, 3, 12, 5, 1, -8},    // 0x3B ';'
+    {264, 9, 9, 11, 1, -8},    // 0x3C '<'
+    {275, 9, 4, 11, 1, -5},    // 0x3D '='
+    {280, 9, 9, 11, 1, -8},    // 0x3E '>'
+    {291, 9, 13, 10, 1, -12},  // 0x3F '?'
+    {306, 17, 16, 18, 1, -12}, // 0x40 '@'
+    {340, 12, 13, 12, 0, -12}, // 0x41 'A'
+    {360, 11, 13, 12, 1, -12}, // 0x42 'B'
+    {378, 11, 13, 13, 1, -12}, // 0x43 'C'
+    {396, 11, 13, 13, 1, -12}, // 0x44 'D'
+    {414, 9, 13, 11, 1, -12},  // 0x45 'E'
+    {429, 8, 13, 11, 1, -12},  // 0x46 'F'
+    {442, 12, 13, 14, 1, -12}, // 0x47 'G'
+    {462, 11, 13, 13, 1, -12}, // 0x48 'H'
+    {480, 2, 13, 5, 2, -12},   // 0x49 'I'
+    {484, 7, 13, 10, 1, -12},  // 0x4A 'J'
+    {496, 11, 13, 12, 1, -12}, // 0x4B 'K'
+    {514, 8, 13, 10, 1, -12},  // 0x4C 'L'
+    {527, 13, 13, 15, 1, -12}, // 0x4D 'M'
+    {549, 11, 13, 13, 1, -12}, // 0x4E 'N'
+    {567, 13, 13, 14, 1, -12}, // 0x4F 'O'
+    {589, 10, 13, 12, 1, -12}, // 0x50 'P'
+    {606, 13, 14, 14, 1, -12}, // 0x51 'Q'
+    {629, 12, 13, 13, 1, -12}, // 0x52 'R'
+    {649, 10, 13, 12, 1, -12}, // 0x53 'S'
+    {666, 9, 13, 11, 1, -12},  // 0x54 'T'
+    {681, 11, 13, 13, 1, -12}, // 0x55 'U'
+    {699, 11, 13, 12, 0, -12}, // 0x56 'V'
+    {717, 17, 13, 17, 0, -12}, // 0x57 'W'
+    {745, 12, 13, 12, 0, -12}, // 0x58 'X'
+    {765, 12, 13, 12, 0, -12}, // 0x59 'Y'
+    {785, 10, 13, 11, 1, -12}, // 0x5A 'Z'
+    {802, 3, 17, 5, 1, -12},   // 0x5B '['
+    {809, 5, 13, 5, 0, -12},   // 0x5C '\'
+    {818, 3, 17, 5, 0, -12},   // 0x5D ']'
+    {825, 7, 7, 8, 1, -12},    // 0x5E '^'
+    {832, 10, 1, 10, 0, 3},    // 0x5F '_'
+    {834, 4, 3, 5, 0, -12},    // 0x60 '`'
+    {836, 9, 10, 10, 1, -9},   // 0x61 'a'
+    {848, 9, 13, 10, 1, -12},  // 0x62 'b'
+    {863, 8, 10, 9, 1, -9},    // 0x63 'c'
+    {873, 8, 13, 10, 1, -12},  // 0x64 'd'
+    {886, 8, 10, 10, 1, -9},   // 0x65 'e'
+    {896, 4, 13, 5, 1, -12},   // 0x66 'f'
+    {903, 8, 14, 10, 1, -9},   // 0x67 'g'
+    {917, 8, 13, 10, 1, -12},  // 0x68 'h'
+    {930, 2, 13, 4, 1, -12},   // 0x69 'i'
+    {934, 4, 17, 4, 0, -12},   // 0x6A 'j'
+    {943, 9, 13, 9, 1, -12},   // 0x6B 'k'
+    {958, 2, 13, 4, 1, -12},   // 0x6C 'l'
+    {962, 13, 10, 15, 1, -9},  // 0x6D 'm'
+    {979, 8, 10, 10, 1, -9},   // 0x6E 'n'
+    {989, 8, 10, 10, 1, -9},   // 0x6F 'o'
+    {999, 9, 13, 10, 1, -9},   // 0x70 'p'
+    {1014, 8, 13, 10, 1, -9},  // 0x71 'q'
+    {1027, 5, 10, 6, 1, -9},   // 0x72 'r'
+    {1034, 8, 10, 9, 1, -9},   // 0x73 's'
+    {1044, 4, 12, 5, 1, -11},  // 0x74 't'
+    {1050, 8, 10, 10, 1, -9},  // 0x75 'u'
+    {1060, 9, 10, 9, 0, -9},   // 0x76 'v'
+    {1072, 13, 10, 13, 0, -9}, // 0x77 'w'
+    {1089, 8, 10, 9, 0, -9},   // 0x78 'x'
+    {1099, 9, 14, 9, 0, -9},   // 0x79 'y'
+    {1115, 7, 10, 9, 1, -9},   // 0x7A 'z'
+    {1124, 4, 17, 6, 1, -12},  // 0x7B '{'
+    {1133, 2, 17, 4, 2, -12},  // 0x7C '|'
+    {1138, 4, 17, 6, 1, -12},  // 0x7D '}'
+    {1147, 7, 3, 9, 1, -7}};   // 0x7E '~'
+
+const GFXglyph OpenSansLight10Glyphs[] = {
+// bitmapOffset, width, height, xAdvance, xOffset, yOffset
+	  {     0,   1,   1,   4,    0,    0 }, // ' '
+	  {     1,   3,   7,   3,    0,   -7 }, // '!'
+	  {     4,   3,   3,   5,    1,   -7 }, // '"'
+	  {     6,   7,   7,   7,    0,   -7 }, // '#'
+	  {    13,   5,   9,   7,    1,   -8 }, // '$'
+	  {    19,   7,   7,   9,    1,   -7 }, // '%'
+	  {    26,   7,   7,   8,    1,   -7 }, // '&'
+	  {    33,   3,   3,   3,    0,   -7 }, // '''
+	  {    35,   4,   9,   4,    0,   -7 }, // '('
+	  {    40,   4,   9,   4,    0,   -7 }, // ')'
+	  {    45,   5,   4,   7,    1,   -7 }, // '*'
+	  {    48,   5,   5,   7,    1,   -6 }, // '+'
+	  {    52,   2,   2,   3,    0,   -1 }, // ','
+	  {    53,   4,   1,   4,    0,   -3 }, // '-'
+	  {    54,   3,   1,   3,    0,   -1 }, // '.'
+	  {    55,   4,   7,   4,    0,   -7 }, // '/'
+	  {    59,   5,   7,   7,    1,   -7 }, // '0'
+	  {    64,   3,   7,   7,    1,   -7 }, // '1'
+	  {    67,   5,   7,   7,    1,   -7 }, // '2'
+	  {    72,   6,   7,   7,    0,   -7 }, // '3'
+	  {    78,   7,   7,   7,    0,   -7 }, // '4'
+	  {    85,   5,   7,   7,    1,   -7 }, // '5'
+	  {    90,   5,   7,   7,    1,   -7 }, // '6'
+	  {    95,   5,   7,   7,    1,   -7 }, // '7'
+	  {   100,   5,   7,   7,    1,   -7 }, // '8'
+	  {   105,   5,   7,   7,    1,   -7 }, // '9'
+	  {   110,   3,   5,   3,    0,   -5 }, // ':'
+	  {   112,   2,   6,   3,    0,   -5 }, // ';'
+	  {   114,   5,   5,   7,    1,   -6 }, // '<'
+	  {   118,   5,   3,   7,    1,   -5 }, // '='
+	  {   120,   5,   5,   7,    1,   -6 }, // '>'
+	  {   124,   5,   7,   5,    0,   -7 }, // '?'
+	  {   129,   8,   8,  10,    1,   -7 }, // '@'
+	  {   137,   7,   7,   7,    0,   -7 }, // 'A'
+	  {   144,   5,   7,   7,    1,   -7 }, // 'B'
+	  {   149,   6,   7,   7,    1,   -7 }, // 'C'
+	  {   155,   6,   7,   8,    1,   -7 }, // 'D'
+	  {   161,   5,   7,   7,    1,   -7 }, // 'E'
+	  {   166,   5,   7,   6,    1,   -7 }, // 'F'
+	  {   171,   6,   7,   8,    1,   -7 }, // 'G'
+	  {   177,   6,   7,   8,    1,   -7 }, // 'H'
+	  {   183,   2,   7,   4,    1,   -7 }, // 'I'
+	  {   185,   3,   9,   3,   -1,   -7 }, // 'J'
+	  {   189,   6,   7,   7,    1,   -7 }, // 'K'
+	  {   195,   5,   7,   6,    1,   -7 }, // 'L'
+	  {   200,   8,   7,  10,    1,   -7 }, // 'M'
+	  {   207,   6,   7,   8,    1,   -7 }, // 'N'
+	  {   213,   7,   7,   9,    1,   -7 }, // 'O'
+	  {   220,   5,   7,   7,    1,   -7 }, // 'P'
+	  {   225,   7,   9,   9,    1,   -7 }, // 'Q'
+	  {   233,   6,   7,   7,    1,   -7 }, // 'R'
+	  {   239,   5,   7,   6,    1,   -7 }, // 'S'
+	  {   244,   6,   7,   6,    0,   -7 }, // 'T'
+	  {   250,   6,   7,   8,    1,   -7 }, // 'U'
+	  {   256,   7,   7,   7,    0,   -7 }, // 'V'
+	  {   263,  10,   7,  10,    0,   -7 }, // 'W'
+	  {   272,   6,   7,   6,    0,   -7 }, // 'X'
+	  {   278,   6,   7,   6,    0,   -7 }, // 'Y'
+	  {   284,   7,   7,   7,    0,   -7 }, // 'Z'
+	  {   291,   3,   9,   4,    1,   -7 }, // '['
+	  {   295,   4,   7,   4,    0,   -7 }, // '\'
+	  {   299,   3,   9,   4,    0,   -7 }, // ']'
+	  {   303,   7,   4,   7,    0,   -7 }, // '^'
+	  {   307,   5,   1,   5,    0,    1 }, // '_'
+	  {   308,   3,   2,   7,    2,   -8 }, // '`'
+	  {   309,   5,   5,   6,    0,   -5 }, // 'a'
+	  {   313,   5,   7,   7,    1,   -7 }, // 'b'
+	  {   318,   5,   5,   6,    1,   -5 }, // 'c'
+	  {   322,   5,   7,   7,    1,   -7 }, // 'd'
+	  {   327,   4,   5,   6,    1,   -5 }, // 'e'
+	  {   330,   5,   7,   4,    0,   -7 }, // 'f'
+	  {   335,   6,   7,   6,    0,   -5 }, // 'g'
+	  {   341,   5,   7,   7,    1,   -7 }, // 'h'
+	  {   346,   3,   7,   3,    0,   -7 }, // 'i'
+	  {   349,   3,   9,   3,   -1,   -7 }, // 'j'
+	  {   353,   5,   7,   6,    1,   -7 }, // 'k'
+	  {   358,   3,   7,   3,    0,   -7 }, // 'l'
+	  {   361,   8,   5,  10,    1,   -5 }, // 'm'
+	  {   366,   5,   5,   7,    1,   -5 }, // 'n'
+	  {   370,   5,   5,   7,    1,   -5 }, // 'o'
+	  {   374,   5,   7,   7,    1,   -5 }, // 'p'
+	  {   379,   5,   7,   7,    1,   -5 }, // 'q'
+	  {   384,   4,   5,   5,    1,   -5 }, // 'r'
+	  {   387,   5,   5,   6,    0,   -5 }, // 's'
+	  {   391,   4,   6,   4,    0,   -6 }, // 't'
+	  {   394,   5,   5,   7,    1,   -5 }, // 'u'
+	  {   398,   6,   5,   6,    0,   -5 }, // 'v'
+	  {   402,   8,   5,   8,    0,   -5 }, // 'w'
+	  {   407,   6,   5,   6,    0,   -5 }, // 'x'
+	  {   411,   6,   7,   6,    0,   -5 }, // 'y'
+	  {   417,   6,   5,   6,    0,   -5 }, // 'z'
+	  {   421,   5,   9,   5,    0,   -7 }, // '{'
+	  {   427,   2,   9,   6,    2,   -7 }, // '|'
+	  {   430,   5,   9,   5,    0,   -7 } // '}'
+};
+
+const GFXglyph OpenSansLight12Glyphs[] = {
+// bitmapOffset, width, height, xAdvance, xOffset, yOffset
+	  {     0,   1,   1,   4,    0,    0 }, // ' '
+	  {     1,   2,   9,   4,    1,   -9 }, // '!'
+	  {     4,   3,   3,   5,    1,   -9 }, // '"'
+	  {     6,   9,   9,   9,    0,   -9 }, // '#'
+	  {    17,   6,  10,   8,    1,   -9 }, // '$'
+	  {    25,   9,   9,  11,    1,   -9 }, // '%'
+	  {    36,   9,   9,  10,    1,   -9 }, // '&'
+	  {    47,   3,   3,   3,    0,   -9 }, // '''
+	  {    49,   4,  11,   4,    0,   -9 }, // '('
+	  {    55,   4,  11,   4,    0,   -9 }, // ')'
+	  {    61,   6,   5,   8,    1,   -9 }, // '*'
+	  {    65,   6,   7,   8,    1,   -8 }, // '+'
+	  {    71,   3,   3,   4,    0,   -1 }, // ','
+	  {    73,   3,   1,   5,    1,   -3 }, // '-'
+	  {    74,   2,   1,   4,    1,   -1 }, // '.'
+	  {    75,   5,   9,   5,    0,   -9 }, // '/'
+	  {    81,   6,   9,   8,    1,   -9 }, // '0'
+	  {    88,   4,   9,   8,    1,   -9 }, // '1'
+	  {    93,   6,   9,   8,    1,   -9 }, // '2'
+	  {   100,   6,   9,   8,    1,   -9 }, // '3'
+	  {   107,   8,   9,   8,    0,   -9 }, // '4'
+	  {   116,   6,   9,   8,    1,   -9 }, // '5'
+	  {   123,   6,   9,   8,    1,   -9 }, // '6'
+	  {   130,   6,   9,   8,    1,   -9 }, // '7'
+	  {   137,   6,   9,   8,    1,   -9 }, // '8'
+	  {   144,   6,   9,   8,    1,   -9 }, // '9'
+	  {   151,   2,   6,   4,    1,   -6 }, // ':'
+	  {   153,   3,   8,   4,    0,   -6 }, // ';'
+	  {   156,   6,   6,   8,    1,   -8 }, // '<'
+	  {   161,   6,   3,   8,    1,   -6 }, // '='
+	  {   164,   6,   6,   8,    1,   -8 }, // '>'
+	  {   169,   6,   9,   6,    0,   -9 }, // '?'
+	  {   176,  10,  10,  12,    1,   -9 }, // '@'
+	  {   189,   8,   9,   8,    0,   -9 }, // 'A'
+	  {   198,   7,   9,   9,    1,   -9 }, // 'B'
+	  {   206,   7,   9,   8,    1,   -9 }, // 'C'
+	  {   214,   7,   9,   9,    1,   -9 }, // 'D'
+	  {   222,   6,   9,   8,    1,   -9 }, // 'E'
+	  {   229,   6,   9,   7,    1,   -9 }, // 'F'
+	  {   236,   8,   9,  10,    1,   -9 }, // 'G'
+	  {   245,   8,   9,  10,    1,   -9 }, // 'H'
+	  {   254,   2,   9,   4,    1,   -9 }, // 'I'
+	  {   257,   4,  11,   4,   -1,   -9 }, // 'J'
+	  {   263,   7,   9,   8,    1,   -9 }, // 'K'
+	  {   271,   6,   9,   7,    1,   -9 }, // 'L'
+	  {   278,   9,   9,  11,    1,   -9 }, // 'M'
+	  {   289,   8,   9,  10,    1,   -9 }, // 'N'
+	  {   298,   8,   9,  10,    1,   -9 }, // 'O'
+	  {   307,   6,   9,   8,    1,   -9 }, // 'P'
+	  {   314,   8,  11,  10,    1,   -9 }, // 'Q'
+	  {   325,   7,   9,   8,    1,   -9 }, // 'R'
+	  {   333,   6,   9,   8,    1,   -9 }, // 'S'
+	  {   340,   7,   9,   7,    0,   -9 }, // 'T'
+	  {   348,   8,   9,  10,    1,   -9 }, // 'U'
+	  {   357,   8,   9,   8,    0,   -9 }, // 'V'
+	  {   366,  12,   9,  12,    0,   -9 }, // 'W'
+	  {   380,   7,   9,   7,    0,   -9 }, // 'X'
+	  {   388,   7,   9,   7,    0,   -9 }, // 'Y'
+	  {   396,   8,   9,   8,    0,   -9 }, // 'Z'
+	  {   405,   4,  11,   5,    1,   -9 }, // '['
+	  {   411,   5,   9,   5,    0,   -9 }, // '\'
+	  {   417,   4,  11,   5,    0,   -9 }, // ']'
+	  {   423,   6,   5,   8,    1,   -9 }, // '^'
+	  {   427,   6,   1,   6,    0,    1 }, // '_'
+	  {   428,   4,   2,   8,    2,   -9 }, // '`'
+	  {   429,   5,   6,   7,    1,   -6 }, // 'a'
+	  {   433,   6,   9,   8,    1,   -9 }, // 'b'
+	  {   440,   6,   6,   7,    1,   -6 }, // 'c'
+	  {   445,   6,   9,   8,    1,   -9 }, // 'd'
+	  {   452,   6,   6,   8,    1,   -6 }, // 'e'
+	  {   457,   5,   9,   5,    0,   -9 }, // 'f'
+	  {   463,   7,   9,   7,    0,   -6 }, // 'g'
+	  {   471,   6,   9,   8,    1,   -9 }, // 'h'
+	  {   478,   2,   9,   4,    1,   -9 }, // 'i'
+	  {   481,   3,  12,   4,    0,   -9 }, // 'j'
+	  {   486,   6,   9,   7,    1,   -9 }, // 'k'
+	  {   493,   2,   9,   4,    1,   -9 }, // 'l'
+	  {   496,  10,   6,  12,    1,   -6 }, // 'm'
+	  {   504,   6,   6,   8,    1,   -6 }, // 'n'
+	  {   509,   6,   6,   8,    1,   -6 }, // 'o'
+	  {   514,   6,   9,   8,    1,   -6 }, // 'p'
+	  {   521,   6,   9,   8,    1,   -6 }, // 'q'
+	  {   528,   5,   6,   6,    1,   -6 }, // 'r'
+	  {   532,   5,   6,   7,    1,   -6 }, // 's'
+	  {   536,   5,   8,   5,    0,   -8 }, // 't'
+	  {   541,   6,   6,   8,    1,   -6 }, // 'u'
+	  {   546,   7,   6,   7,    0,   -6 }, // 'v'
+	  {   552,  10,   6,  10,    0,   -6 }, // 'w'
+	  {   560,   7,   6,   7,    0,   -6 }, // 'x'
+	  {   566,   7,   9,   7,    0,   -6 }, // 'y'
+	  {   574,   5,   6,   7,    1,   -6 }, // 'z'
+	  {   578,   5,  11,   5,    0,   -9 }, // '{'
+	  {   585,   2,  12,   8,    3,   -9 }, // '|'
+	  {   588,   5,  11,   5,    0,   -9 } // '}'
+};
+
+const GFXglyph OpenSansLight14Glyphs[] = {
+// bitmapOffset, width, height, xAdvance, xOffset, yOffset
+	  {     0,   1,   1,   5,    0,    0 }, // ' '
+	  {     1,   2,  10,   4,    1,  -10 }, // '!'
+	  {     4,   4,   4,   6,    1,  -10 }, // '"'
+	  {     6,  10,  10,  10,    0,  -10 }, // '#'
+	  {    19,   7,  12,   9,    1,  -11 }, // '$'
+	  {    30,  10,  10,  12,    1,  -10 }, // '%'
+	  {    43,  10,  10,  11,    1,  -10 }, // '&'
+	  {    56,   2,   4,   4,    1,  -10 }, // '''
+	  {    57,   4,  12,   5,    1,  -10 }, // '('
+	  {    63,   4,  12,   5,    0,  -10 }, // ')'
+	  {    69,   7,   6,   9,    1,  -11 }, // '*'
+	  {    75,   7,   7,   9,    1,   -9 }, // '+'
+	  {    82,   3,   4,   4,    0,   -2 }, // ','
+	  {    84,   4,   1,   6,    1,   -4 }, // '-'
+	  {    85,   2,   1,   4,    1,   -1 }, // '.'
+	  {    86,   6,  10,   6,    0,  -10 }, // '/'
+	  {    94,   7,  10,   9,    1,  -10 }, // '0'
+	  {   103,   5,  10,   9,    1,  -10 }, // '1'
+	  {   110,   7,  10,   9,    1,  -10 }, // '2'
+	  {   119,   7,  10,   9,    1,  -10 }, // '3'
+	  {   128,   9,  10,   9,    0,  -10 }, // '4'
+	  {   140,   7,  10,   9,    1,  -10 }, // '5'
+	  {   149,   7,  10,   9,    1,  -10 }, // '6'
+	  {   158,   7,  10,   9,    1,  -10 }, // '7'
+	  {   167,   7,  10,   9,    1,  -10 }, // '8'
+	  {   176,   7,  10,   9,    1,  -10 }, // '9'
+	  {   185,   2,   8,   4,    1,   -8 }, // ':'
+	  {   187,   3,  10,   4,    0,   -8 }, // ';'
+	  {   191,   7,   7,   9,    1,   -9 }, // '<'
+	  {   198,   7,   3,   9,    1,   -7 }, // '='
+	  {   201,   7,   7,   9,    1,   -9 }, // '>'
+	  {   208,   6,  10,   7,    0,  -10 }, // '?'
+	  {   216,  11,  11,  13,    1,  -10 }, // '@'
+	  {   232,   9,  10,   9,    0,  -10 }, // 'A'
+	  {   244,   8,  10,  10,    1,  -10 }, // 'B'
+	  {   254,   9,  10,  10,    1,  -10 }, // 'C'
+	  {   266,   9,  10,  11,    1,  -10 }, // 'D'
+	  {   278,   7,  10,   9,    1,  -10 }, // 'E'
+	  {   287,   7,  10,   8,    1,  -10 }, // 'F'
+	  {   296,   9,  10,  11,    1,  -10 }, // 'G'
+	  {   308,   9,  10,  11,    1,  -10 }, // 'H'
+	  {   320,   3,  10,   5,    1,  -10 }, // 'I'
+	  {   324,   4,  13,   4,   -1,  -10 }, // 'J'
+	  {   331,   8,  10,   9,    1,  -10 }, // 'K'
+	  {   341,   7,  10,   8,    1,  -10 }, // 'L'
+	  {   350,  11,  10,  13,    1,  -10 }, // 'M'
+	  {   364,   9,  10,  11,    1,  -10 }, // 'N'
+	  {   376,  10,  10,  12,    1,  -10 }, // 'O'
+	  {   389,   7,  10,   9,    1,  -10 }, // 'P'
+	  {   398,  10,  12,  12,    1,  -10 }, // 'Q'
+	  {   413,   8,  10,   9,    1,  -10 }, // 'R'
+	  {   423,   7,  10,   9,    1,  -10 }, // 'S'
+	  {   432,   8,  10,   8,    0,  -10 }, // 'T'
+	  {   442,   9,  10,  11,    1,  -10 }, // 'U'
+	  {   454,   9,  10,   9,    0,  -10 }, // 'V'
+	  {   466,  13,  10,  13,    0,  -10 }, // 'W'
+	  {   483,   9,  10,   9,    0,  -10 }, // 'X'
+	  {   495,   8,  10,   8,    0,  -10 }, // 'Y'
+	  {   505,   7,  10,   9,    1,  -10 }, // 'Z'
+	  {   514,   4,  12,   5,    1,  -10 }, // '['
+	  {   520,   6,  10,   6,    0,  -10 }, // '\'
+	  {   528,   4,  12,   5,    0,  -10 }, // ']'
+	  {   534,   7,   6,   9,    1,  -10 }, // '^'
+	  {   540,   7,   1,   7,    0,    1 }, // '_'
+	  {   541,   3,   2,   9,    3,  -10 }, // '`'
+	  {   542,   6,   8,   8,    1,   -8 }, // 'a'
+	  {   548,   7,  11,   9,    1,  -11 }, // 'b'
+	  {   558,   6,   8,   8,    1,   -8 }, // 'c'
+	  {   564,   7,  11,   9,    1,  -11 }, // 'd'
+	  {   574,   7,   8,   9,    1,   -8 }, // 'e'
+	  {   581,   6,  11,   5,    0,  -11 }, // 'f'
+	  {   590,   8,  11,   8,    0,   -8 }, // 'g'
+	  {   601,   7,  11,   9,    1,  -11 }, // 'h'
+	  {   611,   2,  10,   4,    1,  -10 }, // 'i'
+	  {   614,   4,  13,   4,   -1,  -10 }, // 'j'
+	  {   621,   7,  11,   8,    1,  -11 }, // 'k'
+	  {   631,   2,  11,   4,    1,  -11 }, // 'l'
+	  {   634,  11,   8,  13,    1,   -8 }, // 'm'
+	  {   645,   7,   8,   9,    1,   -8 }, // 'n'
+	  {   652,   7,   8,   9,    1,   -8 }, // 'o'
+	  {   659,   7,  11,   9,    1,   -8 }, // 'p'
+	  {   669,   7,  11,   9,    1,   -8 }, // 'q'
+	  {   679,   5,   8,   6,    1,   -8 }, // 'r'
+	  {   684,   6,   8,   8,    1,   -8 }, // 's'
+	  {   690,   6,  10,   6,    0,  -10 }, // 't'
+	  {   698,   7,   8,   9,    1,   -8 }, // 'u'
+	  {   705,   7,   8,   7,    0,   -8 }, // 'v'
+	  {   712,  11,   8,  11,    0,   -8 }, // 'w'
+	  {   723,   8,   8,   8,    0,   -8 }, // 'x'
+	  {   731,   7,  11,   7,    0,   -8 }, // 'y'
+	  {   741,   5,   8,   7,    1,   -8 }, // 'z'
+	  {   746,   6,  12,   6,    0,  -10 }, // '{'
+	  {   755,   3,  14,   9,    3,  -11 }, // '|'
+	  {   761,   5,  12,   6,    1,  -10 } // '}'
+};
+
+
+const GFXglyph OpenSansLight16Glyphs[] = {
+// bitmapOffset, width, height, xAdvance, xOffset, yOffset
+	  {     0,   1,   1,   5,    0,    0 }, // ' '
+	  {     1,   3,  12,   5,    1,  -12 }, // '!'
+	  {     6,   5,   4,   7,    1,  -12 }, // '"'
+	  {     9,  11,  12,  11,    0,  -12 }, // '#'
+	  {    26,   8,  13,  10,    1,  -12 }, // '$'
+	  {    39,  12,  12,  14,    1,  -12 }, // '%'
+	  {    57,  11,  12,  12,    1,  -12 }, // '&'
+	  {    74,   2,   4,   4,    1,  -12 }, // '''
+	  {    75,   4,  15,   5,    1,  -12 }, // '('
+	  {    83,   4,  15,   5,    0,  -12 }, // ')'
+	  {    91,   8,   7,  10,    1,  -13 }, // '*'
+	  {    98,   8,   7,  10,    1,  -10 }, // '+'
+	  {   105,   3,   4,   4,    0,   -2 }, // ','
+	  {   107,   4,   1,   6,    1,   -5 }, // '-'
+	  {   108,   3,   2,   5,    1,   -2 }, // '.'
+	  {   109,   6,  12,   6,    0,  -12 }, // '/'
+	  {   118,   8,  12,  10,    1,  -12 }, // '0'
+	  {   130,   4,  12,  10,    2,  -12 }, // '1'
+	  {   136,   8,  12,  10,    1,  -12 }, // '2'
+	  {   148,   8,  12,  10,    1,  -12 }, // '3'
+	  {   160,  10,  12,  10,    0,  -12 }, // '4'
+	  {   175,   8,  12,  10,    1,  -12 }, // '5'
+	  {   187,   8,  12,  10,    1,  -12 }, // '6'
+	  {   199,   8,  12,  10,    1,  -12 }, // '7'
+	  {   211,   8,  12,  10,    1,  -12 }, // '8'
+	  {   223,   8,  12,  10,    1,  -12 }, // '9'
+	  {   235,   3,   9,   5,    1,   -9 }, // ':'
+	  {   239,   3,  11,   5,    1,   -9 }, // ';'
+	  {   244,   8,   7,  10,    1,  -10 }, // '<'
+	  {   251,   8,   4,  10,    1,   -8 }, // '='
+	  {   255,   8,   7,  10,    1,  -10 }, // '>'
+	  {   262,   7,  12,   8,    0,  -12 }, // '?'
+	  {   273,  13,  14,  15,    1,  -12 }, // '@'
+	  {   296,  11,  12,  11,    0,  -12 }, // 'A'
+	  {   313,   8,  12,  11,    2,  -12 }, // 'B'
+	  {   325,  10,  12,  11,    1,  -12 }, // 'C'
+	  {   340,   9,  12,  12,    2,  -12 }, // 'D'
+	  {   354,   7,  12,  10,    2,  -12 }, // 'E'
+	  {   365,   7,  12,   9,    2,  -12 }, // 'F'
+	  {   376,  11,  12,  13,    1,  -12 }, // 'G'
+	  {   393,   9,  12,  13,    2,  -12 }, // 'H'
+	  {   407,   3,  12,   5,    1,  -12 }, // 'I'
+	  {   412,   4,  15,   5,   -1,  -12 }, // 'J'
+	  {   420,   8,  12,  10,    2,  -12 }, // 'K'
+	  {   432,   7,  12,   9,    2,  -12 }, // 'L'
+	  {   443,  11,  12,  15,    2,  -12 }, // 'M'
+	  {   460,   9,  12,  13,    2,  -12 }, // 'N'
+	  {   474,  11,  12,  13,    1,  -12 }, // 'O'
+	  {   491,   7,  12,  10,    2,  -12 }, // 'P'
+	  {   502,  11,  15,  13,    1,  -12 }, // 'Q'
+	  {   523,   9,  12,  11,    2,  -12 }, // 'R'
+	  {   537,   8,  12,  10,    1,  -12 }, // 'S'
+	  {   549,   9,  12,   9,    0,  -12 }, // 'T'
+	  {   563,   9,  12,  13,    2,  -12 }, // 'U'
+	  {   577,  10,  12,  10,    0,  -12 }, // 'V'
+	  {   592,  15,  12,  15,    0,  -12 }, // 'W'
+	  {   615,  10,  12,  10,    0,  -12 }, // 'X'
+	  {   630,   9,  12,   9,    0,  -12 }, // 'Y'
+	  {   644,   8,  12,  10,    1,  -12 }, // 'Z'
+	  {   656,   5,  15,   6,    1,  -12 }, // '['
+	  {   666,   6,  12,   6,    0,  -12 }, // '\'
+	  {   675,   5,  15,   6,    0,  -12 }, // ']'
+	  {   685,   8,   7,  10,    1,  -12 }, // '^'
+	  {   692,   8,   1,   8,    0,    1 }, // '_'
+	  {   693,   4,   3,  10,    3,  -13 }, // '`'
+	  {   695,   7,   9,   9,    1,   -9 }, // 'a'
+	  {   703,   8,  13,  11,    2,  -13 }, // 'b'
+	  {   716,   7,   9,   9,    1,   -9 }, // 'c'
+	  {   724,   9,  13,  11,    1,  -13 }, // 'd'
+	  {   739,   8,   9,  10,    1,   -9 }, // 'e'
+	  {   748,   7,  13,   6,    0,  -13 }, // 'f'
+	  {   760,   9,  13,   9,    0,   -9 }, // 'g'
+	  {   775,   8,  13,  10,    1,  -13 }, // 'h'
+	  {   788,   2,  12,   5,    1,  -12 }, // 'i'
+	  {   791,   4,  16,   5,   -1,  -12 }, // 'j'
+	  {   799,   8,  13,   9,    1,  -13 }, // 'k'
+	  {   812,   3,  13,   5,    1,  -13 }, // 'l'
+	  {   817,  13,   9,  15,    1,   -9 }, // 'm'
+	  {   832,   8,   9,  10,    1,   -9 }, // 'n'
+	  {   841,   8,   9,  10,    1,   -9 }, // 'o'
+	  {   850,   8,  13,  11,    2,   -9 }, // 'p'
+	  {   863,   9,  13,  11,    1,   -9 }, // 'q'
+	  {   878,   6,   9,   7,    1,   -9 }, // 'r'
+	  {   885,   6,   9,   8,    1,   -9 }, // 's'
+	  {   892,   6,  11,   6,    0,  -11 }, // 't'
+	  {   901,   8,   9,  10,    1,   -9 }, // 'u'
+	  {   910,   8,   9,   8,    0,   -9 }, // 'v'
+	  {   919,  13,   9,  13,    0,   -9 }, // 'w'
+	  {   934,   9,   9,   9,    0,   -9 }, // 'x'
+	  {   945,   8,  13,   8,    0,   -9 }, // 'y'
+	  {   958,   6,   9,   8,    1,   -9 }, // 'z'
+	  {   965,   5,  15,   7,    1,  -12 }, // '{'
+	  {   975,   2,  17,  10,    4,  -13 }, // '|'
+	  {   980,   6,  15,   7,    1,  -12 } // '}'
+};
+
+const GFXglyph Org_01Glyphs[] = {
+	{0, 0, 0, 6, 0, 1},     // 0x20 ' '
+	{0, 1, 5, 2, 0, -4},    // 0x21 '!'
+	{1, 3, 1, 4, 0, -4},    // 0x22 '"'
+	{2, 5, 5, 6, 0, -4},    // 0x23 '#'
+	{6, 5, 5, 6, 0, -4},    // 0x24 '$'
+	{10, 5, 5, 6, 0, -4},   // 0x25 '%'
+	{14, 5, 5, 6, 0, -4},   // 0x26 '&'
+	{18, 1, 1, 2, 0, -4},   // 0x27 '''
+	{19, 2, 5, 3, 0, -4},   // 0x28 '('
+	{21, 2, 5, 3, 0, -4},   // 0x29 ')'
+	{23, 3, 3, 4, 0, -3},   // 0x2A '*'
+	{25, 3, 3, 4, 0, -3},   // 0x2B '+'
+	{27, 1, 2, 2, 0, 0},    // 0x2C ','
+	{28, 4, 1, 5, 0, -2},   // 0x2D '-'
+	{29, 1, 1, 2, 0, 0},    // 0x2E '.'
+	{30, 5, 5, 6, 0, -4},   // 0x2F '/'
+	{34, 5, 5, 6, 0, -4},   // 0x30 '0'
+	{38, 1, 5, 2, 0, -4},   // 0x31 '1'
+	{39, 5, 5, 6, 0, -4},   // 0x32 '2'
+	{43, 5, 5, 6, 0, -4},   // 0x33 '3'
+	{47, 5, 5, 6, 0, -4},   // 0x34 '4'
+	{51, 5, 5, 6, 0, -4},   // 0x35 '5'
+	{55, 5, 5, 6, 0, -4},   // 0x36 '6'
+	{59, 5, 5, 6, 0, -4},   // 0x37 '7'
+	{63, 5, 5, 6, 0, -4},   // 0x38 '8'
+	{67, 5, 5, 6, 0, -4},   // 0x39 '9'
+	{71, 1, 4, 2, 0, -3},   // 0x3A ':'
+	{72, 1, 4, 2, 0, -3},   // 0x3B ';'
+	{73, 3, 5, 4, 0, -4},   // 0x3C '<'
+	{75, 4, 3, 5, 0, -3},   // 0x3D '='
+	{77, 3, 5, 4, 0, -4},   // 0x3E '>'
+	{79, 5, 5, 6, 0, -4},   // 0x3F '?'
+	{83, 5, 5, 6, 0, -4},   // 0x40 '@'
+	{87, 5, 5, 6, 0, -4},   // 0x41 'A'
+	{91, 5, 5, 6, 0, -4},   // 0x42 'B'
+	{95, 5, 5, 6, 0, -4},   // 0x43 'C'
+	{99, 5, 5, 6, 0, -4},   // 0x44 'D'
+	{103, 5, 5, 6, 0, -4},  // 0x45 'E'
+	{107, 5, 5, 6, 0, -4},  // 0x46 'F'
+	{111, 5, 5, 6, 0, -4},  // 0x47 'G'
+	{115, 5, 5, 6, 0, -4},  // 0x48 'H'
+	{119, 5, 5, 6, 0, -4},  // 0x49 'I'
+	{123, 5, 5, 6, 0, -4},  // 0x4A 'J'
+	{127, 5, 5, 6, 0, -4},  // 0x4B 'K'
+	{131, 5, 5, 6, 0, -4},  // 0x4C 'L'
+	{135, 5, 5, 6, 0, -4},  // 0x4D 'M'
+	{139, 5, 5, 6, 0, -4},  // 0x4E 'N'
+	{143, 5, 5, 6, 0, -4},  // 0x4F 'O'
+	{147, 5, 5, 6, 0, -4},  // 0x50 'P'
+	{151, 5, 5, 6, 0, -4},  // 0x51 'Q'
+	{155, 5, 5, 6, 0, -4},  // 0x52 'R'
+	{159, 5, 5, 6, 0, -4},  // 0x53 'S'
+	{163, 5, 5, 6, 0, -4},  // 0x54 'T'
+	{167, 5, 5, 6, 0, -4},  // 0x55 'U'
+	{171, 5, 5, 6, 0, -4},  // 0x56 'V'
+	{175, 5, 5, 6, 0, -4},  // 0x57 'W'
+	{179, 5, 5, 6, 0, -4},  // 0x58 'X'
+	{183, 5, 5, 6, 0, -4},  // 0x59 'Y'
+	{187, 5, 5, 6, 0, -4},  // 0x5A 'Z'
+	{191, 2, 5, 3, 0, -4},  // 0x5B '['
+	{193, 5, 5, 6, 0, -4},  // 0x5C '\'
+	{197, 2, 5, 3, 0, -4},  // 0x5D ']'
+	{199, 3, 2, 4, 0, -4},  // 0x5E '^'
+	{200, 5, 1, 6, 0, 1},   // 0x5F '_'
+	{201, 1, 1, 2, 0, -4},  // 0x60 '`'
+	{202, 4, 4, 5, 0, -3},  // 0x61 'a'
+	{204, 4, 5, 5, 0, -4},  // 0x62 'b'
+	{207, 4, 4, 5, 0, -3},  // 0x63 'c'
+	{209, 4, 5, 5, 0, -4},  // 0x64 'd'
+	{212, 4, 4, 5, 0, -3},  // 0x65 'e'
+	{214, 3, 5, 4, 0, -4},  // 0x66 'f'
+	{216, 4, 5, 5, 0, -3},  // 0x67 'g'
+	{219, 4, 5, 5, 0, -4},  // 0x68 'h'
+	{222, 1, 4, 2, 0, -3},  // 0x69 'i'
+	{223, 2, 5, 3, 0, -3},  // 0x6A 'j'
+	{225, 4, 5, 5, 0, -4},  // 0x6B 'k'
+	{228, 1, 5, 2, 0, -4},  // 0x6C 'l'
+	{229, 5, 4, 6, 0, -3},  // 0x6D 'm'
+	{232, 4, 4, 5, 0, -3},  // 0x6E 'n'
+	{234, 4, 4, 5, 0, -3},  // 0x6F 'o'
+	{236, 4, 5, 5, 0, -3},  // 0x70 'p'
+	{239, 4, 5, 5, 0, -3},  // 0x71 'q'
+	{242, 4, 4, 5, 0, -3},  // 0x72 'r'
+	{244, 4, 4, 5, 0, -3},  // 0x73 's'
+	{246, 5, 5, 6, 0, -4},  // 0x74 't'
+	{250, 4, 4, 5, 0, -3},  // 0x75 'u'
+	{252, 4, 4, 5, 0, -3},  // 0x76 'v'
+	{254, 5, 4, 6, 0, -3},  // 0x77 'w'
+	{257, 4, 4, 5, 0, -3},  // 0x78 'x'
+	{259, 4, 5, 5, 0, -3},  // 0x79 'y'
+	{262, 4, 4, 5, 0, -3},  // 0x7A 'z'
+	{264, 3, 5, 4, 0, -4},  // 0x7B '{'
+	{266, 1, 5, 2, 0, -4},  // 0x7C '|'
+	{267, 3, 5, 4, 0, -4},  // 0x7D '}'
+	{269, 5, 3, 6, 0, -3}}; // 0x7E '~'
+
+
+/* {offset, width, height, advance cursor, x offset, y offset} */
+const GFXglyph TomThumbGlyphs[] = {
+    {0, 8, 1, 2, 0, -5},   /* 0x20 space */
+    {1, 8, 5, 2, 0, -5},   /* 0x21 exclam */
+    {6, 8, 2, 4, 0, -5},   /* 0x22 quotedbl */
+    {8, 8, 5, 4, 0, -5},   /* 0x23 numbersign */
+    {13, 8, 5, 4, 0, -5},  /* 0x24 dollar */
+    {18, 8, 5, 4, 0, -5},  /* 0x25 percent */
+    {23, 8, 5, 4, 0, -5},  /* 0x26 ampersand */
+    {28, 8, 2, 2, 0, -5},  /* 0x27 quotesingle */
+    {30, 8, 5, 3, 0, -5},  /* 0x28 parenleft */
+    {35, 8, 5, 3, 0, -5},  /* 0x29 parenright */
+    {40, 8, 3, 4, 0, -5},  /* 0x2A asterisk */
+    {43, 8, 3, 4, 0, -4},  /* 0x2B plus */
+    {46, 8, 2, 3, 0, -2},  /* 0x2C comma */
+    {48, 8, 1, 4, 0, -3},  /* 0x2D hyphen */
+    {49, 8, 1, 2, 0, -1},  /* 0x2E period */
+    {50, 8, 5, 4, 0, -5},  /* 0x2F slash */
+    {55, 8, 5, 4, 0, -5},  /* 0x30 zero */
+    {60, 8, 5, 3, 0, -5},  /* 0x31 one */
+    {65, 8, 5, 4, 0, -5},  /* 0x32 two */
+    {70, 8, 5, 4, 0, -5},  /* 0x33 three */
+    {75, 8, 5, 4, 0, -5},  /* 0x34 four */
+    {80, 8, 5, 4, 0, -5},  /* 0x35 five */
+    {85, 8, 5, 4, 0, -5},  /* 0x36 six */
+    {90, 8, 5, 4, 0, -5},  /* 0x37 seven */
+    {95, 8, 5, 4, 0, -5},  /* 0x38 eight */
+    {100, 8, 5, 4, 0, -5}, /* 0x39 nine */
+    {105, 8, 3, 2, 0, -4}, /* 0x3A colon */
+    {108, 8, 4, 3, 0, -4}, /* 0x3B semicolon */
+    {112, 8, 5, 4, 0, -5}, /* 0x3C less */
+    {117, 8, 3, 4, 0, -4}, /* 0x3D equal */
+    {120, 8, 5, 4, 0, -5}, /* 0x3E greater */
+    {125, 8, 5, 4, 0, -5}, /* 0x3F question */
+    {130, 8, 5, 4, 0, -5}, /* 0x40 at */
+    {135, 8, 5, 4, 0, -5}, /* 0x41 A */
+    {140, 8, 5, 4, 0, -5}, /* 0x42 B */
+    {145, 8, 5, 4, 0, -5}, /* 0x43 C */
+    {150, 8, 5, 4, 0, -5}, /* 0x44 D */
+    {155, 8, 5, 4, 0, -5}, /* 0x45 E */
+    {160, 8, 5, 4, 0, -5}, /* 0x46 F */
+    {165, 8, 5, 4, 0, -5}, /* 0x47 G */
+    {170, 8, 5, 4, 0, -5}, /* 0x48 H */
+    {175, 8, 5, 4, 0, -5}, /* 0x49 I */
+    {180, 8, 5, 4, 0, -5}, /* 0x4A J */
+    {185, 8, 5, 4, 0, -5}, /* 0x4B K */
+    {190, 8, 5, 4, 0, -5}, /* 0x4C L */
+    {195, 8, 5, 4, 0, -5}, /* 0x4D M */
+    {200, 8, 5, 4, 0, -5}, /* 0x4E N */
+    {205, 8, 5, 4, 0, -5}, /* 0x4F O */
+    {210, 8, 5, 4, 0, -5}, /* 0x50 P */
+    {215, 8, 5, 4, 0, -5}, /* 0x51 Q */
+    {220, 8, 5, 4, 0, -5}, /* 0x52 R */
+    {225, 8, 5, 4, 0, -5}, /* 0x53 S */
+    {230, 8, 5, 4, 0, -5}, /* 0x54 T */
+    {235, 8, 5, 4, 0, -5}, /* 0x55 U */
+    {240, 8, 5, 4, 0, -5}, /* 0x56 V */
+    {245, 8, 5, 4, 0, -5}, /* 0x57 W */
+    {250, 8, 5, 4, 0, -5}, /* 0x58 X */
+    {255, 8, 5, 4, 0, -5}, /* 0x59 Y */
+    {260, 8, 5, 4, 0, -5}, /* 0x5A Z */
+    {265, 8, 5, 4, 0, -5}, /* 0x5B bracketleft */
+    {270, 8, 3, 4, 0, -4}, /* 0x5C backslash */
+    {273, 8, 5, 4, 0, -5}, /* 0x5D bracketright */
+    {278, 8, 2, 4, 0, -5}, /* 0x5E asciicircum */
+    {280, 8, 1, 4, 0, -1}, /* 0x5F underscore */
+    {281, 8, 2, 3, 0, -5}, /* 0x60 grave */
+    {283, 8, 4, 4, 0, -4}, /* 0x61 a */
+    {287, 8, 5, 4, 0, -5}, /* 0x62 b */
+    {292, 8, 4, 4, 0, -4}, /* 0x63 c */
+    {296, 8, 5, 4, 0, -5}, /* 0x64 d */
+    {301, 8, 4, 4, 0, -4}, /* 0x65 e */
+    {305, 8, 5, 4, 0, -5}, /* 0x66 f */
+    {310, 8, 5, 4, 0, -4}, /* 0x67 g */
+    {315, 8, 5, 4, 0, -5}, /* 0x68 h */
+    {320, 8, 5, 2, 0, -5}, /* 0x69 i */
+    {325, 8, 6, 4, 0, -5}, /* 0x6A j */
+    {331, 8, 5, 4, 0, -5}, /* 0x6B k */
+    {336, 8, 5, 4, 0, -5}, /* 0x6C l */
+    {341, 8, 4, 4, 0, -4}, /* 0x6D m */
+    {345, 8, 4, 4, 0, -4}, /* 0x6E n */
+    {349, 8, 4, 4, 0, -4}, /* 0x6F o */
+    {353, 8, 5, 4, 0, -4}, /* 0x70 p */
+    {358, 8, 5, 4, 0, -4}, /* 0x71 q */
+    {363, 8, 4, 4, 0, -4}, /* 0x72 r */
+    {367, 8, 4, 4, 0, -4}, /* 0x73 s */
+    {371, 8, 5, 4, 0, -5}, /* 0x74 t */
+    {376, 8, 4, 4, 0, -4}, /* 0x75 u */
+    {380, 8, 4, 4, 0, -4}, /* 0x76 v */
+    {384, 8, 4, 4, 0, -4}, /* 0x77 w */
+    {388, 8, 4, 4, 0, -4}, /* 0x78 x */
+    {392, 8, 5, 4, 0, -4}, /* 0x79 y */
+    {397, 8, 4, 4, 0, -4}, /* 0x7A z */
+    {401, 8, 5, 4, 0, -5}, /* 0x7B braceleft */
+    {406, 8, 5, 2, 0, -5}, /* 0x7C bar */
+    {411, 8, 5, 4, 0, -5}, /* 0x7D braceright */
+    {416, 8, 2, 4, 0, -5}, /* 0x7E asciitilde */
+#if 0 //(TOMTHUMB_USE_EXTENDED)
+    {418, 8, 5, 2, 0, -5}, /* 0xA1 exclamdown */
+    {423, 8, 5, 4, 0, -5}, /* 0xA2 cent */
+    {428, 8, 5, 4, 0, -5}, /* 0xA3 sterling */
+    {433, 8, 5, 4, 0, -5}, /* 0xA4 currency */
+    {438, 8, 5, 4, 0, -5}, /* 0xA5 yen */
+    {443, 8, 5, 2, 0, -5}, /* 0xA6 brokenbar */
+    {448, 8, 5, 4, 0, -5}, /* 0xA7 section */
+    {453, 8, 1, 4, 0, -5}, /* 0xA8 dieresis */
+    {454, 8, 3, 4, 0, -5}, /* 0xA9 copyright */
+    {457, 8, 5, 4, 0, -5}, /* 0xAA ordfeminine */
+    {462, 8, 3, 3, 0, -5}, /* 0xAB guillemotleft */
+    {465, 8, 2, 4, 0, -4}, /* 0xAC logicalnot */
+    {467, 8, 1, 3, 0, -3}, /* 0xAD softhyphen */
+    {468, 8, 3, 4, 0, -5}, /* 0xAE registered */
+    {471, 8, 1, 4, 0, -5}, /* 0xAF macron */
+    {472, 8, 3, 4, 0, -5}, /* 0xB0 degree */
+    {475, 8, 5, 4, 0, -5}, /* 0xB1 plusminus */
+    {480, 8, 3, 4, 0, -5}, /* 0xB2 twosuperior */
+    {483, 8, 3, 4, 0, -5}, /* 0xB3 threesuperior */
+    {486, 8, 2, 3, 0, -5}, /* 0xB4 acute */
+    {488, 8, 5, 4, 0, -5}, /* 0xB5 mu */
+    {493, 8, 5, 4, 0, -5}, /* 0xB6 paragraph */
+    {498, 8, 3, 4, 0, -4}, /* 0xB7 periodcentered */
+    {501, 8, 3, 4, 0, -3}, /* 0xB8 cedilla */
+    {504, 8, 3, 2, 0, -5}, /* 0xB9 onesuperior */
+    {507, 8, 5, 4, 0, -5}, /* 0xBA ordmasculine */
+    {512, 8, 3, 3, 0, -5}, /* 0xBB guillemotright */
+    {515, 8, 5, 4, 0, -5}, /* 0xBC onequarter */
+    {520, 8, 5, 4, 0, -5}, /* 0xBD onehalf */
+    {525, 8, 5, 4, 0, -5}, /* 0xBE threequarters */
+    {530, 8, 5, 4, 0, -5}, /* 0xBF questiondown */
+    {535, 8, 5, 4, 0, -5}, /* 0xC0 Agrave */
+    {540, 8, 5, 4, 0, -5}, /* 0xC1 Aacute */
+    {545, 8, 5, 4, 0, -5}, /* 0xC2 Acircumflex */
+    {550, 8, 5, 4, 0, -5}, /* 0xC3 Atilde */
+    {555, 8, 5, 4, 0, -5}, /* 0xC4 Adieresis */
+    {560, 8, 5, 4, 0, -5}, /* 0xC5 Aring */
+    {565, 8, 5, 4, 0, -5}, /* 0xC6 AE */
+    {570, 8, 6, 4, 0, -5}, /* 0xC7 Ccedilla */
+    {576, 8, 5, 4, 0, -5}, /* 0xC8 Egrave */
+    {581, 8, 5, 4, 0, -5}, /* 0xC9 Eacute */
+    {586, 8, 5, 4, 0, -5}, /* 0xCA Ecircumflex */
+    {591, 8, 5, 4, 0, -5}, /* 0xCB Edieresis */
+    {596, 8, 5, 4, 0, -5}, /* 0xCC Igrave */
+    {601, 8, 5, 4, 0, -5}, /* 0xCD Iacute */
+    {606, 8, 5, 4, 0, -5}, /* 0xCE Icircumflex */
+    {611, 8, 5, 4, 0, -5}, /* 0xCF Idieresis */
+    {616, 8, 5, 4, 0, -5}, /* 0xD0 Eth */
+    {621, 8, 5, 4, 0, -5}, /* 0xD1 Ntilde */
+    {626, 8, 5, 4, 0, -5}, /* 0xD2 Ograve */
+    {631, 8, 5, 4, 0, -5}, /* 0xD3 Oacute */
+    {636, 8, 5, 4, 0, -5}, /* 0xD4 Ocircumflex */
+    {641, 8, 5, 4, 0, -5}, /* 0xD5 Otilde */
+    {646, 8, 5, 4, 0, -5}, /* 0xD6 Odieresis */
+    {651, 8, 3, 4, 0, -4}, /* 0xD7 multiply */
+    {654, 8, 5, 4, 0, -5}, /* 0xD8 Oslash */
+    {659, 8, 5, 4, 0, -5}, /* 0xD9 Ugrave */
+    {664, 8, 5, 4, 0, -5}, /* 0xDA Uacute */
+    {669, 8, 5, 4, 0, -5}, /* 0xDB Ucircumflex */
+    {674, 8, 5, 4, 0, -5}, /* 0xDC Udieresis */
+    {679, 8, 5, 4, 0, -5}, /* 0xDD Yacute */
+    {684, 8, 5, 4, 0, -5}, /* 0xDE Thorn */
+    {689, 8, 6, 4, 0, -5}, /* 0xDF germandbls */
+    {695, 8, 5, 4, 0, -5}, /* 0xE0 agrave */
+    {700, 8, 5, 4, 0, -5}, /* 0xE1 aacute */
+    {705, 8, 5, 4, 0, -5}, /* 0xE2 acircumflex */
+    {710, 8, 5, 4, 0, -5}, /* 0xE3 atilde */
+    {715, 8, 5, 4, 0, -5}, /* 0xE4 adieresis */
+    {720, 8, 5, 4, 0, -5}, /* 0xE5 aring */
+    {725, 8, 4, 4, 0, -4}, /* 0xE6 ae */
+    {729, 8, 5, 4, 0, -4}, /* 0xE7 ccedilla */
+    {734, 8, 5, 4, 0, -5}, /* 0xE8 egrave */
+    {739, 8, 5, 4, 0, -5}, /* 0xE9 eacute */
+    {744, 8, 5, 4, 0, -5}, /* 0xEA ecircumflex */
+    {749, 8, 5, 4, 0, -5}, /* 0xEB edieresis */
+    {754, 8, 5, 3, 0, -5}, /* 0xEC igrave */
+    {759, 8, 5, 3, 0, -5}, /* 0xED iacute */
+    {764, 8, 5, 4, 0, -5}, /* 0xEE icircumflex */
+    {769, 8, 5, 4, 0, -5}, /* 0xEF idieresis */
+    {774, 8, 5, 4, 0, -5}, /* 0xF0 eth */
+    {779, 8, 5, 4, 0, -5}, /* 0xF1 ntilde */
+    {784, 8, 5, 4, 0, -5}, /* 0xF2 ograve */
+    {789, 8, 5, 4, 0, -5}, /* 0xF3 oacute */
+    {794, 8, 5, 4, 0, -5}, /* 0xF4 ocircumflex */
+    {799, 8, 5, 4, 0, -5}, /* 0xF5 otilde */
+    {804, 8, 5, 4, 0, -5}, /* 0xF6 odieresis */
+    {809, 8, 5, 4, 0, -5}, /* 0xF7 divide */
+    {814, 8, 4, 4, 0, -4}, /* 0xF8 oslash */
+    {818, 8, 5, 4, 0, -5}, /* 0xF9 ugrave */
+    {823, 8, 5, 4, 0, -5}, /* 0xFA uacute */
+    {828, 8, 5, 4, 0, -5}, /* 0xFB ucircumflex */
+    {833, 8, 5, 4, 0, -5}, /* 0xFC udieresis */
+    {838, 8, 6, 4, 0, -5}, /* 0xFD yacute */
+    {844, 8, 5, 4, 0, -4}, /* 0xFE thorn */
+    {849, 8, 6, 4, 0, -5}, /* 0xFF ydieresis */
+    {855, 8, 1, 2, 0, -1}, /* 0x11D gcircumflex */
+    {856, 8, 5, 4, 0, -5}, /* 0x152 OE */
+    {861, 8, 4, 4, 0, -4}, /* 0x153 oe */
+    {865, 8, 5, 4, 0, -5}, /* 0x160 Scaron */
+    {870, 8, 5, 4, 0, -5}, /* 0x161 scaron */
+    {875, 8, 5, 4, 0, -5}, /* 0x178 Ydieresis */
+    {880, 8, 5, 4, 0, -5}, /* 0x17D Zcaron */
+    {885, 8, 5, 4, 0, -5}, /* 0x17E zcaron */
+    {890, 8, 1, 2, 0, -1}, /* 0xEA4 uni0EA4 */
+    {891, 8, 1, 2, 0, -1}, /* 0x13A0 uni13A0 */
+    {892, 8, 1, 2, 0, -3}, /* 0x2022 bullet */
+    {893, 8, 1, 4, 0, -1}, /* 0x2026 ellipsis */
+    {894, 8, 5, 4, 0, -5}, /* 0x20AC Euro */
+    {899, 8, 5, 4, 0, -5}, /* 0xFFFD uniFFFD */
+#endif
+};
+
diff --git a/drv/display/glyphs.h b/drv/display/glyphs.h
new file mode 100644
index 0000000..88a3377
--- /dev/null
+++ b/drv/display/glyphs.h
@@ -0,0 +1,17 @@
+#ifndef GLYPHS_H
+#define GLYPHS_H
+
+extern const GFXglyph FreeMono12pt7bGlyphs[];
+extern const GFXglyph FreeMono18pt7bGlyphs[];
+extern const GFXglyph FreeMono24pt7bGlyphs[];
+extern const GFXglyph FreeMono9pt7bGlyphs[];
+extern const GFXglyph FreeSans12pt7bGlyphs[];
+extern const GFXglyph FreeSans9pt7bGlyphs[];
+extern const GFXglyph OpenSansLight10Glyphs[];
+extern const GFXglyph OpenSansLight12Glyphs[];
+extern const GFXglyph OpenSansLight14Glyphs[];
+extern const GFXglyph OpenSansLight16Glyphs[];
+extern const GFXglyph Org_01Glyphs[];
+extern const GFXglyph TomThumbGlyphs[];
+
+#endif
diff --git a/drv/display/ssd130x.cpp b/drv/display/ssd130x.cpp
index 018fa21..d3c0830 100644
--- a/drv/display/ssd130x.cpp
+++ b/drv/display/ssd130x.cpp
@@ -22,7 +22,7 @@
 #include "log.h"
 #include "profiling.h"
 
-#include "fonts_ssd1306.h"
+//#include "fonts_ssd1306.h"
 #include <stdlib.h>
 #include <string.h>
 
@@ -42,6 +42,17 @@
 #define TAG MODULE_SSD130X
 
 
+/*
+static Font NativeFont = {
+	.name = "native",
+	.bitmap = Font6x8,
+	.glyph = 0,
+	.first = 32,
+	.last = 0,
+	.yAdvance = 8,
+};
+*/
+
 
 SSD130X::~SSD130X()
 {
@@ -101,12 +112,15 @@ void SSD130X::fillRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t c
 
 uint16_t SSD130X::fontHeight() const
 {
+	/*
 	switch (m_font) {
 	case -1: return 8;
 	case -2: return 16;
 	default:
 		return Fonts[m_font].yAdvance;
 	}
+	*/
+	return m_font->yAdvance;
 }
 
 
@@ -120,8 +134,10 @@ void SSD130X::clrEol()
 
 uint16_t SSD130X::charsPerLine() const
 {
+	/*
 	if (m_font == font_nativedbl)
 		return m_width/CHAR_WIDTH<<1;
+	*/
 	return m_width/CHAR_WIDTH;
 }
 
@@ -132,9 +148,9 @@ uint16_t SSD130X::numLines() const
 }
 
 
-/*
 int SSD130X::setFont(const char *fn)
 {
+	/*
 	if (0 == strcasecmp(fn,"native")) {
 		m_font = (fontid_t)-1;
 		return 0;
@@ -143,15 +159,15 @@ int SSD130X::setFont(const char *fn)
 		m_font = (fontid_t)-2;
 		return 0;
 	}
-	for (int i = 0; i < font_numfonts; ++i) {
-		if (0 == strcasecmp(Fonts[i].name,fn)) {
-			m_font = (fontid_t)i;
+	*/
+	for (int i = 0; i < NumFontsBCM; ++i) {
+		if (0 == strcasecmp(FontsBCM[i].name,fn)) {
+			m_font = FontsBCM+i;
 			return 0;
 		}
 	}
 	return -1;
 }
-*/
 
 
 int SSD130X::readByte(uint8_t x, uint8_t y, uint8_t *b)
@@ -189,6 +205,7 @@ int SSD130X::drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m)
 }
 
 
+/*
 static uint16_t scaleDouble(uint8_t byte)
 {
       uint16_t r = 0;
@@ -205,6 +222,7 @@ static uint16_t scaleDouble(uint8_t byte)
       }
       return r;
 }
+*/
 
 
 /*
@@ -277,16 +295,29 @@ int SSD130X::drawByte(uint8_t x, uint8_t y, uint8_t b)
 }
 
 
-int SSD130X::drawChar(char c)
+void SSD130X::drawChar(char c)
+{
+	if (c == '\r') {
+		m_posx = 0;
+	} else if (c == '\n') {
+		m_posx = 0;
+		m_posy += fontHeight();
+	} else {
+		m_posx += drawChar(m_posx, m_posy, c, 1, 0);
+	}
+}
+
+
+unsigned SSD130X::drawChar(uint16_t x, uint16_t y, char c, int32_t fg, int32_t bg)
 {
 	PROFILE_FUNCTION();
 	switch ((unsigned char) c) {
 	case '\r':
-		m_posx = 0;
+//		m_posx = 0;
 		return 0;
 	case '\n':
-		m_posx = 0;
-		m_posy += fontHeight();
+//		m_posx = 0;
+//		m_posy += fontHeight();
 		return 0;
 	case 176:	// '°'
 		c = 133;
@@ -315,7 +346,7 @@ int SSD130X::drawChar(char c)
 	default:
 		break;
 	}
-	uint8_t x = m_posx;
+	/*
 	if (m_font == -1) {
 		if (c < 32)
 			return 1;
@@ -324,8 +355,7 @@ int SSD130X::drawChar(char c)
 			return 1;
 		for (int c = 0; c < 6; ++c) 
 			drawByte(x++, m_posy, Font6x8[idx+c]);
-		m_posx = x;
-		return 0;
+		return 6;
 	} else if (m_font == -2) {
 		if (c < 32)
 			return 1;
@@ -341,34 +371,35 @@ int SSD130X::drawChar(char c)
 			drawByte(x, m_posy+8, w >> 8);
 			++x;
 		}
-		m_posx = x;
-		return 0;
+		return 12;
 	}
 	const Font *font = Fonts+(int)m_font;
 	if ((font < Fonts) || (font >= Fonts+(int)font_numfonts)) {
 		log_dbug(TAG,"invalid font");
 		return 1;
 	}
-	if ((c < font->first) || (c > font->last))
+	*/
+	if ((c < m_font->first) || (c > m_font->last)) {
+		log_dbug(TAG,"undefined char");
 		return 1;
-	uint8_t ch = c - font->first;
-	const uint8_t *off = font->bitmap + font->glyph[ch].bitmapOffset;
-	uint8_t w = font->glyph[ch].width;
-	uint8_t h = font->glyph[ch].height;
-	int8_t dx = font->glyph[ch].xOffset;
-	int8_t dy = font->glyph[ch].yOffset;
-	uint8_t a = font->glyph[ch].xAdvance;
-	log_dbug(TAG,"drawChar('%c') at %u/%u %ux%u",c,m_posx,m_posy,w,h);
+	}
+	uint8_t ch = c - m_font->first;
+	const uint8_t *off = m_font->bitmap + m_font->glyph[ch].bitmapOffset;
+	uint8_t w = m_font->glyph[ch].width;
+	uint8_t h = m_font->glyph[ch].height;
+	int8_t dx = m_font->glyph[ch].xOffset;
+	int8_t dy = m_font->glyph[ch].yOffset;
+	uint16_t a = m_font->glyph[ch].xAdvance;
+	log_dbug(TAG,"drawChar(%u,%u,'%c') with %ux%u",x,y,c,w,h);
 //	log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l);
-//	clearRect(m_posx,m_posy,dx+w,a);
-//	drawBitmap(m_posx+dx,m_posy+dy+font->yAdvance,w,h,off);
-	drawBitmapNative(m_posx+dx,m_posy+dy+font->yAdvance-1,w,h,off);
-	m_posx += a;
-
-	return 0;
+	clearRect(x,y,dx+w,m_font->yAdvance);
+//	drawBitmap(x+dx,y+dy+font->yAdvance,w,h,off,1,0);
+	drawBitmapNative(x+dx,y+dy+m_font->yAdvance-1,w,h,off);
+	return a;
 }
 
 
+/*
 void SSD130X::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg)
 {
 	unsigned len = w*h;
@@ -385,6 +416,7 @@ void SSD130X::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const u
 		++idx;
 	}
 }
+*/
 
 
 void SSD130X::drawHLine(uint16_t x, uint16_t y, uint16_t n, int32_t col)
@@ -528,6 +560,16 @@ void SSD130X::pSetPixel(uint16_t x, uint16_t y)
 }
 
 
+int SSD130X::setFont(unsigned f)
+{
+	if (f < NumFontsBCM) {
+		m_font = FontsBCM + f;
+		return 0;
+	}
+	return -1;
+}
+
+
 void SSD130X::setPixel(uint16_t x, uint16_t y, int32_t col)
 {
 //	log_dbug(TAG,"setPixel(%u,%u)",(unsigned)x,(unsigned)y);
@@ -595,12 +637,9 @@ int SSD130X::writeHex(uint8_t h, bool comma)
 		c += '0';
 	else
 		c += 'A' - 10;
-	if (drawChar(c))
-		return 1;
-	if (comma) {
-		if (drawChar('.'))
-			return 1;
-	}
+	drawChar(c);
+	if (comma)
+		drawChar('.');
 	return 0;
 }
 
diff --git a/drv/display/ssd130x.h b/drv/display/ssd130x.h
index 4321ae8..dfa35ed 100644
--- a/drv/display/ssd130x.h
+++ b/drv/display/ssd130x.h
@@ -20,7 +20,6 @@
 #define SSD130X_H
 
 #include "display.h"
-#include "fonts_ssd1306.h"
 
 class SSD130X : public MatrixDisplay
 {
@@ -35,9 +34,9 @@ class SSD130X : public MatrixDisplay
 //	int clrEol();
 	uint16_t charsPerLine() const;
 	uint16_t numLines() const;
-//	int setFont(unsigned);
-//	int setFont(const char *fn);
-	void drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg);
+	int setFont(unsigned) override;
+	int setFont(const char *fn) override;
+//	void drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override;
 	void drawHLine(uint16_t x, uint16_t y, uint16_t n, int32_t col = -1) override;
 	void drawVLine(uint16_t x, uint16_t y, uint16_t n, int32_t col = -1) override;
 //	void drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col = -1) override;
@@ -61,11 +60,13 @@ class SSD130X : public MatrixDisplay
 	int drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m);
 	int drawBits(uint8_t x, uint8_t y, uint8_t b, uint8_t n);
 	int drawByte(uint8_t x, uint8_t y, uint8_t b);
-	int drawChar(char c);
+	void drawChar(char c);
+	unsigned drawChar(uint16_t x, uint16_t y, char c, int32_t fg, int32_t bg) override;
 	void drawBitmapNative(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data);
 
 	uint8_t *m_disp = 0;
 	uint8_t m_dirty = 0xff;
+//	fontid_t m_font = font_native;
 };
 
 
diff --git a/drv/i2c/CMakeLists.txt b/drv/i2c/CMakeLists.txt
index 97dd363..d598c67 100644
--- a/drv/i2c/CMakeLists.txt
+++ b/drv/i2c/CMakeLists.txt
@@ -11,6 +11,7 @@ idf_component_register(
 	ina2xx.cpp
 	mcp2300x.cpp
 	mcp2301x.cpp
+	opt3001.cpp
 	pca9685.cpp
 	pcf8574.cpp
 	sgp30.cpp
diff --git a/drv/i2c/bh1750.cpp b/drv/i2c/bh1750.cpp
index 81bc4b6..821daf8 100644
--- a/drv/i2c/bh1750.cpp
+++ b/drv/i2c/bh1750.cpp
@@ -59,11 +59,11 @@ BH1750 *BH1750::create(uint8_t bus, uint8_t addr)
 		return 0;
 	}
 	esp_err_t e;
-#ifdef CONFIG_IDF_TARGET_ESP32
-	int count = 0;
+#if 0 //def CONFIG_IDF_TARGET_ESP32
 	// The timeout retry-logic is for handling an esp32-idf v3.3
 	// init-bug, which has a work-around in the atrium i2c init
 	// code.
+	int count = 0;
 	do {
 		if (++count > 2)
 			return 0;
diff --git a/drv/i2c/bmx.cpp b/drv/i2c/bmx.cpp
index 5e27e59..65e08ed 100644
--- a/drv/i2c/bmx.cpp
+++ b/drv/i2c/bmx.cpp
@@ -40,6 +40,9 @@
 #include <freertos/FreeRTOS.h>
 #include <freertos/task.h>
 
+#define BME_ADDR_MIN		0xec
+#define BME_ADDR_MAX		0xee
+
 #define BMP280_ID		0x58
 #define BME280_ID		0x60
 
@@ -655,8 +658,9 @@ unsigned bmx_scan(uint8_t port)
 	// 7bit			=     8bit with R/W
 	// (0x76,0x77) << 1) | R/_W = 0xec/0xee
 	unsigned num = 0;
-	uint8_t addr = 0xec, id = 0;
+	uint8_t addr = BME_ADDR_MIN;
 	do {
+		uint8_t id = 0;
 		int r = i2c_w1rd(port,addr,BME_REG_ID,&id,sizeof(id));
 		// esp32 i2c stack has a bug and reports timeout
 		// although data was received correctly...
@@ -664,7 +668,7 @@ unsigned bmx_scan(uint8_t port)
 		if ((r >= 0) && (id != 0))
 			num += create_device(port,addr,id);
 		addr += 2;
-	} while (addr <= 0xee);
+	} while (addr <= BME_ADDR_MAX);
 	return num;
 }
 
diff --git a/drv/i2c/ccs811b.cpp b/drv/i2c/ccs811b.cpp
index e5f9744..a78e33f 100644
--- a/drv/i2c/ccs811b.cpp
+++ b/drv/i2c/ccs811b.cpp
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2021, Thomas Maier-Komor
+ *  Copyright (C) 2021-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -23,9 +23,10 @@
 #include "actions.h"
 #include "ccs811b.h"
 #include "cyclic.h"
+#include "env.h"
 #include "i2cdrv.h"
 #include "log.h"
-#include "env.h"
+#include "terminal.h"
 
 
 #define DEV_ADDR_MIN	(0x5a << 1)
@@ -54,6 +55,11 @@
 #define TAG MODULE_CCS811B
 
 
+static const char *States[] = {
+	"idle", "sample", "measure", "update", "read",
+};
+
+
 CCS811B::CCS811B(uint8_t bus, uint8_t addr)
 : I2CDevice(bus, addr, "ccs811b")
 , m_state(st_idle)
@@ -187,8 +193,10 @@ unsigned CCS811B::updateHumidity()
 unsigned CCS811B::read()
 {
 	uint8_t data[6];
-	if (i2c_w1rd(m_bus,m_addr,REG_DATA,data,sizeof(data)))
+	if (i2c_w1rd(m_bus,m_addr,REG_DATA,data,sizeof(data))) {
+		log_warn(TAG,"I2C error");
 		return 0;
+	}
 	if ((data[4] & STATUS_FLAG_ERROR) != 0) {
 		log_dbug(TAG,"error 0x%x",data[5]);
 		return 0;
@@ -232,10 +240,23 @@ uint8_t CCS811B::error()
 }
 
 
-//uint8_t CCS811B::getError()
-//{
-//
-//}
+#ifdef CONFIG_I2C_XCMD
+const char *CCS811B::exeCmd(struct Terminal &t, int argc, const char **args)
+{
+	if (argc == 0) {
+		t.printf("%s is %s\n",m_name,States[m_state]);
+		return 0;
+	}
+	if (0 == strcmp(args[0],"stop")) {
+		m_state = st_idle;
+	} else if (0 == strcmp(args[0],"start")) {
+		m_state = st_measure;
+	} else {
+		return "Invalid argument #1.";
+	}
+	return 0;
+}
+#endif
 
 
 unsigned ccs811b_scan(uint8_t bus)
diff --git a/drv/i2c/ccs811b.h b/drv/i2c/ccs811b.h
index fd8f35d..dc7e173 100644
--- a/drv/i2c/ccs811b.h
+++ b/drv/i2c/ccs811b.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2021, Thomas Maier-Komor
+ *  Copyright (C) 2021-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -34,6 +34,9 @@ class CCS811B : public I2CDevice
 
 	int init();
 	void attach(class EnvObject *);
+#ifdef CONFIG_I2C_XCMD
+	const char *exeCmd(struct Terminal &, int argc, const char **argv) override;
+#endif
 
 	private:
 	static unsigned cyclic(void *);
diff --git a/drv/i2c/hdc1000.cpp b/drv/i2c/hdc1000.cpp
index 3747a47..eab7284 100644
--- a/drv/i2c/hdc1000.cpp
+++ b/drv/i2c/hdc1000.cpp
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2021, Thomas Maier-Komor
+ *  Copyright (C) 2021-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -22,11 +22,12 @@
 
 #include "actions.h"
 #include "cyclic.h"
+#include "env.h"
 #include "event.h"
 #include "hdc1000.h"
 #include "i2cdrv.h"
 #include "log.h"
-#include "env.h"
+#include "terminal.h"
 
 #define REG_TEMP	0x00
 #define REG_HUMID	0x01
@@ -35,137 +36,282 @@
 #define REG_SER23	0xfc
 #define REG_SER45	0xfd
 
+#define BIT_RESET	(1<<15)
+#define BIT_HEATER	(1<<13)
+#define BIT_MEASBOTH	(1<<12)
+
+#define MASK_TRES	(1<<10)
+#define MASK_HRES	(3<<8)
+#define SHIFT_HRES	8
+
 #define TAG MODULE_HDC1000
 
 
-HDC1000 *HDC1000::create(uint8_t bus)
+static const char *States[] = {
+	"idle","readtemp","readhumid","readboth",
+};
+
+
+HDC1000::HDC1000(uint8_t port, uint8_t addr, const char *name)
+: I2CDevice(port,addr,name)
+, m_drvname(name)
+, m_temp("temperature","\u00b0C")
+, m_humid("humidity","%")
 {
-	uint8_t serial[6];
-	if (i2c_w1rd(bus,HDC1000_ADDR,REG_SER01,serial+0,2))
-		return 0;
-	if (i2c_w1rd(bus,HDC1000_ADDR,REG_SER23,serial+2,2))
-		return 0;
-	if (i2c_w1rd(bus,HDC1000_ADDR,REG_SER45,serial+4,2))
+	uint8_t data[2];
+	if (0 == i2c_w1rd(port,addr,REG_CONFIG,data,sizeof(data))) {
+		m_cfg = (data[0] << 8) | data[1];
+		log_dbug(TAG,"config register 0x%04x",m_cfg);
+	}
+}
+
+
+HDC1000 *HDC1000::create(uint8_t bus, uint8_t addr, uint16_t id)
+{
+	const char *name = 0;
+	switch (id) {
+	case 0x1000:
+		name = "hdc1000";
+		break;
+	case 0x1050:
+		name = "hdc1080";
+		break;
+	default:
 		return 0;
-	uint32_t s0 = serial[0] << 24 | serial[1]<<16 | serial[2]<<8 | serial[3];
-	uint16_t s1 = serial[4]<<8 | serial[5];
-	log_info(TAG,"serial id %08x%04x",s0,(unsigned)s1);
-	return new HDC1000(bus);
+	}
+	return new HDC1000(bus,addr,name);
 }
 
 
 int HDC1000::init()
 {
-	m_temp = new EnvNumber("temperature","\u00b0C");
-	m_humid = new EnvNumber("humidity","%");
-	return setSingle(true);
+	return 0;
 }
 
 
-int HDC1000::setSingle(bool single)
+void HDC1000::setSingle(bool single)
 {
 	// independet measure	[12] = 0=single, 1=both
 	// 14 bittemperature:	[10] = 0
 	// 14bit humidity:	[9,8] = 00
-	m_single = single;
-	uint8_t cmd[] =  { HDC1000_ADDR, REG_CONFIG, 0, 0 };
-	if (!single)
-		cmd[2] |= 1<<4;
-	return i2c_write(m_bus,cmd,sizeof(cmd),true,true);
+	if (single)
+		m_cfg &= ~BIT_MEASBOTH;
+	else
+		m_cfg |= BIT_MEASBOTH;
+	m_cfgsynced = false;
+}
+
+
+void HDC1000::setHeater(bool on)
+{
+	uint16_t cfg = m_cfg;
+	if (on)
+		cfg |= BIT_HEATER;
+	else
+		cfg &= ~BIT_HEATER;
+	m_cfgsynced = (cfg != m_cfg);
+	m_cfg = cfg;
 }
 
 
 unsigned HDC1000::cyclic()
 {
-	for (;;) {
-		switch (m_state) {
-		case st_idle:
-			if (m_sample == sm_both) {
-				log_dbug(TAG,"sample both");
-				if (m_single)
-					setSingle(false);
-				if (i2c_write1(m_bus,HDC1000_ADDR, REG_TEMP))
-					break;
-				m_sample = sm_none;
-				m_state = st_readboth;
-				return 15;
-			}
-			if (m_sample & sm_temp) {
-				log_dbug(TAG,"sample temp");
-				if (!m_single)
-					setSingle(true);
-				if (i2c_write1(m_bus,HDC1000_ADDR, REG_TEMP))
-					break;
-				m_state = st_readtemp;
-				m_sample = (sample_t)(m_sample ^ sm_temp);
-				return 8;
-			}
-			if (m_sample & sm_humid) {
-				log_dbug(TAG,"sample humid");
-				if (!m_single)
-					setSingle(true);
-				if (i2c_write1(m_bus,HDC1000_ADDR, REG_HUMID))
-					break;
-				m_state = st_readhumid;
-				m_sample = (sample_t)(m_sample ^ sm_humid);
-				return 8;
-			}
-			return 20;
-		case st_readhumid:
-			{
-				log_dbug(TAG,"read humid");
-				uint8_t data[2];
-				if (i2c_read(m_bus,HDC1000_ADDR,data,sizeof(data)))
-					break;
-				setHumid(data);
-				m_state = st_idle;
-				if (m_sample != sm_none)
-					continue;
-				return 50;
+	switch (m_state) {
+	case st_idle:
+		if (!m_cfgsynced) {
+//			uint16_t cfg = (unsigned) m_tres | (unsigned) m_hres;
+			uint8_t data[] = { m_addr, REG_CONFIG, (uint8_t)(m_cfg >> 8), (uint8_t)(m_cfg & 0xff) };
+			if (i2c_write(m_bus,data,sizeof(data),1,1)) {
+				log_warn(TAG,"config sync failed");
+				break;
 			}
-		case st_readtemp:
-			{
-				log_dbug(TAG,"read temp");
-				uint8_t data[2];
-				if (i2c_read(m_bus,HDC1000_ADDR,data,sizeof(data)))
-					break;
-				setTemp(data);
-				m_state = st_idle;
-				if (m_sample != sm_none)
-					continue;
-				return 50;
-			}
-		case st_readboth:
-			{
-				log_dbug(TAG,"read both");
-				uint8_t data[4];
-				if (i2c_read(m_bus,HDC1000_ADDR,data,sizeof(data)))
-					break;
-				setTemp(data);
-				setHumid(data+2);
-				m_state = st_idle;
-				return 50;
-			}
-		default:
-			abort();
+			m_cfgsynced = true;
+		}
+		if (m_sample == sm_both) {
+			log_dbug(TAG,"sample both");
+			if (i2c_write1(m_bus,m_addr,REG_TEMP))
+				break;
+			m_sample = sm_none;
+			m_state = st_readboth;
+			return 15;
+		}
+		if (m_sample & sm_temp) {
+			log_dbug(TAG,"sample temp");
+			if (i2c_write1(m_bus,m_addr,REG_TEMP))
+				break;
+			m_state = st_readtemp;
+			m_sample = (sample_t)(m_sample ^ sm_temp);
+			return 8;
+		}
+		if (m_sample & sm_humid) {
+			log_dbug(TAG,"sample humid");
+			if (i2c_write1(m_bus, m_addr, REG_HUMID))
+				break;
+			m_state = st_readhumid;
+			m_sample = (sample_t)(m_sample ^ sm_humid);
+			return 8;
+		}
+		return 20;
+	case st_readhumid:
+		{
+			log_dbug(TAG,"read humid");
+			uint8_t data[2];
+			if (i2c_read(m_bus,m_addr,data,sizeof(data)))
+				break;
+			setHumid(data);
+			m_state = st_idle;
+			if (m_sample != sm_none)
+				return 5;
+			return 50;
 		}
-		log_dbug(TAG,"error");
-		m_state = state_t::st_idle;
-		if (m_temp)
-			m_temp->set(NAN);
-		if (m_humid)
-			m_humid->set(NAN);
-		return 1000;
+	case st_readtemp:
+		{
+			log_dbug(TAG,"read temp");
+			uint8_t data[2];
+			if (i2c_read(m_bus,m_addr,data,sizeof(data)))
+				break;
+			setTemp(data);
+			m_state = st_idle;
+			if (m_sample != sm_none)
+				return 5;
+			return 50;
+		}
+	case st_readboth:
+		{
+			log_dbug(TAG,"read both");
+			uint8_t data[4];
+			if (i2c_read(m_bus,m_addr,data,sizeof(data)))
+				break;
+			setTemp(data);
+			setHumid(data+2);
+			m_state = st_idle;
+			return 50;
+		}
+	default:
+		abort();
 	}
+	log_dbug(TAG,"error");
+	m_state = state_t::st_idle;
+	m_temp.set(NAN);
+	m_humid.set(NAN);
+	return 1000;
 }
 
 
+#ifdef CONFIG_I2C_XCMD
+const char *HDC1000::exeCmd(struct Terminal &term, int argc, const char **args)
+{
+	if (argc == 0) {
+		static const uint8_t hres_vals[] = { 14, 11, 8 };
+		unsigned tres = m_cfg & MASK_TRES ? 11 : 14;
+		unsigned hres = hres_vals[(m_cfg & MASK_HRES) >> SHIFT_HRES];
+		const char *heat = (m_cfg & BIT_HEATER) ? "on" : "off";
+		const char *mode = (m_cfg & BIT_MEASBOTH) ? "both" : "single";
+		term.printf(
+			"state: %s\n"
+			"temperature: %ubits\n"
+			"humidity   : %ubits\n"
+			"heater     : %s\n"
+			"mode       : %s\n"
+			, States[m_state]
+			, tres
+			, hres
+			, heat
+			, mode
+		);
+		return 0;
+	}
+	if (0 == strcmp(args[0],"-h")) {
+		term.println(
+			"valid commands:\n"
+			"serial    : prints serial id\n"
+			"hres [res]: set humid resolution to 8,11,14 bits\n"
+			"tres [res]: set humid resolution to 11,14 bits\n"
+			"reset     : perform device reset\n"
+			"seq       : perform measurements sequential\n"
+			"both      : perform measurements together\n"
+			);
+	} else if (0 == strcmp(args[0],"reset")) {
+	} else if (0 == strcmp(args[0],"seq")) {
+		setSingle(true);
+	} else if (0 == strcmp(args[0],"both")) {
+		setSingle(false);
+	} else if (0 == strcmp(args[0],"hres")) {
+		if (argc == 1)
+			return "Missing argument.";
+		char *e;
+		long l = strtol(args[1],&e,0);
+		if (*e)
+			return "Invalid argument #2.";
+		if (l == 8) {
+			m_cfg &= ~MASK_HRES;
+			m_cfg |= hres_8b;
+			m_cfgsynced = false;
+		} else if (l == 11) {
+			m_cfg &= ~MASK_HRES;
+			m_cfg |= hres_11b;
+			m_cfgsynced = false;
+		} else if (l == 14) {
+			m_cfg &= ~MASK_HRES;
+			m_cfg |= hres_14b;
+			m_cfgsynced = false;
+		} else {
+			return "Invalid argument #2.";
+		}
+	} else if (0 == strcmp(args[0],"tres")) {
+		if (argc == 1)
+			return "Missing argument.";
+		char *e;
+		long l = strtol(args[1],&e,0);
+		if (*e)
+			return "Invalid argument #2.";
+		if (l == 11) {
+			m_cfg &= ~MASK_TRES;
+			m_cfg |= tres_11b;
+			m_cfgsynced = false;
+		} else if (l == 14) {
+			m_cfg &= ~MASK_TRES;
+			m_cfg |= tres_14b;
+			m_cfgsynced = false;
+		} else {
+			return "Invalid argument #2.";
+		}
+	} else if (0 == strcmp(args[0],"heater")) {
+		if (0 == strcmp(args[1],"on"))
+			setHeater(true);
+		else if (0 == strcmp(args[1],"1"))
+			setHeater(true);
+		else if (0 == strcmp(args[1],"off"))
+			setHeater(false);
+		else if (0 == strcmp(args[1],"0"))
+			setHeater(false);
+		else
+			return "Invalid argument #2.";
+	} else if (0 == strcmp(args[0],"serial")) {
+		uint8_t serial[6];
+		if (i2c_w1rd(m_bus,m_addr,REG_SER01,serial+0,2))
+			return "I2C error.";
+		if (i2c_w1rd(m_bus,m_addr,REG_SER23,serial+2,2))
+			return "I2C error.";
+		if (i2c_w1rd(m_bus,m_addr,REG_SER45,serial+4,2))
+			return "I2C error.";
+		uint32_t s0 = serial[0] << 24 | serial[1]<<16 | serial[2]<<8 | serial[3];
+		uint16_t s1 = serial[4]<<8 | serial[5];
+		term.printf("serial id %08x%04x",s0,(unsigned)s1);
+	} else {
+		return "Invalid argument #1.";
+	}
+	return 0;
+}
+#endif
+
+
 void HDC1000::setHumid(uint8_t data[])
 {
 	uint16_t humid_raw = (data[0] << 8) | data[1];
 	float h = (float)humid_raw / (1<<16) * 165 - 40;
-	m_humid->set(h);
 	log_dbug(TAG,"humid %G",h);
+	m_humid.set(h);
 }
 
 
@@ -174,8 +320,7 @@ void HDC1000::setTemp(uint8_t data[])
 	uint16_t temp_raw = (data[0] << 8) | data[1];
 	float t = (float)temp_raw / (1<<16) * 165 - 40;
 	log_dbug(TAG,"temp %G",t);
-	if (m_temp)
-		m_temp->set(t);
+	m_temp.set(t);
 }
 
 
@@ -190,6 +335,10 @@ void HDC1000::trigger(void *arg)
 {
 	HDC1000 *drv = (HDC1000 *) arg;
 	drv->m_sample = sm_both;
+	if ((drv->m_cfg & BIT_MEASBOTH) == 0) {
+		drv->m_cfg |= BIT_MEASBOTH;
+		drv->m_cfgsynced = false;
+	}
 }
 
 
@@ -197,6 +346,10 @@ void HDC1000::trigger_temp(void *arg)
 {
 	HDC1000 *drv = (HDC1000 *) arg;
 	drv->m_sample = (sample_t)(drv->m_sample | sm_temp);
+	if (drv->m_cfg & BIT_MEASBOTH) {
+		drv->m_cfg &= ~BIT_MEASBOTH;
+		drv->m_cfgsynced = false;
+	}
 }
 
 
@@ -204,13 +357,17 @@ void HDC1000::trigger_humid(void *arg)
 {
 	HDC1000 *drv = (HDC1000 *) arg;
 	drv->m_sample = (sample_t)(drv->m_sample | sm_humid);
+	if (drv->m_cfg & BIT_MEASBOTH) {
+		drv->m_cfg &= ~BIT_MEASBOTH;
+		drv->m_cfgsynced = false;
+	}
 }
 
 
 void HDC1000::attach(EnvObject *root)
 {
-	root->add(m_temp);
-	root->add(m_humid);
+	root->add(&m_temp);
+	root->add(&m_humid);
 	cyclic_add_task(m_name,hdc1000_cyclic,this,0);
 	action_add(concat(m_name,"!sample"),HDC1000::trigger,(void*)this,"HDC1000 sample data");
 	action_add(concat(m_name,"!temp"),HDC1000::trigger_temp,(void*)this,"HDC1000 sample temperature");
diff --git a/drv/i2c/hdc1000.h b/drv/i2c/hdc1000.h
index 26b20bb..be546e4 100644
--- a/drv/i2c/hdc1000.h
+++ b/drv/i2c/hdc1000.h
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2018-2021, Thomas Maier-Komor
+ *  Copyright (C) 2018-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -19,27 +19,29 @@
 #ifndef HDC1000_H
 #define HDC1000_H
 
+#include <sdkconfig.h>
+#include "env.h"
 #include "i2cdrv.h"
 
-#define HDC1000_ADDR (0x40<<1)
-
 class EnvNumber;
 
+// supports also HDC1080
 struct HDC1000 : public I2CDevice
 {
 	const char *drvName() const
-	{ return "hdc1000"; }
+	{ return m_drvname; }
 
 	int init();
 	void attach(class EnvObject *);
 	unsigned cyclic();
 
-	static HDC1000 *create(uint8_t bus);
+	static HDC1000 *create(uint8_t bus, uint8_t addr, uint16_t id);
+#ifdef CONFIG_I2C_XCMD
+	const char *exeCmd(struct Terminal &, int argc, const char **argv) override;
+#endif
 
 	protected:
-	explicit HDC1000(uint8_t port)
-	: I2CDevice(port,HDC1000_ADDR,drvName())
-	{ }
+	HDC1000(uint8_t port, uint8_t addr, const char *name);
 
 	static void trigger(void *);
 	static void trigger_humid(void *);
@@ -48,16 +50,21 @@ struct HDC1000 : public I2CDevice
 	bool sample();
 	bool read();
 	void handle_error();
-	int setSingle(bool);
+	void setHeater(bool on);
+	void setSingle(bool);
 	void setTemp(uint8_t data[]);
 	void setHumid(uint8_t data[]);
 
-	EnvNumber *m_temp = 0, *m_humid = 0;
+	const char *m_drvname;
+	EnvNumber m_temp, m_humid;
 	typedef enum { st_idle, st_readtemp, st_readhumid, st_readboth } state_t;
 	typedef enum { sm_none, sm_temp, sm_humid, sm_seq, sm_both } sample_t;
+	typedef enum { tres_14b = 0, tres_11b = (1<<10) } tres_t;
+	typedef enum { hres_14b = 0, hres_11b = 0x100, hres_8b = 0x200 } hres_t;
 	state_t m_state = st_idle;
 	sample_t m_sample = sm_none;
-	bool m_single;
+	bool m_cfgsynced = false;	// has the configuration been written to the device?
+	uint16_t m_cfg = 0x1000;	// reset value of device
 };
 
 
diff --git a/drv/i2c/i2cdrv.cpp b/drv/i2c/i2cdrv.cpp
index 19c6136..4cf8269 100644
--- a/drv/i2c/i2cdrv.cpp
+++ b/drv/i2c/i2cdrv.cpp
@@ -31,8 +31,6 @@
 #include <freertos/semphr.h>
 
 #if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
-#include <driver/periph_ctrl.h>
-
 extern "C" esp_err_t i2c_hw_fsm_reset(i2c_port_t);
 #endif
 
@@ -66,6 +64,12 @@ I2CDevice::I2CDevice(uint8_t bus, uint8_t addr, const char *name)
 }
 
 
+void I2CDevice::addIntr(uint8_t intr)
+{
+	log_warn(TAG,"%s does not support interrupts",m_name);
+}
+
+
 void I2CDevice::setName(const char *n)
 {
 	strncpy(m_name,n,sizeof(m_name)-1);
@@ -73,6 +77,18 @@ void I2CDevice::setName(const char *n)
 }
 
 
+I2CDevice *I2CDevice ::getByAddr(uint8_t addr)
+{
+	I2CDevice *dev = m_first;
+	while (dev) {
+		if (dev->getAddr() == addr)
+			return dev;
+		dev = dev->m_next;
+	}
+	return 0;
+}
+
+
 bool I2CDevice::hasInstance(const char *d)
 {
 	size_t l = strlen(d);
@@ -151,7 +167,7 @@ int i2c_read(uint8_t port, uint8_t addr, uint8_t *d, uint8_t n)
 		p = 'p';
 		goto done;
 	}
-	r = i2c_master_cmd_begin((i2c_port_t)port, cmd, 1000 / portTICK_RATE_MS);
+	r = i2c_master_cmd_begin((i2c_port_t)port, cmd, 1000 / portTICK_PERIOD_MS);
 	if (r) {
 		p = 'x';
 		goto done;
@@ -204,7 +220,7 @@ int i2c_w1rd(uint8_t port, uint8_t addr, uint8_t w, uint8_t *d, uint8_t n)
 		p = 't';
 		goto done;
 	}
-	r = i2c_master_cmd_begin((i2c_port_t)port, cmd, 1000 / portTICK_RATE_MS);
+	r = i2c_master_cmd_begin((i2c_port_t)port, cmd, 1000 / portTICK_PERIOD_MS);
 done:
 	i2c_cmd_link_delete(cmd);
 	log_hex(TAG,d,n,"i2c_w1rd(%u,0x%02x,0x%02x,...,%u)=%s %c",port,addr>>1,w,n,esp_err_to_name(r),p);
@@ -220,7 +236,7 @@ int i2c_write0(uint8_t port, uint8_t addr)
 	addr |= I2C_MASTER_WRITE;
 	i2c_master_write_byte(cmd, addr, true);
 	i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_dbug(TAG,"i2c_write0(%u,0x%x)=%s",port,addr>>1,esp_err_to_name(ret));
 	return ret;
@@ -239,7 +255,7 @@ int i2c_write1(uint8_t port, uint8_t addr, uint8_t r)
 	assert(e == 0);
 	e = i2c_master_stop(cmd);
 	assert(e == 0);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_dbug(TAG,"i2c_write1(%u,0x%x,0x%x)=%s",port,addr>>1,r,esp_err_to_name(ret));
 	return ret;
@@ -254,7 +270,7 @@ int i2c_write2(uint8_t port, uint8_t addr, uint8_t r, uint8_t v)
 	uint8_t data[] = { (uint8_t)(addr|I2C_MASTER_WRITE), r, v };
 	i2c_master_write(cmd, data, sizeof(data), true);
 	i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_dbug(TAG,"i2c_write2(%u,0x%x,0x%x,0x%x)=%s",port,addr>>1,r,v,esp_err_to_name(ret));
 	return ret;
@@ -287,7 +303,7 @@ int i2c_write4(uint8_t port, uint8_t addr, uint8_t r0, uint8_t v0, uint8_t r1, u
 		};
 	i2c_master_write(cmd, data, sizeof(data), I2C_MASTER_NACK);
 	i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_dbug(TAG,"i2c_write4(%u,0x%x,0x%x,0x%x,0x%x,0x%x)=%d",port,addr,r0,v0,r1,v1,ret);
 	return ret;
@@ -301,7 +317,7 @@ int i2c_writen(uint8_t port, uint8_t addr, uint8_t *d, unsigned n)
 	i2c_master_write_byte(cmd, addr | I2C_MASTER_WRITE, I2C_MASTER_NACK);
 	i2c_master_write(cmd, d, n, I2C_MASTER_NACK);
 	i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	if (log_module_enabled(TAG)) {
 		log_dbug(TAG,"i2c_writen(%u,0x%x,0x%p,%u)=%d",port,addr,d,n,ret);
@@ -317,7 +333,7 @@ int i2c_write1(uint8_t port, uint8_t d, bool stop)
 	i2c_master_write_byte(cmd, d, I2C_MASTER_NACK);
 	if (stop)
 		i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	if (log_module_enabled(TAG)) {
 		log_dbug(TAG,"i2c_write(%u,0x%p,%u)=%d",port,d,n,ret);
@@ -337,7 +353,7 @@ int i2c_write(uint8_t port, uint8_t *d, unsigned n, uint8_t stop, uint8_t start)
 	i2c_master_write(cmd, d, n, true);
 	if (stop)
 		i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_hex(TAG,d,n,"i2c_write(%u,0x%p,%u,%d,%d)=%s",port,d,n,stop,start,esp_err_to_name(ret));
 	return ret;
@@ -353,7 +369,7 @@ int i2c_write_nack(uint8_t port, uint8_t *d, unsigned n, uint8_t stop, uint8_t s
 	i2c_master_write(cmd, d, n, false);
 	if (stop)
 		i2c_master_stop(cmd);
-	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_RATE_MS);
+	int ret = i2c_master_cmd_begin((i2c_port_t) port, cmd, 1000 / portTICK_PERIOD_MS);
 	i2c_cmd_link_delete(cmd);
 	log_hex(TAG,d,n,"i2c_write_nack(%u,0x%p,%u,%d,%d)=%s",port,d,n,stop,start,esp_err_to_name(ret));
 	return ret;
@@ -383,7 +399,7 @@ int i2c_init(uint8_t port, uint8_t sda, uint8_t scl, unsigned freq, uint8_t xpul
 		conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
 		conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
 	}
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#ifdef ESP32
 	conf.master.clk_speed = freq;
 	// IRAM ISR placements seems to be unsupported on IDF v4.4.x
 //	esp_err_t e = i2c_driver_install((i2c_port_t) port, conf.mode, 0, 0, ESP_INTR_FLAG_IRAM);
@@ -420,9 +436,11 @@ int i2c_init(uint8_t port, uint8_t sda, uint8_t scl, unsigned freq, uint8_t xpul
 	// bus-timeout. The BH1750 drivers deals with that situation, so
 	// keep it the first in the scan!
 #if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#if IDF_VERSION < 50
 	esp_err_t r = i2c_hw_fsm_reset((i2c_port_t)port);
 	assert(r == 0);
 #endif
+#endif
 #ifdef CONFIG_BH1750
 	// autoscan conflicts with TCA9555
 	log_info(TAG,"search bh1750");
diff --git a/drv/i2c/i2cdrv.h b/drv/i2c/i2cdrv.h
index 7f370ce..7c87c82 100644
--- a/drv/i2c/i2cdrv.h
+++ b/drv/i2c/i2cdrv.h
@@ -52,13 +52,16 @@ class I2CDevice
 
 	uint8_t getAddr() const
 	{ return m_addr >> 1; }
-	
+
 #ifdef CONFIG_I2C_XCMD
 	virtual const char *exeCmd(struct Terminal &, int argc, const char **argv)
 	{ return "Not supported."; }
 #endif
 
+	virtual void addIntr(uint8_t gpio);
+
 	static bool hasInstance(const char *);
+	static I2CDevice *getByAddr(uint8_t addr);
 
 	protected:
 	I2CDevice(uint8_t bus, uint8_t addr, const char *name);
diff --git a/drv/i2c/opt3001.cpp b/drv/i2c/opt3001.cpp
new file mode 100644
index 0000000..c6b86d7
--- /dev/null
+++ b/drv/i2c/opt3001.cpp
@@ -0,0 +1,143 @@
+/*
+ *  Copyright (C) 2023, Thomas Maier-Komor
+ *  Atrium Firmware Package for ESP
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <sdkconfig.h>
+
+#ifdef CONFIG_OPT3001
+
+#include "opt3001.h"
+#include "log.h"
+
+#define REG_RESULT	0x00
+#define REG_CONFIG	0x01
+#define REG_LOWLIM	0x02
+#define REG_HIGHLIM	0x03
+#define REG_MANID	0x7e
+#define REG_DEVID	0x7f
+
+#define DEV_ADDR_LOW	0x44
+#define DEV_ADDR_HIGH	0x47
+
+#define BITS_EXP	0xf000
+#define BITS_FRAC	0x0fff
+#define BITS_RANGE	0xf000
+#define BITS_CONVTIME	(1<<11)
+#define BITS_MODE	0x0600
+#define BITS_OVFL	0x0100
+#define BITS_RDY	0x0080
+#define BITS_FLAGHIGH	0x0840
+#define BITS_FLAGLOW	0x0820
+#define BITS_LATCH	0x0010
+#define BITS_POL	0x0008
+#define BITS_MASKEXP	0x0004
+#define BITS_FAULTCNT	0x0003
+
+#define MODE_OFF	0x0000
+#define MODE_SINGLE	0x0200
+#define MODE_CONT	0x0400
+
+#define TAG MODULE_OPT3001
+
+
+static const float Ranges[] =
+	{ 40.95, 81.90, 163.8, 327.6, 655.2, 1310.4, 2620.8
+	, 5241.6, 10483.2, 20966.4, 41932.8, 89865.6
+};
+
+
+OPT3001::OPT3001(unsigned bus, unsigned addr)
+: I2CDevice(bus,addr)
+, m_lux("luminance","lux")
+{
+}
+
+
+void OPT3001::addIntr(uint8_t gpio)
+{
+	xio_cfg_t cfg = XIOCFG_INIT;
+	cfg.cfg_io = xio_cfg_io_in;
+	cfg.cfg_pull = xio_cfg_pull_up;
+	cfg.cfg_intr = xio_cfg_intr_fall;
+	if (0 > xio_config(gpio,cfg)) {
+		log_warn(TAG,"gpio %u as interrupt failed",gpio);
+	} else if (xio_set_intr(gpio,intr,b)) {
+		log_warn(TAG,"add handler for gpio %u interrupt failed",gpio);
+	}
+}
+
+void OPT3001::attach(EnvObject *root)
+{
+	root->add(&m_lum);
+	root->add(&m_press);
+	cyclic_add_task(m_name,OPT3001::cyclic,this,0);
+	action_add(concat(m_name,"!sample"),sample,(void*)this,"OPT3001 sample data");
+}
+
+
+unsigned OPT3001::cyclic(void *arg)
+{
+	read();
+	return 1000;
+}
+
+
+OPT3001 *OPT3001::create(unsigned bus, unsigned addr)
+{
+	return new OPT3001(bus,addr);
+}
+
+
+#ifdef CONFIG_I2C_XCMD
+const char *OPT3001::exeCmd(Terminal &term, int argc, const char **args)
+{
+	// TODO
+	return 0;
+}
+#endif
+
+
+void OPT3001::intr(void *arg)
+{
+	OPT3001 *dev = (OPT3001 *) arg;
+	// TODO
+}
+
+
+int OPT3001::read()
+{
+	uint8_t data[2];
+	if (int r = i2c_w1rd(m_bus,m_addr,REG_RESULT,data,sizeof(data)))
+		return r;
+	uint16_t val = ((uint16_t)data[0] << 8) | data[1];
+	uint8_t exp = val >> 12;
+	uint16_t &= 0xfff;
+	float scale = ((float)(1<<exp))/100.0;
+	float lum = (float)val * scale;
+	m_lux.set(lum);
+	return 0;
+}
+
+
+void OPT3001::sample(void *arg)
+{
+	OPT3001 *dev = (OPT3001 *) arg;
+	dev->read();
+}
+
+
+#endif // CONFIG_OPT3001
diff --git a/drv/i2c/opt3001.h b/drv/i2c/opt3001.h
new file mode 100644
index 0000000..febc548
--- /dev/null
+++ b/drv/i2c/opt3001.h
@@ -0,0 +1,45 @@
+/*
+ *  Copyright (C) 2023, Thomas Maier-Komor
+ *  Atrium Firmware Package for ESP
+ *
+ *  This program is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef OPT3001_H
+#define OPT3001_H
+
+#include <sdkconfig.h>
+#include "env.h"
+#include "i2cdrv.h"
+
+struct OPT3001 : public I2CDevice
+{
+	static unsigned scan(unsigned bus);
+
+	void attach(EnvObject *root) override;
+	void addIntr(uint8_t intr) override;
+	unsigned cyclic(void *arg);
+#ifdef CONFIG_I2C_XCMD
+	const char *exeCmd(Terminal &term, int argc, const char **args) override;
+#endif
+	int read();
+
+	private:
+	OPT3001(unsigned bus, unsigned addr);
+	void sample(void *arg);
+
+	EnvNumber m_lux;
+};
+
+#endif
diff --git a/drv/i2c/ssd1306.cpp b/drv/i2c/ssd1306.cpp
index 7be3768..b3c54d6 100644
--- a/drv/i2c/ssd1306.cpp
+++ b/drv/i2c/ssd1306.cpp
@@ -24,7 +24,7 @@
 #include "log.h"
 #include "profiling.h"
 
-#include "fonts_ssd1306.h"
+//#include "fonts.h"
 #include <stdlib.h>
 #include <string.h>
 
@@ -153,7 +153,7 @@ void SSD1306::clear()
 }
 */
 
-
+/*
 uint8_t SSD1306::fontHeight() const
 {
 	switch (m_font) {
@@ -163,6 +163,7 @@ uint8_t SSD1306::fontHeight() const
 		return Fonts[m_font].yAdvance;
 	}
 }
+*/
 
 
 /*
@@ -184,7 +185,6 @@ uint16_t SSD1306::numLines() const
 {
 	return m_height/fontHeight();
 }
-*/
 
 
 int SSD1306::setFont(const char *fn)
@@ -205,6 +205,7 @@ int SSD1306::setFont(const char *fn)
 	}
 	return -1;
 }
+*/
 
 
 void SSD1306::flush()
@@ -480,6 +481,7 @@ void SSD1306::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const u
 		++idx;
 	}
 }
+*/
 
 
 static uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb)
@@ -496,12 +498,13 @@ static uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb)
 }
 
 
-int SSD1306::drawBitmap_ssd1306(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data)
+//int SSD1306::drawBitmap_ssd1306(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data)
+void SSD1306::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg)
 {
 	static const uint8_t masks[] = {0x1,0x3,0x7,0xf,0x1f,0x3f,0x7f};
 	unsigned len = w*h;
 	uint16_t bitoff = 0;
-	log_dbug(TAG,"drawBitmap_fast(%u,%u,%u,%u) %u/%u",x,y,w,h,len,len/8);
+	log_dbug(TAG,"SSD1306::drawBitmap(%u,%u,%u,%u) %u/%u",x,y,w,h,len,len/8);
 	for (uint8_t x0 = x; x0 < x+w; ++x0) {
 		uint8_t yoff = y;
 		uint8_t numb = h;
@@ -533,10 +536,10 @@ int SSD1306::drawBitmap_ssd1306(uint16_t x, uint16_t y, uint16_t w, uint16_t h,
 			}
 		}
 	}
-	return 0;
+//	return 0;
 }
 
-
+/*
 int SSD1306::pClrPixel(uint16_t x, uint16_t y)
 {
 //	log_dbug(TAG,"clrPixel(%u,%u)",(unsigned)x,(unsigned)y);
@@ -750,6 +753,7 @@ SSD1306 *SSD1306::create(uint8_t bus, uint8_t addr)
 
 unsigned ssd1306_scan(uint8_t bus)
 {
+	log_dbug(TAG,"searching for SSD1306");
 	uint8_t cmd[] = { (0x3c << 1), CMD_NOP };
 	if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) {
 		new SSD1306(bus,cmd[0]);
diff --git a/drv/i2c/ssd1306.h b/drv/i2c/ssd1306.h
index c0a2516..b5a312d 100644
--- a/drv/i2c/ssd1306.h
+++ b/drv/i2c/ssd1306.h
@@ -20,7 +20,7 @@
 #define SSD1306_H
 
 #include "ssd130x.h"
-#include "fonts_ssd1306.h"
+//#include "fonts.h"
 #include "i2cdrv.h"
 
 class SSD1306 : public SSD130X, public I2CDevice
@@ -36,7 +36,7 @@ class SSD1306 : public SSD130X, public I2CDevice
 
 	static SSD1306 *create(uint8_t bus, uint8_t addr);
 	int init(uint8_t maxx, uint8_t maxy, uint8_t options);
-//	int drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override;
+	void drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override;
 //	int drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col) override;
 
 	/*
@@ -70,7 +70,7 @@ class SSD1306 : public SSD130X, public I2CDevice
 	*/
 
 	void flush() override;
-	int setFont(const char *) override;
+//	int setFont(const char *) override;
 	int setBrightness(uint8_t contrast) override;
 //	int setPos(uint16_t x, uint16_t y) override;
 	int setInvert(bool inv) override;
@@ -98,15 +98,16 @@ class SSD1306 : public SSD130X, public I2CDevice
 	int drawChar(char c);
 	int readByte(uint8_t x, uint8_t y, uint8_t *b);
 	int drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m);
-	uint8_t fontHeight() const;
+//	uint8_t fontHeight() const;
 
 	static SSD1306 *Instance;
 //	uint8_t m_maxx = 0, m_maxy = 0, m_posx = 0, m_posy = 0;
 //	uint8_t *m_disp = 0;
 //	uint8_t m_dirty = 0xff;
-	fontid_t m_font = font_native;
+//	fontid_t m_font = font_native;
 };
 
+unsigned ssd1306_scan(uint8_t bus);
 
 #endif
 
diff --git a/drv/i2c/ti.cpp b/drv/i2c/ti.cpp
index fc572c7..1e539f1 100644
--- a/drv/i2c/ti.cpp
+++ b/drv/i2c/ti.cpp
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2021, Thomas Maier-Komor
+ *  Copyright (C) 2021-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -26,28 +26,51 @@
 #define DEV_ADDR	(0x40<<1)
 #define REG_MANU_ID	0xfe	// manufacturer id register
 #define REG_DEV_ID	0xff	// device id register for TI
+#define DEV_ADDR_LOW	(0x44<<1)
+#define DEV_ADDR_HIGH	(0x47<<1)
 
 #define TAG MODULE_TI
 
-unsigned ti_scan(uint8_t bus)
+
+static unsigned scan_addr(uint8_t bus, uint8_t addr)
 {
-	unsigned n = 0;
 	uint8_t data[2];
-	if (i2c_w1rd(bus,DEV_ADDR,REG_MANU_ID,data,sizeof(data)))
-		return n;
+	if (i2c_w1rd(bus,addr,REG_MANU_ID,data,sizeof(data)))
+		return 0;
 	if ((data[0] != 0x54) || (data[1] != 0x49))
-		return n;
-	if (i2c_w1rd(bus,DEV_ADDR,REG_DEV_ID,data,sizeof(data)))
-		return n;
-	log_dbug(TAG,"found TI device %02x%02x",data[0],data[1]);
+		return 0;
+	if (i2c_w1rd(bus,addr,REG_DEV_ID,data,sizeof(data)))
+		return 0;
+	uint16_t id = (data[0] << 8) | data[1];
+	log_dbug(TAG,"found TI device 0x%04x",id);
 #ifdef CONFIG_HDC1000
-	if ((data[0] == 0x10) && (data[1] == 0x50)) {
-		if (I2CDevice *s = HDC1000::create(bus)) {
+	if ((id = 0x1000) || (id == 0x1050)) {
+		if (I2CDevice *s = HDC1000::create(bus,addr,id)) {
+			s->init();
+			return 1;
+		}
+	}
+#endif
+#ifdef CONFIG_OPT3001
+	if (id == 0x3001) {
+		if (I2CDevice *s = OPT3001::create(bus,addr)) {
 			s->init();
-			++n;
+			return 1;
 		}
 	}
 #endif
+	return 0;
+
+}
+
+
+unsigned ti_scan(uint8_t bus)
+{
+	unsigned n = 0;
+	log_info(TAG,"search TI devices on bus %u",bus);
+	scan_addr(bus,DEV_ADDR);
+	for (uint8_t addr = DEV_ADDR_LOW; addr <= DEV_ADDR_HIGH; addr += 2)
+		scan_addr(bus,addr);
 	return n;
 }
 
diff --git a/drv/onewire/onewire.cpp b/drv/onewire/onewire.cpp
index 7b810bb..8b26b32 100644
--- a/drv/onewire/onewire.cpp
+++ b/drv/onewire/onewire.cpp
@@ -35,7 +35,7 @@
 #define ets_delay_us esp_rom_delay_us
 #endif
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#ifdef ESP32
 #include <rom/crc.h>
 #define ENTER_CRITICAL() portDISABLE_INTERRUPTS()
 #define EXIT_CRITICAL() portENABLE_INTERRUPTS()
diff --git a/drv/relay/relay.h b/drv/relay/relay.h
index a2be003..33cd925 100644
--- a/drv/relay/relay.h
+++ b/drv/relay/relay.h
@@ -75,7 +75,7 @@ class Relay
 
 	private:
 	Relay(const char *, xio_t gpio, uint32_t minitv, bool onlvl);
-	static void timerCallback(void *);
+	static void timerCallback(TimerHandle_t h);
 	void sync();
 
 	static Relay *Relays;
diff --git a/drv/spi/ili9341.cpp b/drv/spi/ili9341.cpp
index e0faa3c..29380c1 100644
--- a/drv/spi/ili9341.cpp
+++ b/drv/spi/ili9341.cpp
@@ -37,7 +37,7 @@
 #define ets_delay_us esp_rom_delay_us
 #endif
 
-#if 1
+#if 0
 #define log_devel log_dbug
 #else
 #define log_devel(...)
@@ -135,6 +135,7 @@ struct CmdName {
 	const char *name;
 };
 
+
 CmdName CmdNames[] = {
 	{ CMD_NOP, "NOP" },
 	{ CMD_RESET, "RESET" },
@@ -205,6 +206,26 @@ CmdName CmdNames[] = {
 ILI9341 *ILI9341::Instance = 0;
 
 
+static IRAM_ATTR void ili9341_pre_cb(spi_transaction_t *t)
+{
+	if (ili_trans_t *i = (ili_trans_t *) t->user) {
+		if (i->setc)
+			gpio_set_level(i->gpio,0);
+		else if (i->setd)
+			gpio_set_level(i->gpio,1);
+	}
+}
+
+
+static IRAM_ATTR void ili9341_post_cb(spi_transaction_t *t)
+{
+	if (ili_trans_t *i = (ili_trans_t *) t->user) {
+		if (i->sem)
+			xSemaphoreGive(i->sem);
+	}
+}
+
+
 ILI9341::ILI9341(uint8_t cs, uint8_t dc, int8_t reset, SemaphoreHandle_t sem, spi_device_handle_t hdl)
 : MatrixDisplay(cs_bgr16)
 , SpiDevice(drvName(), cs)
@@ -263,18 +284,6 @@ void ILI9341::checkPowerMode()
 }
 
 
-inline void ILI9341::setC()
-{
-	gpio_set_level(m_dc,0);
-}
-
-
-inline void ILI9341::setD()
-{
-	gpio_set_level(m_dc,1);
-}
-
-
 #ifdef CONFIG_IDF_TARGET_ESP8266
 ILI9341 *ILI9341::create(spi_host_device_t host, int8_t cs, int8_t dc, int8_t reset)
 #else
@@ -313,9 +322,11 @@ ILI9341 *ILI9341::create(spi_host_device_t host, spi_device_interface_config_t &
 	cfg.command_bits = 0;
 	cfg.address_bits = 0;
 	cfg.cs_ena_pretrans = 0;
-	cfg.clock_speed_hz = SPI_MASTER_FREQ_8M;	// maximum: 10MHz
+//	cfg.clock_speed_hz = SPI_MASTER_FREQ_8M;	// maximum: 10MHz
+	cfg.clock_speed_hz = SPI_MASTER_FREQ_10M;	// maximum: 10MHz
 	cfg.queue_size = 8;
-	cfg.post_cb = spidrv_post_cb_relsem;
+	cfg.pre_cb = ili9341_pre_cb;
+	cfg.post_cb = ili9341_post_cb;
 	spi_device_handle_t hdl;
 	if (esp_err_t e = spi_bus_add_device(host,&cfg,&hdl)) {
 		log_warn(TAG,"device add failed: %s",esp_err_to_name(e));
@@ -424,16 +435,6 @@ int ILI9341::setBrightness(uint8_t v)
 }
 
 
-uint8_t ILI9341::fontHeight() const
-{
-	switch (m_font) {
-	case -1: return 8;
-	case -2: return 16;
-	default:
-		return Fonts[m_font].yAdvance;
-	}
-}
-
 void ILI9341::flush()
 {
 	log_dbug(TAG,"flush %ux%u",m_width,m_height);
@@ -487,14 +488,14 @@ void ILI9341::commitOffScreen()
 	// TODO: full-off-screen is in non-DMA - i.e. could be one transaction
 	uint32_t n = m_osw*m_osh<<1;
 	uint32_t t = n > SPI_MAX_TX ? SPI_MAX_TX : n;
-	writeData((uint8_t*)m_os,t);
+	writeBytes((uint8_t*)m_os,t,pre_d);
 	uint32_t off = 0;
 	n -= t;
 	while (n) {
 		off += t;
 		t = n > SPI_MAX_TX ? SPI_MAX_TX : n;
 		writeCmd(CMD_WRMEMC);
-		writeData((uint8_t*)m_os+off,t);
+		writeBytes((uint8_t*)m_os+off,t,pre_d);
 		n -= t;
 	}
 }
@@ -639,10 +640,12 @@ void ILI9341::fillRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t c
 		unsigned b = (n*2 > SPI_MAX_TX) ? (SPI_MAX_TX>>1) : n;
 		log_dbug(TAG,"n=%u, b=%u",n,b);
 		wmemset((wchar_t*)m_temp,col,b);
-		setD();
+//		setD();
+		preop_t pre = pre_d;
 		do {
 			unsigned s = ((n<<1) > SPI_MAX_TX) ? SPI_MAX_TX : n<<1;
-			writeBytes((uint8_t*)m_temp,s);
+			writeBytes((uint8_t*)m_temp,s,pre);
+			pre = pre_none;
 			n -= (s >> 1);
 		} while (n);
 	}
@@ -663,10 +666,8 @@ int ILI9341::readRegs(uint8_t reg, uint8_t *data, uint8_t num)
 	}
 	assert(num > 1);
 	bzero(data,num);
-	setC();
-	spi_transaction_t *t = getTransaction();
-	bzero(t,sizeof(*t));
-	t->user = m_sem;
+	spi_transaction_t *t = getTransaction(pre_c);
+	((ili_trans_t *)t->user)->sem = m_sem;
 	if (num <= 4) {
 		t->tx_data[0] = reg;
 		t->flags = SPI_TRANS_USE_RXDATA|SPI_TRANS_USE_TXDATA;
@@ -712,8 +713,7 @@ unsigned ILI9341::drawText(uint16_t x, uint16_t y, const char *txt, int n, int32
 	log_dbug(TAG,"drawText(%d,%d,'%s')",x,y,txt);
 	if (n < 0)
 		n = strlen(txt);
-	const Font *font = Fonts+(int)m_font;
-	uint16_t h= font->yAdvance;
+	uint16_t h= m_font->yAdvance;
 	uint16_t a = 0;
 	const char *at = txt, *e = txt + n;
 	while (at != e) {
@@ -766,32 +766,6 @@ unsigned ILI9341::drawText(uint16_t x, uint16_t y, const char *txt, int n, int32
 		++at;
 	}
 	return a;
-#if 0
-	uint16_t width = 0;
-	const char *e = txt + n;
-	const char *at = txt;
-	while (at != e) {
-		char c = *at++;
-		if ((c < font->first) || (c > font->last))
-			continue;
-		if (c == '\n') {
-			height += font->yAdvance;
-		} else {
-			uint8_t ch = c - font->first;
-			if (x + font->glyph[ch].xAdvance > m_width)
-				break;
-			width += font->glyph[ch].xAdvance;
-		}
-	}
-	e = at;
-	at = txt;
-	while (at != e) {
-		// TODO
-		uint8_t c = *at++;
-		const uint8_t *data = font->bitmap + font->glyph[c].bitmapOffset;
-	}
-	return a;
-#endif
 }
 
 
@@ -805,24 +779,9 @@ int ILI9341::writeCmd(uint8_t v)
 				break;
 			}
 		}
-		log_devel(TAG,"writeCmd 0x%02x/CMD_%s",v,cmd);
-	}
-#if 0
-	setC();
-	spi_transaction_t t;
-	bzero(&t,sizeof(t));
-	t.user = m_sem;
-	t.cmd = v;
-	if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) {
-		log_warn(TAG,"error queuing writeCmd: %s",esp_err_to_name(e));
-		return -1;
+		log_dbug(TAG,"writeCmd 0x%02x/CMD_%s",v,cmd);
 	}
-	if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT))
-		abort_on_mutex(m_sem,"ili9341");
-#else
-	setC();
-	writeByte(v);
-#endif
+	writeByte(v,pre_c);
 	return 0;
 }
 
@@ -839,27 +798,8 @@ int ILI9341::writeCmdArg(uint8_t v, uint8_t a)
 		}
 		log_dbug(TAG,"writeCmdArg 0x%02x/CMD_%s 0x%02x",v,cmd,a);
 	}
-#if 0
-	setC();
-	spi_transaction_t t;
-	bzero(&t,sizeof(t));
-	t.user = m_sem;
-	t.cmd = v;
-	t.length = 8;
-	t.tx_data[0] = v;
-	t.flags = SPI_TRANS_USE_TXDATA;
-	if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) {
-		log_warn(TAG,"error queuing writeCmdArg: %s",esp_err_to_name(e));
-		return -1;
-	}
-	if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT))
-		abort_on_mutex(m_sem,"ili9341");
-#else
-	setC();
-	writeByte(v);
-	setD();
-	writeByte(a);
-#endif
+	writeByte(v,pre_c);
+	writeByte(a,pre_d);
 	return 0;
 }
 
@@ -876,80 +816,51 @@ int ILI9341::writeCmdArg(uint8_t v, uint8_t *a, size_t n)
 		}
 		log_hex(TAG,a,n,"writeCmdArg 0x%02x/CMD_%s",v,cmd);
 	}
-#if 0
-	setC();
-	spi_transaction_t t;
-	bzero(&t,sizeof(t));
-	t.user = m_sem;
-	t.cmd = v;
-	t.length = n << 3;
-	if (n <= 4) {
-		t.flags = SPI_TRANS_USE_TXDATA;
-		memcpy(t.tx_data,a,n);
-	} else {
-		t.tx_buffer = a;
-	}
-	if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) {
-		log_warn(TAG,"error queuing writeCmdArg: %s",esp_err_to_name(e));
-		return -1;
-	}
-	if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT))
-		abort_on_mutex(m_sem,"ili9341");
-#else
-	setC();
-	writeByte(v);
-	setD();
-	writeBytes(a,n);
-#endif
+	writeByte(v,pre_c);
+	writeBytes(a,n,pre_d);
 	return 0;
 }
 
 
 int ILI9341::writeData(uint8_t v)
 {
-	setD();
-	return writeByte(v);
+	return writeByte(v,pre_d);
 }
 
 
 int ILI9341::writeData(uint8_t *v, unsigned len)
 {
-	setD();
-	return writeBytes(v,len);
+	return writeBytes(v,len,pre_d);
 }
 
 
 int ILI9341::readData(uint8_t *v, unsigned len)
 {
-	setD();
-	return readBytes(v,len);
+	return readBytes(v,len,pre_d);
 }
 
 
-int ILI9341::readBytes(uint8_t *data, unsigned len)
+int ILI9341::readBytes(uint8_t *data, unsigned len, preop_t pre)
 {
-	// TODO test
 	log_devel(TAG,"readBytes %p: %u",data,len);
 	assert(data);
 	esp_err_t e = 0;
-	size_t off = 0;
 	spi_device_acquire_bus(m_hdl,portMAX_DELAY);
 	while (len) {
-		spi_transaction_t *t = getTransaction();
-		bzero(t,sizeof(*t));
-		t->tx_buffer = data + off;
-		t->rx_buffer = data + off;
+		spi_transaction_t *t = getTransaction(pre);
+		t->tx_buffer = data;
+		t->rx_buffer = data;
 		if (len > SPI_MAX_TX) {
 			t->length = SPI_MAX_TX<<3;
 			t->rxlength = SPI_MAX_TX<<3;
 			t->flags = SPI_TRANS_CS_KEEP_ACTIVE;
 			len -= SPI_MAX_TX;
-			off += SPI_MAX_TX;
+			data += SPI_MAX_TX;
 		} else {
 			t->length = len<<3;
 			t->rxlength = len<<3;
 			len = 0;
-			t->user = m_sem;
+			((ili_trans_t *)t->user)->sem = m_sem;
 		}
 		log_devel(TAG,"readBytes %d@%p",t->length>>3,t->tx_buffer);
 		e = spi_device_queue_trans(m_hdl,t,portMAX_DELAY);
@@ -965,11 +876,9 @@ int ILI9341::readBytes(uint8_t *data, unsigned len)
 }
 
 
-int ILI9341::writeByte(uint8_t v)
+int ILI9341::writeByte(uint8_t v, preop_t pre)
 {
-	spi_transaction_t *t = getTransaction();
-	bzero(t,sizeof(*t));
-//	t->user = m_sem;
+	spi_transaction_t *t = getTransaction(pre);
 	t->cmd = v;
 	t->length = 8;
 	t->flags = SPI_TRANS_USE_TXDATA;
@@ -978,34 +887,43 @@ int ILI9341::writeByte(uint8_t v)
 		log_warn(TAG,"error queuing writeByte: %s",esp_err_to_name(e));
 		return -1;
 	}
-//	if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT))
-//		abort_on_mutex(m_sem,"ili9341");
 //	log_dbug(TAG,"writeB 0x%02x",v);
 	return 0;
 }
 
 
-spi_transaction_t *ILI9341::getTransaction()
+spi_transaction_t *ILI9341::getTransaction(preop_t pre)
 {
+	ili_trans_t *i = 0;
 	while (m_xtrans == 0xff) {
 		spi_transaction_t *r;
-		esp_err_t x = spi_device_get_trans_result(m_hdl,&r,portMAX_DELAY);
-		if (x == 0) {
-			int id = r - m_trans;
-			if ((id >= 0) && (id < 8))
-				m_xtrans &= ~(1<<id);
+		if (0 == spi_device_get_trans_result(m_hdl,&r,portMAX_DELAY)) {
+			i = (ili_trans_t *)r;
+			int id = i - m_trans;
+			assert((id >= 0) && (id < sizeof(m_trans)/sizeof(m_trans[0])));
+			break;
 		}
 	}
-	unsigned x = 0;
-	while (m_xtrans & (1 << x))
-		++x;
-	m_xtrans |= (1<<x);
-	assert(x < 8);
-	return m_trans+x;
+	if (i == 0) {
+		unsigned x = 0;
+		while (m_xtrans & (1 << x))
+			++x;
+		m_xtrans |= (1<<x);
+		assert(x < sizeof(m_trans)/sizeof(m_trans[0]));
+		i = m_trans+x;
+	}
+	bzero(i,sizeof(ili_trans_t));
+	i->trans.user = i;
+	i->gpio = m_dc;
+	if (pre == pre_c)
+		i->setc = true;
+	else if (pre == pre_d)
+		i->setd = true;
+	return &i->trans;
 }
 
 
-int ILI9341::writeBytes(uint8_t *data, unsigned len)
+int ILI9341::writeBytes(uint8_t *data, unsigned len, preop_t pre)
 {
 	PROFILE_FUNCTION();
 	log_devel(TAG,"writeBytes %u@%p",len,data);
@@ -1013,18 +931,18 @@ int ILI9341::writeBytes(uint8_t *data, unsigned len)
 	esp_err_t e = 0;
 	uint8_t *end = data + len;
 	while (data != end) {
-		spi_transaction_t *t = getTransaction();
-		bzero(t,sizeof(spi_transaction_t));
+		spi_transaction_t *t = getTransaction(pre);
+		pre = pre_none;
 		t->rxlength = 8;
 		t->flags = SPI_TRANS_USE_RXDATA;
 		t->tx_buffer = data;
+		pre = pre_none;
 		if (end-data > SPI_MAX_TX) {
 			t->length = SPI_MAX_TX<<3;
 			data += SPI_MAX_TX;
 		} else {
-			t->length = len<<3;
-			t->user = m_sem;
-			len = 0;
+			t->length = (end-data)<<3;
+			((ili_trans_t *)t->user)->sem = m_sem;
 			data = end;
 		}
 //		log_devel(TAG,"writeBytes %d@%p",t.length>>3,t.tx_buffer);
diff --git a/drv/spi/ili9341.h b/drv/spi/ili9341.h
index e7dfd5b..7118fc9 100644
--- a/drv/spi/ili9341.h
+++ b/drv/spi/ili9341.h
@@ -29,6 +29,14 @@
 #include <driver/gpio.h>
 
 
+struct ili_trans_t {
+	spi_transaction_t trans;
+	SemaphoreHandle_t sem;
+	gpio_num_t gpio;
+	bool setc, setd;
+};
+
+
 class ILI9341 : public MatrixDisplay, public SpiDevice
 {
 	public:
@@ -45,12 +53,6 @@ class ILI9341 : public MatrixDisplay, public SpiDevice
 	void flush() override;
 	int32_t getColor(color_t) const override;
 
-	int setFont(unsigned f) override
-	{
-		m_font = (fontid_t) f;
-		return 0;
-	}
-
 	int setBrightness(uint8_t contrast) override;
 	int setInvert(bool inv) override;
 	int setOn(bool on) override;
@@ -73,17 +75,17 @@ class ILI9341 : public MatrixDisplay, public SpiDevice
 
 	private:
 	ILI9341(uint8_t cs, uint8_t cd, int8_t r, SemaphoreHandle_t sem, spi_device_handle_t hdl);
-	uint8_t fontHeight() const;
+
+	typedef enum { pre_none, pre_c, pre_d } preop_t;
+
 	static void postCallback(spi_transaction_t *t);
-	void setC();
-	void setD();
 	void sleepIn();
 	void sleepOut();
 	void reset();
 	int readRegs(uint8_t reg, uint8_t *data, uint8_t num);
-	int readBytes(uint8_t *data, unsigned len);
-	int writeByte(uint8_t);
-	int writeBytes(uint8_t *data, unsigned len);
+	int readBytes(uint8_t *data, unsigned len, preop_t = pre_none);
+	int writeByte(uint8_t, preop_t = pre_none);
+	int writeBytes(uint8_t *data, unsigned len, preop_t = pre_none);
 	int readData(uint8_t *data, unsigned len);
 	int writeData(uint8_t data);
 	int writeData(uint8_t *data, unsigned len);
@@ -97,7 +99,7 @@ class ILI9341 : public MatrixDisplay, public SpiDevice
 	void commitOffScreen();
 
 	static int readRegs(spi_device_handle_t hdl, uint8_t reg, uint8_t num, uint8_t *data, SemaphoreHandle_t);
-	spi_transaction_t *getTransaction();
+	spi_transaction_t *getTransaction(preop_t);
 
 	static ILI9341 *Instance;
 	uint32_t m_oss = 0;
@@ -106,7 +108,7 @@ class ILI9341 : public MatrixDisplay, public SpiDevice
 	uint16_t m_osx = 0xffff, m_osy = 0xffff, m_osw, m_osh;
 	spi_device_handle_t m_hdl;
 	SemaphoreHandle_t m_sem;
-	spi_transaction_t m_trans[8];
+	ili_trans_t m_trans[8];
 	uint8_t m_xtrans = 0;
 	bool m_fos = false;	// full off-screen memory
 	gpio_num_t m_dc, m_reset;
diff --git a/drv/spi/ssd1309.cpp b/drv/spi/ssd1309.cpp
index c4bac3c..a736666 100644
--- a/drv/spi/ssd1309.cpp
+++ b/drv/spi/ssd1309.cpp
@@ -24,7 +24,7 @@
 #include "log.h"
 #include "profiling.h"
 
-#include "fonts_ssd1306.h"
+//#include "fonts.h"
 #include <stdlib.h>
 #include <string.h>
 
@@ -282,7 +282,6 @@ void SSD1309::clear()
 	m_posy = 0;
 	log_dbug(TAG,"clear: dirty %x",m_dirty);
 }
-*/
 
 
 uint8_t SSD1309::fontHeight() const
@@ -291,12 +290,11 @@ uint8_t SSD1309::fontHeight() const
 	case -1: return 8;
 	case -2: return 16;
 	default:
-		return Fonts[m_font].yAdvance;
+		return FontsCM[m_font].yAdvance;
 	}
 }
 
 
-/*
 int SSD1309::clrEol()
 {
 	clearRect(m_posx,m_posy,m_width-m_posx,fontHeight());
diff --git a/drv/spi/ssd1309.h b/drv/spi/ssd1309.h
index d9827df..5564ac7 100644
--- a/drv/spi/ssd1309.h
+++ b/drv/spi/ssd1309.h
@@ -20,7 +20,7 @@
 #define SSD1309_H
 
 #include "ssd130x.h"
-#include "fonts_ssd1306.h"
+//#include "fonts.h"
 #include "spidrv.h"
 
 #include <freertos/FreeRTOS.h>
@@ -113,7 +113,7 @@ class SSD1309 : public SSD130X, public SpiDevice
 	void drawHLine(uint16_t x, uint16_t y, uint16_t n);
 	void drawVLine(uint16_t x, uint16_t y, uint16_t n);
 	int drawChar(char c);
-	uint8_t fontHeight() const;
+//	uint8_t fontHeight() const;
 #ifndef CONFIG_IDF_TARGET_ESP8266
 	static void postCallback(spi_transaction_t *t);
 #endif
@@ -129,7 +129,7 @@ class SSD1309 : public SSD130X, public SpiDevice
 	gpio_num_t m_dc, m_reset;
 //	uint8_t m_maxx = 0, m_maxy = 0, m_posx = 0, m_posy = 0, m_dirty = 0xff;
 //	uint8_t m_dirty = 0xff;
-	fontid_t m_font = font_native;
+//	fontid_t m_font = font_native;
 };
 
 
diff --git a/drv/spi/sx1276.cpp b/drv/spi/sx1276.cpp
index 0c17686..0a7c9bb 100644
--- a/drv/spi/sx1276.cpp
+++ b/drv/spi/sx1276.cpp
@@ -33,6 +33,7 @@
 #include <driver/gpio.h>
 #include <driver/spi_master.h>
 #include <esp_timer.h>
+#include <rom/ets_sys.h>
 
 
 #define REG_FIFO			0x00
diff --git a/drv/spi/xpt2046.cpp b/drv/spi/xpt2046.cpp
index d5074f4..6eb15fb 100644
--- a/drv/spi/xpt2046.cpp
+++ b/drv/spi/xpt2046.cpp
@@ -45,6 +45,9 @@
 #define REG_Z1		(BIT_START|BIT_A1|BIT_A0)
 #define REG_Z2		(BIT_START|BIT_A2)
 
+#if IDF_VERSION >= 50
+#define gpio_pad_select_gpio(...)
+#endif
 
 XPT2046 *XPT2046::Instance = 0;
 
diff --git a/drv/ws8212b/ws2812b.cpp b/drv/ws8212b/ws2812b.cpp
index 8d4457c..1947929 100644
--- a/drv/ws8212b/ws2812b.cpp
+++ b/drv/ws8212b/ws2812b.cpp
@@ -20,9 +20,6 @@
 
 
 #ifdef CONFIG_RGBLEDS
-// CONFIG_IDF_TARGET_ESP32 rmt does not work before IDF release v3.2!!!
-// CONFIG_IDF_TARGET_ESP8266 for some reason doesn't achieve the necessary performance!!!
-// Placing the critical section in IRAM didn't give any benfit.
 
 #include "log.h"
 #include "ws2812b.h"
@@ -171,9 +168,9 @@ IRAM_ATTR void ws2812b_reset(unsigned gpio, uint16_t tr)
 #endif	// CONFIG_IDF_TARGET_ESP8266
 
 
-int WS2812BDrv::init(gpio_num_t gpio, size_t nleds, rmt_channel_t ch)
+int WS2812BDrv::init(gpio_num_t gpio, size_t nleds, int ch)
 {
-	log_dbug(TAG,"init(%u,%u,%u)",gpio,nleds,ch);
+	log_dbug(TAG,"init(%u,%u,%d)",gpio,nleds,ch);
 #if defined CONFIG_IDF_TARGET_ESP8266
 	int f = esp_clk_cpu_freq();
 	if (f == 160000000) {
@@ -195,14 +192,69 @@ int WS2812BDrv::init(gpio_num_t gpio, size_t nleds, rmt_channel_t ch)
 #endif
 	m_num = 0;
 	m_gpio = gpio;
-	m_set = (uint8_t*) calloc(1,nleds*3*2);
+	m_set = (uint8_t*) malloc(nleds*3*2);
 	if (m_set == 0) {
 		log_error(TAG,"Out of memory.");
 		return 1;
 	}
+	bzero(m_set,nleds*3*2);
 	m_cur = m_set+nleds*3;
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
-	if (ch == (rmt_channel_t)-1) {
+#if IDF_VERSION >= 50
+	rmt_tx_channel_config_t txccfg;
+	bzero(&txccfg,sizeof(txccfg));
+	txccfg.clk_src = RMT_CLK_SRC_DEFAULT;
+	txccfg.gpio_num = gpio;
+//	txccfg.mem_block_symbols = nleds*3;
+	txccfg.mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL;
+	txccfg.resolution_hz = 80000000;
+	txccfg.trans_queue_depth = 1;
+//	txccfg.flags.with_dma = 1;
+	if (esp_err_t e = rmt_new_tx_channel(&txccfg,&m_ch))
+		log_warn(TAG,"create tx channel: %s",esp_err_to_name(e));
+	rmt_enable(m_ch);
+	/*
+	rmt_bytes_encoder_config_t benccfg = {
+		.bit0 = {
+			.level0 = 1,
+			.duration0 = T0H,
+			.level1 = 0,
+			.duration1 = T0L,
+		},
+		.bit1 = {
+			.level0 = 1,
+			.duration0 = T1H,
+			.level1 = 0,
+			.duration1 = T1L,
+		},
+		.flags = {
+			.msb_first = 1,
+		},
+	};
+	*/
+	rmt_bytes_encoder_config_t benccfg;
+	bzero(&benccfg,sizeof(benccfg));
+	benccfg.bit0.level0 = 1;
+	benccfg.bit0.duration0 = T0H;
+	benccfg.bit0.level1 = 0;
+	benccfg.bit0.duration1 = T0L;
+	benccfg.bit1.level0 = 1;
+	benccfg.bit1.duration0 = T1H;
+	benccfg.bit1.level1 = 0;
+	benccfg.bit1.duration1 = T1L;
+	benccfg.flags.msb_first = 1;
+	if (esp_err_t e = rmt_new_bytes_encoder(&benccfg, &m_benc))
+		log_warn(TAG,"create byte encoder: %s",esp_err_to_name(e));
+	rmt_copy_encoder_config_t cenccfg = {};
+	if (esp_err_t e = rmt_new_copy_encoder(&cenccfg, &m_cenc))
+		log_warn(TAG,"create copy encoder: %s",esp_err_to_name(e));
+	bzero(&m_rstsym,sizeof(m_rstsym));
+//	m_rstsym.level0 = 0;
+	m_rstsym.duration0 = TR;
+//	m_rstsym.level1 = 0;
+//	m_rstsym.duration1 = 0;
+#else
+	if (ch == -1) {
 		log_warn(TAG,"channel not set");
 		return 1;
 	}
@@ -211,7 +263,7 @@ int WS2812BDrv::init(gpio_num_t gpio, size_t nleds, rmt_channel_t ch)
 		log_error(TAG,"Out of memory.");
 		return 1;
 	}
-	m_ch = ch;
+	m_ch = (rmt_channel_t)ch;
 	rmt_config_t rmt_tx;
 	memset(&rmt_tx,0,sizeof(rmt_tx));
 	rmt_tx.channel = m_ch;
@@ -232,7 +284,8 @@ int WS2812BDrv::init(gpio_num_t gpio, size_t nleds, rmt_channel_t ch)
 		return 1;
 	}
 	log_dbug(TAG,"rmt driver installed on channel %u",m_ch);
-#else
+#endif
+#else	// no SOC_RMT_GROUPS
 	gpio_pad_select_gpio(m_gpio);
 	if (esp_err_t e = gpio_set_direction(m_gpio, GPIO_MODE_OUTPUT)) {
 		log_warn(TAG,"cannot set %u to output: %s",m_gpio,esp_err_to_name(e));
@@ -323,7 +376,7 @@ void WS2812BDrv::set_leds(uint32_t rgb)
 }
 
 
-void WS2812BDrv::timerCallback(void *h)
+void WS2812BDrv::timerCallback(TimerHandle_t h)
 {
 	WS2812BDrv *d = (WS2812BDrv *)pvTimerGetTimerID(h);
 	bool remain = false;
@@ -363,8 +416,17 @@ void WS2812BDrv::commit()
 		return;
 	//log_info(TAG,"update0");
 	assert(m_set);
-	uint8_t *v = m_cur, *e = m_cur+m_num*3;
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
+#if IDF_VERSION >= 50
+//	rmt_encode_state_t st;
+//	m_benc->encode(m_benc,m_ch,v,m_num*3,&st);
+	rmt_transmit_config_t txcfg;
+	bzero(&txcfg,sizeof(txcfg));
+	txcfg.loop_count = 0;
+	if (esp_err_t e = rmt_transmit(m_ch,m_benc,m_cur,m_num*3,&txcfg))
+		log_warn(TAG,"error transmitting: %s",esp_err_to_name(e));
+#else
+	uint8_t *v = m_cur, *e = m_cur+m_num*3;
 	assert(m_items);
 	rmt_item32_t *r = m_items;
 	while (v != e) {
@@ -392,7 +454,9 @@ void WS2812BDrv::commit()
 	assert(r-m_items <= 24*m_num+1);
 	//log_info(TAG,"writing %u items",r-m_items);
 	rmt_write_items(m_ch, m_items, m_num*24+1, false);
+#endif
 #else
+	uint8_t *v = m_cur, *e = m_cur+m_num*3;
 	uint8_t tmp[e-v];		// move data to IRAM!
 	memcpy(tmp,v,sizeof(tmp));
 	ws2812b_write(1 << m_gpio,tmp,tmp+sizeof(tmp),m_t0l,m_t0h,m_t1l,m_t1h);
@@ -405,12 +469,20 @@ void WS2812BDrv::reset()
 {
 	//log_info(TAG,"reset0");
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
+#if IDF_VERSION >= 50
+#else
 	rmt_item32_t rst;
 	rst.level0 = 0;
 	rst.level1 = 0;
 	rst.duration0 = TR;
 	rst.duration1 = 0;
 	rmt_write_items(m_ch, &rst, 1, true);
+#endif
+	rmt_transmit_config_t txcfg;
+	bzero(&txcfg,sizeof(txcfg));
+	txcfg.loop_count = 0;
+	if (esp_err_t e = rmt_transmit(m_ch,m_cenc,&m_rstsym,1,&txcfg))
+		log_warn(TAG,"error transmitting: %s",esp_err_to_name(e));
 #else
 	ws2812b_reset(1 << m_gpio,m_tr);
 #endif
diff --git a/drv/ws8212b/ws2812b.h b/drv/ws8212b/ws2812b.h
index fc84498..ba2b0bb 100644
--- a/drv/ws8212b/ws2812b.h
+++ b/drv/ws8212b/ws2812b.h
@@ -27,9 +27,13 @@
 #if IDF_VERSION >= 44
 #include <soc/soc_caps.h>
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
+#if IDF_VERSION >= 50
+#include <driver/rmt_tx.h>
+#else
 #include <driver/rmt.h>
 #endif
 #endif
+#endif
 
 #ifndef SOC_RMT_GROUPS
 #define SOC_RMT_GROUPS 0
@@ -66,7 +70,7 @@ class WS2812BDrv
 		free(m_name);
 	}
 
-	int init(gpio_num_t gpio, size_t nleds, rmt_channel_t ch = (rmt_channel_t)-1);
+	int init(gpio_num_t gpio, size_t nleds, int ch = -1);
 	void set_led(size_t l, uint8_t r, uint8_t g, uint8_t b);
 	void set_led(size_t l, uint32_t rgb);
 	void set_leds(uint32_t rgb);
@@ -85,7 +89,7 @@ class WS2812BDrv
 	WS2812BDrv(const WS2812BDrv &);
 	WS2812BDrv& operator = (const WS2812BDrv &);
 
-	static void timerCallback(void *);
+	static void timerCallback(TimerHandle_t h);
 	void commit();
 
 	static WS2812BDrv *First;
@@ -93,13 +97,21 @@ class WS2812BDrv
 	WS2812BDrv *m_next = 0;
 	uint8_t *m_set, *m_cur;
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
+#if IDF_VERSION >= 50
+	rmt_encoder_t *m_benc = 0, *m_cenc = 0;
+	rmt_symbol_word_t m_rstsym;
+	rmt_channel_handle_t m_ch;
+#else
 	rmt_item32_t *m_items = 0;
+#endif
 #endif
 	size_t m_num;
 	TimerHandle_t m_tmr;
 	gpio_num_t m_gpio;
 #if defined SOC_RMT_GROUPS && SOC_RMT_GROUPS > 0
+#if IDF_VERSION < 50
 	rmt_channel_t m_ch;
+#endif
 #else
 	uint8_t m_t0l,m_t0h,m_t1l,m_t1h;
 	uint16_t m_tr;
diff --git a/drv/xio/esp32-c3_io.cpp b/drv/xio/esp32-c3_io.cpp
index e2e6020..148b182 100644
--- a/drv/xio/esp32-c3_io.cpp
+++ b/drv/xio/esp32-c3_io.cpp
@@ -18,7 +18,7 @@
 
 #include <sdkconfig.h>
 
-#if defined CONFIG_IDF_TARGET_ESP32C3 && defined CONFIG_IOEXTENDERS
+#if (defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32C6) && defined CONFIG_IOEXTENDERS
 
 #include "coreio.h"
 #include "log.h"
@@ -26,7 +26,7 @@
 #include "soc/gpio_periph.h"
 #include <errno.h>
 #include <driver/gpio.h>
-
+#include <rom/gpio.h>
 
 #define TAG MODULE_GPIO
 
diff --git a/drv/xio/esp32_io.cpp b/drv/xio/esp32_io.cpp
index 279ddcc..f3d4ff9 100644
--- a/drv/xio/esp32_io.cpp
+++ b/drv/xio/esp32_io.cpp
@@ -66,12 +66,15 @@ struct CoreIO1 : public XioCluster
 	int set_lvl(uint8_t io, xio_lvl_t v) override;
 	const char *getName() const override;
 	unsigned numIOs() const override;
+#define COREIO0_NUMIO 32
 #if defined CONFIG_IDF_TARGET_ESP32
 	#define COREIO1_NUMIO 8
 #elif defined CONFIG_IDF_TARGET_ESP32S2
 	#define COREIO1_NUMIO 15
 #elif defined CONFIG_IDF_TARGET_ESP32S3
 	#define COREIO1_NUMIO 17
+//#elif defined CONFIG_IDF_TARGET_ESP32C6
+//	#define COREIO1_NUMIO 17
 #else
 #error unknown device
 #endif
@@ -96,7 +99,7 @@ const char *CoreIO1::getName() const
 
 unsigned CoreIO0::numIOs() const
 {
-	return 32;
+	return COREIO0_NUMIO;
 }
 
 
@@ -109,7 +112,7 @@ unsigned CoreIO1::numIOs() const
 int CoreIO0::config(uint8_t num, xio_cfg_t cfg)
 {
 	log_dbug(TAG,"config0 %u,0x%x",num,cfg);
-	if (num >= 32) {
+	if (num >= COREIO0_NUMIO) {
 		log_warn(TAG,"invalid gpio%u",num);
 		return -EINVAL;
 	}
@@ -184,6 +187,7 @@ int CoreIO0::config(uint8_t num, xio_cfg_t cfg)
 	}
 
 	if (cfg.cfg_pull == xio_cfg_pull_keep) {
+		log_dbug(TAG,"keep pull %u",num);
 	} else if (cfg.cfg_pull == xio_cfg_pull_none) {
 		REG_CLR_BIT(GPIO_PIN_MUX_REG[num], FUN_PU);
 		REG_CLR_BIT(GPIO_PIN_MUX_REG[num], FUN_PD);
@@ -245,18 +249,20 @@ int CoreIO0::config(uint8_t num, xio_cfg_t cfg)
 int CoreIO1::config(uint8_t num, xio_cfg_t cfg)
 {
 	log_dbug(TAG,"config1 %u,0x%x",num,cfg);
-	if (num >= 8) {
-		log_warn(TAG,"invalid gpio%u",num);
+	if (num >= COREIO1_NUMIO) {
+		log_warn(TAG,"invalid gpio%u",num+32);
 		return -EINVAL;
 	}
+	int r = 0;
 	uint8_t xnum = num+32;
 	if (cfg.cfg_io == xio_cfg_io_keep) {
+		log_dbug(TAG,"keep io %u",xnum);
 	} else if (cfg.cfg_io == xio_cfg_io_in) {
 		gpio_pad_select_gpio(xnum);
 		PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[xnum]);
 		GPIO.enable1_w1tc.data = (1 << num);
 		GPIO.pin[xnum].pad_driver = 0;
-		REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (num * 4), SIG_GPIO_OUT_IDX);
+		REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (xnum * 4), SIG_GPIO_OUT_IDX);
 	} else if (cfg.cfg_io == xio_cfg_io_out) {
 		gpio_pad_select_gpio(xnum);
 		PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[xnum]);
@@ -274,14 +280,25 @@ int CoreIO1::config(uint8_t num, xio_cfg_t cfg)
 	}
 
 	if (cfg.cfg_pull == xio_cfg_pull_keep) {
+		log_dbug(TAG,"keep pull %u",xnum);
+		if (REG_GET_BIT(GPIO_PIN_MUX_REG[xnum],FUN_PU))
+			r |= xio_cap_pullup;
+		if (REG_GET_BIT(GPIO_PIN_MUX_REG[xnum],FUN_PD))
+			r |= xio_cap_pulldown;
 	} else if (cfg.cfg_pull == xio_cfg_pull_none) {
+		log_dbug(TAG,"pull none %u",xnum);
 		REG_CLR_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PU);
 		REG_CLR_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PD);
 	} else if (cfg.cfg_pull == xio_cfg_pull_up) {
+		log_dbug(TAG,"pull up %u",xnum);
+		REG_CLR_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PD);
 		REG_SET_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PU);
 	} else if (cfg.cfg_pull == xio_cfg_pull_down) {
+		log_dbug(TAG,"pull down %u",xnum);
+		REG_CLR_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PU);
 		REG_SET_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PD);
 	} else if (cfg.cfg_pull == xio_cfg_pull_updown) {
+		log_dbug(TAG,"pull updown %u",num);
 		REG_SET_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PU);
 		REG_SET_BIT(GPIO_PIN_MUX_REG[xnum], FUN_PD);
 	} else {
@@ -289,6 +306,7 @@ int CoreIO1::config(uint8_t num, xio_cfg_t cfg)
 	}
 	
 	if (cfg.cfg_intr == xio_cfg_intr_keep) {
+		log_dbug(TAG,"keep intr %u",xnum);
 	} else if (cfg.cfg_intr == xio_cfg_intr_disable) {
 		GPIO.pin[xnum].int_type = cfg.cfg_intr;
 		GPIO.pin[xnum].int_ena = 0;
@@ -309,6 +327,9 @@ int CoreIO1::config(uint8_t num, xio_cfg_t cfg)
 	}
 
 	if (cfg.cfg_wakeup == xio_cfg_wakeup_keep) {
+		log_dbug(TAG,"keep wakeup %u",xnum);
+		if (REG_GET_BIT(GPIO_PIN_MUX_REG[xnum],SLP_SEL))
+			r |= xio_cap_wakeup;
 	} else if (cfg.cfg_wakeup == xio_cfg_wakeup_disable) {
 		GPIO.pin[xnum].wakeup_enable = 0;
 	} else if (GPIO.pin[xnum].int_type == 4) {
@@ -319,7 +340,7 @@ int CoreIO1::config(uint8_t num, xio_cfg_t cfg)
 		return -EINVAL;
 	}
 
-	return 0x1ff;
+	return r;
 }
 
 
@@ -333,7 +354,7 @@ xio_cfg_t CoreIO0::get_config() const
 
 int CoreIO0::get_dir(uint8_t num) const
 {
-	if (num >= 32)
+	if (num >= COREIO0_NUMIO)
 		return -1;
 	if (GPIO.pin[num].pad_driver)
 		return xio_cfg_io_od;
@@ -357,7 +378,7 @@ int CoreIO1::get_dir(uint8_t num) const
 
 int CoreIO0::get_lvl(uint8_t num)
 {
-	if (num < 32) {
+	if (num < COREIO0_NUMIO) {
 		if (GPIO.enable & (1 << num))
 			return (GPIO.out >> num) & 0x1;
 		else
@@ -369,7 +390,7 @@ int CoreIO0::get_lvl(uint8_t num)
 
 int CoreIO1::get_lvl(uint8_t num)
 {
-	if (num < 32) {
+	if (num < COREIO0_NUMIO) {
 		if (GPIO.enable1.data & (1 << num))
 			return (GPIO.out >> num) & 0x1;
 		else
@@ -485,7 +506,7 @@ int CoreIO1::setm(uint32_t v, uint32_t m)
 
 int CoreIO0::set_intr(uint8_t gpio, xio_intrhdlr_t hdlr, void *arg)
 {
-	if (gpio >= 32) {
+	if (gpio >= COREIO0_NUMIO) {
 		log_warn(TAG,"set intr: invalid gpio%u",gpio);
 		return -EINVAL;
 	}
@@ -636,7 +657,7 @@ int coreio_lvl_set(uint8_t num, xio_lvl_t l)
 void coreio_register()
 {
 	if (esp_err_t e = gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1 | ESP_INTR_FLAG_IRAM))
-		log_error(TAG,"isr service %d",e);
+		log_warn(TAG,"install isr service: %s",esp_err_to_name(e));
 	GpioCluster0.attach(0);
 	GpioCluster1.attach(32);
 }
diff --git a/drv/xio/xio.h b/drv/xio/xio.h
index fa88ce4..46bcaf2 100644
--- a/drv/xio/xio.h
+++ b/drv/xio/xio.h
@@ -24,6 +24,7 @@
 #elif defined CONFIG_IDF_TARGET_ESP32S2
 #elif defined CONFIG_IDF_TARGET_ESP32S3
 #elif defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32C6
 #else
 #error include sdkconfig.h before xio.h
 #endif
diff --git a/hwcfg.wfc b/hwcfg.wfc
index cff0d1a..8671626 100644
--- a/hwcfg.wfc
+++ b/hwcfg.wfc
@@ -250,16 +250,17 @@ bitset i2cdev_t
 	// result in misdetections.
 	uint8 addr : 0..6;
 	i2cdrv_t drv : 8..15;
+	uint8 intr : 16..21;	// 0 = no interrupt, >0: (intr-1)=gpio
 }
 
 
 message I2CConfig
 {
-	uint8 port = 1		[ default = 0 ];
-	sint8 sda = 2		[ unset = -1 ];
-	sint8 scl = 3		[ unset = -1 ];
-	unsigned freq = 4	[ default = 100000 ];
-	bool xpullup = 5	[ unset = false ];	// have external pull-ups
+	uint8 port = 1			[ default = 0 ];
+	sint8 sda = 2			[ unset = -1 ];
+	sint8 scl = 3			[ unset = -1 ];
+	unsigned freq = 4		[ default = 100000 ];
+	bool xpullup = 5		[ unset = false ];	// have external pull-ups
 	repeated i2cdev_t devices = 6	[ packed = true, ifdef=CONFIG_I2C_XDEV ];
 }
 
@@ -420,6 +421,7 @@ enum spidrv_t
 	spidrv_ssd1309 = 2;
 	spidrv_ili9341 = 3;
 	spidrv_xpt2046 = 4;
+	spidrv_sdcard = 5;
 }
 
 
diff --git a/main/CMakeLists.txt b/main/CMakeLists.txt
index ada93be..7a3683f 100644
--- a/main/CMakeLists.txt
+++ b/main/CMakeLists.txt
@@ -51,5 +51,6 @@ idf_component_register(
 	REQUIRES
 	actions app_update button cyclic event dht display event fatfs
 	hc-sr04 hlw8012 i2c logging lua max7219 memfiles onewire relay
-	spi timefuse tlc5947 wpa_supplicant ws8212b espcoredump
-)
+	spi timefuse tlc5947 wpa_supplicant ws8212b espcoredump vfs
+	spi_flash esp_hw_support esp_adc esp_netif esp_rom esp_rom
+	esp_wifi mbedtls)
diff --git a/main/HttpServer.cpp b/main/HttpServer.cpp
index fdcb170..06d9dad 100644
--- a/main/HttpServer.cpp
+++ b/main/HttpServer.cpp
@@ -78,7 +78,11 @@ void HttpServer::addDirectory(const char *d)
 
 void HttpServer::addFunction(const char *name, www_fun_t f)
 {
-	m_functions.insert(make_pair(name,f));
+#if IDF_VERSION >= 50
+	m_functions[name] = f;
+#else
+	m_functions.insert(pair<const char *,www_fun_t>(name,f));
+#endif
 }
 
 
@@ -276,6 +280,8 @@ void HttpServer::performPUT(HttpRequest *req)
 	log_devel(TAG,"put request %s",uri);
 	const char *sl = strrchr(uri,'/');
 	char fn[strlen(m_wwwroot)+strlen(sl)];
+	strcpy(fn,m_wwwroot);
+	strcat(fn,sl);
 	int fd = open(fn,O_CREAT|O_WRONLY,0666);
 	LwTcp *con = req->getConnection();
 	HttpResponse ans;
diff --git a/main/Kconfig b/main/Kconfig
index c644180..201bc01 100644
--- a/main/Kconfig
+++ b/main/Kconfig
@@ -188,7 +188,7 @@ config SPIFFS
 	help
 		SPI Flash File-System
 config FATFS
-	depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3
+	depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
 	bool "fatfs"
 	default false
 	help
@@ -216,7 +216,7 @@ config ROMFS_VFS_NUMFDS
 config USB_HOST_FS
 	bool "USB host filesystem via openocd"
 	default false
-	depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3
+	depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
 	help
 		"mount openocd host filesystem to /usb"
 endmenu # filesystem
@@ -245,6 +245,14 @@ config GPIOS
 	help
 		Named GPIO support
 
+config CORETEMP
+	bool "core temperature sensor"
+	default false
+	depends on DEVEL
+	help
+		Core temperature sensor support is buggy in the IDF. 
+		Workarounds are applied, but may cause build failures.
+
 config IOEXTENDERS
 	bool "I/O extenders"
 	default true
@@ -386,6 +394,13 @@ config MCP2301X
 	help
 		I2C driver for MCP2301x devices (16-port GPIO expander)
 
+config OPT3001
+	depends on I2C && DEVEL
+	bool "opt3001"
+	default true
+	help
+		I2C driver for OPT3001 (light intensity sensor)
+
 config INA2XX
 	bool "ina219"
 	depends on I2C_XDEV
@@ -474,10 +489,17 @@ config SSD1309
 config ILI9341
 	bool "ILI9341"
 	default false
-	depends on SPI && (IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3)
+	depends on SPI && (IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6)
 	help
 		dirver for 4-wire SPI attached ILI9341 display
 
+config SDCARD
+	bool "SD-Card"
+	default true
+	depends on SPI
+	help
+		SD-card/TF-card support
+
 config XPT2046
 	bool "XPT2046"
 	default true
@@ -526,7 +548,7 @@ config DEVEL
 
 config VERIFY_HEAP
 	bool "verify heap"
-	depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3
+	depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
 	default false
 
 config FUNCTION_TIMING
diff --git a/main/adc.cpp b/main/adc.cpp
index c5ee6b2..8b011ac 100644
--- a/main/adc.cpp
+++ b/main/adc.cpp
@@ -25,10 +25,22 @@
 #include "globals.h"
 #include "hwcfg.h"
 #include "log.h"
+#include "profiling.h"
 #include "ringbuf.h"
 #include "terminal.h"
 
+#if IDF_VERSION > 50
+#include <esp_adc/adc_oneshot.h>
+#include <esp_adc/adc_cali_scheme.h>
+#ifdef CONFIG_CORETEMP
+#include <driver/temperature_sensor.h>
+#include <hal/adc_ll.h>
+//#include <hal/temperature_sensor_ll.h>
+#include <soc/temperature_sensor_periph.h>
+#endif
+#else
 #include <driver/adc.h>
+#endif
 
 #ifdef CONFIG_LUA
 #include "luaext.h"
@@ -42,8 +54,11 @@ extern "C" {
 #define TAG MODULE_ADC
 
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#ifdef ESP32
 #include <driver/rtc_io.h>
+#if IDF_VERSION >= 50
+#define DEFAULT_ADC_WIDTH ((adc_bitwidth_t)(SOC_ADC_DIGI_MAX_BITWIDTH))
+#else
 #define DEFAULT_ADC_WIDTH ((adc_bits_width_t)((int)ADC_WIDTH_MAX-1))
 #if defined CONFIG_IDF_TARGET_ESP32
 #include <soc/sens_reg.h>
@@ -56,58 +71,95 @@ extern "C" {
 #elif defined CONFIG_IDF_TARGET_ESP32C3
 #include <driver/temp_sensor.h>
 #endif
+#endif
 
 
 struct AdcSignal : public EnvObject
 {
-	AdcSignal(const char *name, adc_unit_t u, adc_channel_t ch)
-	: EnvObject(name)
-	, unit(u)
-	, channel(ch)
-	, raw("raw")
-	, volt("voltage","mV")
-	, phys("physical","","%4.0f")
-	{
-		add(&raw);
-		add(&volt);
-		add(&phys);
-	}
-
+#if IDF_VERSION >= 50
+	AdcSignal(const char *name, adc_oneshot_unit_handle_t h, adc_unit_t u, adc_channel_t ch, adc_atten_t a, unsigned w)
+#else
 	AdcSignal(const char *name, adc_unit_t u, adc_channel_t ch, unsigned w)
+#endif
 	: EnvObject(name)
+#if IDF_VERSION >= 50
+	, hdl(h)
+#endif
 	, unit(u)
 	, channel(ch)
-	, ringbuf(new SlidingWindow<uint16_t>(w))
+	, atten(a)
+	, ringbuf(w > 1 ? new SlidingWindow<uint16_t>(w) : 0)
 	, raw("raw")
 	, volt("voltage","mV")
 	, phys("physical")
 	{
 		add(&raw);
 		add(&volt);
+
+#if IDF_VERSION >= 50
+		cali = 0;
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+		log_dbug(TAG, "calibration scheme is curve fitting");
+		adc_cali_curve_fitting_config_t cali_config = {
+			.unit_id = unit,
+			.atten = atten,
+			.bitwidth = ADC_BITWIDTH_DEFAULT,
+		};
+		if (esp_err_t ret = adc_cali_create_scheme_curve_fitting(&cali_config, &cali))
+			log_warn(TAG,"calibration failure: %s",esp_err_to_name(ret));
+#elif ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+		log_dbug(TAG, "calibration scheme is line fitting");
+		adc_cali_line_fitting_config_t cali_config = {
+			.unit_id = unit,
+			.atten = atten,
+			.bitwidth = ADC_BITWIDTH_DEFAULT,
+#if CONFIG_IDF_TARGET_ESP32
+			.default_vref = ADC_CALI_LINE_FITTING_EFUSE_VAL_DEFAULT_VREF,
+#endif
+		};
+		if (esp_err_t ret = adc_cali_create_scheme_line_fitting(&cali_config, &cali))
+			log_warn(TAG,"calibration failure: %s",esp_err_to_name(ret));
+#endif
+#endif
 	}
 
 	void set(float x)
 	{
-		raw.set(x);
 		float v = 0;
+		raw.set(x);
+#if IDF_VERSION >= 50
+		if (cali) {
+			int voltage;
+			if (esp_err_t e = adc_cali_raw_to_voltage(cali, (int)x, &voltage))
+				log_warn(TAG,"converting ADC%u,%u: %s",unit,channel,esp_err_to_name(e));
+			else
+				v = voltage;
+		}
+		volt.set(v);
+#else
 		switch (atten) {
 		case ADC_ATTEN_DB_0:
-			v = x * 950.0 / 4095.0;
+//			v = x * 950.0 / 4095.0;
+			v = x * 750.0 / 4095.0;
 			break;
 		case ADC_ATTEN_DB_2_5:
-			v = x * 1250.0 / 4095.0;
+//			v = x * 1250.0 / 4095.0;
+			v = x * 1050.0 / 4095.0;
 			break;
 		case ADC_ATTEN_DB_6:
-			v = x * 1750.0 / 4095.0;
+//			v = x * 1750.0 / 4095.0;
+			v = x * 1300.0 / 4095.0;
 			break;
 		case ADC_ATTEN_DB_11:
-			v = x * 2450.0 / 4095.0;
+//			v = x * 2450.0 / 4095.0;
+			v = x * 2500.0 / 4095.0;
 			break;
 		default:
 			break;
 		}
 		volt.set(v);
-		phys.set(x*scale+offset);
+#endif
+		phys.set(v*scale+offset);
 	}
 
 	void addPhysical(float s, float o, const char *dim)
@@ -118,6 +170,10 @@ struct AdcSignal : public EnvObject
 		add(&phys);
 	}
 
+#if IDF_VERSION >= 50
+	adc_oneshot_unit_handle_t hdl;
+	adc_cali_handle_t cali;
+#endif
 	adc_unit_t unit;
 	adc_channel_t channel;
 	adc_atten_t atten;
@@ -130,16 +186,28 @@ struct AdcSignal : public EnvObject
 
 static unsigned NumAdc = 0;
 static AdcSignal **Adcs = 0;
+#if IDF_VERSION >= 50
+typedef adc_bitwidth_t adc_bits_width_t;
+#else
 static adc_bits_width_t U2Width = DEFAULT_ADC_WIDTH;
+#endif
 
+//#if IDF_VERSION < 50 && defined CONFIG_IDF_TARGET_ESP32
 #if defined CONFIG_IDF_TARGET_ESP32
+
 static EnvNumber *Hall = 0;
 
 
 static void hall_sample(void *)
 {
 	if (Hall) {
+#if IDF_VERSION >= 50
+		// TODO not implemented
+		abort();
+		int32_t v = 0;
+#else
 		int32_t v = hall_sensor_read();
+#endif
 		Hall->set(v);
 	}
 }
@@ -149,13 +217,18 @@ void hall_setup()
 {
 	if (!HWConf.has_adc() || HWConf.adc().hall_name().empty())
 		return;
+#if IDF_VERSION >= 50
+//	adc_ll_hall_enable();
+	// TODO implement
+#else
 	if (esp_err_t e = adc1_config_width(DEFAULT_ADC_WIDTH)) {
 		log_error(TAG,"set hall sensor to 12bits: %s",esp_err_to_name(e));
-	} else {
-		Hall = new EnvNumber(HWConf.adc().hall_name().c_str());
-		RTData->add(Hall);
-		action_add("hall!sample",hall_sample,Hall,"take an hall-sensor sample");
+		return;
 	}
+#endif
+	Hall = new EnvNumber(HWConf.adc().hall_name().c_str());
+	RTData->add(Hall);
+	action_add("hall!sample",hall_sample,Hall,"take an hall-sensor sample");
 }
 
 
@@ -182,6 +255,14 @@ static void adc_sample_cb(void *arg)
 	AdcSignal *s = (AdcSignal*)arg;
 	int sample = 0;
 	assert(s);
+#if IDF_VERSION >= 50
+	int raw;
+	if (esp_err_t e = adc_oneshot_read(s->hdl, s->channel, &raw)) {
+		log_warn(TAG,"reading ADC%u,%u: %s",s->unit,s->channel,esp_err_to_name(e));
+		return;
+	}
+	sample = raw;
+#else
 	if (s->unit == 1) {
 		sample = adc1_get_raw((adc1_channel_t)s->channel);
 	} else if (s->unit == 2) {
@@ -190,6 +271,7 @@ static void adc_sample_cb(void *arg)
 			return;
 		}
 	}
+#endif
 	if (s->ringbuf) {
 		s->ringbuf->put(sample);
 		float a = s->ringbuf->avg();
@@ -210,11 +292,94 @@ static unsigned adc_cyclic_cb(void *arg)
 }
 
 
+#ifdef CONFIG_CORETEMP
+
+#if IDF_VERSION >= 50
+static temperature_sensor_handle_t TSensHdl = 0;
+
+// BEGIN import from IDF private header for BUG workaround
+typedef enum { TEMP_SENSOR_FSM_INIT, TEMP_SENSOR_FSM_ENABLE, } temp_sensor_fsm_t;
+struct temperature_sensor_obj_t {
+	const temperature_sensor_attribute_t *tsens_attribute;
+	temp_sensor_fsm_t  fsm;
+	temperature_sensor_clk_src_t clk_src;
+#if SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
+	intr_handle_t temp_sensor_isr_handle;
+	temperature_thres_cb_t threshold_cbs;
+	void *cb_user_arg;
+#endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
+};
+
+static int8_t s_temperature_regval_2_celsius(temperature_sensor_handle_t tsens, uint8_t regval)
+{
+	return TEMPERATURE_SENSOR_LL_ADC_FACTOR * regval - TEMPERATURE_SENSOR_LL_DAC_FACTOR * tsens->tsens_attribute->offset - TEMPERATURE_SENSOR_LL_OFFSET_FACTOR;
+}
+// END of import from IDF private header for BUG workaround
+
+// IDF BUG workaround by NoNullptr from github
+static inline uint32_t temperature_sensor_ll_get_raw_value_bugfix(void)
+{
+	if (!SENS.sar_peri_clk_gate_conf.tsens_clk_en ||
+			!SENS.sar_tctrl2.tsens_xpd_force ||
+			!SENS.sar_tctrl.tsens_power_up_force ||
+			!SENS.sar_tctrl.tsens_power_up ||
+			!SENS.sar_tctrl.tsens_dump_out
+	   ) {
+s:              SENS.sar_peri_clk_gate_conf.tsens_clk_en = true;
+		SENS.sar_tctrl2.tsens_xpd_force = true;
+		SENS.sar_tctrl.tsens_power_up_force = true;
+		SENS.sar_tctrl.tsens_power_up = true;
+		vTaskDelay(pdMS_TO_TICKS(10));
+	}
+	SENS.sar_tctrl.tsens_dump_out = 1;
+	while (!SENS.sar_tctrl.tsens_ready) {
+		if (!SENS.sar_peri_clk_gate_conf.tsens_clk_en ||
+				!SENS.sar_tctrl2.tsens_xpd_force ||
+				!SENS.sar_tctrl.tsens_power_up_force ||
+				!SENS.sar_tctrl.tsens_power_up ||
+				!SENS.sar_tctrl.tsens_dump_out
+		   ) {
+			goto s;
+		}
+	}
+	SENS.sar_tctrl.tsens_dump_out = 0;
+	return SENS.sar_tctrl.tsens_out;
+}
+
+static unsigned temp_cyclic(void *arg)
+{
+	PROFILE_FUNCTION();
+#if 1	// IDF still buggy?
+	uint32_t raw = temperature_sensor_ll_get_raw_value_bugfix();
+	EnvNumber *t = (EnvNumber *) arg;
+	t->set(s_temperature_regval_2_celsius(TSensHdl,raw));
+#else
+	float celsius;
+	if (0 == temperature_sensor_get_celsius(TSensHdl,&celsius)) {
+		EnvNumber *t = (EnvNumber *) arg;
+		t->set(celsius);
+	}
+#endif
+	return 200;
+}
+
+
+void temp_sensor_setup()
+{
+	log_info(TAG,"temperature sensor setup");
+	temperature_sensor_config_t cfg = TEMPERATURE_SENSOR_CONFIG_DEFAULT(10,60);
+	temperature_sensor_install(&cfg,&TSensHdl);
+	EnvNumber *t = RTData->add("core-temperature",NAN,"\u00b0C","%4.1f");
+	temperature_sensor_enable(TSensHdl);
+	cyclic_add_task("coretemp",temp_cyclic,t,0);
+}
+
+
+#elif defined CONFIG_IDF_TARGET_ESP32C3
 // S2 support seems to be broken
 // S3 had trouble, too - what config is causing this issue?
 //#if defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
 //#if defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
-#if defined CONFIG_IDF_TARGET_ESP32C3
 static unsigned temp_cyclic(void *arg)
 {
 	float celsius;
@@ -238,9 +403,8 @@ void temp_sensor_setup()
 		log_warn(TAG,"temperature sensor init failed");
 	}
 }
-#else
-#define temp_sensor_setup()
 #endif
+#endif // CONFIG_CORETEMP
 
 
 static AdcSignal *getAdc(const char *arg)
@@ -301,16 +465,26 @@ static const char *adc_sample(Terminal &t, const char *arg)
 
 void adc_setup()
 {
+#ifdef CONFIG_CORETEMP
 	temp_sensor_setup();
+#endif
 	assert(Adcs == 0);
 	if (!HWConf.has_adc())
 		return;
 	const auto &conf = HWConf.adc();
-#ifndef CONFIG_IDF_TARGET_ESP32C3
+	adc_bitwidth_t w1 = ADC_BITWIDTH_DEFAULT;
+	adc_bitwidth_t w2 = ADC_BITWIDTH_DEFAULT;
+#if IDF_VERSION >= 50
+	if (conf.has_adc1_bits())
+		w1 = (adc_bitwidth_t) conf.adc1_bits();
+	if (conf.has_adc2_bits())
+		w2 = (adc_bitwidth_t) conf.adc2_bits();
+#else
 	if (conf.adc1_bits()) {
 		if (esp_err_t e = adc_set_data_width(ADC_UNIT_1,(adc_bits_width_t)conf.adc1_bits()))
 			log_warn(TAG,"set adc1 data width %dbits: %s",conf.adc1_bits()+9,esp_err_to_name(e));
 	}
+#ifndef CONFIG_IDF_TARGET_ESP32C3
 	if (conf.has_adc2_bits()) {
 		if (esp_err_t e = adc_set_data_width(ADC_UNIT_2,(adc_bits_width_t)conf.adc2_bits()))
 			log_warn(TAG,"set adc2 data width %dbits: %s",conf.adc2_bits()+9,esp_err_to_name(e));
@@ -319,20 +493,27 @@ void adc_setup()
 	} else {
 		U2Width = DEFAULT_ADC_WIDTH;
 	}
+#endif
 #endif
 	unsigned num = 0;
 	NumAdc = conf.channels_size();
 	log_info(TAG,"%u channels",NumAdc);
 	Adcs = (AdcSignal **) malloc(sizeof(AdcSignal*)*NumAdc);
 	bzero(Adcs,sizeof(AdcSignal*)*NumAdc);
+	adc_oneshot_unit_handle_t hdl1 = 0, hdl2 = 0;
 	for (const AdcChannel &c : conf.channels()) {
 		unsigned u = c.unit();
 		if ((u < 1) || (u > 2)) {
 			log_warn(TAG,"invalid unit %u",u);
 			continue;
 		}
+		adc_unit_t unit = u == 1 ? ADC_UNIT_1 : ADC_UNIT_2;
 		int ch = c.ch();
+#if IDF_VERSION >= 50
+		if (ch >= SOC_ADC_CHANNEL_NUM(unit)) {
+#else
 		if (((u == 1) && (ch >= ADC1_CHANNEL_MAX)) || ((u == 2) && (ch >= ADC2_CHANNEL_MAX))) {
+#endif
 			log_warn(TAG,"invalid channel %u",ch);
 			continue;
 		}
@@ -344,7 +525,41 @@ void adc_setup()
 			log_dbug(TAG,"created name %s",name);
 		}
 		adc_atten_t atten = (adc_atten_t)c.atten();
-		log_dbug(TAG,"init %s on ADC%u.%u, atten %u",n,u,ch,atten);
+		int gpio = -1;
+		adc_oneshot_channel_to_io(unit,(adc_channel_t)ch,&gpio);
+		log_info(TAG,"init %s on ADC%u.%u at GPIO%u, atten %u",n,u,ch,gpio,atten);
+#if IDF_VERSION >= 50
+		adc_oneshot_unit_handle_t hdl = 0;
+		adc_oneshot_unit_init_cfg_t ucfg;
+		ucfg.unit_id = unit;
+//		ucfg.clk_src = ADC_DEFAULT_CLOCK;
+		ucfg.clk_src = (adc_oneshot_clk_src_t)0;
+		ucfg.ulp_mode = ADC_ULP_MODE_DISABLE;
+		if (u == 1) {
+			if (hdl1 == 0) {
+				if (esp_err_t e = adc_oneshot_new_unit(&ucfg,&hdl1)) {
+					log_warn(TAG,"ADC unit %d: %s",u,esp_err_to_name(e));
+					continue;
+				}
+			}
+			hdl = hdl1;
+		} else if (u == 2) {
+			if (hdl2 == 0) {
+				if (esp_err_t e = adc_oneshot_new_unit(&ucfg,&hdl2)) {
+					log_warn(TAG,"ADC unit %d: %s",u,esp_err_to_name(e));
+					continue;
+				}
+			}
+			hdl = hdl2;
+		} else {
+			abort();
+		}
+		adc_oneshot_chan_cfg_t cc;
+		cc.atten = atten;
+		cc.bitwidth = u == 1 ? w1 : w2;
+		adc_oneshot_config_channel(hdl,(adc_channel_t)ch,&cc);
+		Adcs[num] = new AdcSignal(n,hdl,(adc_unit_t)u,(adc_channel_t)ch,atten,c.window());
+#else
 		if (u == 1) {
 			if (esp_err_t e = adc1_config_channel_atten((adc1_channel_t)ch,atten)) {
 				log_warn(TAG,"set ADC1.%u atten: %s",ch,esp_err_to_name(e));
@@ -360,11 +575,8 @@ void adc_setup()
 				continue;
 			}
 		}
-		if (auto w = c.window()) {
-			Adcs[num] = new AdcSignal(n,(adc_unit_t)u,(adc_channel_t)ch,w);
-		} else {
-			Adcs[num] = new AdcSignal(n,(adc_unit_t)u,(adc_channel_t)ch);
-		}
+		Adcs[num] = new AdcSignal(n,(adc_unit_t)u,(adc_channel_t)ch,c.window());
+#endif
 		Adcs[num]->atten = atten;
 		if (c.has_scale() || c.has_offset() || c.has_dim()) {
 			Adcs[num]->addPhysical(c.scale(),c.offset(),c.dim().c_str());
@@ -377,24 +589,23 @@ void adc_setup()
 			action_add(concat(n,"!sample"),adc_sample_cb,Adcs[num],"take an ADC sample");
 		}
 		++num;
-		log_info(TAG,"%s on ADC%u.%u",n,u,ch);
 	}
 	NumAdc = num;
+#if IDF_VERSION < 50
 	if (num)
 		adc_power_acquire();
 #ifndef CONFIG_IDF_TARGET_ESP32C3
 	if (esp_err_t e = adc_set_data_inv(ADC_UNIT_1,true))
 		log_warn(TAG,"set non-inverting mode on ADC1: %s",esp_err_to_name(e));
 #endif
+#endif
 }
 
 
 const char *adc(Terminal &term, int argc, const char *args[])
 {
-	if (argc == 1) {
-		term.printf("adc is %sinitialized\n",Adcs ? "" : "not ");
-		return 0;
-	}
+	if (argc == 1)
+		return adc_print(term,0);;
 #if 0 // for debugging purposes
 	term.printf("read ctrl 0x%lx\n",REG_READ(SENS_SAR_READ_CTRL_REG));
 	term.printf("sar start 0x%lx\n",REG_READ(SENS_SAR_START_FORCE_REG));
diff --git a/main/dimmer.cpp b/main/dimmer.cpp
index 66125ab..38067bc 100644
--- a/main/dimmer.cpp
+++ b/main/dimmer.cpp
@@ -38,6 +38,9 @@
 #elif defined CONFIG_IDF_TARGET_ESP32C3
 #include <driver/ledc.h>
 #define SPEED_MODE LEDC_LOW_SPEED_MODE
+#elif defined CONFIG_IDF_TARGET_ESP32C6
+#include <driver/ledc.h>
+#define SPEED_MODE LEDC_LOW_SPEED_MODE
 #else
 #error missing implementation
 #endif
@@ -242,7 +245,7 @@ unsigned dimmer_fade(void *)
 			log_warn(TAG,"set duty %d",e);
 		if (esp_err_t e = pwm_start())
 			log_warn(TAG,"pwm start %d",e);
-#elif defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined ESP32
 		ledc_set_duty(SPEED_MODE,d->channel,v);
 		ledc_update_duty(SPEED_MODE,d->channel);
 #else
@@ -458,7 +461,7 @@ void dimmer_setup()
 		duties[nch] = (conf.config() & 1) ? DIM_MAX : 0;
 		dim->duty = duties[nch];
 		++nch;
-#elif defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined ESP32
 		dim->channel = (ledc_channel_t) conf.pwm_ch();
 		gpio_set_direction(dim->gpio,GPIO_MODE_OUTPUT);
 		ledc_channel_config_t ch;
diff --git a/main/displays.cpp b/main/displays.cpp
index 2524f9e..cc6d517 100644
--- a/main/displays.cpp
+++ b/main/displays.cpp
@@ -36,6 +36,7 @@
 
 void display_setup()
 {
+#ifdef CONFIG_MAX7219
 	if (HWConf.has_max7219()) {
 		// 5V level adjustment necessary
 		// ESP8266 is not capable of driving directly
@@ -45,6 +46,7 @@ void display_setup()
 			MAX7219Drv::create((xio_t)c.clk(),(xio_t)c.dout(),(xio_t)c.cs(),c.odrain());
 		}
 	}
+#endif
 	if (HWConf.has_display()) {
 		const DisplayConfig &c = HWConf.display();
 		if (!c.has_type() || !c.has_maxx()) {
diff --git a/main/fs.cpp b/main/fs.cpp
index be5ad19..9d7370d 100644
--- a/main/fs.cpp
+++ b/main/fs.cpp
@@ -144,7 +144,7 @@ void rootfs_init()
 	vfs.opendir = rootfs_vfs_opendir;
 	vfs.readdir = rootfs_vfs_readdir;
 	vfs.readdir_r = rootfs_vfs_readdir_r;
-	if (esp_err_t e = esp_vfs_register("/",&vfs,0))
+	if (esp_err_t e = esp_vfs_register("",&vfs,0))
 		log_warn(TAG,"VFS register rootfs: %s",esp_err_to_name(e));
 	else
 		log_info(TAG,"rootfs mounted");
@@ -211,7 +211,11 @@ static void fatfs_init()
 	fatconf.max_files = 4;
 	fatconf.allocation_unit_size = CONFIG_WL_SECTOR_SIZE;
 	SpiFatFs = WL_INVALID_HANDLE;
+#if IDF_VERSION >= 50
+	if (esp_err_t r = esp_vfs_fat_spiflash_mount_rw_wl(MOUNT_POINT, DATA_PARTITION, &fatconf, &SpiFatFs)) {
+#else
 	if (esp_err_t r = esp_vfs_fat_spiflash_mount(MOUNT_POINT, DATA_PARTITION, &fatconf, &SpiFatFs)) {
+#endif
 		log_error(TAG,"mount %s on %s with fatfs: %s", DATA_PARTITION, MOUNT_POINT, esp_err_to_name(r));
 		SpiFatFs = WL_INVALID_HANDLE;
 	} else  {
@@ -223,15 +227,24 @@ static void fatfs_init()
 
 static int shell_format_fatfs(Terminal &term, const char *arg)
 {
-	if (SpiFatFs != WL_INVALID_HANDLE)
+	if (SpiFatFs != WL_INVALID_HANDLE) {
+#if IDF_VERSION >= 50
+		esp_vfs_fat_spiflash_unmount_rw_wl(MOUNT_POINT, SpiFatFs);
+#else
 		esp_vfs_fat_spiflash_unmount(MOUNT_POINT, SpiFatFs);
+#endif
+	}
 	esp_vfs_fat_mount_config_t fatconf;
 	bzero(&fatconf,sizeof(fatconf));
 	fatconf.format_if_mount_failed = true;
 	fatconf.max_files = 4;
 	fatconf.allocation_unit_size = CONFIG_WL_SECTOR_SIZE;
 	SpiFatFs = WL_INVALID_HANDLE;
+#if IDF_VERSION >= 50
+	if (esp_err_t r = esp_vfs_fat_spiflash_mount_rw_wl(MOUNT_POINT, arg, &fatconf, &SpiFatFs)) {
+#else
 	if (esp_err_t r = esp_vfs_fat_spiflash_mount(MOUNT_POINT, arg, &fatconf, &SpiFatFs)) {
+#endif
 		term.printf("unable to mount flash with fatfs: %s\n",esp_err_to_name(r));
 		SpiFatFs = WL_INVALID_HANDLE;
 	} else {
@@ -270,9 +283,11 @@ static void init_hwconf()
 
 static void romfs_init()
 {
+#ifndef CONFIG_ESPTOOLPY_FLASHSIZE_1MB
 	if (const char *r = romfs_setup()) {
 		rootfs_add(r);
 	}
+#endif
 	if (HWConf.calcSize() == 0)
 		init_hwconf();
 }
diff --git a/main/fs.h b/main/fs.h
index e88db68..8c885b3 100644
--- a/main/fs.h
+++ b/main/fs.h
@@ -29,4 +29,6 @@ extern "C"
 #endif
 void fs_init();
 
+void rootfs_add(const char *);
+
 #endif
diff --git a/main/globals.cpp b/main/globals.cpp
index b7eeae7..fb00124 100644
--- a/main/globals.cpp
+++ b/main/globals.cpp
@@ -243,7 +243,7 @@ static int daylight_saving_cet(struct tm *tm)
 }
 
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP8266
+#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP8266
 int get_time_of_day(uint8_t *h, uint8_t *m, uint8_t *s, uint8_t *wd, uint8_t *mday, uint8_t *month, unsigned *year)
 {
 	time_t now;
diff --git a/main/gpios.cpp b/main/gpios.cpp
index 5f96c72..367ee56 100644
--- a/main/gpios.cpp
+++ b/main/gpios.cpp
@@ -35,6 +35,8 @@
 #include <driver/gpio.h>
 #ifdef CONFIG_IDF_TARGET_ESP8266
 #include <esp8266/gpio_struct.h>
+#else
+#include <hal/gpio_ll.h>
 #endif
 
 #ifdef CONFIG_LUA
diff --git a/main/httpd.cpp b/main/httpd.cpp
index 10888c6..0f369da 100644
--- a/main/httpd.cpp
+++ b/main/httpd.cpp
@@ -48,6 +48,11 @@
 
 #ifdef ESP32
 #include <esp_core_dump.h>
+#if IDF_VERSION < 50
+#include <esp_spi_flash.h>
+#else
+#include <spi_flash_mmap.h>
+#endif
 #endif
 #include <esp_ota_ops.h>
 
@@ -423,25 +428,37 @@ static void updateFirmware(HttpRequest *r)
 		free(tmp);
 		return;
 	} else {
-		auto p = esp_partition_find_first(ESP_PARTITION_TYPE_DATA,ESP_PARTITION_SUBTYPE_ANY,part);
-		addr = p->address;
+		updatep = esp_partition_find_first(ESP_PARTITION_TYPE_DATA,ESP_PARTITION_SUBTYPE_ANY,part);
+		addr = updatep->address;
 		const char *err = 0;
-		if (p == 0) {
+		if (updatep == 0) {
 			sprintf(st,"no ROMFS partition '%s'",part);
 			err = st;
-		} else if (s > p->size) {
+		} else if (s > updatep->size) {
 			// ROMFS/DATA partition
 			err = "image too big";
-		} else if (esp_err_t e = spi_flash_erase_range(addr,p->size)) {
-			sprintf(st,"erase failed %s",esp_err_to_name(e));
+#if IDF_VERSION >= 50
+		} else if (esp_err_t e = esp_partition_erase_range(updatep,0,updatep->size)) {
+			sprintf(st,"erase partition: %s",esp_err_to_name(e));
+			err = st;
+		} else if (s0 <= 0) {
+		} else if (esp_err_t e = esp_partition_write_raw(updatep,0,r->getContent(),s0)) {
+			sprintf(st,"write partition: %s",esp_err_to_name(e));
+			err = st;
+			addr = s0;
+			s -= s0;
+#else
+		} else if (esp_err_t e = spi_flash_erase_range(addr,updatep->size)) {
+			sprintf(st,"erase failed: %s",esp_err_to_name(e));
 			err = st;
 		} else if (s0 > 0) {
-			if (esp_err_t e = spi_flash_write(p->address,r->getContent(),s0)) {
+			if (esp_err_t e = spi_flash_write(addr,r->getContent(),s0)) {
 				sprintf(st,"SPI write: %s",esp_err_to_name(e));
 				err = st;
 			}
 			addr += s0;
 			s -= s0;
+#endif
 		}
 		if (err) {
 			UpdateState->set(err);
@@ -455,7 +472,7 @@ static void updateFirmware(HttpRequest *r)
 		return;
 	}
 	while (s > 0) {
-		sprintf(st,"updating at 0x%x, %d to go",addr,s);
+		sprintf(st,"updating at 0x%x, %d to go",(unsigned)addr,s);
 		UpdateState->set(st);
 		log_dbug(TAG,st);
 		int n = c->read(buf,s > FLASHBUFSIZE ? FLASHBUFSIZE : s);
@@ -469,10 +486,16 @@ static void updateFirmware(HttpRequest *r)
 			return;
 		}
 		esp_err_t e;
-		if (app)
+		if (app) {
 			e = esp_ota_write(ota,buf,n);
-		else
+		} else {
+#if IDF_VERSION >= 50
+			e = esp_partition_write_raw(updatep,addr,buf,n);
+
+#else
 			e = spi_flash_write(addr,buf,n);
+#endif
+		}
 		if (e) {
 			snprintf(st,sizeof(st),"write error: %d",e);
 			UpdateState->set(st);
diff --git a/main/i2c.cpp b/main/i2c.cpp
index ef75b2c..38dd379 100644
--- a/main/i2c.cpp
+++ b/main/i2c.cpp
@@ -45,7 +45,7 @@
 
 
 #ifdef CONFIG_I2C_XDEV 
-static inline void i2c_scan_device(uint8_t bus, uint8_t addr, i2cdrv_t drv)
+static inline void i2c_scan_device(uint8_t bus, uint8_t addr, i2cdrv_t drv, int8_t intr)
 {
 	switch (drv) {
 #ifdef CONFIG_PCF8574
@@ -105,7 +105,10 @@ static inline void i2c_scan_device(uint8_t bus, uint8_t addr, i2cdrv_t drv)
 #endif
 #ifdef CONFIG_SSD1306
 	case i2cdrv_ssd1306:
-		SSD1306::create(bus,addr);
+		if (addr)
+			SSD1306::create(bus,addr);
+		else
+			ssd1306_scan(bus);
 		break;
 #endif
 	default:
@@ -130,7 +133,15 @@ void i2c_setup(void)
 				log_warn(TAG,"error %d",r);
 #ifdef CONFIG_I2C_XDEV 
 			for (i2cdev_t d : c.devices()) {
-				i2c_scan_device(bus,d & 0xff,(i2cdrv_t)((d >> 8) & 0xff));
+				uint8_t addr = d & 0xff;
+				uint8_t intr = (d >> 16) & 0x3f;
+				if (i2cdrv_t drv = (i2cdrv_t)((d >> 8) & 0xff))
+					i2c_scan_device(bus,addr,drv,intr-1);
+				if (intr && addr) {
+					I2CDevice *dev = I2CDevice::getByAddr(addr);
+					if (dev)
+						dev->addIntr(intr-1);
+				}
 			}
 #endif
 		}
diff --git a/main/leds.cpp b/main/leds.cpp
index 93618ca..630d082 100644
--- a/main/leds.cpp
+++ b/main/leds.cpp
@@ -265,16 +265,25 @@ static void update_mode(LedMode *ctx, uint32_t now)
 			l = ledmode_medium;
 		else
 			l = ctx->mode;
-	} else if (StationMode == station_connected)
+	} else if (StationMode == station_connected) {
+#ifdef CONFIG_AT_ACTIONS
 		l = alarms_enabled() ? ledmode_off : ledmode_pulse_seldom;
-	else if (StationMode == station_starting)
+#else
+		l = ledmode_off;
+#endif
+	} else if (StationMode == station_starting) {
 		l = ledmode_medium;
-	else if (StationMode == station_disconnected)
+	} else if (StationMode == station_disconnected) {
 		l = ledmode_slow;
-	else if (StationMode == station_stopped)
+	} else if (StationMode == station_stopped) {
+#ifdef CONFIG_AT_ACTIONS
 		l = alarms_enabled() ? ledmode_on : ledmode_neg_seldom;
-	else
+#else
+		l = ledmode_on;
+#endif
+	} else {
 		abort();
+	}
 	if (l != ctx->mode) {
 		log_dbug(TAG,"switching to %s",ModeNames[l]);
 		ctx->mode = l;
diff --git a/main/ledstrip.cpp b/main/ledstrip.cpp
index 7b447d5..44fa508 100644
--- a/main/ledstrip.cpp
+++ b/main/ledstrip.cpp
@@ -357,7 +357,7 @@ void rgbleds_setup()
 		unsigned nleds = c.nleds();
 		WS2812BDrv *drv = new WS2812BDrv(name);
 #if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
-		if (drv->init((gpio_num_t)c.gpio(),nleds,(rmt_channel_t)c.ch()))
+		if (drv->init((gpio_num_t)c.gpio(),nleds,c.ch()))
 			continue;
 #else
 		if (drv->init((gpio_num_t)c.gpio(),nleds))
diff --git a/main/ota.cpp b/main/ota.cpp
index ddd5574..82896dd 100644
--- a/main/ota.cpp
+++ b/main/ota.cpp
@@ -620,7 +620,13 @@ static const char *to_part(Terminal &t, void *arg, char *buf, size_t s)
 	//t.printf("to_part %u@%x\n",s,*addr);
 	if (s > p->size)
 		return "End of partition.";
+#if IDF_VERSION >= 50
+	// TODO FIXME moving partiton address in to_part might not be a
+	// good idea
+	esp_err_t e = esp_partition_write_raw(p,0,buf,s);
+#else
 	esp_err_t e = spi_flash_write(p->address,buf,s);
+#endif
 	if (e) {
 		t.printf("flash error %s\n",esp_err_to_name(e));
 		return "";
@@ -668,10 +674,13 @@ const char *update_part(Terminal &t, char *source, const char *dest)
 	uint32_t s = p->size;
 	t.printf("erasing %d@%x\n",p->size,p->address);
 	t.sync();
-	if (esp_err_t e = spi_flash_erase_range(p->address,p->size)) {
-		t.println("error erasing");
+#if IDF_VERSION >= 50
+	if (esp_err_t e = esp_partition_erase_range(p,0,p->size))
 		return esp_err_to_name(e);
-	}
+#else
+	if (esp_err_t e = spi_flash_erase_range(p->address,p->size))
+		return esp_err_to_name(e);
+#endif
 	const char *r;
 	switch (uri.prot) {
 	case prot_http:
diff --git a/main/romfs.cpp b/main/romfs.cpp
index ffcdba5..eb29c2d 100644
--- a/main/romfs.cpp
+++ b/main/romfs.cpp
@@ -32,8 +32,12 @@
 #include "log.h"
 #include <esp_vfs.h>
 #include <esp_partition.h>
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#ifdef ESP32
+#if IDF_VERSION >= 50
+#include <spi_flash_mmap.h>
+#else
 #include <esp_spi_flash.h>
+#endif
 #else
 #include <spi_flash.h>
 #endif
@@ -65,7 +69,7 @@ typedef struct RomEntry32
 #elif defined CONFIG_IDF_TARGET_ESP8266
 #define RomEntry RomEntry16
 #define ROMFS_MAGIC "ROMFS16"
-#elif defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined ESP32
 #define RomEntry RomEntry32
 #define ROMFS_MAGIC "ROMFS32"
 #else
@@ -130,7 +134,7 @@ const char *romfs_name(int i)
 }
 
 
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3
+#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3
 void *romfs_mmap(int i)
 {
 	if ((i < 0) || (i >= NumEntries))
@@ -171,7 +175,7 @@ int romfs_read_at(int i, char *buf, size_t n, size_t o)
 	assert(((uint32_t)buf & 3) == 0);
 	if (o+n > s)
 		n = s-o;
-#if defined CONFIG_IDF_TARGET_ESP32 ||  defined CONFIG_IDF_TARGET_ESP32S2
+#ifdef ESP32
 	memcpy(buf,(void*)(RomfsBaseAddr+off+o),n);
 #else
 	if (auto e = spi_flash_read(RomfsBaseAddr+off+o,buf,n)) {
@@ -408,7 +412,11 @@ const char *romfs_setup()
 	while (pi != 0) {
 		p = esp_partition_get(pi);
 		uint8_t magic[8];
+#if IDF_VERSION >= 50
+		esp_partition_read_raw(p,0,(char *)magic,sizeof(magic));
+#else
 		spi_flash_read(p->address,magic,sizeof(magic));
+#endif
 		log_hex(TAG,magic,sizeof(magic),"partition %s",p->label);
 		if (0 == memcmp(magic,ROMFS_MAGIC,sizeof(magic))) {
 			log_info(TAG,"%s has ROMFS",p->label);
@@ -445,7 +453,7 @@ const char *romfs_setup()
 
 	RomfsBaseAddr = p->address;
 	RomfsSpace = p->size;
-#if defined CONFIG_IDF_TARGET_ESP32 ||  defined CONFIG_IDF_TARGET_ESP32S2
+#ifdef ESP32
 	spi_flash_mmap_handle_t handle;
 	if (esp_err_t e = spi_flash_mmap(p->address,p->size,SPI_FLASH_MMAP_DATA,(const void**)&RomfsBaseAddr,&handle)) {
 		log_error(TAG,"mmap failed: %s",esp_err_to_name(e));
diff --git a/main/screen.cpp b/main/screen.cpp
index b4be8f7..1209e7e 100644
--- a/main/screen.cpp
+++ b/main/screen.cpp
@@ -24,7 +24,7 @@
 #include "cyclic.h"
 #include "display.h"
 #include "env.h"
-#include "fonts_ssd1306.h"
+#include "fonts.h"
 #include "globals.h"
 #include "hwcfg.h"
 #include "log.h"
@@ -640,6 +640,67 @@ static int luax_fb_drawrect(lua_State *L)
 }
 
 
+static int luax_fb_drawline(lua_State *L)
+{
+	if (MatrixDisplay *md = Ctx->disp->toMatrixDisplay()) {
+		int x = luaL_checkinteger(L,1);
+		int y = luaL_checkinteger(L,2);
+		int w = luaL_checkinteger(L,3);
+		int h = luaL_checkinteger(L,4);
+		int32_t fgc = -1;
+		if (lua_isinteger(L,5))
+			fgc = lua_tointeger(L,5);
+		else if (lua_isstring(L,5))
+			fgc = md->getColor(color_get(lua_tostring(L,5)));
+		md->drawLine(x,y,w,h,fgc);
+		return 0;
+	}
+	lua_pushliteral(L,"fb_drawrect: no display.");
+	lua_error(L);
+	return 0;
+}
+
+
+static int luax_fb_drawhline(lua_State *L)
+{
+	if (MatrixDisplay *md = Ctx->disp->toMatrixDisplay()) {
+		int x = luaL_checkinteger(L,1);
+		int y = luaL_checkinteger(L,2);
+		int l = luaL_checkinteger(L,3);
+		int32_t fgc = -1;
+		if (lua_isinteger(L,4))
+			fgc = lua_tointeger(L,4);
+		else if (lua_isstring(L,4))
+			fgc = md->getColor(color_get(lua_tostring(L,4)));
+		md->drawHLine(x,y,l,fgc);
+		return 0;
+	}
+	lua_pushliteral(L,"fb_drawrect: no display.");
+	lua_error(L);
+	return 0;
+}
+
+
+static int luax_fb_drawvline(lua_State *L)
+{
+	if (MatrixDisplay *md = Ctx->disp->toMatrixDisplay()) {
+		int x = luaL_checkinteger(L,1);
+		int y = luaL_checkinteger(L,2);
+		int l = luaL_checkinteger(L,3);
+		int32_t fgc = -1;
+		if (lua_isinteger(L,4))
+			fgc = lua_tointeger(L,4);
+		else if (lua_isstring(L,4))
+			fgc = md->getColor(color_get(lua_tostring(L,4)));
+		md->drawVLine(x,y,l,fgc);
+		return 0;
+	}
+	lua_pushliteral(L,"fb_drawrect: no display.");
+	lua_error(L);
+	return 0;
+}
+
+
 static int luax_fb_drawtext(lua_State *L)
 {
 	if (MatrixDisplay *md = Ctx->disp->toMatrixDisplay()) {
@@ -690,6 +751,9 @@ static int luax_fb_fillrect(lua_State *L)
 static const LuaFn FbFunctions[] = {
 	{ "fb_drawrect", luax_fb_drawrect, "draw rectangle" },
 	{ "fb_drawtext", luax_fb_drawtext, "draw text string" },
+	{ "fb_drawline", luax_fb_drawline, "draw line" },
+	{ "fb_drawhline", luax_fb_drawhline, "draw horizontal line" },
+	{ "fb_drawvline", luax_fb_drawvline, "draw vertical line" },
 	{ "fb_fillrect", luax_fb_fillrect, "fill rectangle" },
 	{ "fb_setbgcol", luax_fb_setbgcol, "set background color" },
 	{ "fb_setfgcol", luax_fb_setfgcol, "set foreground color" },
diff --git a/main/settings.cpp b/main/settings.cpp
index 1db3c48..606c1e7 100644
--- a/main/settings.cpp
+++ b/main/settings.cpp
@@ -37,8 +37,11 @@
 
 #include <esp_ota_ops.h>
 #include <esp_system.h>
+#include <esp_netif.h>
 #include <esp_wifi.h>
-#include <sstream>
+#if IDF_VERSION >= 50
+#include <rom/ets_sys.h>
+#endif
 
 #include <lwip/err.h>
 #include <lwip/dns.h>
@@ -57,11 +60,9 @@ void esp_yield(void);
 #endif
 
 
-//#include <nvs.h>
-//#include <nvs_flash.h>
-#include <esp_netif.h>
 #include <stdlib.h>
 #include <string.h>
+#include <sstream>
 
 #include "settings.h"
 #include "dht.h"
@@ -474,9 +475,16 @@ static void set_cfg_err(uint8_t v)
 static void initNodename()
 {
 	uint8_t mac[6];
-	esp_err_t e = esp_wifi_get_mac(WIFI_IF_STA,mac);
+	esp_err_t e;
+#if IDF_VERSION >= 50
+	e = ESP_ERR_NOT_FOUND;
+	if (esp_netif_t *nif = esp_netif_next(0))
+		e = esp_netif_get_mac(nif,mac);
+#else
+	e = esp_wifi_get_mac(WIFI_IF_STA,mac);
 	if (ESP_OK != e)
 		e = esp_wifi_get_mac(WIFI_IF_AP,mac);
+#endif
 	if (ESP_OK != e) {
 		log_warn(TAG,"no MAC address: %s",esp_err_to_name(e));
 		uint32_t r = esp_random();
@@ -514,7 +522,9 @@ void cfg_clear_nodecfg()
 void cfg_factory_reset(void *)
 {
 	nvm_erase_all();
+#if IDF_VERSION < 50
 	esp_wifi_restore();
+#endif
 	esp_restart();
 }
 
diff --git a/main/shell.cpp b/main/shell.cpp
index a42d8d6..839ab54 100644
--- a/main/shell.cpp
+++ b/main/shell.cpp
@@ -56,8 +56,14 @@
 #include <esp_system.h>
 #include <esp_ota_ops.h>
 #include <esp_partition.h>
-#include <esp_wifi.h>
 #include <esp_netif.h>
+#include <esp_wifi.h>
+
+#if IDF_VERSION >= 50
+#include <spi_flash_mmap.h>
+#include <esp_chip_info.h>
+#include <rom/ets_sys.h>
+#endif
 
 #define TAG MODULE_SHELL
 
@@ -74,15 +80,6 @@
 #ifdef CONFIG_FATFS
 #include <ff.h>
 #endif
-
-#ifndef CONFIG_ROMFS
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
-#include <esp_spi_flash.h>
-#else
-#include <spi_flash.h>
-#endif
-#endif
-
 #if defined CONFIG_FATFS || defined CONFIG_SPIFFS
 #define HAVE_FS
 #endif
@@ -111,7 +108,7 @@ extern "C" {
 #if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
 #if IDF_VERSION >= 40
 extern "C" {
-#include <esp32/clk.h>
+//#include <esp32/clk.h>
 }
 #include <soc/rtc.h>
 #else
@@ -799,14 +796,20 @@ static const char *shell_xxd(Terminal &term, int argc, const char *args[])
 
 static const char *shell_reboot(Terminal &term, int argc, const char *args[])
 {
+#if CONFIG_MQTT
 	mqtt_stop();
+#endif
+#if CONFIG_SYSLOG
 	syslog_stop();
+#endif
 	term.println("rebooting...");
 	term.sync();
 	term.disconnect();
 	vTaskDelay(400);
+#if IDF_VERSION < 50
 #ifndef CONFIG_IDF_TARGET_ESP8266
 	esp_unregister_shutdown_handler((shutdown_handler_t)esp_wifi_stop);
+#endif
 #endif
 	esp_restart();
 	return 0;
@@ -854,9 +857,15 @@ static const char *part(Terminal &term, int argc, const char *args[])
 			return "Invalid argument #1.";
 		if (esp_partition_iterator_t i = esp_partition_find(ESP_PARTITION_TYPE_DATA,ESP_PARTITION_SUBTYPE_ANY,args[2])) {
 			if (const esp_partition_t *p = esp_partition_get(i)) {
+#if IDF_VERSION >= 50
+				if (esp_err_t e = esp_partition_erase_range(p,0,p->size)) {
+					return esp_err_to_name(e);
+				}
+#else
 				if (esp_err_t e = spi_flash_erase_range(p->address,p->size)) {
 					return esp_err_to_name(e);
 				}
+#endif
 				return 0;
 			}
 		}
@@ -924,11 +933,26 @@ const char *mac(Terminal &term, int argc, const char *args[])
 		return "Invalid argument #1.";
 	} else if (argc == 2) {
 		if (args[1][1] == 'l') {
+#if IDF_VERSION >= 50
+
+			esp_netif_t *nif = esp_netif_next(0);
+			while (nif) {
+				char name[8];
+				name[0] = 0;
+				if (esp_netif_get_mac(nif,mac)) {
+				} else if (esp_netif_get_netif_impl_name(nif,name)) {
+				} else {
+					print_mac(term,name,mac);
+				}
+				nif = esp_netif_next(nif);
+			}
+#else
 			if (ESP_OK == esp_wifi_get_mac(WIFI_IF_AP,mac))
 				print_mac(term,"softap",mac);
 			if (ESP_OK == esp_wifi_get_mac(WIFI_IF_STA,mac))
 				print_mac(term,"station",mac);
 			return 0;
+#endif
 		}
 	}
 	if (0 == term.getPrivLevel())
@@ -2079,7 +2103,11 @@ static const char *cpu(Terminal &term, int argc, const char *args[])
 		return "Invalid number of arguments.";
 	}
 	if (argc == 1) {
-		int f = esp_clk_cpu_freq();
+#if IDF_VERSION >= 50
+		uint32_t mhz = ets_get_cpu_frequency();
+#else
+//		uint32_t f = ets_get_cpu_freq();
+		int32_t f = esp_clk_cpu_freq();
 		unsigned mhz;
 		switch (f) {
 #ifdef RTC_CPU_FREQ_80M
@@ -2110,6 +2138,7 @@ static const char *cpu(Terminal &term, int argc, const char *args[])
 		default:
 			mhz = f/1000000;
 		}
+#endif
 		esp_chip_info_t ci;
 		esp_chip_info(&ci);
 		term.printf("ESP%u (rev %d) with %d core%s @ %uMHz"
@@ -2363,6 +2392,40 @@ static int flashtest(Terminal &term, int argc, const char *args[])
 */
 
 
+#if IDF_VERSION >= 50
+static void print_ipinfo(Terminal &t, esp_netif_t *itf, esp_netif_ip_info_t *i)
+{
+	char name[8], ipstr[32],gwstr[32];
+	uint8_t mac[6];
+	uint8_t m = 0;
+	uint32_t nm = ntohl(i->netmask.addr);
+	while (nm & (1<<(31-m)))
+		++m;
+	if (esp_netif_get_netif_impl_name(itf,name))
+		return;
+	t.printf("if%d/%s (%s):\n",esp_netif_get_netif_impl_index(itf),name,esp_netif_get_desc(itf));
+	if (ESP_OK == esp_netif_get_mac(itf,mac))
+		t.printf("\tmac       : %02x:%02x:%02x:%02x:%02x:%02x\n",
+			mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]);
+	esp_netif_ip_info_t ipconfig;
+	if (ESP_OK == esp_netif_get_ip_info(itf,&ipconfig)) {
+		ip4addr_ntoa_r((ip4_addr_t *)&i->ip.addr,ipstr,sizeof(ipstr));
+		ip4addr_ntoa_r((ip4_addr_t *)&i->gw.addr,gwstr,sizeof(gwstr));
+		t.printf("\tipv4      : %s/%d, gw: %s, %s\n",ipstr,m,gwstr,esp_netif_is_netif_up(itf) ? "up":"down");
+	}
+#if defined CONFIG_LWIP_IPV6
+	esp_ip6_addr_t ip6;
+	if (ESP_OK == esp_netif_get_ip6_linklocal(itf,&ip6)) {
+		ip6addr_ntoa_r((ip6_addr_t*)&ip6,ipstr,sizeof(ipstr));
+		t.printf("\tlink-local: %s\n",ipstr);
+	}
+	if (ESP_OK == esp_netif_get_ip6_global(itf,&ip6)) {
+		ip6addr_ntoa_r((ip6_addr_t*)&ip6,ipstr,sizeof(ipstr));
+		t.printf("\tglobal    : %s\n",ipstr);
+	}
+#endif
+}
+#else
 static void print_ipinfo(Terminal &t, const char *itf, tcpip_adapter_ip_info_t *i, bool up)
 {
 	uint8_t m = 0;
@@ -2372,8 +2435,9 @@ static void print_ipinfo(Terminal &t, const char *itf, tcpip_adapter_ip_info_t *
 	char ipstr[32],gwstr[32];
 	ip4addr_ntoa_r((ip4_addr_t *)&i->ip.addr,ipstr,sizeof(ipstr));
 	ip4addr_ntoa_r((ip4_addr_t *)&i->gw.addr,gwstr,sizeof(gwstr));
-	t.printf("%s%s gw=%s %s\n",itf,ipstr,gwstr,up ? "up":"down");
+	t.printf("%s%s/%u gw=%s %s\n",itf,ipstr,m,gwstr,up ? "up":"down");
 }
+#endif
 
 
 static const char *ifconfig(Terminal &term, int argc, const char *args[])
@@ -2381,6 +2445,15 @@ static const char *ifconfig(Terminal &term, int argc, const char *args[])
 	if (argc != 1) {
 		return "Invalid number of arguments.";
 	}
+#if IDF_VERSION >= 50
+	esp_netif_t *nif = esp_netif_next(0);
+	while (nif) {
+		esp_netif_ip_info_t ipconfig;
+		if (ESP_OK == esp_netif_get_ip_info(nif,&ipconfig))
+			print_ipinfo(term, nif, &ipconfig);
+		nif = esp_netif_next(nif);
+	} 
+#else
 	tcpip_adapter_ip_info_t ipconfig;
 	if (ESP_OK == tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &ipconfig))
 		print_ipinfo(term, "if0/sta ip=", &ipconfig, wifi_station_isup());
@@ -2395,6 +2468,7 @@ static const char *ifconfig(Terminal &term, int argc, const char *args[])
 		term.printf("if0/sta %s (global)\n", inet6_ntoa(IP6G));
 	if (!ip6_addr_isany_val(IP6LL))
 		term.printf("if0/sta %s (link-local)\n", inet6_ntoa(IP6LL), wifi_station_isup());
+#endif
 #endif
 	return 0;
 }
@@ -2409,7 +2483,7 @@ static const char *version(Terminal &term, int argc, const char *args[])
 {
 	if (argc != 1)
 		return "Invalid number of arguments.";
-	int32_t s = (uint32_t) &LDTIMESTAMP;
+	time_t s = (uint32_t) &LDTIMESTAMP;
 	struct tm tm;
 	gmtime_r((time_t *)&s,&tm);
 	term.printf("Atrium Version %s\n"
@@ -2547,7 +2621,9 @@ ExeName ExeNames[] = {
 	{"lua",0,xluac,"run a lua script",lua_man},
 	{"luac",0,xluac,"compile lua script",luac_man},
 #endif
+#if IDF_VERSION < 50
 	{"mac",0,mac,"MAC addresses",mac_man},
+#endif
 	{"mem",0,mem,"RAM statistics",mem_man},
 #ifdef CONFIG_FATFS
 	{"mkdir",1,shell_mkdir,"make directory",0},
diff --git a/main/spi.cpp b/main/spi.cpp
index 684f6f7..5498d56 100644
--- a/main/spi.cpp
+++ b/main/spi.cpp
@@ -21,6 +21,7 @@
 #ifdef CONFIG_SPI
 
 #include "env.h"
+#include "fs.h"
 #include "hwcfg.h"
 #include "globals.h"
 #include "ili9341.h"
@@ -31,6 +32,12 @@
 #include "terminal.h"
 #include "xpt2046.h"
 
+#ifdef CONFIG_SDCARD
+#include <driver/sdspi_host.h>
+#include <sdmmc_cmd.h>
+#include <esp_vfs.h>
+#include <esp_vfs_fat.h>
+#endif
 
 #ifdef CONFIG_IDF_TARGET_ESP8266
 #include <driver/spi.h>
@@ -42,6 +49,89 @@
 #define TAG MODULE_SPI
 
 
+#ifdef CONFIG_SDCARD
+struct SDCard : public SpiDevice
+{
+	static SDCard *create(spi_host_device_t host, spi_device_interface_config_t &cfg, int8_t intr);
+	void attach(class EnvObject *) override;
+	const char *drvName() const override;
+	int init() override;
+	const char *exeCmd(struct Terminal &, int argc, const char **argv) override;
+
+	private:
+	SDCard(spi_host_device_t host, gpio_num_t cs)
+	: SpiDevice(drvName(), cs)
+	, m_host(host)
+	{ }
+
+	sdmmc_card_t *m_card = 0;
+	spi_host_device_t m_host;
+	bool m_mounted = false;
+};
+
+void SDCard::attach(class EnvObject *)
+{
+}
+
+const char *SDCard::drvName() const
+{
+	return "sdcard";
+}
+
+int SDCard::init()
+{
+	log_info(TAG, "mounting sd-card");
+	sdmmc_host_t sdh = SDSPI_HOST_DEFAULT();
+
+	sdspi_device_config_t sdspi = SDSPI_DEVICE_CONFIG_DEFAULT();
+	sdspi.gpio_cs = (gpio_num_t) m_cs;
+	sdspi.host_id = m_host;
+
+	esp_vfs_fat_sdmmc_mount_config_t mnt = {
+		.format_if_mount_failed = false,
+		.max_files = 4,
+		.allocation_unit_size = 16 << 10,
+		.disk_status_check_enable = false,
+	};
+	if (esp_err_t e = esp_vfs_fat_sdspi_mount("/sdcard", &sdh, &sdspi, &mnt, &m_card)) {
+		log_warn(TAG,"mount failed: %s",esp_err_to_name(e));
+		return e;
+	}
+	rootfs_add("/sdcard");
+	m_mounted = true;
+#if 0
+	sdspi_dev_handle_t hdl;
+	sdspi_device_config_t devcfg = SDSPI_DEVICE_CONFIG_DEFAULT();
+	devcfg.gpio_cs = (gpio_num_t) m_cs;
+
+	if (esp_err_t e = sdspi_host_init()) {
+		log_warn(TAG,"sdspi host intt: %s",esp_err_to_name(e));
+		return 1;
+	}
+	if (esp_err_t e = sdspi_host_init_device(&devcfg,&hdl)) {
+		log_warn(TAG,"sdspi host intt device: %s",esp_err_to_name(e));
+		return 1;
+	}
+	if (esp_err_t e = sdspi_host_set_card_clk(hdl,20000)) {
+		log_warn(TAG,"sdspi card clock: %s",esp_err_to_name(e));
+		return 1;
+	}
+#endif
+	return 0;
+}
+
+const char *SDCard::exeCmd(struct Terminal &, int argc, const char **argv)
+{
+	return 0;
+}
+
+
+SDCard *SDCard::create(spi_host_device_t host, spi_device_interface_config_t &cfg, int8_t intr)
+{
+	return new SDCard(host, (gpio_num_t) cfg.spics_io_num);
+}
+#endif
+
 static void spi_init_device(spi_host_device_t host, spidrv_t drv, int8_t cs, int8_t intr, int8_t reset, int8_t cd)
 {
 	spi_device_interface_config_t cfg;
@@ -83,6 +173,11 @@ static void spi_init_device(spi_host_device_t host, spidrv_t drv, int8_t cs, int
 	case spidrv_xpt2046:
 		XPT2046::create(host,cfg,intr);
 		break;
+#endif
+#ifdef CONFIG_SDCARD
+	case spidrv_sdcard:
+		SDCard::create(host,cfg,intr);
+		break;
 #endif
 	default:
 		log_warn(TAG,"unknown device SPI device type %d",drv);
@@ -114,6 +209,10 @@ void spi_setup()
 {
 	for (const auto &c : HWConf.spibus()) {
 		int8_t host = c.host();
+		if (host == 0) {
+			log_warn(TAG,"SPI host 0 cannot be used");
+			continue;
+		}
 		spi_bus_config_t cfg;
 		bzero(&cfg,sizeof(cfg));
 //		cfg.max_transfer_sz = 0;		// use defaults
@@ -146,13 +245,15 @@ void spi_setup()
 			cfg.quadwp_io_num = -1;
 			cfg.quadhd_io_num = -1;
 		}
-		if (esp_err_t e = spi_bus_initialize((spi_host_device_t)host,&cfg,c.has_dma() ? (spi_common_dma_t)c.dma() : SPI_DMA_CH_AUTO)) {
+		spi_host_device_t hdev = (spi_host_device_t)(host-1);
+		spi_dma_chan_t dma = c.has_dma() ? (spi_common_dma_t)c.dma() : SPI_DMA_CH_AUTO;
+		if (esp_err_t e = spi_bus_initialize(hdev,&cfg,dma)) {
 			log_warn(TAG,"error initializing SPI host %u: %s",host,esp_err_to_name(e));
-		} else {
-			log_info(TAG,"initialized SPI%u",host);
-			for (auto &d : c.devices()) {
-				spi_init_device((spi_host_device_t)host,d.drv(),d.cs(),d.intr(),d.reset(),d.cd());
-			}
+			continue;
+		}
+		log_info(TAG,"initialized SPI%u",host);
+		for (auto &d : c.devices()) {
+			spi_init_device(hdev,d.drv(),d.cs(),d.intr(),d.reset(),d.cd());
 		}
 	}
 	SpiDevice *d = SpiDevice::getFirst();
diff --git a/main/startup.cpp b/main/startup.cpp
index ef3b05c..3031743 100644
--- a/main/startup.cpp
+++ b/main/startup.cpp
@@ -28,9 +28,7 @@
 #endif
 
 extern "C" {
-#if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32S3 || defined CONFIG_IDF_TARGET_ESP32C3
-#include <esp32/clk.h>
-#else
+#ifndef ESP32
 #include <esp_clk.h>
 #endif
 }
@@ -62,6 +60,11 @@ extern "C" {
 #include "env.h"
 #include "wifi.h"
 
+#if IDF_VERSION >= 50
+#include <rom/ets_sys.h>
+#include <esp_chip_info.h>
+#endif
+
 #ifdef CONFIG_IDF_TARGET_ESP8266
 #include <spi_flash.h>
 #include <driver/rtc.h>
@@ -127,6 +130,9 @@ void settings_setup();
 
 static void system_info()
 {
+#if IDF_VERSION >= 50
+	uint32_t mhz = ets_get_cpu_frequency();
+#else
 	int f = esp_clk_cpu_freq();
 	unsigned mhz;
 	switch (f) {
@@ -155,6 +161,7 @@ static void system_info()
 	default:
 		mhz = f/1000000;
 	}
+#endif
 	esp_chip_info_t ci;
 	esp_chip_info(&ci);
 	log_info(TAG,"ESP%u (rev %d) with %d core%s @ %uMHz%s"
diff --git a/main/support.h b/main/support.h
index 5075897..0544a54 100644
--- a/main/support.h
+++ b/main/support.h
@@ -30,7 +30,7 @@ class stream;
 
 struct CStrLess
 {
-	bool operator () (const char *l, const char *r)
+	bool operator () (const char *l, const char *r) const
 	{
 		return strcmp(l,r) < 0;
 	}
@@ -38,7 +38,7 @@ struct CStrLess
 
 struct SubstrLess
 {
-	bool operator () (const char *l, const char *r)
+	bool operator () (const char *l, const char *r) const
 	{
 		size_t ll = strlen(l);
 		size_t rl = strlen(r);
diff --git a/main/syslog.cpp b/main/syslog.cpp
index 704e865..602fb8b 100644
--- a/main/syslog.cpp
+++ b/main/syslog.cpp
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2018-2022, Thomas Maier-Komor
+ *  Copyright (C) 2018-2023, Thomas Maier-Komor
  *  Atrium Firmware Package for ESP
  *
  *  This program is free software: you can redistribute it and/or modify
@@ -158,7 +158,7 @@ static int sendmsg(LogMsg *m)
 		n = snprintf(header,sizeof(header),"<%d>1 %4u-%02u-%02uT%02u:%02u:%02u.%03uZ %.*s %s - - - "
 			, 16 << 3 | lvl	// facility local use = 16, pri = (facility)<<3|serverity
 			, tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday
-			, tm.tm_hour, tm.tm_min, tm.tm_sec, m->ts%1000
+			, tm.tm_hour, tm.tm_min, tm.tm_sec, (unsigned)(m->ts%1000)
 			, HostnameLen
 			, Hostname
 			, mod
diff --git a/main/udpctrl.cpp b/main/udpctrl.cpp
index d54ad6c..96be7a9 100644
--- a/main/udpctrl.cpp
+++ b/main/udpctrl.cpp
@@ -43,7 +43,7 @@
 
 #if defined CONFIG_IDF_TARGET_ESP32 || defined CONFIG_IDF_TARGET_ESP32S3
 #define stacksize 4096
-#elif defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32C3
+#elif defined CONFIG_IDF_TARGET_ESP32S2 || defined CONFIG_IDF_TARGET_ESP32C3 || defined CONFIG_IDF_TARGET_ESP32C6
 #define APP_CPU_NUM 0
 #define stacksize 4096
 #else
diff --git a/main/wifi.cpp b/main/wifi.cpp
index 08046c2..e3e983f 100644
--- a/main/wifi.cpp
+++ b/main/wifi.cpp
@@ -29,17 +29,23 @@
 #include "wifi.h"
 
 #include <esp_err.h>
-#include <esp_wifi.h>
-#include <esp_smartconfig.h>
-#include <smartconfig_ack.h>
 #include <esp_wps.h>
-#if IDF_VERSION < 40
+#include <esp_wifi.h>
+
+#if IDF_VERSION >= 50
+typedef esp_etm_event_t system_event_t;
+#elif IDF_VERSION >= 44
+#include <esp_event_legacy.h>
+#elif IDF_VERSION < 40
 #include <esp_event_loop.h>
 #endif
-#if IDF_VERSION >= 44
-#include <esp_event_legacy.h>
+
+#ifdef CONFIG_SMARTCONFIG
+#include <esp_smartconfig.h>
+#include <smartconfig_ack.h>
 #endif
 
+
 #include <lwip/ip_addr.h>
 
 #include <string.h>
@@ -71,6 +77,21 @@ esp_err_t system_event_sta_connected_handle_default(system_event_t *);	// IDF
 esp_err_t system_event_sta_disconnected_handle_default(system_event_t *);	// IDF
 }
 
+
+#if IDF_VERSION >= 50
+esp_netif_t *netif_get_station()
+{
+	esp_netif_t *itf = esp_netif_next(0);
+	while (itf) {
+		const char *desc = esp_netif_get_desc(itf);
+		if (0 == strcmp(desc,"sta"))
+			return itf;
+		itf = esp_netif_next(itf);
+	}
+	return 0;
+}
+#endif
+
 #if IDF_VERSION >= 40
 static void event_handler(void* arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
 {
@@ -82,9 +103,16 @@ static void event_handler(void* arg, esp_event_base_t event_base, int32_t event_
 			WifiRetry = 0;
 			StationMode = station_starting;
 		} else if (event_id == WIFI_EVENT_STA_CONNECTED) {
-#if defined CONFIG_LWIP_IPV6 || defined ESP32
+#if defined CONFIG_LWIP_IPV6 //|| defined ESP32
+#if IDF_VERSION >= 50
+			if (esp_netif_t *itf = netif_get_station()) {
+				if (esp_err_t e = esp_netif_create_ip6_linklocal(itf))
+					log_warn(TAG,"create IPv6 linklocal on station: %s",esp_err_to_name(e));
+			}
+#else
 			if (esp_err_t e = tcpip_adapter_create_ip6_linklocal(TCPIP_ADAPTER_IF_STA))
 				log_warn(TAG,"create IPv6 linklocal on station: %s",esp_err_to_name(e));
+#endif
 #endif
 		} else if (event_id == WIFI_EVENT_STA_STOP) {
 			if (0 == StationDownTS)
@@ -125,6 +153,7 @@ static void event_handler(void* arg, esp_event_base_t event_base, int32_t event_
 			Status |= STATUS_WIFI_UP | STATUS_STATION_UP;
 			StationMode = station_connected;
 			event_trigger(StationUpEv);
+#if defined CONFIG_LWIP_IPV6
 		} else if (event_id == IP_EVENT_GOT_IP6) {
 			ip_event_got_ip6_t* event = (ip_event_got_ip6_t*) event_data;
 			ip6_addr_t ip;
@@ -138,6 +167,7 @@ static void event_handler(void* arg, esp_event_base_t event_base, int32_t event_
 			Status |= STATUS_WIFI_UP | STATUS_STATION_UP;
 			StationMode = station_connected;
 			event_trigger(StationUpEv);
+#endif
 		} else if (event_id == IP_EVENT_STA_LOST_IP) {
 			log_info(TAG, "lost IP");
 			if (0 == StationDownTS)
@@ -188,7 +218,12 @@ static esp_err_t wifi_event_handler(system_event_t *event)
 	case SYSTEM_EVENT_STA_CONNECTED:
 		log_info(TAG,"station " MACSTR " connected",MAC2STR(event->event_info.sta_connected.mac));
 		system_event_sta_connected_handle_default(event);	// IDF
-#if defined CONFIG_LWIP_IPV6 || defined ESP32
+#if IDF_VERSION >= 50
+		if (esp_netif_t *itf = netif_get_station()) {
+			if (esp_err_t e = esp_netif_create_ip6_linklocal(itf))
+				log_warn(TAG,"create IPv6 linklocal on station: %s",esp_err_to_name(e));
+		}
+#elif defined CONFIG_LWIP_IPV6 || defined ESP32
 		if (esp_err_t e = tcpip_adapter_create_ip6_linklocal(TCPIP_ADAPTER_IF_STA))
 			log_warn(TAG,"create IPv6 linklocal on station: %s",esp_err_to_name(e));
 #endif
@@ -212,7 +247,7 @@ static esp_err_t wifi_event_handler(system_event_t *event)
 			ip6_addr_t ip;
 			assert(sizeof(ip) == sizeof(event->event_info.got_ip6.ip6_info.ip));
 			memcpy(&ip,event->event_info.got_ip6.ip6_info.ip.addr,sizeof(ip));
-			log_info(TAG,"station got IP %s",ip6addr_ntoa(&ip));
+			log_info(TAG,"station got IPv6 %s",ip6addr_ntoa(&ip));
 			if (ip6_addr_islinklocal(&ip))
 				memcpy(&IP6LL,&event->event_info.got_ip6.ip6_info.ip,sizeof(IP6LL));
 			else
@@ -527,21 +562,35 @@ bool wifi_start_station(const char *ssid, const char *pass)
 		return false;
 	}
 	if (station.has_addr4() && station.has_netmask4()) {
-		tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
-		tcpip_adapter_ip_info_t ipi;
-		bzero(&ipi,sizeof(ipi));
-		ipi.ip.addr = station.addr4();
 		uint32_t nm = 0;
 		uint8_t nmb = station.netmask4();
 		while (nmb--) {
 			nm <<= 1;
 			nm |= 1;
 		}
+#if IDF_VERSION >= 50
+		esp_netif_t *sta = netif_get_station();
+		assert(sta);
+		if (esp_err_t e = esp_netif_dhcpc_stop(sta))
+			log_warn(TAG,"stop DHCP client on station failed: %s",esp_err_to_name(e));
+		esp_netif_ip_info_t ipi;
+		ipi.ip.addr = station.addr4();
+		ipi.netmask.addr = (uint32_t)nm;
+		if (station.has_gateway4())
+			ipi.gw.addr = station.gateway4();
+		if (esp_err_t e = esp_netif_set_ip_info(sta,&ipi))
+			log_warn(TAG,"set static IP on station failed: %s",esp_err_to_name(e));
+#else
+		tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
+		tcpip_adapter_ip_info_t ipi;
+		bzero(&ipi,sizeof(ipi));
+		ipi.ip.addr = station.addr4();
 		ipi.netmask.addr = (uint32_t)nm;
 		if (station.has_gateway4())
 			ipi.gw.addr = station.gateway4();
 		tcpip_adapter_dhcpc_stop(TCPIP_ADAPTER_IF_STA);
 		tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_STA,&ipi);
+#endif
 		initDns();
 	} else if (station.has_addr4() || station.has_netmask4()) {
 		log_warn(TAG,"incomplete static IP");
@@ -743,6 +792,11 @@ int wifi_setup()
 	esp_netif_init();
 	esp_event_loop_create_default();
 	esp_netif_create_default_wifi_sta();
+#if IDF_VERSION >= 50
+	wifi_init_config_t wcfg = WIFI_INIT_CONFIG_DEFAULT();
+	if (esp_err_t e = esp_wifi_init(&wcfg))
+		log_warn(TAG,"wifi init: %s",esp_err_to_name(e));
+#endif
 	esp_wifi_set_default_wifi_sta_handlers();
 	if (esp_err_t e = esp_event_handler_register(WIFI_EVENT, ESP_EVENT_ANY_ID, &event_handler, 0))
 		log_warn(TAG,"set wifi handler: %s",esp_err_to_name(e));
diff --git a/mkatrium.sh b/mkatrium.sh
index 6e4b622..43e4a8a 100755
--- a/mkatrium.sh
+++ b/mkatrium.sh
@@ -61,6 +61,10 @@ elif  [ "$CONFIG_IDF_TARGET_ESP32C3" == "y" ]; then
 	export IDF_PATH=$IDF_ESP32
 	export ESP_FAM=32
 	export IDF_TARGET=esp32c3
+elif  [ "$CONFIG_IDF_TARGET_ESP32C6" == "y" ]; then
+	export IDF_PATH=$IDF_ESP32
+	export ESP_FAM=32
+	export IDF_TARGET=esp32c6
 elif  [ "$CONFIG_IDF_TARGET_ESP8266" == "y" ]; then
 	make PROJECT=$1 $2
 	exit
diff --git a/patches/esp32-lwip-v5.1.diff b/patches/esp32-lwip-v5.1.diff
new file mode 100644
index 0000000..60a74d1
--- /dev/null
+++ b/patches/esp32-lwip-v5.1.diff
@@ -0,0 +1,93 @@
+diff --git a/src/core/dns.c b/src/core/dns.c
+index e7b52d24..9945d9e5 100644
+--- a/src/core/dns.c
++++ b/src/core/dns.c
+@@ -292,7 +292,9 @@ static err_t dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADD
+ 
+ /* forward declarations */
+ static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port);
++#if 0
+ static void dns_check_entries(void);
++#endif
+ static void dns_call_found(u8_t idx, ip_addr_t *addr);
+ 
+ /*-----------------------------------------------------------------------------
+@@ -320,6 +322,7 @@ const ip_addr_t dns_mquery_v6group = DNS_MQUERY_IPV6_GROUP_INIT;
+  * Initialize the resolver: set up the UDP pcb and configure the default server
+  * (if DNS_SERVER_ADDRESS is set).
+  */
++#if 0
+ void
+ dns_init(void)
+ {
+@@ -371,6 +374,7 @@ dns_init(void)
+   dns_init_local();
+ #endif
+ }
++#endif
+ 
+ /**
+  * @ingroup dns
+@@ -379,6 +383,7 @@ dns_init(void)
+  * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS
+  * @param dnsserver IP address of the DNS server to set
+  */
++#if 0
+ void
+ dns_setserver(u8_t numdns, const ip_addr_t *dnsserver)
+ {
+@@ -390,6 +395,7 @@ dns_setserver(u8_t numdns, const ip_addr_t *dnsserver)
+     }
+   }
+ }
++#endif
+ 
+ /**
+  * Clears the DNS cache
+@@ -433,6 +439,7 @@ static void dns_timeout_cb(void *arg)
+  * The DNS resolver client timer - handle retries and timeouts and should
+  * be called every DNS_TMR_INTERVAL milliseconds (every second by default).
+  */
++#if 0
+ void
+ dns_tmr(void)
+ {
+@@ -487,6 +494,7 @@ dns_init_local(void)
+   }
+ #endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */
+ }
++#endif
+ 
+ /**
+  * @ingroup dns
+@@ -1190,6 +1198,7 @@ dns_check_entry(u8_t i)
+ /**
+  * Call dns_check_entry for each entry in dns_table - check all entries.
+  */
++#if 0
+ static void
+ dns_check_entries(void)
+ {
+@@ -1199,6 +1208,7 @@ dns_check_entries(void)
+     dns_check_entry(i);
+   }
+ }
++#endif
+ 
+ /**
+  * Save TTL and call dns_call_found for correct response.
+@@ -1598,12 +1608,14 @@ dns_enqueue(const char *name, size_t hostnamelen, dns_found_callback found,
+  * @param callback_arg argument to pass to the callback function
+  * @return a err_t return code.
+  */
++#if 0
+ err_t
+ dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found,
+                   void *callback_arg)
+ {
+   return dns_gethostbyname_addrtype(hostname, addr, found, callback_arg, LWIP_DNS_ADDRTYPE_DEFAULT);
+ }
++#endif
+ 
+ #if ESP_DNS
+ static bool dns_server_is_set (void)
diff --git a/projects/esp32-c3_4m b/projects/esp32-c3_4m
index 41d3f96..2a71aca 100644
--- a/projects/esp32-c3_4m
+++ b/projects/esp32-c3_4m
@@ -1,40 +1,266 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_GDMA_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
+CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
+CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
+CONFIG_SOC_XT_WDT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
+CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
+CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_HMAC_SUPPORTED=y
+CONFIG_SOC_DIG_SIGN_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_MEMPROT_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_AES_SUPPORT_DMA=y
+CONFIG_SOC_AES_GDMA=y
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
+CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1
+CONFIG_SOC_ADC_PATT_LEN_MAX=8
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
+CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
+CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
+CONFIG_SOC_APB_BACKUP_DMA=y
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
+CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
+CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000
+CONFIG_SOC_CPU_CORES_NUM=1
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=8
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=8
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=0x80000000
+CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072
+CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
+CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
+CONFIG_SOC_GDMA_GROUPS=1
+CONFIG_SOC_GDMA_PAIRS_PER_GROUP=3
+CONFIG_SOC_GDMA_TX_RX_SHARE_INTERRUPT=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=22
+CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
+CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
+CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
+CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y
+CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0
+CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y
+CONFIG_SOC_I2C_NUM=1
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
+CONFIG_SOC_I2C_SUPPORT_XTAL=y
+CONFIG_SOC_I2C_SUPPORT_RTC=y
+CONFIG_SOC_I2S_NUM=1
+CONFIG_SOC_I2S_HW_VERSION_2=y
+CONFIG_SOC_I2S_SUPPORTS_XTAL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PCM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
+CONFIG_SOC_I2S_SUPPORTS_TDM=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=6
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
+CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
+CONFIG_SOC_MMU_PERIPH_NUM=1
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48
+CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
+CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
+CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
+CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
+CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
+CONFIG_SOC_RMT_SUPPORT_XTAL=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
+CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128
+CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108
+CONFIG_SOC_RTCIO_PIN_COUNT=0
+CONFIG_SOC_RSA_MAX_BIT_LEN=3072
+CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
+CONFIG_SOC_SHA_SUPPORT_DMA=y
+CONFIG_SOC_SHA_SUPPORT_RESUME=y
+CONFIG_SOC_SHA_GDMA=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA224=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_PERIPH_NUM=2
+CONFIG_SOC_SPI_MAX_CS_NUM=6
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_SUPPORT_DDRCLK=y
+CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
+CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
+CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
+CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
+CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y
+CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
+CONFIG_SOC_SYSTIMER_ALARM_NUM=3
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
+CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
+CONFIG_SOC_SYSTIMER_INT_LEVEL=y
+CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
+CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_BRP_MAX=16384
+CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
+CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y
+CONFIG_SOC_EFUSE_DIS_USB_JTAG=y
+CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y
+CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_ICACHE=y
+CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
+CONFIG_SOC_SECURE_BOOT_V2_RSA=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
+CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
+CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
+CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512
+CONFIG_SOC_UART_NUM=2
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
+CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
+CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
+CONFIG_SOC_UART_REQUIRE_CORE_RESET=y
+CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
+CONFIG_SOC_COEX_HW_PTI=y
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
+CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
+CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_CPU_PD=y
+CONFIG_SOC_PM_SUPPORT_WIFI_PD=y
+CONFIG_SOC_PM_SUPPORT_BT_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
+CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y
+CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
+CONFIG_SOC_WIFI_HW_TSF=y
+CONFIG_SOC_WIFI_FTM_SUPPORT=y
+CONFIG_SOC_WIFI_GCMP_SUPPORT=y
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BLE_50_SUPPORTED=y
+CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_RISCV=y
+CONFIG_IDF_TARGET_ARCH="riscv"
 CONFIG_IDF_TARGET="esp32c3"
 CONFIG_IDF_TARGET_ESP32C3=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="riscv32-esp-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -50,7 +276,6 @@ CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y
 # CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set
 # CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set
 CONFIG_BOOTLOADER_LOG_LEVEL=3
-CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y
 # CONFIG_BOOTLOADER_FACTORY_RESET is not set
 # CONFIG_BOOTLOADER_APP_TEST is not set
 CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y
@@ -69,13 +294,41 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
-CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
-CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
+CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_PREFERRED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+CONFIG_SECURE_ROM_DL_MODE_ENABLED=y
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
+CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3
+CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
+CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y
+CONFIG_ESP_ROM_GET_CLK_FREQ=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
+CONFIG_ESP_ROM_HAS_SPI_FLASH=y
+CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
+CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
+
 #
 # Boot ROM Behavior
 #
@@ -88,7 +341,6 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_NO_STUB=y
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
@@ -100,6 +352,7 @@ CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
 # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
 CONFIG_ESPTOOLPY_FLASHFREQ="80m"
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
@@ -110,22 +363,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -145,13 +389,14 @@ CONFIG_PARTITION_TABLE_MD5=y
 #
 # Compiler options
 #
-CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
-# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set
+# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 # CONFIG_COMPILER_OPTIMIZATION_PERF is not set
 # CONFIG_COMPILER_OPTIMIZATION_NONE is not set
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -163,7 +408,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
 # CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -176,15 +421,13 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_USB_CDC is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -192,59 +435,94 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
+# Driver Configurations
 #
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
 
 #
-# Driver configurations
+# Legacy ADC Configuration
 #
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# ADC configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_ADC_FORCE_XPD_FSM is not set
-CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# MCPWM configuration
-#
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
-
-#
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
 
 #
-# UART configuration
+# Temperature sensor Configuration
+#
+# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
+# end of Temperature sensor Configuration
+
+#
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
+# end of UART Configuration
 
 #
-# GDMA Configuration
+# GPIO Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
+# end of GPIO Configuration
+
+#
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# RMT Configuration
+#
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# I2S Configuration
+#
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# USB Serial/JTAG Configuration
+#
+# end of USB Serial/JTAG Configuration
+# end of Driver Configurations
 
 #
 # eFuse Bit Manager
@@ -266,42 +544,19 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
 # end of ESP-TLS
 
 #
-# ESP32C3-Specific
+# ADC and ADC Calibration
 #
-# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set
-CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y
-CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160
-# CONFIG_ESP32C3_REV_MIN_0 is not set
-# CONFIG_ESP32C3_REV_MIN_1 is not set
-# CONFIG_ESP32C3_REV_MIN_2 is not set
-CONFIG_ESP32C3_REV_MIN_3=y
-# CONFIG_ESP32C3_REV_MIN_4 is not set
-CONFIG_ESP32C3_REV_MIN=3
-CONFIG_ESP32C3_DEBUG_OCDAWARE=y
-CONFIG_ESP32C3_BROWNOUT_DET=y
-CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
-# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
-CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
-CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
-# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set
-# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024
-# CONFIG_ESP32C3_NO_BLOBS is not set
-# end of ESP32C3-Specific
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
+# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
+# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set
+# end of ADC and ADC Calibration
 
 #
-# ADC-Calibration
+# Wireless Coexistence
 #
-# end of ADC-Calibration
+# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -318,6 +573,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -350,12 +606,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-# CONFIG_OTA_ALLOW_HTTP is not set
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set
 # end of ESP HTTPS OTA
 
 #
@@ -368,6 +626,24 @@ CONFIG_HTTPD_PURGE_BUF_LEN=32
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+# CONFIG_ESP32C3_REV_MIN_0 is not set
+# CONFIG_ESP32C3_REV_MIN_1 is not set
+# CONFIG_ESP32C3_REV_MIN_2 is not set
+CONFIG_ESP32C3_REV_MIN_3=y
+# CONFIG_ESP32C3_REV_MIN_4 is not set
+CONFIG_ESP32C3_REV_MIN_FULL=3
+CONFIG_ESP_REV_MIN_FULL=3
+
+#
+# Maximum Supported ESP32-C3 Revision (Rev v0.99)
+#
+CONFIG_ESP32C3_REV_MAX_FULL=99
+CONFIG_ESP_REV_MAX_FULL=99
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -375,6 +651,7 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4
@@ -389,27 +666,52 @@ CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
 # end of Sleep Config
 
+CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND=y
+
 #
 # RTC Clock Config
 #
-# CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB is not set
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# GDMA Configuration
+#
+# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GDMA_ISR_IRAM_SAFE is not set
+# end of GDMA Configuration
+
+#
+# Main XTAL Config
+#
+CONFIG_XTAL_FREQ_40=y
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -419,9 +721,16 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
 #
 # PHY
 #
@@ -429,7 +738,13 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
 CONFIG_ESP_PHY_ENABLE_USB=y
+# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
 # end of PHY
 
 #
@@ -439,21 +754,28 @@ CONFIG_ESP_PHY_ENABLE_USB=y
 CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
 # end of Power Management
 
+#
+# ESP PSRAM
+#
+
 #
 # ESP Ringbuf
 #
 # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
 # end of ESP Ringbuf
 
 #
 # ESP System Settings
 #
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
 CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
 CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
@@ -462,11 +784,8 @@ CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
 #
 # Memory protection
 #
-CONFIG_ESP_SYSTEM_MEMPROT_DEPCHECK=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
-CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
-CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE=512
 # end of Memory protection
 
 CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
@@ -481,18 +800,42 @@ CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
 # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
 # CONFIG_ESP_CONSOLE_NONE is not set
 CONFIG_ESP_CONSOLE_SECONDARY_NONE=y
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y
 CONFIG_ESP_CONSOLE_UART_NUM=0
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 # CONFIG_ESP_TASK_WDT_PANIC is not set
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=7
+# end of Brownout Detector
+
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -501,6 +844,11 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
 CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 # end of High resolution timer (esp_timer)
@@ -508,33 +856,54 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
-CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
-CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=6
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set
+CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=6
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_FTM_ENABLE is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
-# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_ESP_WIFI_GCMP_SUPPORT is not set
 # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -556,6 +925,12 @@ CONFIG_ESP_COREDUMP_SUMMARY_STACKDUMP_SIZE=1024
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+# CONFIG_FATFS_LFN_NONE is not set
+# CONFIG_FATFS_LFN_HEAP is not set
+CONFIG_FATFS_LFN_STACK=y
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -579,90 +954,71 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-# CONFIG_FATFS_LFN_NONE is not set
-# CONFIG_FATFS_LFN_HEAP is not set
-CONFIG_FATFS_LFN_STACK=y
 CONFIG_FATFS_MAX_LFN=63
 CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
-# CONFIG_FATFS_API_ENCODING_UTF_16 is not set
 # CONFIG_FATFS_API_ENCODING_UTF_8 is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=4096
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-CONFIG_FMB_PORT_TASK_AFFINITY=0x7FFFFFFF
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_FMB_TIMER_PORT_ENABLED is not set
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 CONFIG_FREERTOS_UNICORE=y
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
-CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
-# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
-CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
-CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 CONFIG_FREERTOS_HZ=100
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
+CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
 # CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is not set
 CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
-CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
+# end of Kernel
+
+#
+# Port
+#
 CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
 CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
+CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
+# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
+CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
+CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -670,9 +1026,11 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -686,21 +1044,15 @@ CONFIG_HEAP_TRACING_STANDALONE=y
 # CONFIG_HEAP_TRACING_TOHOST is not set
 CONFIG_HEAP_TRACING=y
 CONFIG_HEAP_TRACING_STACK_DEPTH=0
+# CONFIG_HEAP_USE_HOOKS is not set
 CONFIG_HEAP_TASK_TRACKING=y
+# CONFIG_HEAP_TRACE_HASH_MAP is not set
 CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS=y
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -727,6 +1079,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 # CONFIG_LWIP_IRAM_OPTIMIZATION is not set
@@ -742,17 +1095,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 # CONFIG_LWIP_IP4_REASSEMBLY is not set
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -763,6 +1120,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 CONFIG_LWIP_IPV6_AUTOCONFIG=y
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -790,7 +1148,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -843,6 +1200,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -860,6 +1218,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -878,13 +1239,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -902,11 +1265,13 @@ CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200
 CONFIG_MBEDTLS_HARDWARE_AES=y
 CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_SHA=y
 CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -923,7 +1288,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -932,16 +1296,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -950,9 +1309,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -972,6 +1328,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -996,26 +1353,11 @@ CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1037,6 +1379,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1045,21 +1391,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set
-CONFIG_OPENSSL_ASSERT_EXIT=y
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1070,6 +1415,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1080,8 +1433,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
-# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
 CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
@@ -1092,9 +1443,23 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1151,6 +1516,7 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
@@ -1166,6 +1532,11 @@ CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
 # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
 # end of Unity unit testing library
 
+#
+# Root Hub configuration
+#
+# end of Root Hub configuration
+
 #
 # Virtual file system
 #
@@ -1195,22 +1566,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1265,6 +1624,7 @@ CONFIG_USB_HOST_FS=y
 CONFIG_USB_DIAGLOG=y
 CONFIG_USB_CONSOLE=y
 CONFIG_GPIOS=y
+# CONFIG_CORETEMP is not set
 CONFIG_IOEXTENDERS=y
 CONFIG_LEDS=y
 CONFIG_BUTTON=y
@@ -1285,6 +1645,7 @@ CONFIG_PCF8574=y
 CONFIG_TCA9555=y
 CONFIG_MCP2300X=y
 CONFIG_MCP2301X=y
+# CONFIG_OPT3001 is not set
 CONFIG_INA2XX=y
 CONFIG_SI7021=y
 CONFIG_BMX280=y
@@ -1298,6 +1659,7 @@ CONFIG_SPI=y
 # CONFIG_SX1276 is not set
 CONFIG_SSD1309=y
 CONFIG_ILI9341=y
+# CONFIG_SDCARD is not set
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1315,14 +1677,11 @@ CONFIG_DEVEL=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="riscv32-esp-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1336,17 +1695,11 @@ CONFIG_LOG_BOOTLOADER_LEVEL=3
 # CONFIG_FLASHMODE_QOUT is not set
 CONFIG_FLASHMODE_DIO=y
 # CONFIG_FLASHMODE_DOUT is not set
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
-CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
-# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
+# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set
+# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
+CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set
@@ -1357,45 +1710,103 @@ CONFIG_STACK_CHECK_NONE=y
 # CONFIG_STACK_CHECK_STRONG is not set
 # CONFIG_STACK_CHECK_ALL is not set
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
-CONFIG_ADC2_DISABLE_DAC=y
+# CONFIG_EXTERNAL_COEX_ENABLE is not set
+# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+# CONFIG_OTA_ALLOW_HTTP is not set
 # CONFIG_ESP_SYSTEM_PD_FLASH is not set
 CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y
-CONFIG_IPC_TASK_STACK_SIZE=1536
+CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y
+# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
 CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
-CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
-CONFIG_ESP32H2_MEMPROT_FEATURE=y
-CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK=y
+# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set
+CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y
+CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160
+CONFIG_ESP32C3_MEMPROT_FEATURE=y
+CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK=y
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 # CONFIG_CONSOLE_UART_DEFAULT is not set
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART_NUM=0
 CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 # CONFIG_TASK_WDT_PANIC is not set
 CONFIG_TASK_WDT_TIMEOUT_S=5
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP32C3_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32C3_BROWNOUT_DET=y
+CONFIG_ESP32C3_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_7=y
+CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set
+CONFIG_BROWNOUT_DET_LVL=7
+CONFIG_ESP32C3_BROWNOUT_DET_LVL=7
+CONFIG_IPC_TASK_STACK_SIZE=1536
 CONFIG_TIMER_TASK_STACK_SIZE=3584
-# CONFIG_EXTERNAL_COEX_ENABLE is not set
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1405,25 +1816,12 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64
 CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_MB_TIMER_PORT_ENABLED is not set
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1435,7 +1833,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1445,6 +1842,10 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
+# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set
+# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
diff --git a/projects/esp32-c6_4m b/projects/esp32-c6_4m
new file mode 100644
index 0000000..14a0900
--- /dev/null
+++ b/projects/esp32-c6_4m
@@ -0,0 +1,1913 @@
+#
+# Automatically generated file. DO NOT EDIT.
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_GDMA_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_ETM_SUPPORTED=y
+CONFIG_SOC_PARLIO_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_IEEE802154_SUPPORTED=y
+CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
+CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
+CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_LP_CORE_SUPPORTED=y
+CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_HMAC_SUPPORTED=y
+CONFIG_SOC_DIG_SIGN_SUPPORTED=y
+CONFIG_SOC_ECC_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_APM_SUPPORTED=y
+CONFIG_SOC_PMU_SUPPORTED=y
+CONFIG_SOC_PAU_SUPPORTED=y
+CONFIG_SOC_LP_TIMER_SUPPORTED=y
+CONFIG_SOC_LP_AON_SUPPORTED=y
+CONFIG_SOC_LP_I2C_SUPPORTED=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_AES_SUPPORT_DMA=y
+CONFIG_SOC_AES_GDMA=y
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
+CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=1
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=7
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1
+CONFIG_SOC_ADC_PATT_LEN_MAX=8
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
+CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_TEMPERATURE_SHARE_INTR=y
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
+CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
+CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=1
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y
+CONFIG_SOC_INT_PLIC_SUPPORTED=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=4
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=4
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=0x80000000
+CONFIG_SOC_CPU_HAS_PMA=y
+CONFIG_SOC_CPU_IDRAM_SPLIT_USING_PMP=y
+CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072
+CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
+CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
+CONFIG_SOC_GDMA_GROUPS=1
+CONFIG_SOC_GDMA_PAIRS_PER_GROUP=3
+CONFIG_SOC_GDMA_SUPPORT_ETM=y
+CONFIG_SOC_ETM_GROUPS=1
+CONFIG_SOC_ETM_CHANNELS_PER_GROUP=50
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=31
+CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
+CONFIG_SOC_GPIO_FLEX_GLITCH_FILTER_NUM=8
+CONFIG_SOC_GPIO_SUPPORT_ETM=y
+CONFIG_SOC_GPIO_ETM_EVENTS_PER_GROUP=8
+CONFIG_SOC_GPIO_ETM_TASKS_PER_GROUP=8
+CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y
+CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y
+CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x000000007FFFFF00
+CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
+CONFIG_SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP=y
+CONFIG_SOC_RTCIO_PIN_COUNT=8
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y
+CONFIG_SOC_I2C_NUM=1
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
+CONFIG_SOC_I2C_SUPPORT_XTAL=y
+CONFIG_SOC_I2C_SUPPORT_RTC=y
+CONFIG_SOC_LP_I2C_NUM=1
+CONFIG_SOC_LP_I2C_FIFO_LEN=16
+CONFIG_SOC_I2S_NUM=1
+CONFIG_SOC_I2S_HW_VERSION_2=y
+CONFIG_SOC_I2S_SUPPORTS_XTAL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PCM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
+CONFIG_SOC_I2S_SUPPORTS_TDM=y
+CONFIG_SOC_LEDC_SUPPORT_PLL_DIV_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=6
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20
+CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
+CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED=y
+CONFIG_SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX=16
+CONFIG_SOC_LEDC_FADE_PARAMS_BIT_WIDTH=10
+CONFIG_SOC_MMU_PAGE_SIZE_CONFIGURABLE=y
+CONFIG_SOC_MMU_PERIPH_NUM=1
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
+CONFIG_SOC_MMU_DI_VADDR_SHARED=y
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=4
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE=y
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48
+CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
+CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
+CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
+CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
+CONFIG_SOC_RMT_SUPPORT_XTAL=y
+CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
+CONFIG_SOC_MCPWM_GROUPS=1
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y
+CONFIG_SOC_MCPWM_SUPPORT_ETM=y
+CONFIG_SOC_MCPWM_CAPTURE_CLK_FROM_GROUP=y
+CONFIG_SOC_PARLIO_GROUPS=1
+CONFIG_SOC_PARLIO_TX_UNITS_PER_GROUP=1
+CONFIG_SOC_PARLIO_RX_UNITS_PER_GROUP=1
+CONFIG_SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH=16
+CONFIG_SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH=16
+CONFIG_SOC_PARLIO_TX_RX_SHARE_INTERRUPT=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=3072
+CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
+CONFIG_SOC_SHA_SUPPORT_DMA=y
+CONFIG_SOC_SHA_SUPPORT_RESUME=y
+CONFIG_SOC_SHA_GDMA=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA224=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4
+CONFIG_SOC_SDM_CLK_SUPPORT_PLL_F80M=y
+CONFIG_SOC_SDM_CLK_SUPPORT_XTAL=y
+CONFIG_SOC_SPI_PERIPH_NUM=2
+CONFIG_SOC_SPI_MAX_CS_NUM=6
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_SUPPORT_DDRCLK=y
+CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
+CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
+CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
+CONFIG_SOC_SPI_SUPPORT_CLK_PLL_F80M=y
+CONFIG_SOC_SPI_SUPPORT_CLK_RC_FAST=y
+CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
+CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y
+CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y
+CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
+CONFIG_SOC_SYSTIMER_ALARM_NUM=3
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
+CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
+CONFIG_SOC_SYSTIMER_SUPPORT_RC_FAST=y
+CONFIG_SOC_SYSTIMER_INT_LEVEL=y
+CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
+CONFIG_SOC_SYSTIMER_SUPPORT_ETM=y
+CONFIG_SOC_LP_TIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_LP_TIMER_BIT_WIDTH_HI=16
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
+CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
+CONFIG_SOC_TIMER_GROUP_SUPPORT_RC_FAST=y
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2
+CONFIG_SOC_TIMER_SUPPORT_ETM=y
+CONFIG_SOC_TWAI_CONTROLLER_NUM=2
+CONFIG_SOC_TWAI_CLK_SUPPORT_XTAL=y
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_BRP_MAX=32768
+CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
+CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y
+CONFIG_SOC_EFUSE_DIS_USB_JTAG=y
+CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y
+CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_ICACHE=y
+CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
+CONFIG_SOC_SECURE_BOOT_V2_RSA=y
+CONFIG_SOC_SECURE_BOOT_V2_ECC=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
+CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
+CONFIG_SOC_UART_NUM=2
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_UART_SUPPORT_PLL_F80M_CLK=y
+CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
+CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
+CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
+CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
+CONFIG_SOC_COEX_HW_PTI=y
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
+CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_BEACON_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_CPU_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_PM_SUPPORT_XTAL32K_PD=y
+CONFIG_SOC_PM_SUPPORT_RC32K_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_TOP_PD=y
+CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE=y
+CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y
+CONFIG_SOC_PM_CPU_RETENTION_BY_SW=y
+CONFIG_SOC_PM_MODEM_RETENTION_BY_REGDMA=y
+CONFIG_SOC_PM_PAU_LINK_NUM=4
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_MODEM_CLOCK_IS_INDEPENDENT=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_CLK_OSC_SLOW_SUPPORTED=y
+CONFIG_SOC_CLK_RC32K_SUPPORTED=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y
+CONFIG_SOC_TEMPERATURE_SENSOR_INTR_SUPPORT=y
+CONFIG_SOC_WIFI_HW_TSF=y
+CONFIG_SOC_WIFI_FTM_SUPPORT=y
+CONFIG_SOC_WIFI_GCMP_SUPPORT=y
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_HE_SUPPORT=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_ESP_NIMBLE_CONTROLLER=y
+CONFIG_SOC_BLE_50_SUPPORTED=y
+CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
+CONFIG_SOC_BLE_POWER_CONTROL_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_IDF_CMAKE=y
+CONFIG_IDF_TARGET_ARCH_RISCV=y
+CONFIG_IDF_TARGET_ARCH="riscv"
+CONFIG_IDF_TARGET="esp32c6"
+CONFIG_IDF_TARGET_ESP32C6=y
+CONFIG_IDF_FIRMWARE_CHIP_ID=0x000D
+
+#
+# Build type
+#
+CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
+# CONFIG_APP_BUILD_TYPE_RAM is not set
+CONFIG_APP_BUILD_GENERATE_BINARIES=y
+CONFIG_APP_BUILD_BOOTLOADER=y
+CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
+# end of Build type
+
+#
+# Bootloader config
+#
+CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0
+CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set
+# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set
+CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y
+# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set
+# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set
+CONFIG_BOOTLOADER_LOG_LEVEL=3
+# CONFIG_BOOTLOADER_FACTORY_RESET is not set
+# CONFIG_BOOTLOADER_APP_TEST is not set
+CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y
+CONFIG_BOOTLOADER_WDT_ENABLE=y
+# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set
+CONFIG_BOOTLOADER_WDT_TIME_MS=9000
+# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set
+# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set
+CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0
+# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set
+CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
+# end of Bootloader config
+
+#
+# Security features
+#
+CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_ECC_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_PREFERRED=y
+# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
+# CONFIG_SECURE_BOOT is not set
+# CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+CONFIG_SECURE_ROM_DL_MODE_ENABLED=y
+# end of Security features
+
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
+CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3
+CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
+CONFIG_ESP_ROM_GET_CLK_FREQ=y
+CONFIG_ESP_ROM_HAS_RVFPLIB=y
+CONFIG_ESP_ROM_HAS_HAL_WDT=y
+CONFIG_ESP_ROM_HAS_HAL_SYSTIMER=y
+CONFIG_ESP_ROM_HAS_HEAP_TLSF=y
+CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
+CONFIG_ESP_ROM_HAS_SPI_FLASH=y
+CONFIG_ESP_ROM_HAS_REGI2C_BUG=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT=y
+CONFIG_ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE=y
+CONFIG_ESP_ROM_WDT_INIT_PATCH=y
+CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
+CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
+
+#
+# Boot ROM Behavior
+#
+CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
+# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set
+# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set
+# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set
+# end of Boot ROM Behavior
+
+#
+# Serial flasher config
+#
+# CONFIG_ESPTOOLPY_NO_STUB is not set
+# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
+# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHMODE="dio"
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
+# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
+CONFIG_ESPTOOLPY_FLASHFREQ="80m"
+# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
+# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
+CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
+CONFIG_ESPTOOLPY_BEFORE_RESET=y
+# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
+CONFIG_ESPTOOLPY_BEFORE="default_reset"
+CONFIG_ESPTOOLPY_AFTER_RESET=y
+# CONFIG_ESPTOOLPY_AFTER_NORESET is not set
+CONFIG_ESPTOOLPY_AFTER="hard_reset"
+CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
+# end of Serial flasher config
+
+#
+# Partition Table
+#
+# CONFIG_PARTITION_TABLE_SINGLE_APP is not set
+# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set
+# CONFIG_PARTITION_TABLE_TWO_OTA is not set
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="ptables/esp32_4m-ptable.csv"
+CONFIG_PARTITION_TABLE_FILENAME="ptables/esp32_4m-ptable.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0x8000
+CONFIG_PARTITION_TABLE_MD5=y
+# end of Partition Table
+
+#
+# Compiler options
+#
+CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
+# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set
+# CONFIG_COMPILER_OPTIMIZATION_PERF is not set
+# CONFIG_COMPILER_OPTIMIZATION_NONE is not set
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
+# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
+# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+# CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_RVFPLIB=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
+# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
+CONFIG_COMPILER_HIDE_PATHS_MACROS=y
+# CONFIG_COMPILER_CXX_EXCEPTIONS is not set
+# CONFIG_COMPILER_CXX_RTTI is not set
+CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
+# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set
+# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
+# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
+# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
+# CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
+# CONFIG_COMPILER_DUMP_RTL_FILES is not set
+# end of Compiler options
+
+#
+# Component config
+#
+
+#
+# Application Level Tracing
+#
+# CONFIG_APPTRACE_DEST_JTAG is not set
+CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
+CONFIG_APPTRACE_LOCK_ENABLE=y
+# end of Application Level Tracing
+
+#
+# Bluetooth
+#
+# CONFIG_BT_ENABLED is not set
+# end of Bluetooth
+
+#
+# Driver Configurations
+#
+
+#
+# Legacy ADC Configuration
+#
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
+
+#
+# Legacy ADC Calibration Configuration
+#
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
+
+#
+# SPI Configuration
+#
+# CONFIG_SPI_MASTER_IN_IRAM is not set
+CONFIG_SPI_MASTER_ISR_IN_IRAM=y
+# CONFIG_SPI_SLAVE_IN_IRAM is not set
+CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
+# end of SPI Configuration
+
+#
+# TWAI Configuration
+#
+# CONFIG_TWAI_ISR_IN_IRAM is not set
+# end of TWAI Configuration
+
+#
+# Temperature sensor Configuration
+#
+# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
+# CONFIG_TEMP_SENSOR_ISR_IRAM_SAFE is not set
+# end of Temperature sensor Configuration
+
+#
+# UART Configuration
+#
+# CONFIG_UART_ISR_IN_IRAM is not set
+# end of UART Configuration
+
+#
+# GPIO Configuration
+#
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
+# end of GPIO Configuration
+
+#
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# PCNT Configuration
+#
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
+
+#
+# RMT Configuration
+#
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# MCPWM Configuration
+#
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
+
+#
+# I2S Configuration
+#
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# USB Serial/JTAG Configuration
+#
+# end of USB Serial/JTAG Configuration
+
+#
+# Parallel IO Configuration
+#
+# CONFIG_PARLIO_ENABLE_DEBUG_LOG is not set
+# CONFIG_PARLIO_ISR_IRAM_SAFE is not set
+# end of Parallel IO Configuration
+# end of Driver Configurations
+
+#
+# eFuse Bit Manager
+#
+# CONFIG_EFUSE_CUSTOM_TABLE is not set
+# CONFIG_EFUSE_VIRTUAL is not set
+CONFIG_EFUSE_MAX_BLK_LEN=256
+# end of eFuse Bit Manager
+
+#
+# ESP-TLS
+#
+CONFIG_ESP_TLS_USING_MBEDTLS=y
+# CONFIG_ESP_TLS_USE_DS_PERIPHERAL is not set
+# CONFIG_ESP_TLS_SERVER is not set
+# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
+# CONFIG_ESP_TLS_INSECURE is not set
+# end of ESP-TLS
+
+#
+# ADC and ADC Calibration
+#
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
+# end of ADC and ADC Calibration
+
+#
+# Wireless Coexistence
+#
+CONFIG_ESP_COEX_SW_COEXIST_ENABLE=y
+# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
+# end of Wireless Coexistence
+
+#
+# Common ESP-related
+#
+CONFIG_ESP_ERR_TO_NAME_LOOKUP=y
+# end of Common ESP-related
+
+#
+# Ethernet
+#
+# CONFIG_ETH_USE_SPI_ETHERNET is not set
+# CONFIG_ETH_USE_OPENETH is not set
+# end of Ethernet
+
+#
+# Event Loop Library
+#
+# CONFIG_ESP_EVENT_LOOP_PROFILING is not set
+CONFIG_ESP_EVENT_POST_FROM_ISR=y
+CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y
+# end of Event Loop Library
+
+#
+# GDB Stub
+#
+# end of GDB Stub
+
+#
+# ESP HTTP client
+#
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS is not set
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set
+# end of ESP HTTP client
+
+#
+# HTTP Server
+#
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=512
+CONFIG_HTTPD_MAX_URI_LEN=512
+CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
+CONFIG_HTTPD_PURGE_BUF_LEN=32
+# CONFIG_HTTPD_LOG_PURGE_DATA is not set
+# CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
+# end of HTTP Server
+
+#
+# ESP HTTPS OTA
+#
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set
+# end of ESP HTTPS OTA
+
+#
+# ESP HTTPS server
+#
+# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set
+# end of ESP HTTPS server
+
+#
+# Hardware Settings
+#
+
+#
+# Chip revision
+#
+CONFIG_ESP32C6_REV_MIN_0=y
+# CONFIG_ESP32C6_REV_MIN_1 is not set
+CONFIG_ESP32C6_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32-C6 Revision (Rev v0.99)
+#
+CONFIG_ESP32C6_REV_MAX_FULL=99
+CONFIG_ESP_REV_MAX_FULL=99
+# end of Chip revision
+
+#
+# MAC Config
+#
+CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_ADDR_UNIVERSE_IEEE802154=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
+# CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES_TWO is not set
+CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES_FOUR=y
+CONFIG_ESP32C6_UNIVERSAL_MAC_ADDRESSES=4
+# end of MAC Config
+
+#
+# Sleep Config
+#
+# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set
+CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y
+CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
+# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+# end of Sleep Config
+
+#
+# RTC Clock Config
+#
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_RC32K is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
+# end of RTC Clock Config
+
+#
+# Peripheral Control
+#
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# ETM Configuration
+#
+# CONFIG_ETM_ENABLE_DEBUG_LOG is not set
+# end of ETM Configuration
+
+#
+# GDMA Configuration
+#
+# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GDMA_ISR_IRAM_SAFE is not set
+# end of GDMA Configuration
+
+#
+# Main XTAL Config
+#
+CONFIG_XTAL_FREQ_40=y
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
+
+#
+# LCD and Touch Panel
+#
+
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
+#
+# LCD Peripheral Configuration
+#
+CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
+# end of LCD Peripheral Configuration
+# end of LCD and Touch Panel
+
+#
+# ESP NETIF Adapter
+#
+CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
+CONFIG_ESP_NETIF_TCPIP_LWIP=y
+# CONFIG_ESP_NETIF_LOOPBACK is not set
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
+# end of ESP NETIF Adapter
+
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
+#
+# PHY
+#
+CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
+# CONFIG_ESP_PHY_ENABLE_USB is not set
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
+# end of PHY
+
+#
+# Power Management
+#
+# CONFIG_PM_ENABLE is not set
+CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
+# CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is not set
+# end of Power Management
+
+#
+# ESP PSRAM
+#
+
+#
+# ESP Ringbuf
+#
+# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
+# end of ESP Ringbuf
+
+#
+# ESP System Settings
+#
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_120 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
+# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
+CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
+# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
+CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
+CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
+CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
+# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set
+
+#
+# Memory protection
+#
+CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT=y
+# end of Memory protection
+
+CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
+CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584
+CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
+# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
+CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
+CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048
+CONFIG_ESP_CONSOLE_UART_DEFAULT=y
+# CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is not set
+# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
+# CONFIG_ESP_CONSOLE_NONE is not set
+# CONFIG_ESP_CONSOLE_SECONDARY_NONE is not set
+CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG=y
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y
+CONFIG_ESP_CONSOLE_UART=y
+CONFIG_ESP_CONSOLE_UART_NUM=0
+CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
+CONFIG_ESP_INT_WDT=y
+CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
+# CONFIG_ESP_TASK_WDT_PANIC is not set
+CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+# CONFIG_ESP_PANIC_HANDLER_IRAM is not set
+# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
+CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=7
+# end of Brownout Detector
+
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
+# end of ESP System Settings
+
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
+# end of IPC (Inter-Processor Call)
+
+#
+# High resolution timer (esp_timer)
+#
+# CONFIG_ESP_TIMER_PROFILING is not set
+CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
+CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
+CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
+CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
+# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
+CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
+# end of High resolution timer (esp_timer)
+
+#
+# Wi-Fi
+#
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set
+CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=6
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
+# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
+# CONFIG_ESP_WIFI_FTM_ENABLE is not set
+CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE=y
+# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set
+# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
+CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
+# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
+CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+CONFIG_ESP_WIFI_ENABLE_WIFI_TX_STATS=y
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+CONFIG_ESP_WIFI_ENABLE_WIFI_RX_STATS=y
+CONFIG_ESP_WIFI_ENABLE_WIFI_RX_MU_STATS=y
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
+# end of Wi-Fi
+
+#
+# Core dump
+#
+# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set
+CONFIG_ESP_COREDUMP_ENABLE_TO_UART=y
+# CONFIG_ESP_COREDUMP_ENABLE_TO_NONE is not set
+CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN=y
+# CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF is not set
+CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
+CONFIG_ESP_COREDUMP_ENABLE=y
+CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64
+CONFIG_ESP_COREDUMP_UART_DELAY=0
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
+CONFIG_ESP_COREDUMP_DECODE_INFO=y
+# CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set
+CONFIG_ESP_COREDUMP_DECODE="info"
+# end of Core dump
+
+#
+# FAT Filesystem support
+#
+CONFIG_FATFS_VOLUME_COUNT=2
+CONFIG_FATFS_LFN_NONE=y
+# CONFIG_FATFS_LFN_HEAP is not set
+# CONFIG_FATFS_LFN_STACK is not set
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
+# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
+CONFIG_FATFS_CODEPAGE_437=y
+# CONFIG_FATFS_CODEPAGE_720 is not set
+# CONFIG_FATFS_CODEPAGE_737 is not set
+# CONFIG_FATFS_CODEPAGE_771 is not set
+# CONFIG_FATFS_CODEPAGE_775 is not set
+# CONFIG_FATFS_CODEPAGE_850 is not set
+# CONFIG_FATFS_CODEPAGE_852 is not set
+# CONFIG_FATFS_CODEPAGE_855 is not set
+# CONFIG_FATFS_CODEPAGE_857 is not set
+# CONFIG_FATFS_CODEPAGE_860 is not set
+# CONFIG_FATFS_CODEPAGE_861 is not set
+# CONFIG_FATFS_CODEPAGE_862 is not set
+# CONFIG_FATFS_CODEPAGE_863 is not set
+# CONFIG_FATFS_CODEPAGE_864 is not set
+# CONFIG_FATFS_CODEPAGE_865 is not set
+# CONFIG_FATFS_CODEPAGE_866 is not set
+# CONFIG_FATFS_CODEPAGE_869 is not set
+# CONFIG_FATFS_CODEPAGE_932 is not set
+# CONFIG_FATFS_CODEPAGE_936 is not set
+# CONFIG_FATFS_CODEPAGE_949 is not set
+# CONFIG_FATFS_CODEPAGE_950 is not set
+CONFIG_FATFS_CODEPAGE=437
+CONFIG_FATFS_FS_LOCK=0
+CONFIG_FATFS_TIMEOUT_MS=10000
+CONFIG_FATFS_PER_FILE_CACHE=y
+# CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
+# end of FAT Filesystem support
+
+#
+# FreeRTOS
+#
+
+#
+# Kernel
+#
+# CONFIG_FREERTOS_SMP is not set
+CONFIG_FREERTOS_UNICORE=y
+CONFIG_FREERTOS_HZ=100
+CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
+# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
+# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
+CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
+CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
+CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
+CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
+CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
+CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
+CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
+CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
+CONFIG_FREERTOS_USE_TRACE_FACILITY=y
+CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
+# CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is not set
+CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
+# end of Kernel
+
+#
+# Port
+#
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
+CONFIG_FREERTOS_ISR_STACKSIZE=1536
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
+CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
+# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
+CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
+CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
+# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
+# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
+# end of FreeRTOS
+
+#
+# Hardware Abstraction Layer (HAL) and Low Level (LL)
+#
+CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
+# CONFIG_HAL_ASSERTION_DISABLE is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
+# CONFIG_HAL_ASSERTION_ENABLE is not set
+CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y
+CONFIG_HAL_WDT_USE_ROM_IMPL=y
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
+# end of Hardware Abstraction Layer (HAL) and Low Level (LL)
+
+#
+# Heap memory debugging
+#
+CONFIG_HEAP_POISONING_DISABLED=y
+# CONFIG_HEAP_POISONING_LIGHT is not set
+# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set
+CONFIG_HEAP_TRACING_OFF=y
+# CONFIG_HEAP_TRACING_STANDALONE is not set
+# CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
+# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+CONFIG_HEAP_TLSF_USE_ROM_IMPL=y
+# end of Heap memory debugging
+
+#
+# IEEE 802.15.4
+#
+CONFIG_IEEE802154_ENABLED=y
+CONFIG_IEEE802154_RX_BUFFER_SIZE=20
+# CONFIG_IEEE802154_CCA_CARRIER is not set
+CONFIG_IEEE802154_CCA_ED=y
+# CONFIG_IEEE802154_CCA_CARRIER_OR_ED is not set
+# CONFIG_IEEE802154_CCA_CARRIER_AND_ED is not set
+CONFIG_IEEE802154_CCA_MODE=1
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
+# CONFIG_IEEE802154_MULTI_PAN_ENABLE is not set
+# CONFIG_IEEE802154_TIMING_OPTIMIZATION is not set
+# end of IEEE 802.15.4
+
+#
+# Log output
+#
+# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set
+# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set
+# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set
+CONFIG_LOG_DEFAULT_LEVEL_INFO=y
+# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set
+# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y
+# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set
+# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set
+CONFIG_LOG_MAXIMUM_LEVEL=3
+CONFIG_LOG_COLORS=y
+CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
+# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
+# end of Log output
+
+#
+# LWIP
+#
+CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
+# CONFIG_LWIP_NETIF_API is not set
+CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
+CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
+# CONFIG_LWIP_L2_TO_L3_COPY is not set
+CONFIG_LWIP_IRAM_OPTIMIZATION=y
+CONFIG_LWIP_TIMERS_ONDEMAND=y
+CONFIG_LWIP_MAX_SOCKETS=10
+# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set
+# CONFIG_LWIP_SO_LINGER is not set
+CONFIG_LWIP_SO_REUSE=y
+CONFIG_LWIP_SO_REUSE_RXTOALL=y
+# CONFIG_LWIP_SO_RCVBUF is not set
+# CONFIG_LWIP_NETBUF_RECVINFO is not set
+CONFIG_LWIP_IP4_FRAG=y
+# CONFIG_LWIP_IP4_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
+# CONFIG_LWIP_IP_FORWARD is not set
+# CONFIG_LWIP_STATS is not set
+CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
+CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
+CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
+# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
+CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
+# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
+CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
+
+#
+# DHCP server
+#
+CONFIG_LWIP_DHCPS=y
+CONFIG_LWIP_DHCPS_LEASE_UNIT=60
+CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
+# end of DHCP server
+
+# CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
+# CONFIG_LWIP_IPV6 is not set
+# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8
+
+#
+# TCP
+#
+CONFIG_LWIP_MAX_ACTIVE_TCP=16
+CONFIG_LWIP_MAX_LISTENING_TCP=16
+CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y
+CONFIG_LWIP_TCP_MAXRTX=12
+CONFIG_LWIP_TCP_SYNMAXRTX=12
+CONFIG_LWIP_TCP_MSS=1440
+CONFIG_LWIP_TCP_TMR_INTERVAL=250
+CONFIG_LWIP_TCP_MSL=60000
+CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000
+CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744
+CONFIG_LWIP_TCP_WND_DEFAULT=5744
+CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
+CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
+# CONFIG_LWIP_TCP_SACK_OUT is not set
+CONFIG_LWIP_TCP_OVERSIZE_MSS=y
+# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
+# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
+CONFIG_LWIP_TCP_RTO_TIME=1500
+# end of TCP
+
+#
+# UDP
+#
+CONFIG_LWIP_MAX_UDP_PCBS=16
+CONFIG_LWIP_UDP_RECVMBOX_SIZE=6
+# end of UDP
+
+#
+# Checksums
+#
+# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set
+# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set
+CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y
+# end of Checksums
+
+CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
+CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
+# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set
+CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF
+# CONFIG_LWIP_PPP_SUPPORT is not set
+# CONFIG_LWIP_SLIP_SUPPORT is not set
+
+#
+# ICMP
+#
+CONFIG_LWIP_ICMP=y
+# CONFIG_LWIP_MULTICAST_PING is not set
+# CONFIG_LWIP_BROADCAST_PING is not set
+# end of ICMP
+
+#
+# LWIP RAW API
+#
+CONFIG_LWIP_MAX_RAW_PCBS=16
+# end of LWIP RAW API
+
+#
+# SNTP
+#
+CONFIG_LWIP_SNTP_MAX_SERVERS=1
+# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set
+CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
+# end of SNTP
+
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
+CONFIG_LWIP_ESP_LWIP_ASSERT=y
+
+#
+# Hooks
+#
+# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set
+CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y
+# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set
+CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
+# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
+# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+# end of Hooks
+
+# CONFIG_LWIP_DEBUG is not set
+# end of LWIP
+
+#
+# mbedTLS
+#
+CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y
+# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set
+# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set
+CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y
+CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384
+CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
+# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set
+# CONFIG_MBEDTLS_DEBUG is not set
+
+#
+# mbedTLS v3.x related
+#
+# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
+# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
+# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
+# CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE is not set
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
+
+#
+# Certificate Bundle
+#
+# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set
+# end of Certificate Bundle
+
+# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set
+# CONFIG_MBEDTLS_CMAC_C is not set
+CONFIG_MBEDTLS_HARDWARE_AES=y
+CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
+CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
+CONFIG_MBEDTLS_HARDWARE_SHA=y
+CONFIG_MBEDTLS_HARDWARE_ECC=y
+# CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK is not set
+CONFIG_MBEDTLS_ROM_MD5=y
+# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
+# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
+CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
+# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
+CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
+# CONFIG_MBEDTLS_SHA512_C is not set
+CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
+# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set
+# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set
+# CONFIG_MBEDTLS_TLS_DISABLED is not set
+CONFIG_MBEDTLS_TLS_SERVER=y
+CONFIG_MBEDTLS_TLS_CLIENT=y
+CONFIG_MBEDTLS_TLS_ENABLED=y
+
+#
+# TLS Key Exchange Methods
+#
+# CONFIG_MBEDTLS_PSK_MODES is not set
+CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
+# end of TLS Key Exchange Methods
+
+# CONFIG_MBEDTLS_SSL_RENEGOTIATION is not set
+CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
+# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
+# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
+# CONFIG_MBEDTLS_SSL_ALPN is not set
+# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set
+# CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS is not set
+
+#
+# Symmetric Ciphers
+#
+CONFIG_MBEDTLS_AES_C=y
+# CONFIG_MBEDTLS_CAMELLIA_C is not set
+# CONFIG_MBEDTLS_DES_C is not set
+# CONFIG_MBEDTLS_BLOWFISH_C is not set
+# CONFIG_MBEDTLS_XTEA_C is not set
+CONFIG_MBEDTLS_CCM_C=y
+CONFIG_MBEDTLS_GCM_C=y
+# CONFIG_MBEDTLS_NIST_KW_C is not set
+# end of Symmetric Ciphers
+
+# CONFIG_MBEDTLS_RIPEMD160_C is not set
+
+#
+# Certificates
+#
+CONFIG_MBEDTLS_PEM_PARSE_C=y
+CONFIG_MBEDTLS_PEM_WRITE_C=y
+CONFIG_MBEDTLS_X509_CRL_PARSE_C=y
+CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
+# end of Certificates
+
+CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
+CONFIG_MBEDTLS_ECDH_C=y
+CONFIG_MBEDTLS_ECDSA_C=y
+CONFIG_MBEDTLS_ECJPAKE_C=y
+CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
+# CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED is not set
+CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
+# CONFIG_MBEDTLS_POLY1305_C is not set
+# CONFIG_MBEDTLS_CHACHA20_C is not set
+# CONFIG_MBEDTLS_HKDF_C is not set
+# CONFIG_MBEDTLS_THREADING_C is not set
+CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y
+# CONFIG_MBEDTLS_SECURITY_RISKS is not set
+# end of mbedTLS
+
+#
+# ESP-MQTT Configurations
+#
+# CONFIG_MQTT_PROTOCOL_311 is not set
+# CONFIG_MQTT_PROTOCOL_5 is not set
+# CONFIG_MQTT_TRANSPORT_SSL is not set
+# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set
+# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set
+# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set
+# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set
+# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set
+# CONFIG_MQTT_CUSTOM_OUTBOX is not set
+# end of ESP-MQTT Configurations
+
+#
+# Newlib
+#
+CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
+# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set
+# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set
+# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set
+# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
+CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
+# CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
+# end of Newlib
+
+#
+# NVS
+#
+# CONFIG_NVS_ASSERT_ERROR_CHECK is not set
+# end of NVS
+
+#
+# OpenThread
+#
+# CONFIG_OPENTHREAD_ENABLED is not set
+# end of OpenThread
+
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+# CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 is not set
+# CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2 is not set
+# end of Protocomm
+
+#
+# PThreads
+#
+CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5
+CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
+CONFIG_PTHREAD_STACK_MIN=768
+CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
+CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
+# end of PThreads
+
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
+#
+# SPI Flash driver
+#
+# CONFIG_SPI_FLASH_VERIFY_WRITE is not set
+# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set
+CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
+# CONFIG_SPI_FLASH_ROM_IMPL is not set
+CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
+# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
+# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
+# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
+CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
+CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
+CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1
+CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
+# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set
+# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
+# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
+
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
+#
+# Auto-detect flash chips
+#
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+# CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_GD_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP is not set
+# CONFIG_SPI_FLASH_SUPPORT_TH_CHIP is not set
+# end of Auto-detect flash chips
+
+CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y
+# end of SPI Flash driver
+
+#
+# SPIFFS Configuration
+#
+CONFIG_SPIFFS_MAX_PARTITIONS=3
+
+#
+# SPIFFS Cache Configuration
+#
+CONFIG_SPIFFS_CACHE=y
+CONFIG_SPIFFS_CACHE_WR=y
+# CONFIG_SPIFFS_CACHE_STATS is not set
+# end of SPIFFS Cache Configuration
+
+CONFIG_SPIFFS_PAGE_CHECK=y
+CONFIG_SPIFFS_GC_MAX_RUNS=10
+# CONFIG_SPIFFS_GC_STATS is not set
+CONFIG_SPIFFS_PAGE_SIZE=256
+CONFIG_SPIFFS_OBJ_NAME_LEN=32
+# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set
+CONFIG_SPIFFS_USE_MAGIC=y
+CONFIG_SPIFFS_USE_MAGIC_LENGTH=y
+CONFIG_SPIFFS_META_LENGTH=4
+CONFIG_SPIFFS_USE_MTIME=y
+
+#
+# Debug Configuration
+#
+# CONFIG_SPIFFS_DBG is not set
+# CONFIG_SPIFFS_API_DBG is not set
+# CONFIG_SPIFFS_GC_DBG is not set
+# CONFIG_SPIFFS_CACHE_DBG is not set
+# CONFIG_SPIFFS_CHECK_DBG is not set
+# CONFIG_SPIFFS_TEST_VISUALISATION is not set
+# end of Debug Configuration
+# end of SPIFFS Configuration
+
+#
+# TCP Transport
+#
+
+#
+# Websocket
+#
+# CONFIG_WS_TRANSPORT is not set
+# end of Websocket
+# end of TCP Transport
+
+#
+# Ultra Low Power (ULP) Co-processor
+#
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
+
+#
+# Unity unit testing library
+#
+CONFIG_UNITY_ENABLE_FLOAT=y
+CONFIG_UNITY_ENABLE_DOUBLE=y
+# CONFIG_UNITY_ENABLE_64BIT is not set
+# CONFIG_UNITY_ENABLE_COLOR is not set
+CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
+# CONFIG_UNITY_ENABLE_FIXTURE is not set
+# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
+# end of Unity unit testing library
+
+#
+# Root Hub configuration
+#
+# end of Root Hub configuration
+
+#
+# Virtual file system
+#
+CONFIG_VFS_SUPPORT_IO=y
+CONFIG_VFS_SUPPORT_DIR=y
+# CONFIG_VFS_SUPPORT_SELECT is not set
+# CONFIG_VFS_SUPPORT_TERMIOS is not set
+
+#
+# Host File System I/O (Semihosting)
+#
+CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1
+# end of Host File System I/O (Semihosting)
+# end of Virtual file system
+
+#
+# Wear Levelling
+#
+# CONFIG_WL_SECTOR_SIZE_512 is not set
+CONFIG_WL_SECTOR_SIZE_4096=y
+CONFIG_WL_SECTOR_SIZE=4096
+# end of Wear Levelling
+
+#
+# Wi-Fi Provisioning Manager
+#
+CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
+CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
+# CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION is not set
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
+# end of Wi-Fi Provisioning Manager
+
+#
+# Atrium
+#
+CONFIG_WFC_TARGET="esp32"
+
+#
+# software services
+#
+CONFIG_CONSOLE_UART_TX=-1
+CONFIG_CONSOLE_UART_RX=-1
+CONFIG_UART_CONSOLE=y
+CONFIG_HWCONF_DYNAMIC=y
+CONFIG_LUA=y
+CONFIG_THRESHOLDS=y
+CONFIG_INTEGRATED_HELP=y
+CONFIG_AT_ACTIONS=y
+CONFIG_HOLIDAYS=y
+CONFIG_TERMSERV=y
+CONFIG_STATEMACHINES=y
+# CONFIG_APP_PARAMS is not set
+# end of software services
+
+#
+# networking services
+#
+CONFIG_OTA=y
+CONFIG_UDNS=y
+CONFIG_MQTT=y
+CONFIG_HTTP=y
+# CONFIG_FTP is not set
+CONFIG_TELNET=y
+CONFIG_SYSLOG=y
+CONFIG_INFLUX=y
+CONFIG_UDPCTRL=y
+CONFIG_WPS=y
+# CONFIG_SMARTCONFIG is not set
+# end of networking services
+
+#
+# filesystem support
+#
+CONFIG_FATFS=y
+CONFIG_ROMFS=y
+CONFIG_ROMFS_VFS=y
+CONFIG_ROMFS_VFS_NUMFDS=4
+CONFIG_USB_HOST_FS=y
+# end of filesystem support
+
+#
+# hardware support
+#
+CONFIG_USB_CONSOLE=y
+CONFIG_GPIOS=y
+CONFIG_IOEXTENDERS=y
+CONFIG_LEDS=y
+CONFIG_BUTTON=y
+CONFIG_ROTARYENCODER=y
+CONFIG_RELAY=y
+CONFIG_ONEWIRE=y
+CONFIG_DISPLAY=y
+CONFIG_MAX7219=y
+CONFIG_HT16K33=y
+CONFIG_SSD1306=y
+# CONFIG_DHT is not set
+CONFIG_I2C=y
+CONFIG_I2C_XCMD=y
+CONFIG_I2C_XDEV=y
+CONFIG_PCA9685=y
+CONFIG_PCF8574=y
+CONFIG_TCA9555=y
+CONFIG_MCP2300X=y
+CONFIG_MCP2301X=y
+CONFIG_INA2XX=y
+CONFIG_SI7021=y
+CONFIG_BMX280=y
+# CONFIG_BME680 is not set
+CONFIG_HDC1000=y
+CONFIG_APDS9930=y
+CONFIG_SGP30=y
+CONFIG_CCS811B=y
+CONFIG_BH1750=y
+CONFIG_SPI=y
+CONFIG_SSD1309=y
+# CONFIG_ILI9341 is not set
+CONFIG_SDCARD=y
+CONFIG_XPT2046=y
+CONFIG_HCSR04=y
+CONFIG_DIMMER=y
+CONFIG_RGBLEDS=y
+CONFIG_TLC5947=y
+# end of hardware support
+
+#
+# development tools and experimental/alpha drivers (disable all)
+#
+# CONFIG_DEVEL is not set
+# CONFIG_VERIFY_HEAP is not set
+# CONFIG_FUNCTION_TIMING is not set
+# end of development tools and experimental/alpha drivers (disable all)
+# end of Atrium
+# end of Component config
+
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
+
+# Deprecated options for backward compatibility
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
+CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y
+# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set
+# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set
+CONFIG_LOG_BOOTLOADER_LEVEL=3
+# CONFIG_APP_ROLLBACK_ENABLE is not set
+# CONFIG_FLASH_ENCRYPTION_ENABLED is not set
+# CONFIG_FLASHMODE_QIO is not set
+# CONFIG_FLASHMODE_QOUT is not set
+CONFIG_FLASHMODE_DIO=y
+# CONFIG_FLASHMODE_DOUT is not set
+CONFIG_MONITOR_BAUD=115200
+CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
+CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
+# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
+# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
+CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
+# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
+# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set
+CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2
+# CONFIG_CXX_EXCEPTIONS is not set
+CONFIG_STACK_CHECK_NONE=y
+# CONFIG_STACK_CHECK_NORM is not set
+# CONFIG_STACK_CHECK_STRONG is not set
+# CONFIG_STACK_CHECK_ALL is not set
+# CONFIG_WARN_WRITE_STRINGS is not set
+# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
+CONFIG_ESP32_APPTRACE_DEST_NONE=y
+CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
+CONFIG_SW_COEXIST_ENABLE=y
+CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y
+CONFIG_ESP_WIFI_SW_COEXIST_ENABLE=y
+# CONFIG_EXTERNAL_COEX_ENABLE is not set
+# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
+# CONFIG_EVENT_LOOP_PROFILING is not set
+CONFIG_POST_EVENTS_FROM_ISR=y
+CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+# CONFIG_OTA_ALLOW_HTTP is not set
+# CONFIG_ESP_SYSTEM_PD_FLASH is not set
+CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
+CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
+CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
+CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
+CONFIG_MAIN_TASK_STACK_SIZE=3584
+CONFIG_CONSOLE_UART_DEFAULT=y
+# CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
+# CONFIG_ESP_CONSOLE_UART_NONE is not set
+CONFIG_CONSOLE_UART=y
+CONFIG_CONSOLE_UART_NUM=0
+CONFIG_CONSOLE_UART_BAUDRATE=115200
+CONFIG_INT_WDT=y
+CONFIG_INT_WDT_TIMEOUT_MS=300
+CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
+# CONFIG_TASK_WDT_PANIC is not set
+CONFIG_TASK_WDT_TIMEOUT_S=5
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+CONFIG_BROWNOUT_DET_LVL=7
+CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_TIMER_TASK_STACK_SIZE=3584
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1
+CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
+# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
+CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y
+# CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
+CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN=y
+# CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF is not set
+CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
+CONFIG_ESP32_ENABLE_COREDUMP=y
+CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64
+CONFIG_ESP32_CORE_DUMP_UART_DELAY=0
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
+CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y
+# CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set
+CONFIG_ESP32_CORE_DUMP_DECODE="info"
+CONFIG_TIMER_TASK_PRIORITY=1
+CONFIG_TIMER_TASK_STACK_DEPTH=2048
+CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_L2_TO_L3_COPY is not set
+CONFIG_ESP_GRATUITOUS_ARP=y
+CONFIG_GARP_TMR_INTERVAL=60
+CONFIG_TCPIP_RECVMBOX_SIZE=32
+CONFIG_TCP_MAXRTX=12
+CONFIG_TCP_SYNMAXRTX=12
+CONFIG_TCP_MSS=1440
+CONFIG_TCP_MSL=60000
+CONFIG_TCP_SND_BUF_DEFAULT=5744
+CONFIG_TCP_WND_DEFAULT=5744
+CONFIG_TCP_RECVMBOX_SIZE=6
+CONFIG_TCP_QUEUE_OOSEQ=y
+CONFIG_TCP_OVERSIZE_MSS=y
+# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
+# CONFIG_TCP_OVERSIZE_DISABLE is not set
+CONFIG_UDP_RECVMBOX_SIZE=6
+CONFIG_TCPIP_TASK_STACK_SIZE=3072
+CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
+# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
+CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
+# CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
+CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
+CONFIG_ESP32_PTHREAD_STACK_MIN=768
+CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
+CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
+# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
+# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
+# CONFIG_SUPPORT_TERMIOS is not set
+CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
+# End of deprecated options
diff --git a/projects/esp32-s2_4m b/projects/esp32-s2_4m
index f909cba..4fdae91 100644
--- a/projects/esp32-s2_4m
+++ b/projects/esp32-s2_4m
@@ -1,40 +1,291 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DAC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_CP_DMA_SUPPORTED=y
+CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_RISCV_COPROC_SUPPORTED=y
+CONFIG_SOC_USB_OTG_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
+CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
+CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
+CONFIG_SOC_CACHE_SUPPORT_WRAP=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_PSRAM_DMA_CAPABLE=y
+CONFIG_SOC_XT_WDT_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_SUPPORTED=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_HMAC_SUPPORTED=y
+CONFIG_SOC_DIG_SIGN_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_MEMPROT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED=y
+CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=32
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=2
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=13
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=13
+CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
+CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
+CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y
+CONFIG_SOC_CP_DMA_MAX_BUFFER_SIZE=4095
+CONFIG_SOC_CPU_CORES_NUM=1
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DAC_CHAN_NUM=2
+CONFIG_SOC_DAC_RESOLUTION=8
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=47
+CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
+CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
+CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y
+CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x7FFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00007FFFFC000000
+CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_ALLOW_REG_ACCESS=y
+CONFIG_SOC_DEDIC_GPIO_HAS_INTERRUPT=y
+CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
+CONFIG_SOC_I2C_SUPPORT_REF_TICK=y
+CONFIG_SOC_I2C_SUPPORT_APB=y
+CONFIG_SOC_I2S_NUM=1
+CONFIG_SOC_I2S_HW_VERSION_1=y
+CONFIG_SOC_I2S_SUPPORTS_APLL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_DMA_EQUAL=y
+CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA=y
+CONFIG_SOC_I2S_APLL_MIN_FREQ=250000000
+CONFIG_SOC_I2S_APLL_MAX_FREQ=500000000
+CONFIG_SOC_I2S_APLL_MIN_RATE=10675
+CONFIG_SOC_I2S_LCD_I80_VARIANT=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=1
+CONFIG_SOC_LCD_I80_BUS_WIDTH=24
+CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_REF_TICK=y
+CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
+CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=5
+CONFIG_SOC_MMU_PERIPH_NUM=1
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=4
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=64
+CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
+CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
+CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
+CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
+CONFIG_SOC_RMT_SUPPORT_REF_TICK=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT=y
+CONFIG_SOC_RTCIO_PIN_COUNT=22
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_DMA_CHAN_NUM=3
+CONFIG_SOC_SPI_MAX_CS_NUM=6
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=72
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=8192
+CONFIG_SOC_SPI_SUPPORT_DDRCLK=y
+CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
+CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
+CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
+CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
+CONFIG_SOC_SPI_SUPPORT_OCT=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_COUNTER_NUM=y
+CONFIG_SOC_SYSTIMER_ALARM_NUM=3
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=32
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=64
+CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TOUCH_VERSION_2=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=15
+CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3
+CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_BRP_MAX=32768
+CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
+CONFIG_SOC_UART_NUM=2
+CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_REF_TICK=y
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y
+CONFIG_SOC_USB_PERIPH_NUM=y
+CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
+CONFIG_SOC_SHA_SUPPORT_DMA=y
+CONFIG_SOC_SHA_SUPPORT_RESUME=y
+CONFIG_SOC_SHA_CRYPTO_DMA=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA224=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_224=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_256=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_T=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_DMA=y
+CONFIG_SOC_AES_SUPPORT_GCM=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y
+CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y
+CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_BOOT_REMAP=y
+CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT=y
+CONFIG_SOC_EFUSE_DIS_ICACHE=y
+CONFIG_SOC_SECURE_BOOT_V2_RSA=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
+CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y
+CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
+CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=4
+CONFIG_SOC_AES_CRYPTO_DMA=y
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_192=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_WIFI_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_CLK_APLL_SUPPORTED=y
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MIN_HZ=350000000
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MAX_HZ=500000000
+CONFIG_SOC_APLL_MIN_HZ=5303031
+CONFIG_SOC_APLL_MAX_HZ=125000000
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_COEX_HW_PTI=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
+CONFIG_SOC_WIFI_HW_TSF=y
+CONFIG_SOC_WIFI_FTM_SUPPORT=y
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_WIFI_NAN_SUPPORT=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32s2"
 CONFIG_IDF_TARGET_ESP32S2=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0002
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32s2-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -69,13 +320,31 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
-CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
-CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
+CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_PREFERRED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+CONFIG_SECURE_ROM_DL_MODE_ENABLED=y
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_UART_BUF_SWITCH=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_REGI2C_BUG=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+
 #
 # Boot ROM Behavior
 #
@@ -88,7 +357,6 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
@@ -100,6 +368,7 @@ CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
 # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
 CONFIG_ESPTOOLPY_FLASHFREQ="80m"
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
@@ -110,22 +379,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -152,6 +412,7 @@ CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -162,7 +423,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -175,69 +436,115 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
 #
-# ESP-ASIO
+# Driver Configurations
 #
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
 
 #
-# CoAP Configuration
-#
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
-
+# Legacy ADC Configuration
 #
-# Driver configurations
-#
-
-#
-# ADC configuration
-#
-# CONFIG_ADC_FORCE_XPD_FSM is not set
 CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# MCPWM configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
 
 #
-# UART configuration
+# Temperature sensor Configuration
+#
+# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
+# end of Temperature sensor Configuration
+
+#
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
+# end of UART Configuration
+
+#
+# GPIO Configuration
+#
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
+# end of GPIO Configuration
+
+#
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# PCNT Configuration
+#
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
 
 #
-# GDMA Configuration
+# RMT Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# I2S Configuration
+#
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# DAC Configuration
+#
+# CONFIG_DAC_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_DAC_ISR_IRAM_SAFE is not set
+# CONFIG_DAC_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_DAC_ENABLE_DEBUG_LOG is not set
+# end of DAC Configuration
+# end of Driver Configurations
 
 #
 # eFuse Bit Manager
@@ -259,63 +566,18 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
 # end of ESP-TLS
 
 #
-# ESP32S2-specific
+# ADC and ADC Calibration
 #
-# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set
-CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160=y
-# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 is not set
-CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=160
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
+CONFIG_ADC_DISABLE_DAC_OUTPUT=y
+# end of ADC and ADC Calibration
 
 #
-# Cache config
+# Wireless Coexistence
 #
-CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y
-# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set
-# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set
-CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y
-# CONFIG_ESP32S2_DATA_CACHE_0KB is not set
-CONFIG_ESP32S2_DATA_CACHE_8KB=y
-# CONFIG_ESP32S2_DATA_CACHE_16KB is not set
-# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set
-CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y
-# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set
-# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set
-# end of Cache config
-
-# CONFIG_ESP32S2_SPIRAM_SUPPORT is not set
-# CONFIG_ESP32S2_TRAX is not set
-CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0
-CONFIG_ESP32S2_DEBUG_OCDAWARE=y
-CONFIG_ESP32S2_BROWNOUT_DET=y
-CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set
-CONFIG_ESP32S2_BROWNOUT_DET_LVL=7
-CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576
-# CONFIG_ESP32S2_NO_BLOBS is not set
-CONFIG_ESP32S2_KEEP_USB_ALIVE=y
-# CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set
-# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set
-# end of ESP32S2-specific
-
-#
-# ADC-Calibration
-#
-# end of ADC-Calibration
+# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -332,6 +594,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -364,12 +627,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-# CONFIG_OTA_ALLOW_HTTP is not set
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set
 # end of ESP HTTPS OTA
 
 #
@@ -382,11 +647,27 @@ CONFIG_HTTPD_PURGE_BUF_LEN=32
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+CONFIG_ESP32S2_REV_MIN_0=y
+# CONFIG_ESP32S2_REV_MIN_1 is not set
+CONFIG_ESP32S2_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32-S2 Revision (Rev v1.99)
+#
+CONFIG_ESP32S2_REV_MAX_FULL=199
+CONFIG_ESP_REV_MAX_FULL=199
+# end of Chip revision
+
 #
 # MAC Config
 #
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO=y
 # CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set
 CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y
 CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2
@@ -405,23 +686,40 @@ CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 #
 # RTC Clock Config
 #
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=576
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=2048
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# Main XTAL Config
+#
+CONFIG_XTAL_FREQ_40=y
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -431,9 +729,16 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
 #
 # PHY
 #
@@ -441,7 +746,12 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
 # CONFIG_ESP_PHY_ENABLE_USB is not set
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
 # end of PHY
 
 #
@@ -450,21 +760,62 @@ CONFIG_ESP_PHY_MAX_TX_POWER=20
 # CONFIG_PM_ENABLE is not set
 # end of Power Management
 
+#
+# ESP PSRAM
+#
+# CONFIG_SPIRAM is not set
+# end of ESP PSRAM
+
 #
 # ESP Ringbuf
 #
 # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
 # end of ESP Ringbuf
 
 #
 # ESP System Settings
 #
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
+
+#
+# Cache config
+#
+CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y
+# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set
+# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set
+CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y
+# CONFIG_ESP32S2_DATA_CACHE_0KB is not set
+CONFIG_ESP32S2_DATA_CACHE_8KB=y
+# CONFIG_ESP32S2_DATA_CACHE_16KB is not set
+# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set
+CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y
+# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set
+# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set
+# end of Cache config
+
+#
+# Memory
+#
+# CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set
+# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set
+# end of Memory
+
+#
+# Trace memory
+#
+# CONFIG_ESP32S2_TRAX is not set
+CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
 CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
 CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
@@ -472,11 +823,8 @@ CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
 #
 # Memory protection
 #
-CONFIG_ESP_SYSTEM_MEMPROT_DEPCHECK=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
-CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
-CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE=4
 # end of Memory protection
 
 CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
@@ -496,15 +844,40 @@ CONFIG_ESP_CONSOLE_UART_NUM=0
 CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 # CONFIG_ESP_TASK_WDT_PANIC is not set
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=7
+# end of Brownout Detector
+
+CONFIG_ESP32S2_KEEP_USB_ALIVE=y
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=2048
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -513,6 +886,11 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
 CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 # end of High resolution timer (esp_timer)
@@ -520,32 +898,54 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-CONFIG_ESP32_WIFI_CSI_ENABLED=y
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=6
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-# CONFIG_ESP32_WIFI_IRAM_OPT is not set
-# CONFIG_ESP32_WIFI_RX_IRAM_OPT is not set
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP_WIFI_CSI_ENABLED=y
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=6
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+# CONFIG_ESP_WIFI_IRAM_OPT is not set
+# CONFIG_ESP_WIFI_RX_IRAM_OPT is not set
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_FTM_ENABLE is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
-# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+# CONFIG_ESP_WIFI_NAN_ENABLE is not set
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -560,6 +960,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64
 CONFIG_ESP_COREDUMP_UART_DELAY=0
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 CONFIG_ESP_COREDUMP_DECODE_INFO=y
 # CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set
 CONFIG_ESP_COREDUMP_DECODE="info"
@@ -568,6 +969,12 @@ CONFIG_ESP_COREDUMP_DECODE="info"
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+CONFIG_FATFS_LFN_NONE=y
+# CONFIG_FATFS_LFN_HEAP is not set
+# CONFIG_FATFS_LFN_STACK is not set
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -591,85 +998,67 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-CONFIG_FATFS_LFN_NONE=y
-# CONFIG_FATFS_LFN_HEAP is not set
-# CONFIG_FATFS_LFN_STACK is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=4096
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-CONFIG_FMB_PORT_TASK_AFFINITY=0x7FFFFFFF
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_FMB_TIMER_PORT_ENABLED is not set
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 CONFIG_FREERTOS_UNICORE=y
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
-CONFIG_FREERTOS_CORETIMER_0=y
-# CONFIG_FREERTOS_CORETIMER_1 is not set
-CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
-CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 CONFIG_FREERTOS_HZ=100
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
+CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
 # CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is not set
 # CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set
+# end of Kernel
+
+#
+# Port
+#
 CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
 CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
+CONFIG_FREERTOS_CORETIMER_0=y
+# CONFIG_FREERTOS_CORETIMER_1 is not set
+CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -677,9 +1066,11 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -691,20 +1082,13 @@ CONFIG_HEAP_POISONING_DISABLED=y
 CONFIG_HEAP_TRACING_OFF=y
 # CONFIG_HEAP_TRACING_STANDALONE is not set
 # CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -731,6 +1115,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 CONFIG_LWIP_IRAM_OPTIMIZATION=y
@@ -746,17 +1131,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 # CONFIG_LWIP_IP4_REASSEMBLY is not set
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -767,6 +1156,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 CONFIG_LWIP_IPV6_AUTOCONFIG=y
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -794,7 +1184,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -847,6 +1236,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -864,6 +1254,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -882,13 +1275,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -907,11 +1302,13 @@ CONFIG_MBEDTLS_HARDWARE_AES=y
 CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_GCM=y
 CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_SHA=y
 CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -928,7 +1325,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -937,16 +1333,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -955,9 +1346,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -977,6 +1365,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -1001,26 +1390,11 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1042,6 +1416,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1050,21 +1428,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set
-CONFIG_OPENSSL_ASSERT_EXIT=y
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1075,6 +1452,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1084,7 +1469,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
 CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
@@ -1094,9 +1478,23 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1153,46 +1551,15 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
 #
-# TinyUSB Stack
-#
-CONFIG_TINYUSB=y
-CONFIG_TINYUSB_DEBUG_LEVEL=2
-
-#
-# TinyUSB task configuration
-#
-# CONFIG_TINYUSB_NO_DEFAULT_TASK is not set
-CONFIG_TINYUSB_TASK_PRIORITY=5
-CONFIG_TINYUSB_TASK_STACK_SIZE=4096
-# end of TinyUSB task configuration
-
-#
-# Descriptor configuration
-#
-CONFIG_TINYUSB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_TINYUSB_DESC_USE_DEFAULT_PID=y
-CONFIG_TINYUSB_DESC_BCD_DEVICE=0x0100
-CONFIG_TINYUSB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_TINYUSB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_TINYUSB_DESC_SERIAL_STRING="123456"
-# end of Descriptor configuration
-
-#
-# Massive Storage Class (MSC)
-#
-# CONFIG_TINYUSB_MSC_ENABLED is not set
-# end of Massive Storage Class (MSC)
-
-#
-# Communication Device Class (CDC)
+# Ultra Low Power (ULP) Co-processor
 #
-# CONFIG_TINYUSB_CDC_ENABLED is not set
-# end of Communication Device Class (CDC)
-# end of TinyUSB Stack
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
 
 #
 # Unity unit testing library
@@ -1214,6 +1581,15 @@ CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256
 CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set
+
+#
+# Root Hub configuration
+#
+CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250
+CONFIG_USB_HOST_RESET_HOLD_MS=30
+CONFIG_USB_HOST_RESET_RECOVERY_MS=30
+CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10
+# end of Root Hub configuration
 # end of USB-OTG
 
 #
@@ -1246,22 +1622,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1314,6 +1678,7 @@ CONFIG_USB_HOST_FS=y
 # hardware support
 #
 CONFIG_GPIOS=y
+# CONFIG_CORETEMP is not set
 CONFIG_IOEXTENDERS=y
 CONFIG_LEDS=y
 CONFIG_BUTTON=y
@@ -1334,6 +1699,7 @@ CONFIG_PCF8574=y
 CONFIG_TCA9555=y
 CONFIG_MCP2300X=y
 CONFIG_MCP2301X=y
+# CONFIG_OPT3001 is not set
 CONFIG_INA2XX=y
 CONFIG_SI7021=y
 CONFIG_BMX280=y
@@ -1346,6 +1712,7 @@ CONFIG_BH1750=y
 CONFIG_SPI=y
 # CONFIG_SX1276 is not set
 CONFIG_SSD1309=y
+# CONFIG_SDCARD is not set
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1363,14 +1730,12 @@ CONFIG_DEVEL=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32s2-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
+# CONFIG_ESP32S2_NO_BLOBS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1384,16 +1749,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=5
 # CONFIG_FLASHMODE_QOUT is not set
 CONFIG_FLASHMODE_DIO=y
 # CONFIG_FLASHMODE_DOUT is not set
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
+# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1405,33 +1764,46 @@ CONFIG_STACK_CHECK_NONE=y
 # CONFIG_STACK_CHECK_STRONG is not set
 # CONFIG_STACK_CHECK_ALL is not set
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
 CONFIG_ADC2_DISABLE_DAC=y
+# CONFIG_EXTERNAL_COEX_ENABLE is not set
+# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+# CONFIG_OTA_ALLOW_HTTP is not set
 # CONFIG_ESP_SYSTEM_PD_FLASH is not set
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=2048
+CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y
+# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32S2_SPIRAM_SUPPORT is not set
+# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_80 is not set
+CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160=y
+# CONFIG_ESP32S2_DEFAULT_CPU_FREQ_240 is not set
+CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ=160
 # CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
 CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP32S2_PANIC_GDBSTUB is not set
 CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
-CONFIG_ESP32H2_MEMPROT_FEATURE=y
-CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK=y
+CONFIG_ESP32S2_MEMPROT_FEATURE=y
+CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK=y
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 CONFIG_CONSOLE_UART_DEFAULT=y
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART=y
 CONFIG_CONSOLE_UART_NUM=0
@@ -1439,12 +1811,66 @@ CONFIG_CONSOLE_UART_BAUDRATE=115200
 CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 # CONFIG_TASK_WDT_PANIC is not set
 CONFIG_TASK_WDT_TIMEOUT_S=5
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP32S2_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32S2_BROWNOUT_DET=y
+CONFIG_ESP32S2_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_7=y
+CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_BROWNOUT_DET_LVL=7
+CONFIG_ESP32S2_BROWNOUT_DET_LVL=7
+CONFIG_IPC_TASK_STACK_SIZE=2048
 CONFIG_TIMER_TASK_STACK_SIZE=3584
-# CONFIG_EXTERNAL_COEX_ENABLE is not set
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP32_WIFI_CSI_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+# CONFIG_ESP32_WIFI_IRAM_OPT is not set
+# CONFIG_ESP32_WIFI_RX_IRAM_OPT is not set
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1454,28 +1880,16 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64
 CONFIG_ESP32_CORE_DUMP_UART_DELAY=0
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y
 # CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set
 CONFIG_ESP32_CORE_DUMP_DECODE="info"
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_MB_TIMER_PORT_ENABLED is not set
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1487,7 +1901,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1497,6 +1910,12 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_SYSTIMER=y
+CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32S2_TIME_SYSCALL_USE_SYSTIMER is not set
+# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
@@ -1505,18 +1924,7 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
-CONFIG_USB_ENABLED=y
-CONFIG_USB_DEBUG_LEVEL=2
-# CONFIG_USB_DO_NOT_CREATE_TASK is not set
-CONFIG_USB_TASK_PRIORITY=5
-CONFIG_USB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_USB_DESC_USE_DEFAULT_PID=y
-CONFIG_USB_DESC_BCDDEVICE=0x0100
-CONFIG_USB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_USB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_USB_DESC_SERIAL_STRING="123456"
-# CONFIG_USB_MSC_ENABLED is not set
-# CONFIG_USB_CDC_ENABLED is not set
+# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set
 CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
 CONFIG_SUPPORT_TERMIOS=y
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
diff --git a/projects/esp32-s3_4m b/projects/esp32-s3_4m
index e09cb60..b889bc2 100644
--- a/projects/esp32-s3_4m
+++ b/projects/esp32-s3_4m
@@ -1,40 +1,337 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_GDMA_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_LCDCAM_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
+CONFIG_SOC_CACHE_SUPPORT_WRAP=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_RISCV_COPROC_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_USB_OTG_SUPPORTED=y
+CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
+CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
+CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
+CONFIG_SOC_SDMMC_HOST_SUPPORTED=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_PSRAM_DMA_CAPABLE=y
+CONFIG_SOC_XT_WDT_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_HMAC_SUPPORTED=y
+CONFIG_SOC_DIG_SIGN_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_MEMPROT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
+CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=24
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
+CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
+CONFIG_SOC_APB_BACKUP_DMA=y
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
+CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y
+CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=2
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FPU=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096
+CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
+CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
+CONFIG_SOC_GDMA_GROUPS=y
+CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5
+CONFIG_SOC_GDMA_SUPPORT_PSRAM=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=49
+CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
+CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
+CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y
+CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000
+CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
+CONFIG_SOC_I2C_SUPPORT_XTAL=y
+CONFIG_SOC_I2C_SUPPORT_RTC=y
+CONFIG_SOC_I2S_NUM=2
+CONFIG_SOC_I2S_HW_VERSION_2=y
+CONFIG_SOC_I2S_SUPPORTS_XTAL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PCM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
+CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
+CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4
+CONFIG_SOC_I2S_SUPPORTS_TDM=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
+CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
+CONFIG_SOC_MCPWM_GROUPS=2
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
+CONFIG_SOC_MMU_PERIPH_NUM=1
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=4
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48
+CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
+CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
+CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
+CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
+CONFIG_SOC_RMT_SUPPORT_XTAL=y
+CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_SUPPORT_DMA=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_RGB_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=1
+CONFIG_SOC_LCD_RGB_PANELS=1
+CONFIG_SOC_LCD_I80_BUS_WIDTH=16
+CONFIG_SOC_LCD_RGB_DATA_WIDTH=16
+CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y
+CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128
+CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549
+CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128
+CONFIG_SOC_RTCIO_PIN_COUNT=22
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=y
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_MAX_CS_NUM=6
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_SUPPORT_DDRCLK=y
+CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
+CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
+CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
+CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
+CONFIG_SOC_SPI_SUPPORT_OCT=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
+CONFIG_SOC_SYSTIMER_ALARM_NUM=3
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
+CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
+CONFIG_SOC_SYSTIMER_INT_LEVEL=y
+CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
+CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TOUCH_VERSION_2=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=15
+CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3
+CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y
+CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_BRP_MAX=16384
+CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
+CONFIG_SOC_UART_NUM=3
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
+CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
+CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
+CONFIG_SOC_UART_REQUIRE_CORE_RESET=y
+CONFIG_SOC_USB_PERIPH_NUM=y
+CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
+CONFIG_SOC_SHA_SUPPORT_DMA=y
+CONFIG_SOC_SHA_SUPPORT_RESUME=y
+CONFIG_SOC_SHA_GDMA=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA224=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_224=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_256=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_T=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_DMA=y
+CONFIG_SOC_AES_GDMA=y
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_CPU_PD=y
+CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y
+CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y
+CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y
+CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_USB_JTAG=y
+CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y
+CONFIG_SOC_EFUSE_DIS_ICACHE=y
+CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
+CONFIG_SOC_SECURE_BOOT_V2_RSA=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
+CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y
+CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
+CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
+CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
+CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
+CONFIG_SOC_COEX_HW_PTI=y
+CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y
+CONFIG_SOC_SDMMC_NUM_SLOTS=2
+CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
+CONFIG_SOC_WIFI_HW_TSF=y
+CONFIG_SOC_WIFI_FTM_SUPPORT=y
+CONFIG_SOC_WIFI_GCMP_SUPPORT=y
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BLE_50_SUPPORTED=y
+CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32s3"
 CONFIG_IDF_TARGET_ESP32S3=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32s3-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -69,13 +366,42 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
-CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
-CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
+CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_PREFERRED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+CONFIG_SECURE_ROM_DL_MODE_ENABLED=y
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
+CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
+CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4
+CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y
+CONFIG_ESP_ROM_GET_CLK_FREQ=y
+CONFIG_ESP_ROM_HAS_HAL_WDT=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
+CONFIG_ESP_ROM_HAS_SPI_FLASH=y
+CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
+CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
+
 #
 # Boot ROM Behavior
 #
@@ -88,9 +414,9 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_OCT_FLASH is not set
+CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
 CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
@@ -101,6 +427,7 @@ CONFIG_ESPTOOLPY_FLASHMODE="dio"
 CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
 # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
 CONFIG_ESPTOOLPY_FLASHFREQ="80m"
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
@@ -111,22 +438,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -153,6 +471,7 @@ CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -163,7 +482,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -176,15 +495,15 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART0 is not set
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_UART2 is not set
+# CONFIG_APPTRACE_DEST_USB_CDC is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -192,59 +511,112 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
-#
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
-
-#
-# Driver configurations
+# Driver Configurations
 #
 
 #
-# ADC configuration
+# Legacy ADC Configuration
 #
-# CONFIG_ADC_FORCE_XPD_FSM is not set
-CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# MCPWM configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
+
+#
+# Temperature sensor Configuration
+#
+# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
+# end of Temperature sensor Configuration
 
 #
-# UART configuration
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
+# end of UART Configuration
 
 #
-# GDMA Configuration
+# GPIO Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
+# end of GPIO Configuration
+
+#
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# PCNT Configuration
+#
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
+
+#
+# RMT Configuration
+#
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# MCPWM Configuration
+#
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
+
+#
+# I2S Configuration
+#
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# USB Serial/JTAG Configuration
+#
+# end of USB Serial/JTAG Configuration
+# end of Driver Configurations
 
 #
 # eFuse Bit Manager
@@ -266,74 +638,18 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
 # end of ESP-TLS
 
 #
-# ESP32S3-Specific
+# ADC and ADC Calibration
 #
-# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
-CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y
-# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set
-CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160
-
-#
-# Cache config
-#
-CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
-CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
-CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP is not set
-# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
-CONFIG_ESP32S3_DATA_CACHE_32KB=y
-# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
-CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
-# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
-CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
-CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
-# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
-CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
-# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
-CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
-# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
-# end of Cache config
-
-# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
-# CONFIG_ESP32S3_TRAX is not set
-CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=0
-CONFIG_ESP32S3_DEBUG_OCDAWARE=y
-CONFIG_ESP32S3_BROWNOUT_DET=y
-CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
-CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
-CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
-# CONFIG_ESP32S3_NO_BLOBS is not set
-# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set
-# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
-# end of ESP32S3-Specific
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
+# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
+# end of ADC and ADC Calibration
 
 #
-# ADC-Calibration
+# Wireless Coexistence
 #
-# end of ADC-Calibration
+# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -350,6 +666,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -382,12 +699,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-# CONFIG_OTA_ALLOW_HTTP is not set
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set
 # end of ESP HTTPS OTA
 
 #
@@ -400,6 +719,22 @@ CONFIG_HTTPD_PURGE_BUF_LEN=32
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+CONFIG_ESP32S3_REV_MIN_0=y
+# CONFIG_ESP32S3_REV_MIN_1 is not set
+# CONFIG_ESP32S3_REV_MIN_2 is not set
+CONFIG_ESP32S3_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32-S3 Revision (Rev v0.99)
+#
+CONFIG_ESP32S3_REV_MAX_FULL=99
+CONFIG_ESP_REV_MAX_FULL=99
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -407,6 +742,7 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4
@@ -420,30 +756,55 @@ CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
 # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set
 CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
 # end of Sleep Config
 
 #
 # RTC Clock Config
 #
-CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# GDMA Configuration
+#
+# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GDMA_ISR_IRAM_SAFE is not set
+# end of GDMA Configuration
+
+#
+# Main XTAL Config
+#
+CONFIG_XTAL_FREQ_40=y
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set
+# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -453,9 +814,16 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
 #
 # PHY
 #
@@ -463,7 +831,13 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
 # CONFIG_ESP_PHY_ENABLE_USB is not set
+# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
 # end of PHY
 
 #
@@ -474,21 +848,71 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
 CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y
 # end of Power Management
 
+#
+# ESP PSRAM
+#
+# CONFIG_SPIRAM is not set
+# end of ESP PSRAM
+
 #
 # ESP Ringbuf
 #
 # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
 # end of ESP Ringbuf
 
 #
 # ESP System Settings
 #
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
+
+#
+# Cache config
+#
+CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
+CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
+# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
+CONFIG_ESP32S3_DATA_CACHE_32KB=y
+# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
+CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
+# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
+CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
+CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
+# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
+# end of Cache config
+
+#
+# Memory
+#
+# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set
+# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
+# end of Memory
+
+#
+# Trace memory
+#
+# CONFIG_ESP32S3_TRAX is not set
+CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
 CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
 CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
@@ -496,6 +920,8 @@ CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
 #
 # Memory protection
 #
+CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
+CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
 # end of Memory protection
 
 CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
@@ -511,19 +937,44 @@ CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
 # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
 # CONFIG_ESP_CONSOLE_NONE is not set
 CONFIG_ESP_CONSOLE_SECONDARY_NONE=y
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y
 CONFIG_ESP_CONSOLE_MULTIPLE_UART=y
 CONFIG_ESP_CONSOLE_UART_NUM=-1
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 # CONFIG_ESP_TASK_WDT_PANIC is not set
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=7
+# end of Brownout Detector
+
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -532,6 +983,11 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
 CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 # end of High resolution timer (esp_timer)
@@ -539,24 +995,27 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=6
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=6
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_FTM_ENABLE is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
@@ -565,6 +1024,25 @@ CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -579,6 +1057,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64
 CONFIG_ESP_COREDUMP_UART_DELAY=0
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 CONFIG_ESP_COREDUMP_DECODE_INFO=y
 # CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set
 CONFIG_ESP_COREDUMP_DECODE="info"
@@ -587,6 +1066,12 @@ CONFIG_ESP_COREDUMP_DECODE="info"
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+CONFIG_FATFS_LFN_NONE=y
+# CONFIG_FATFS_LFN_HEAP is not set
+# CONFIG_FATFS_LFN_STACK is not set
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -610,84 +1095,66 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-CONFIG_FATFS_LFN_NONE=y
-# CONFIG_FATFS_LFN_HEAP is not set
-# CONFIG_FATFS_LFN_STACK is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=4096
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-CONFIG_FMB_PORT_TASK_AFFINITY=0x7FFFFFFF
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_FMB_TIMER_PORT_ENABLED is not set
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 CONFIG_FREERTOS_UNICORE=y
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
-CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
-# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
-CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
-CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 CONFIG_FREERTOS_HZ=100
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
+CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 # CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS is not set
 # CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set
+# end of Kernel
+
+#
+# Port
+#
 CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
 CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
+CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
+# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
+CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -695,9 +1162,12 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_WDT_USE_ROM_IMPL=y
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -709,20 +1179,13 @@ CONFIG_HEAP_POISONING_DISABLED=y
 CONFIG_HEAP_TRACING_OFF=y
 # CONFIG_HEAP_TRACING_STANDALONE is not set
 # CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -749,6 +1212,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 # CONFIG_LWIP_IRAM_OPTIMIZATION is not set
@@ -764,17 +1228,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 # CONFIG_LWIP_IP4_REASSEMBLY is not set
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -785,6 +1253,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 CONFIG_LWIP_IPV6_AUTOCONFIG=y
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -812,7 +1281,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -865,6 +1333,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -882,6 +1351,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -900,13 +1372,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -924,11 +1398,13 @@ CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200
 CONFIG_MBEDTLS_HARDWARE_AES=y
 CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_SHA=y
 CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -945,7 +1421,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -954,16 +1429,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -972,9 +1442,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -994,6 +1461,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -1018,26 +1486,11 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1059,6 +1512,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1067,21 +1524,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set
-CONFIG_OPENSSL_ASSERT_EXIT=y
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1092,6 +1548,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1102,8 +1566,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
-# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
 CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
@@ -1113,9 +1575,23 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1173,49 +1649,15 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
 #
-# TinyUSB Stack
+# Ultra Low Power (ULP) Co-processor
 #
-CONFIG_TINYUSB=y
-CONFIG_TINYUSB_DEBUG_LEVEL=2
-
-#
-# TinyUSB task configuration
-#
-# CONFIG_TINYUSB_NO_DEFAULT_TASK is not set
-CONFIG_TINYUSB_TASK_PRIORITY=5
-CONFIG_TINYUSB_TASK_STACK_SIZE=4096
-# end of TinyUSB task configuration
-
-#
-# Descriptor configuration
-#
-CONFIG_TINYUSB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_TINYUSB_DESC_USE_DEFAULT_PID=y
-CONFIG_TINYUSB_DESC_BCD_DEVICE=0x0100
-CONFIG_TINYUSB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_TINYUSB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_TINYUSB_DESC_SERIAL_STRING="123456"
-CONFIG_TINYUSB_DESC_CDC_STRING="Espressif CDC Device"
-# end of Descriptor configuration
-
-#
-# Massive Storage Class (MSC)
-#
-# CONFIG_TINYUSB_MSC_ENABLED is not set
-# end of Massive Storage Class (MSC)
-
-#
-# Communication Device Class (CDC)
-#
-CONFIG_TINYUSB_CDC_ENABLED=y
-CONFIG_TINYUSB_CDC_RX_BUFSIZE=64
-CONFIG_TINYUSB_CDC_TX_BUFSIZE=64
-# end of Communication Device Class (CDC)
-# end of TinyUSB Stack
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
 
 #
 # Unity unit testing library
@@ -1237,6 +1679,15 @@ CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256
 CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set
+
+#
+# Root Hub configuration
+#
+CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250
+CONFIG_USB_HOST_RESET_HOLD_MS=30
+CONFIG_USB_HOST_RESET_RECOVERY_MS=30
+CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10
+# end of Root Hub configuration
 # end of USB-OTG
 
 #
@@ -1269,22 +1720,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1337,6 +1776,7 @@ CONFIG_ROMFS=y
 # CONFIG_USB_DIAGLOG is not set
 # CONFIG_USB_CONSOLE is not set
 # CONFIG_GPIOS is not set
+# CONFIG_CORETEMP is not set
 CONFIG_IOEXTENDERS=y
 CONFIG_LEDS=y
 CONFIG_BUTTON=y
@@ -1357,6 +1797,7 @@ CONFIG_I2C_XDEV=y
 # CONFIG_TCA9555 is not set
 # CONFIG_MCP2300X is not set
 # CONFIG_MCP2301X is not set
+# CONFIG_OPT3001 is not set
 CONFIG_INA2XX=y
 CONFIG_SI7021=y
 CONFIG_BMX280=y
@@ -1370,6 +1811,7 @@ CONFIG_SPI=y
 # CONFIG_SX1276 is not set
 # CONFIG_SSD1309 is not set
 # CONFIG_ILI9341 is not set
+# CONFIG_SDCARD is not set
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1387,14 +1829,11 @@ CONFIG_DEVEL=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32s3-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1408,16 +1847,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=5
 # CONFIG_FLASHMODE_QOUT is not set
 CONFIG_FLASHMODE_DIO=y
 # CONFIG_FLASHMODE_DOUT is not set
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
+# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1429,42 +1862,106 @@ CONFIG_STACK_CHECK_NONE=y
 # CONFIG_STACK_CHECK_STRONG is not set
 # CONFIG_STACK_CHECK_ALL is not set
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
-CONFIG_ADC2_DISABLE_DAC=y
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
+# CONFIG_EXTERNAL_COEX_ENABLE is not set
+# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+# CONFIG_OTA_ALLOW_HTTP is not set
 # CONFIG_ESP_SYSTEM_PD_FLASH is not set
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=1536
+CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
 CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
-CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
+# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 # CONFIG_CONSOLE_UART_DEFAULT is not set
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART_NUM=-1
 CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 # CONFIG_TASK_WDT_PANIC is not set
 CONFIG_TASK_WDT_TIMEOUT_S=5
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP32S3_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32S3_BROWNOUT_DET=y
+CONFIG_ESP32S3_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_7=y
+CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_BROWNOUT_DET_LVL=7
+CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
+CONFIG_IPC_TASK_STACK_SIZE=1536
 CONFIG_TIMER_TASK_STACK_SIZE=3584
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1474,28 +1971,16 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64
 CONFIG_ESP32_CORE_DUMP_UART_DELAY=0
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y
 # CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set
 CONFIG_ESP32_CORE_DUMP_DECODE="info"
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_MB_TIMER_PORT_ENABLED is not set
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1507,7 +1992,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1517,6 +2001,12 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
+CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
@@ -1525,21 +2015,6 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
-CONFIG_USB_ENABLED=y
-CONFIG_USB_DEBUG_LEVEL=2
-# CONFIG_USB_DO_NOT_CREATE_TASK is not set
-CONFIG_USB_TASK_PRIORITY=5
-CONFIG_USB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_USB_DESC_USE_DEFAULT_PID=y
-CONFIG_USB_DESC_BCDDEVICE=0x0100
-CONFIG_USB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_USB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_USB_DESC_SERIAL_STRING="123456"
-CONFIG_USB_DESC_CDC_STRING="Espressif CDC Device"
-# CONFIG_USB_MSC_ENABLED is not set
-CONFIG_USB_CDC_ENABLED=y
-CONFIG_USB_CDC_RX_BUFSIZE=64
-CONFIG_USB_CDC_TX_BUFSIZE=64
 CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
 CONFIG_SUPPORT_TERMIOS=y
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
diff --git a/projects/esp32-s3_8m b/projects/esp32-s3_8m
index 284faa2..a98751c 100644
--- a/projects/esp32-s3_8m
+++ b/projects/esp32-s3_8m
@@ -1,40 +1,337 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_GDMA_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_LCDCAM_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y
+CONFIG_SOC_CACHE_SUPPORT_WRAP=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_RISCV_COPROC_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_USB_OTG_SUPPORTED=y
+CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y
+CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y
+CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y
+CONFIG_SOC_SDMMC_HOST_SUPPORTED=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_PSRAM_DMA_CAPABLE=y
+CONFIG_SOC_XT_WDT_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_HMAC_SUPPORTED=y
+CONFIG_SOC_DIG_SIGN_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_MEMPROT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_ARBITER_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y
+CONFIG_SOC_ADC_MONITOR_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=24
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y
+CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y
+CONFIG_SOC_APB_BACKUP_DMA=y
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y
+CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y
+CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=2
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FPU=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096
+CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16
+CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100
+CONFIG_SOC_GDMA_GROUPS=y
+CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5
+CONFIG_SOC_GDMA_SUPPORT_PSRAM=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=49
+CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y
+CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y
+CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y
+CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000
+CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8
+CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y
+CONFIG_SOC_I2C_SUPPORT_XTAL=y
+CONFIG_SOC_I2C_SUPPORT_RTC=y
+CONFIG_SOC_I2S_NUM=2
+CONFIG_SOC_I2S_HW_VERSION_2=y
+CONFIG_SOC_I2S_SUPPORTS_XTAL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PCM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2
+CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
+CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4
+CONFIG_SOC_I2S_SUPPORTS_TDM=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14
+CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y
+CONFIG_SOC_MCPWM_GROUPS=2
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1
+CONFIG_SOC_MMU_PERIPH_NUM=1
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=4
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48
+CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y
+CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y
+CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y
+CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y
+CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y
+CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y
+CONFIG_SOC_RMT_SUPPORT_XTAL=y
+CONFIG_SOC_RMT_SUPPORT_RC_FAST=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_SUPPORT_DMA=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_RGB_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=1
+CONFIG_SOC_LCD_RGB_PANELS=1
+CONFIG_SOC_LCD_I80_BUS_WIDTH=16
+CONFIG_SOC_LCD_RGB_DATA_WIDTH=16
+CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y
+CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128
+CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549
+CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128
+CONFIG_SOC_RTCIO_PIN_COUNT=22
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=y
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_MAX_CS_NUM=6
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_SUPPORT_DDRCLK=y
+CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_CD_SIG=y
+CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y
+CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y
+CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y
+CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16
+CONFIG_SOC_SPI_SUPPORT_OCT=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y
+CONFIG_SOC_SYSTIMER_COUNTER_NUM=2
+CONFIG_SOC_SYSTIMER_ALARM_NUM=3
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32
+CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20
+CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y
+CONFIG_SOC_SYSTIMER_INT_LEVEL=y
+CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54
+CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TOUCH_VERSION_2=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=15
+CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3
+CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y
+CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_BRP_MAX=16384
+CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y
+CONFIG_SOC_UART_NUM=3
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y
+CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_RTC_CLK=y
+CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y
+CONFIG_SOC_UART_REQUIRE_CORE_RESET=y
+CONFIG_SOC_USB_PERIPH_NUM=y
+CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968
+CONFIG_SOC_SHA_SUPPORT_DMA=y
+CONFIG_SOC_SHA_SUPPORT_RESUME=y
+CONFIG_SOC_SHA_GDMA=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA224=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_224=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_256=y
+CONFIG_SOC_SHA_SUPPORT_SHA512_T=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_DMA=y
+CONFIG_SOC_AES_GDMA=y
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_CPU_PD=y
+CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y
+CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y
+CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y
+CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y
+CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_USB_JTAG=y
+CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y
+CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y
+CONFIG_SOC_EFUSE_DIS_ICACHE=y
+CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y
+CONFIG_SOC_SECURE_BOOT_V2_RSA=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3
+CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y
+CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y
+CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16
+CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192
+CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y
+CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y
+CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y
+CONFIG_SOC_COEX_HW_PTI=y
+CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y
+CONFIG_SOC_SDMMC_NUM_SLOTS=2
+CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y
+CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y
+CONFIG_SOC_WIFI_HW_TSF=y
+CONFIG_SOC_WIFI_FTM_SUPPORT=y
+CONFIG_SOC_WIFI_GCMP_SUPPORT=y
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BLE_50_SUPPORTED=y
+CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32s3"
 CONFIG_IDF_TARGET_ESP32S3=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32s3-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -69,13 +366,42 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
-CONFIG_SECURE_BOOT_SUPPORTS_RSA=y
-CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y
+CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y
+CONFIG_SECURE_BOOT_V2_PREFERRED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
+CONFIG_SECURE_ROM_DL_MODE_ENABLED=y
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y
+CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y
+CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4
+CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y
+CONFIG_ESP_ROM_GET_CLK_FREQ=y
+CONFIG_ESP_ROM_HAS_HAL_WDT=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y
+CONFIG_ESP_ROM_HAS_SPI_FLASH=y
+CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y
+CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y
+
 #
 # Boot ROM Behavior
 #
@@ -88,9 +414,9 @@ CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_OCT_FLASH is not set
+CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
 CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
@@ -101,6 +427,7 @@ CONFIG_ESPTOOLPY_FLASHMODE="dio"
 CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
 # CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set
 # CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set
+CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y
 CONFIG_ESPTOOLPY_FLASHFREQ="80m"
 # CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set
@@ -111,22 +438,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="8MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -153,6 +471,7 @@ CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -163,7 +482,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -176,15 +495,15 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART0 is not set
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_UART2 is not set
+# CONFIG_APPTRACE_DEST_USB_CDC is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -192,59 +511,112 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
+# Driver Configurations
 #
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
 
 #
-# Driver configurations
+# Legacy ADC Configuration
 #
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# ADC configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_ADC_FORCE_XPD_FSM is not set
-CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# MCPWM configuration
-#
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
-
-#
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
+
+#
+# Temperature sensor Configuration
+#
+# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set
+# end of Temperature sensor Configuration
 
 #
-# UART configuration
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
+# end of UART Configuration
 
 #
-# GDMA Configuration
+# GPIO Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
+# end of GPIO Configuration
+
+#
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# PCNT Configuration
+#
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
+
+#
+# RMT Configuration
+#
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# MCPWM Configuration
+#
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
+
+#
+# I2S Configuration
+#
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# USB Serial/JTAG Configuration
+#
+# end of USB Serial/JTAG Configuration
+# end of Driver Configurations
 
 #
 # eFuse Bit Manager
@@ -266,105 +638,18 @@ CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y
 # end of ESP-TLS
 
 #
-# ESP32S3-Specific
+# ADC and ADC Calibration
 #
-# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
-CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y
-# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set
-CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
+# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set
+# end of ADC and ADC Calibration
 
 #
-# Cache config
+# Wireless Coexistence
 #
-CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
-CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
-CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
-CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
-# CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP is not set
-# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
-CONFIG_ESP32S3_DATA_CACHE_32KB=y
-# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
-CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
-# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
-CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
-CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
-# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
-CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
-# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
-CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
-# CONFIG_ESP32S3_DATA_CACHE_WRAP is not set
-# end of Cache config
-
-CONFIG_ESP32S3_SPIRAM_SUPPORT=y
-
-#
-# SPI RAM config
-#
-CONFIG_SPIRAM_MODE_QUAD=y
-# CONFIG_SPIRAM_MODE_OCT is not set
-CONFIG_SPIRAM_TYPE_AUTO=y
-# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
-CONFIG_SPIRAM_SIZE=-1
-CONFIG_SPIRAM_CLK_IO=30
-CONFIG_SPIRAM_CS_IO=26
-# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
-# CONFIG_SPIRAM_RODATA is not set
-# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
-# CONFIG_SPIRAM_SPEED_120M is not set
-# CONFIG_SPIRAM_SPEED_80M is not set
-CONFIG_SPIRAM_SPEED_40M=y
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_BOOT_INIT=y
-CONFIG_SPIRAM_IGNORE_NOTFOUND=y
-# CONFIG_SPIRAM_USE_MEMMAP is not set
-# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
-CONFIG_SPIRAM_USE_MALLOC=y
-CONFIG_SPIRAM_MEMTEST=y
-CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
-# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
-CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
-# end of SPI RAM config
-
-# CONFIG_ESP32S3_TRAX is not set
-CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32S3_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM=0
-CONFIG_ESP32S3_DEBUG_OCDAWARE=y
-CONFIG_ESP32S3_BROWNOUT_DET=y
-CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
-CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
-CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
-# CONFIG_ESP32S3_NO_BLOBS is not set
-# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set
-# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
-# end of ESP32S3-Specific
-
-#
-# ADC-Calibration
-#
-# end of ADC-Calibration
+# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -381,6 +666,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -413,12 +699,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-# CONFIG_OTA_ALLOW_HTTP is not set
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set
 # end of ESP HTTPS OTA
 
 #
@@ -431,6 +719,22 @@ CONFIG_HTTPD_PURGE_BUF_LEN=32
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+CONFIG_ESP32S3_REV_MIN_0=y
+# CONFIG_ESP32S3_REV_MIN_1 is not set
+# CONFIG_ESP32S3_REV_MIN_2 is not set
+CONFIG_ESP32S3_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32-S3 Revision (Rev v0.99)
+#
+CONFIG_ESP32S3_REV_MAX_FULL=99
+CONFIG_ESP_REV_MAX_FULL=99
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -438,6 +742,7 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4
@@ -451,30 +756,55 @@ CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
 CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y
 CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
 # end of Sleep Config
 
 #
 # RTC Clock Config
 #
-CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB=y
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# GDMA Configuration
+#
+# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GDMA_ISR_IRAM_SAFE is not set
+# end of GDMA Configuration
+
+#
+# Main XTAL Config
+#
+CONFIG_XTAL_FREQ_40=y
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set
+# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -484,9 +814,16 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
 #
 # PHY
 #
@@ -494,7 +831,13 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP_PHY_MAX_TX_POWER=20
+# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set
 CONFIG_ESP_PHY_ENABLE_USB=y
+# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
 # end of PHY
 
 #
@@ -505,34 +848,116 @@ CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
 CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y
 # end of Power Management
 
+#
+# ESP PSRAM
+#
+CONFIG_SPIRAM=y
+
+#
+# SPI RAM config
+#
+CONFIG_SPIRAM_MODE_QUAD=y
+# CONFIG_SPIRAM_MODE_OCT is not set
+CONFIG_SPIRAM_TYPE_AUTO=y
+# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
+# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
+CONFIG_SPIRAM_CLK_IO=30
+CONFIG_SPIRAM_CS_IO=26
+# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
+# CONFIG_SPIRAM_RODATA is not set
+# CONFIG_SPIRAM_SPEED_120M is not set
+# CONFIG_SPIRAM_SPEED_80M is not set
+CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED=40
+CONFIG_SPIRAM_BOOT_INIT=y
+CONFIG_SPIRAM_IGNORE_NOTFOUND=y
+# CONFIG_SPIRAM_USE_MEMMAP is not set
+# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
+CONFIG_SPIRAM_USE_MALLOC=y
+CONFIG_SPIRAM_MEMTEST=y
+CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
+# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
+CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
+# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
+# end of SPI RAM config
+# end of ESP PSRAM
+
 #
 # ESP Ringbuf
 #
 # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
 # end of ESP Ringbuf
 
 #
 # ESP System Settings
 #
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
+
+#
+# Cache config
+#
+CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y
+CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y
+CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32
+# CONFIG_ESP32S3_DATA_CACHE_16KB is not set
+CONFIG_ESP32S3_DATA_CACHE_32KB=y
+# CONFIG_ESP32S3_DATA_CACHE_64KB is not set
+CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000
+# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set
+CONFIG_ESP32S3_DATA_CACHE_8WAYS=y
+CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8
+# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y
+# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set
+CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32
+# end of Cache config
+
+#
+# Memory
+#
+# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set
+# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set
+# end of Memory
+
+#
+# Trace memory
+#
+# CONFIG_ESP32S3_TRAX is not set
+CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
-CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y
 CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y
 
 #
 # Memory protection
 #
+CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y
+CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y
 # end of Memory protection
 
 CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584
 CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y
+# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set
 # CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set
 CONFIG_ESP_MAIN_TASK_AFFINITY=0x0
 CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048
@@ -542,19 +967,48 @@ CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
 # CONFIG_ESP_CONSOLE_UART_CUSTOM is not set
 # CONFIG_ESP_CONSOLE_NONE is not set
 CONFIG_ESP_CONSOLE_SECONDARY_NONE=y
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y
 CONFIG_ESP_CONSOLE_MULTIPLE_UART=y
 CONFIG_ESP_CONSOLE_UART_NUM=-1
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_INT_WDT_CHECK_CPU1=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 # CONFIG_ESP_TASK_WDT_PANIC is not set
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=5
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=7
+# end of Brownout Detector
+
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1536
+CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
+CONFIG_ESP_IPC_ISR_ENABLE=y
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -563,6 +1017,11 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
 CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 # end of High resolution timer (esp_timer)
@@ -570,25 +1029,30 @@ CONFIG_ESP_TIMER_IMPL_SYSTIMER=y
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=6
-# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=6
+# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_FTM_ENABLE is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
@@ -597,6 +1061,25 @@ CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -611,11 +1094,18 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_CHECK_BOOT=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 # end of Core dump
 
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+# CONFIG_FATFS_LFN_NONE is not set
+# CONFIG_FATFS_LFN_HEAP is not set
+CONFIG_FATFS_LFN_STACK=y
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -639,90 +1129,71 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-# CONFIG_FATFS_LFN_NONE is not set
-# CONFIG_FATFS_LFN_HEAP is not set
-CONFIG_FATFS_LFN_STACK=y
 CONFIG_FATFS_MAX_LFN=63
 CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
-# CONFIG_FATFS_API_ENCODING_UTF_16 is not set
 # CONFIG_FATFS_API_ENCODING_UTF_8 is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=4096
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-CONFIG_FMB_PORT_TASK_AFFINITY=0x7FFFFFFF
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_FMB_TIMER_PORT_ENABLED is not set
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
-CONFIG_FREERTOS_UNICORE=y
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
-CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
-# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
-CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
-CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y
+# CONFIG_FREERTOS_SMP is not set
+# CONFIG_FREERTOS_UNICORE is not set
 CONFIG_FREERTOS_HZ=100
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
-# CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is not set
-# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set
+CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
+CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
+# end of Kernel
+
+#
+# Port
+#
 CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
 CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y
+CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y
+# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set
+CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y
+CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -730,9 +1201,12 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_WDT_USE_ROM_IMPL=y
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -746,21 +1220,15 @@ CONFIG_HEAP_TRACING_STANDALONE=y
 # CONFIG_HEAP_TRACING_TOHOST is not set
 CONFIG_HEAP_TRACING=y
 CONFIG_HEAP_TRACING_STACK_DEPTH=2
+# CONFIG_HEAP_USE_HOOKS is not set
 CONFIG_HEAP_TASK_TRACKING=y
+# CONFIG_HEAP_TRACE_HASH_MAP is not set
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -787,6 +1255,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 # CONFIG_LWIP_IRAM_OPTIMIZATION is not set
@@ -802,17 +1271,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 # CONFIG_LWIP_IP4_REASSEMBLY is not set
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -823,6 +1296,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 CONFIG_LWIP_IPV6_AUTOCONFIG=y
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -850,7 +1324,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -875,6 +1348,7 @@ CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y
 CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072
 CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set
+# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set
 CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_LWIP_PPP_SUPPORT is not set
 CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3
@@ -903,6 +1377,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -920,6 +1395,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -939,13 +1417,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -963,11 +1443,13 @@ CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200
 CONFIG_MBEDTLS_HARDWARE_AES=y
 CONFIG_MBEDTLS_AES_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_MPI=y
+CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y
 CONFIG_MBEDTLS_HARDWARE_SHA=y
 CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -984,7 +1466,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -993,16 +1474,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -1011,9 +1487,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -1033,6 +1506,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -1057,26 +1531,11 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1098,6 +1557,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1106,31 +1569,41 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set
-CONFIG_OPENSSL_ASSERT_EXIT=y
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
 CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_PTHREAD_STACK_MIN=768
+CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y
+# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set
+# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set
 CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1141,8 +1614,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
-# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
 CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20
@@ -1152,9 +1623,23 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1212,46 +1697,15 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
 #
-# TinyUSB Stack
+# Ultra Low Power (ULP) Co-processor
 #
-CONFIG_TINYUSB=y
-CONFIG_TINYUSB_DEBUG_LEVEL=2
-
-#
-# TinyUSB task configuration
-#
-# CONFIG_TINYUSB_NO_DEFAULT_TASK is not set
-CONFIG_TINYUSB_TASK_PRIORITY=5
-CONFIG_TINYUSB_TASK_STACK_SIZE=4096
-# end of TinyUSB task configuration
-
-#
-# Descriptor configuration
-#
-CONFIG_TINYUSB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_TINYUSB_DESC_USE_DEFAULT_PID=y
-CONFIG_TINYUSB_DESC_BCD_DEVICE=0x0100
-CONFIG_TINYUSB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_TINYUSB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_TINYUSB_DESC_SERIAL_STRING="123456"
-# end of Descriptor configuration
-
-#
-# Massive Storage Class (MSC)
-#
-# CONFIG_TINYUSB_MSC_ENABLED is not set
-# end of Massive Storage Class (MSC)
-
-#
-# Communication Device Class (CDC)
-#
-# CONFIG_TINYUSB_CDC_ENABLED is not set
-# end of Communication Device Class (CDC)
-# end of TinyUSB Stack
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
 
 #
 # Unity unit testing library
@@ -1273,6 +1727,15 @@ CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256
 CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set
 # CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set
+
+#
+# Root Hub configuration
+#
+CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250
+CONFIG_USB_HOST_RESET_HOLD_MS=30
+CONFIG_USB_HOST_RESET_RECOVERY_MS=30
+CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10
+# end of Root Hub configuration
 # end of USB-OTG
 
 #
@@ -1305,22 +1768,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1375,6 +1826,7 @@ CONFIG_ROMFS_VFS_NUMFDS=4
 # CONFIG_USB_DIAGLOG is not set
 CONFIG_USB_CONSOLE=y
 CONFIG_GPIOS=y
+# CONFIG_CORETEMP is not set
 CONFIG_IOEXTENDERS=y
 CONFIG_LEDS=y
 CONFIG_BUTTON=y
@@ -1395,6 +1847,7 @@ CONFIG_PCF8574=y
 CONFIG_TCA9555=y
 CONFIG_MCP2300X=y
 CONFIG_MCP2301X=y
+# CONFIG_OPT3001 is not set
 CONFIG_INA2XX=y
 CONFIG_SI7021=y
 CONFIG_BMX280=y
@@ -1408,6 +1861,7 @@ CONFIG_SPI=y
 # CONFIG_SX1276 is not set
 CONFIG_SSD1309=y
 CONFIG_ILI9341=y
+CONFIG_SDCARD=y
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1425,14 +1879,11 @@ CONFIG_FUNCTION_TIMING=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32s3-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1446,16 +1897,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=5
 # CONFIG_FLASHMODE_QOUT is not set
 CONFIG_FLASHMODE_DIO=y
 # CONFIG_FLASHMODE_DOUT is not set
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+CONFIG_OPTIMIZATION_LEVEL_DEBUG=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y
+# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1467,43 +1912,112 @@ CONFIG_STACK_CHECK_NONE=y
 # CONFIG_STACK_CHECK_STRONG is not set
 # CONFIG_STACK_CHECK_ALL is not set
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
-CONFIG_ADC2_DISABLE_DAC=y
-CONFIG_DEFAULT_PSRAM_CLK_IO=30
-CONFIG_DEFAULT_PSRAM_CS_IO=26
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
+# CONFIG_EXTERNAL_COEX_ENABLE is not set
+# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=1536
+# CONFIG_OTA_ALLOW_HTTP is not set
+CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+# CONFIG_REDUCE_PHY_TX_POWER is not set
+# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set
 CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
-CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP=y
+CONFIG_ESP32S3_SPIRAM_SUPPORT=y
+CONFIG_DEFAULT_PSRAM_CLK_IO=30
+CONFIG_DEFAULT_PSRAM_CS_IO=26
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y
+# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set
+CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 # CONFIG_CONSOLE_UART_DEFAULT is not set
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART_NUM=-1
 CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
+CONFIG_INT_WDT_CHECK_CPU1=y
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 # CONFIG_TASK_WDT_PANIC is not set
 CONFIG_TASK_WDT_TIMEOUT_S=5
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
+CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP32S3_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32S3_BROWNOUT_DET=y
+CONFIG_ESP32S3_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_7=y
+CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set
+CONFIG_BROWNOUT_DET_LVL=7
+CONFIG_ESP32S3_BROWNOUT_DET_LVL=7
+CONFIG_IPC_TASK_STACK_SIZE=1536
 CONFIG_TIMER_TASK_STACK_SIZE=3584
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+CONFIG_ESP32_WIFI_RX_BA_WIN=6
+# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1512,25 +2026,13 @@ CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF=y
 CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=4096
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-# CONFIG_MB_TIMER_PORT_ENABLED is not set
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1542,7 +2044,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1550,28 +2051,26 @@ CONFIG_UDP_RECVMBOX_SIZE=6
 CONFIG_TCPIP_TASK_STACK_SIZE=3072
 CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set
+# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y
+CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
+CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y
+# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set
+# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set
 CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
-CONFIG_USB_ENABLED=y
-CONFIG_USB_DEBUG_LEVEL=2
-# CONFIG_USB_DO_NOT_CREATE_TASK is not set
-CONFIG_USB_TASK_PRIORITY=5
-CONFIG_USB_DESC_USE_ESPRESSIF_VID=y
-CONFIG_USB_DESC_USE_DEFAULT_PID=y
-CONFIG_USB_DESC_BCDDEVICE=0x0100
-CONFIG_USB_DESC_MANUFACTURER_STRING="Espressif Systems"
-CONFIG_USB_DESC_PRODUCT_STRING="Espressif Device"
-CONFIG_USB_DESC_SERIAL_STRING="123456"
-# CONFIG_USB_MSC_ENABLED is not set
-# CONFIG_USB_CDC_ENABLED is not set
 CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
 CONFIG_SUPPORT_TERMIOS=y
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
diff --git a/projects/esp32_4m b/projects/esp32_4m
index a23b54b..ade0d8c 100644
--- a/projects/esp32_4m
+++ b/projects/esp32_4m
@@ -1,40 +1,235 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED="Not determined"
+CONFIG_SOC_TWAI_BRP_DIV_SUPPORTED="Not determined"
+CONFIG_SOC_DPORT_WORKAROUND="Not determined"
+CONFIG_SOC_CAPS_ECO_VER_MAX=301
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DAC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_SDMMC_HOST_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_EMAC_SUPPORTED=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL=5
+CONFIG_SOC_XTAL_SUPPORT_26M=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_XTAL_SUPPORT_AUTO_DETECT=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=16
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=2
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=20
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=2
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FPU=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DAC_CHAN_NUM=2
+CONFIG_SOC_DAC_RESOLUTION=8
+CONFIG_SOC_DAC_DMA_16BIT_ALIGN=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=40
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0xFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0xEF0FEA
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_APB=y
+CONFIG_SOC_I2S_NUM=2
+CONFIG_SOC_I2S_HW_VERSION_1=y
+CONFIG_SOC_I2S_SUPPORTS_APLL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
+CONFIG_SOC_I2S_PDM_MAX_RX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_ADC_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_ADC=y
+CONFIG_SOC_I2S_SUPPORTS_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA=y
+CONFIG_SOC_I2S_TRANS_SIZE_ALIGN_WORD=y
+CONFIG_SOC_I2S_LCD_I80_VARIANT=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=2
+CONFIG_SOC_LCD_I80_BUS_WIDTH=24
+CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_REF_TICK=y
+CONFIG_SOC_LEDC_SUPPORT_HS_MODE=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20
+CONFIG_SOC_MCPWM_GROUPS=2
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MMU_PERIPH_NUM=2
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=3
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=8
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=64
+CONFIG_SOC_RMT_SUPPORT_REF_TICK=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT=y
+CONFIG_SOC_RTCIO_PIN_COUNT=18
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED=y
+CONFIG_SOC_SPI_AS_CS_SUPPORTED=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_DMA_CHAN_NUM=2
+CONFIG_SOC_SPI_MAX_CS_NUM=3
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=8192
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=64
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TOUCH_VERSION_1=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=10
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT=y
+CONFIG_SOC_UART_NUM=3
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_REF_TICK=y
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SHA_SUPPORT_PARALLEL_ENG=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_192=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_SECURE_BOOT_V1=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_CLK_APLL_SUPPORTED=y
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MIN_HZ=350000000
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MAX_HZ=500000000
+CONFIG_SOC_APLL_MIN_HZ=5303031
+CONFIG_SOC_APLL_MAX_HZ=125000000
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_SDMMC_USE_IOMUX=y
+CONFIG_SOC_SDMMC_NUM_SLOTS=2
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_WIFI_NAN_SUPPORT=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BT_CLASSIC_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32"
 CONFIG_IDF_TARGET_ESP32=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -70,15 +265,33 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
+CONFIG_SECURE_BOOT_V1_SUPPORTED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_HAS_UART_BUF_SWITCH=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
@@ -100,22 +313,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -142,6 +346,7 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -153,7 +358,7 @@ CONFIG_COMPILER_HIDE_PATHS_MACROS=y
 CONFIG_COMPILER_STACK_CHECK_MODE_ALL=y
 CONFIG_COMPILER_STACK_CHECK=y
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -166,15 +371,13 @@ CONFIG_COMPILER_STACK_CHECK=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_UART2 is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -182,75 +385,119 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
+# Driver Configurations
 #
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
 
 #
-# Driver configurations
-#
-
+# Legacy ADC Configuration
 #
-# ADC configuration
-#
-# CONFIG_ADC_FORCE_XPD_FSM is not set
 CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# MCPWM configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
+CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CAL_LUT_ENABLE=y
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# SPI configuration
+# SPI Configuration
 #
-# CONFIG_SPI_MASTER_IN_IRAM is not set
-# CONFIG_SPI_MASTER_ISR_IN_IRAM is not set
+CONFIG_SPI_MASTER_IN_IRAM=y
+CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 # CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
 # CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set
 # CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
 
 #
-# UART configuration
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
-
-#
-# RTCIO configuration
-#
-# CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC is not set
-# end of RTCIO configuration
+# end of UART Configuration
 
 #
 # GPIO Configuration
 #
 # CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set
+CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y
 # end of GPIO Configuration
 
 #
-# GDMA Configuration
+# Sigma Delta Modulator Configuration
+#
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
+
+#
+# GPTimer Configuration
+#
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
+
+#
+# PCNT Configuration
+#
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
+
+#
+# RMT Configuration
+#
+CONFIG_RMT_ISR_IRAM_SAFE=y
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
+
+#
+# MCPWM Configuration
+#
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
+
+#
+# I2S Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
+
+#
+# DAC Configuration
+#
+# CONFIG_DAC_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_DAC_ISR_IRAM_SAFE is not set
+# CONFIG_DAC_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_DAC_ENABLE_DEBUG_LOG is not set
+CONFIG_DAC_DMA_AUTO_16BIT_ALIGN=y
+# end of DAC Configuration
+# end of Driver Configurations
 
 #
 # eFuse Bit Manager
@@ -268,61 +515,32 @@ CONFIG_EFUSE_MAX_BLK_LEN=192
 #
 CONFIG_ESP_TLS_USING_MBEDTLS=y
 # CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
-# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
 # CONFIG_ESP_TLS_SERVER is not set
 # CONFIG_ESP_TLS_PSK_VERIFICATION is not set
 # CONFIG_ESP_TLS_INSECURE is not set
 # end of ESP-TLS
 
 #
-# ESP32-specific
+# ADC and ADC Calibration
 #
-# CONFIG_ESP32_REV_MIN_0 is not set
-CONFIG_ESP32_REV_MIN_1=y
-# CONFIG_ESP32_REV_MIN_2 is not set
-# CONFIG_ESP32_REV_MIN_3 is not set
-CONFIG_ESP32_REV_MIN=1
-CONFIG_ESP32_DPORT_WORKAROUND=y
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
-CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
-CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
-# CONFIG_ESP32_SPIRAM_SUPPORT is not set
-# CONFIG_ESP32_TRAX is not set
-CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0
-# CONFIG_ESP32_DEBUG_OCDAWARE is not set
-# CONFIG_ESP32_BROWNOUT_DET is not set
-CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
-CONFIG_ESP32_XTAL_FREQ_40=y
-# CONFIG_ESP32_XTAL_FREQ_26 is not set
-# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
-CONFIG_ESP32_XTAL_FREQ=40
-# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_ESP32_NO_BLOBS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
-# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
-CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
-# end of ESP32-specific
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
 
 #
-# ADC-Calibration
+# ADC Calibration Configurations
 #
-CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
-CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
-CONFIG_ADC_CAL_LUT_ENABLE=y
-# end of ADC-Calibration
+CONFIG_ADC_CALI_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CALI_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CALI_LUT_ENABLE=y
+# end of ADC Calibration Configurations
+
+CONFIG_ADC_DISABLE_DAC_OUTPUT=y
+# end of ADC and ADC Calibration
+
+#
+# Wireless Coexistence
+#
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -354,9 +572,9 @@ CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y
 #
 # ESP HTTP client
 #
-CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS is not set
 # CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set
-CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y
+# CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH is not set
 # end of ESP HTTP client
 
 #
@@ -368,12 +586,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-CONFIG_OTA_ALLOW_HTTP=y
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP=y
 # end of ESP HTTPS OTA
 
 #
@@ -386,6 +606,26 @@ CONFIG_OTA_ALLOW_HTTP=y
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+# CONFIG_ESP32_REV_MIN_0 is not set
+CONFIG_ESP32_REV_MIN_1=y
+# CONFIG_ESP32_REV_MIN_1_1 is not set
+# CONFIG_ESP32_REV_MIN_2 is not set
+# CONFIG_ESP32_REV_MIN_3 is not set
+# CONFIG_ESP32_REV_MIN_3_1 is not set
+CONFIG_ESP32_REV_MIN=1
+CONFIG_ESP32_REV_MIN_FULL=100
+CONFIG_ESP_REV_MIN_FULL=100
+
+#
+# Maximum Supported ESP32 Revision (Rev v3.99)
+#
+CONFIG_ESP32_REV_MAX_FULL=399
+CONFIG_ESP_REV_MAX_FULL=399
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -393,9 +633,11 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4
+# CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR is not set
 # end of MAC Config
 
 #
@@ -406,30 +648,48 @@ CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
 # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set
 CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
 # end of Sleep Config
 
 #
 # RTC Clock Config
 #
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
-CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
-CONFIG_ESP_IPC_ISR_ENABLE=y
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# Main XTAL Config
+#
+# CONFIG_XTAL_FREQ_26 is not set
+CONFIG_XTAL_FREQ_40=y
+# CONFIG_XTAL_FREQ_AUTO is not set
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -439,9 +699,16 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
+#
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
 #
 # PHY
 #
@@ -449,6 +716,10 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP_PHY_MAX_TX_POWER=20
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
 # end of PHY
 
 #
@@ -457,21 +728,51 @@ CONFIG_ESP_PHY_MAX_TX_POWER=20
 # CONFIG_PM_ENABLE is not set
 # end of Power Management
 
+#
+# ESP PSRAM
+#
+# CONFIG_SPIRAM is not set
+# end of ESP PSRAM
+
 #
 # ESP Ringbuf
 #
 # CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
 # end of ESP Ringbuf
 
 #
 # ESP System Settings
 #
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240
+
+#
+# Memory
+#
+# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
+
+#
+# Non-backward compatible options
+#
+# CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM is not set
+# end of Non-backward compatible options
+# end of Memory
+
+#
+# Trace memory
+#
+# CONFIG_ESP32_TRAX is not set
+CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 
 #
 # Memory protection
@@ -496,17 +797,36 @@ CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=3000
 CONFIG_ESP_INT_WDT_CHECK_CPU1=y
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 CONFIG_ESP_TASK_WDT_PANIC=y
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=15
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+# CONFIG_ESP_DEBUG_OCDAWARE is not set
 # CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is not set
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+# CONFIG_ESP_BROWNOUT_DET is not set
+# end of Brownout Detector
+
+# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
+CONFIG_ESP_IPC_ISR_ENABLE=y
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -515,40 +835,67 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
-# CONFIG_ESP_TIMER_IMPL_FRC2 is not set
 CONFIG_ESP_TIMER_IMPL_TG0_LAC=y
 # end of High resolution timer (esp_timer)
 
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=16
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
-# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=16
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
 # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+# CONFIG_ESP_WIFI_NAN_ENABLE is not set
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -564,11 +911,18 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_CHECK_BOOT=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=32
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 # end of Core dump
 
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+# CONFIG_FATFS_LFN_NONE is not set
+# CONFIG_FATFS_LFN_HEAP is not set
+CONFIG_FATFS_LFN_STACK=y
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -592,92 +946,71 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-# CONFIG_FATFS_LFN_NONE is not set
-# CONFIG_FATFS_LFN_HEAP is not set
-CONFIG_FATFS_LFN_STACK=y
 CONFIG_FATFS_MAX_LFN=63
 CONFIG_FATFS_API_ENCODING_ANSI_OEM=y
-# CONFIG_FATFS_API_ENCODING_UTF_16 is not set
 # CONFIG_FATFS_API_ENCODING_UTF_8 is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=2048
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-# CONFIG_FMB_PORT_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_FMB_PORT_TASK_AFFINITY_CPU0=y
-# CONFIG_FMB_PORT_TASK_AFFINITY_CPU1 is not set
-CONFIG_FMB_PORT_TASK_AFFINITY=0x0
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_FMB_TIMER_PORT_ENABLED=y
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 # CONFIG_FREERTOS_UNICORE is not set
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
-CONFIG_FREERTOS_CORETIMER_0=y
-# CONFIG_FREERTOS_CORETIMER_1 is not set
-CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_HZ=1000
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2048
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=8
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
 CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
 CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
+# end of Kernel
+
+#
+# Port
+#
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+# CONFIG_FREERTOS_FPU_IN_ISR is not set
+CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
+CONFIG_FREERTOS_CORETIMER_0=y
+# CONFIG_FREERTOS_CORETIMER_1 is not set
+CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
 # CONFIG_FREERTOS_RUN_TIME_STATS_USING_CPU_CLK is not set
-CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_FREERTOS_FPU_IN_ISR is not set
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
 # end of FreeRTOS
 
 #
@@ -685,9 +1018,10 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -699,21 +1033,14 @@ CONFIG_HEAP_POISONING_COMPREHENSIVE=y
 CONFIG_HEAP_TRACING_OFF=y
 # CONFIG_HEAP_TRACING_STANDALONE is not set
 # CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
 CONFIG_HEAP_TASK_TRACKING=y
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -741,6 +1068,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 CONFIG_LWIP_TCPIP_CORE_LOCKING=y
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 CONFIG_LWIP_IRAM_OPTIMIZATION=y
@@ -756,17 +1084,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 CONFIG_LWIP_IP4_REASSEMBLY=y
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -780,6 +1112,7 @@ CONFIG_LWIP_AUTOIP=y
 CONFIG_LWIP_AUTOIP_TRIES=2
 CONFIG_LWIP_AUTOIP_MAX_CONFLICTS=9
 CONFIG_LWIP_AUTOIP_RATE_LIMIT_INTERVAL=20
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 CONFIG_LWIP_IPV6_AUTOCONFIG=y
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -807,7 +1140,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -861,6 +1193,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -878,6 +1211,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -896,13 +1232,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -924,9 +1262,10 @@ CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
-CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
-CONFIG_MBEDTLS_SHA512_C=y
+# CONFIG_MBEDTLS_ECDSA_DETERMINISTIC is not set
+# CONFIG_MBEDTLS_SHA512_C is not set
 CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y
 # CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set
 # CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set
@@ -940,7 +1279,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -948,18 +1286,13 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
-CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
+# CONFIG_MBEDTLS_SSL_RENEGOTIATION is not set
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
-CONFIG_MBEDTLS_SSL_ALPN=y
-CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
-CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
+# CONFIG_MBEDTLS_SSL_ALPN is not set
+# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set
+# CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS is not set
 
 #
 # Symmetric Ciphers
@@ -967,9 +1300,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -989,21 +1319,22 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
 CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y
-CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y
+# CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED is not set
+# CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED is not set
 CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_POLY1305_C is not set
 # CONFIG_MBEDTLS_CHACHA20_C is not set
@@ -1013,30 +1344,12 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
-CONFIG_MQTT_PROTOCOL_311=y
-CONFIG_MQTT_TRANSPORT_SSL=y
-CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
-CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
+# CONFIG_MQTT_PROTOCOL_311 is not set
+# CONFIG_MQTT_PROTOCOL_5 is not set
+# CONFIG_MQTT_TRANSPORT_SSL is not set
 # CONFIG_MQTT_MSG_ID_INCREMENTAL is not set
 # CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set
 # CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set
@@ -1055,6 +1368,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1063,21 +1380,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
-# CONFIG_OPENSSL_ASSERT_EXIT is not set
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+# CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0 is not set
+# CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1 is not set
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1091,6 +1407,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1100,7 +1424,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
 # CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
@@ -1111,9 +1434,21 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1168,11 +1503,16 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 # Websocket
 #
-CONFIG_WS_TRANSPORT=y
-CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_TRANSPORT is not set
 # end of Websocket
 # end of TCP Transport
 
+#
+# Ultra Low Power (ULP) Co-processor
+#
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
+
 #
 # Unity unit testing library
 #
@@ -1185,6 +1525,11 @@ CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
 # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
 # end of Unity unit testing library
 
+#
+# Root Hub configuration
+#
+# end of Root Hub configuration
+
 #
 # Virtual file system
 #
@@ -1214,22 +1559,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1265,7 +1598,7 @@ CONFIG_SYSLOG=y
 CONFIG_INFLUX=y
 CONFIG_UDPCTRL=y
 CONFIG_WPS=y
-CONFIG_SMARTCONFIG=y
+# CONFIG_SMARTCONFIG is not set
 # end of networking services
 
 #
@@ -1313,6 +1646,7 @@ CONFIG_BH1750=y
 CONFIG_SPI=y
 CONFIG_SSD1309=y
 CONFIG_ILI9341=y
+# CONFIG_SDCARD is not set
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1331,14 +1665,14 @@ CONFIG_VERIFY_HEAP=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
+# CONFIG_ESP32_NO_BLOBS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1352,16 +1686,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=3
 # CONFIG_FLASHMODE_QOUT is not set
 # CONFIG_FLASHMODE_DIO is not set
 CONFIG_FLASHMODE_DOUT=y
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1374,45 +1702,54 @@ CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2
 CONFIG_STACK_CHECK_ALL=y
 CONFIG_STACK_CHECK=y
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
 CONFIG_ADC2_DISABLE_DAC=y
-# CONFIG_SPIRAM_SUPPORT is not set
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ULP_COPROC_ENABLED is not set
-CONFIG_ULP_COPROC_RESERVE_MEM=0
-# CONFIG_BROWNOUT_DET is not set
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
-# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_NO_BLOBS is not set
-# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+CONFIG_OTA_ALLOW_HTTP=y
 # CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set
 CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
 CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
 # CONFIG_ESP_SYSTEM_PD_FLASH is not set
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
+# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
+CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
+# CONFIG_ESP32_XTAL_FREQ_26 is not set
+CONFIG_ESP32_XTAL_FREQ_40=y
+# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
+CONFIG_ESP32_XTAL_FREQ=40
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
+# CONFIG_SPIRAM_SUPPORT is not set
+# CONFIG_ESP32_SPIRAM_SUPPORT is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
+CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
+CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
+CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+# CONFIG_ESP32_PANIC_PRINT_HALT is not set
+CONFIG_ESP32_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP32_PANIC_GDBSTUB is not set
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=8192
 CONFIG_CONSOLE_UART_DEFAULT=y
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART=y
 CONFIG_CONSOLE_UART_NUM=0
@@ -1421,12 +1758,53 @@ CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=3000
 CONFIG_INT_WDT_CHECK_CPU1=y
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 CONFIG_TASK_WDT_PANIC=y
 CONFIG_TASK_WDT_TIMEOUT_S=15
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+# CONFIG_ESP32_DEBUG_OCDAWARE is not set
+# CONFIG_BROWNOUT_DET is not set
+# CONFIG_ESP32_BROWNOUT_DET is not set
+# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_IPC_TASK_STACK_SIZE=1024
 CONFIG_TIMER_TASK_STACK_SIZE=4096
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1436,25 +1814,13 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 # CONFIG_ESP32_COREDUMP_CHECKSUM_SHA256 is not set
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=32
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_MB_TIMER_PORT_ENABLED=y
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1466,7 +1832,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1477,6 +1842,12 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_HRT=y
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
@@ -1488,6 +1859,7 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
+# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
 # CONFIG_SUPPORT_TERMIOS is not set
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
 # End of deprecated options
diff --git a/projects/esp32_4m_min b/projects/esp32_4m_min
index 4e8c225..0c00c60 100644
--- a/projects/esp32_4m_min
+++ b/projects/esp32_4m_min
@@ -1,40 +1,235 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED="Not determined"
+CONFIG_SOC_TWAI_BRP_DIV_SUPPORTED="Not determined"
+CONFIG_SOC_DPORT_WORKAROUND="Not determined"
+CONFIG_SOC_CAPS_ECO_VER_MAX=301
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DAC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_SDMMC_HOST_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_EMAC_SUPPORTED=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL=5
+CONFIG_SOC_XTAL_SUPPORT_26M=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_XTAL_SUPPORT_AUTO_DETECT=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=16
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=2
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=20
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=2
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FPU=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DAC_CHAN_NUM=2
+CONFIG_SOC_DAC_RESOLUTION=8
+CONFIG_SOC_DAC_DMA_16BIT_ALIGN=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=40
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0xFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0xEF0FEA
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_APB=y
+CONFIG_SOC_I2S_NUM=2
+CONFIG_SOC_I2S_HW_VERSION_1=y
+CONFIG_SOC_I2S_SUPPORTS_APLL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
+CONFIG_SOC_I2S_PDM_MAX_RX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_ADC_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_ADC=y
+CONFIG_SOC_I2S_SUPPORTS_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA=y
+CONFIG_SOC_I2S_TRANS_SIZE_ALIGN_WORD=y
+CONFIG_SOC_I2S_LCD_I80_VARIANT=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=2
+CONFIG_SOC_LCD_I80_BUS_WIDTH=24
+CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_REF_TICK=y
+CONFIG_SOC_LEDC_SUPPORT_HS_MODE=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20
+CONFIG_SOC_MCPWM_GROUPS=2
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MMU_PERIPH_NUM=2
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=3
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=8
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=64
+CONFIG_SOC_RMT_SUPPORT_REF_TICK=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT=y
+CONFIG_SOC_RTCIO_PIN_COUNT=18
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED=y
+CONFIG_SOC_SPI_AS_CS_SUPPORTED=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_DMA_CHAN_NUM=2
+CONFIG_SOC_SPI_MAX_CS_NUM=3
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=8192
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=64
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TOUCH_VERSION_1=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=10
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT=y
+CONFIG_SOC_UART_NUM=3
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_REF_TICK=y
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SHA_SUPPORT_PARALLEL_ENG=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_192=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_SECURE_BOOT_V1=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_CLK_APLL_SUPPORTED=y
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MIN_HZ=350000000
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MAX_HZ=500000000
+CONFIG_SOC_APLL_MIN_HZ=5303031
+CONFIG_SOC_APLL_MAX_HZ=125000000
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_SDMMC_USE_IOMUX=y
+CONFIG_SOC_SDMMC_NUM_SLOTS=2
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_WIFI_NAN_SUPPORT=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BT_CLASSIC_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32"
 CONFIG_IDF_TARGET_ESP32=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -70,15 +265,33 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
+CONFIG_SECURE_BOOT_V1_SUPPORTED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_HAS_UART_BUF_SWITCH=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
@@ -100,22 +313,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -142,6 +346,7 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -153,7 +358,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NORM=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 CONFIG_COMPILER_STACK_CHECK=y
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -166,15 +371,13 @@ CONFIG_COMPILER_STACK_CHECK=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_UART2 is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -182,235 +385,163 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
+# Driver Configurations
 #
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
 
 #
-# Driver configurations
+# Legacy ADC Configuration
 #
-
-#
-# ADC configuration
-#
-# CONFIG_ADC_FORCE_XPD_FSM is not set
 CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# MCPWM configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
+CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CAL_LUT_ENABLE=y
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
 # CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set
 # CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
 
 #
-# UART configuration
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
-
-#
-# RTCIO configuration
-#
-# CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC is not set
-# end of RTCIO configuration
+# end of UART Configuration
 
 #
 # GPIO Configuration
 #
 # CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
 # end of GPIO Configuration
 
 #
-# GDMA Configuration
+# Sigma Delta Modulator Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
 
 #
-# eFuse Bit Manager
+# GPTimer Configuration
 #
-# CONFIG_EFUSE_CUSTOM_TABLE is not set
-# CONFIG_EFUSE_VIRTUAL is not set
-# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set
-CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
-# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set
-CONFIG_EFUSE_MAX_BLK_LEN=192
-# end of eFuse Bit Manager
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
 
 #
-# ESP-TLS
+# PCNT Configuration
 #
-CONFIG_ESP_TLS_USING_MBEDTLS=y
-# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
-# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
-# CONFIG_ESP_TLS_SERVER is not set
-# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
-# CONFIG_ESP_TLS_INSECURE is not set
-# end of ESP-TLS
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
 
 #
-# ESP32-specific
+# RMT Configuration
 #
-CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y
-CONFIG_ESP32_REV_MIN_0=y
-# CONFIG_ESP32_REV_MIN_1 is not set
-# CONFIG_ESP32_REV_MIN_2 is not set
-# CONFIG_ESP32_REV_MIN_3 is not set
-CONFIG_ESP32_REV_MIN=0
-CONFIG_ESP32_DPORT_WORKAROUND=y
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
-CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
-CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
-CONFIG_ESP32_SPIRAM_SUPPORT=y
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
 
 #
-# SPI RAM config
+# MCPWM Configuration
 #
-CONFIG_SPIRAM_TYPE_AUTO=y
-# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
-CONFIG_SPIRAM_SIZE=-1
-CONFIG_SPIRAM_SPEED_40M=y
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_BOOT_INIT=y
-CONFIG_SPIRAM_IGNORE_NOTFOUND=y
-# CONFIG_SPIRAM_USE_MEMMAP is not set
-# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
-CONFIG_SPIRAM_USE_MALLOC=y
-CONFIG_SPIRAM_MEMTEST=y
-CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
-# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
-CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
-# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
-# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set
-CONFIG_SPIRAM_CACHE_WORKAROUND=y
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
 
 #
-# SPIRAM cache workaround debugging
+# I2S Configuration
 #
-CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW=y
-# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST is not set
-# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS is not set
-# end of SPIRAM cache workaround debugging
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
 
 #
-# SPIRAM workaround libraries placement
+# DAC Configuration
 #
-CONFIG_SPIRAM_CACHE_LIBJMP_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBMATH_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBIO_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBTIME_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBCHAR_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBMEM_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBSTR_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBRAND_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBENV_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBFILE_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBMISC_IN_IRAM=y
-# end of SPIRAM workaround libraries placement
-
-CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
-CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
-# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
+# CONFIG_DAC_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_DAC_ISR_IRAM_SAFE is not set
+# CONFIG_DAC_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_DAC_ENABLE_DEBUG_LOG is not set
+CONFIG_DAC_DMA_AUTO_16BIT_ALIGN=y
+# end of DAC Configuration
+# end of Driver Configurations
 
 #
-# PSRAM clock and cs IO for ESP32-DOWD
+# eFuse Bit Manager
 #
-CONFIG_D0WD_PSRAM_CLK_IO=17
-CONFIG_D0WD_PSRAM_CS_IO=16
-# end of PSRAM clock and cs IO for ESP32-DOWD
+# CONFIG_EFUSE_CUSTOM_TABLE is not set
+# CONFIG_EFUSE_VIRTUAL is not set
+# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set
+CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
+# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set
+CONFIG_EFUSE_MAX_BLK_LEN=192
+# end of eFuse Bit Manager
 
 #
-# PSRAM clock and cs IO for ESP32-D2WD
+# ESP-TLS
 #
-CONFIG_D2WD_PSRAM_CLK_IO=9
-CONFIG_D2WD_PSRAM_CS_IO=10
-# end of PSRAM clock and cs IO for ESP32-D2WD
+CONFIG_ESP_TLS_USING_MBEDTLS=y
+# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
+# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
+# CONFIG_ESP_TLS_SERVER is not set
+# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
+# CONFIG_ESP_TLS_INSECURE is not set
+# end of ESP-TLS
 
 #
-# PSRAM clock and cs IO for ESP32-PICO
+# ADC and ADC Calibration
 #
-CONFIG_PICO_PSRAM_CS_IO=10
-# end of PSRAM clock and cs IO for ESP32-PICO
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
 
-# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set
-CONFIG_SPIRAM_SPIWP_SD3_PIN=7
-# CONFIG_SPIRAM_2T_MODE is not set
-# end of SPI RAM config
+#
+# ADC Calibration Configurations
+#
+CONFIG_ADC_CALI_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CALI_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CALI_LUT_ENABLE=y
+# end of ADC Calibration Configurations
 
-# CONFIG_ESP32_TRAX is not set
-CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0
-CONFIG_ESP32_DEBUG_OCDAWARE=y
-CONFIG_ESP32_BROWNOUT_DET=y
-CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set
-CONFIG_ESP32_BROWNOUT_DET_LVL=0
-CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
-CONFIG_ESP32_XTAL_FREQ_40=y
-# CONFIG_ESP32_XTAL_FREQ_26 is not set
-# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
-CONFIG_ESP32_XTAL_FREQ=40
-# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_ESP32_NO_BLOBS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
-# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
-CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
-# end of ESP32-specific
+CONFIG_ADC_DISABLE_DAC_OUTPUT=y
+# end of ADC and ADC Calibration
 
 #
-# ADC-Calibration
+# Wireless Coexistence
 #
-CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
-CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
-CONFIG_ADC_CAL_LUT_ENABLE=y
-# end of ADC-Calibration
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -435,6 +566,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -467,12 +599,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-CONFIG_OTA_ALLOW_HTTP=y
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP=y
 # end of ESP HTTPS OTA
 
 #
@@ -485,6 +619,26 @@ CONFIG_OTA_ALLOW_HTTP=y
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+CONFIG_ESP32_REV_MIN_0=y
+# CONFIG_ESP32_REV_MIN_1 is not set
+# CONFIG_ESP32_REV_MIN_1_1 is not set
+# CONFIG_ESP32_REV_MIN_2 is not set
+# CONFIG_ESP32_REV_MIN_3 is not set
+# CONFIG_ESP32_REV_MIN_3_1 is not set
+CONFIG_ESP32_REV_MIN=0
+CONFIG_ESP32_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32 Revision (Rev v3.99)
+#
+CONFIG_ESP32_REV_MAX_FULL=399
+CONFIG_ESP_REV_MAX_FULL=399
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -492,9 +646,11 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4
+# CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR is not set
 # end of MAC Config
 
 #
@@ -505,30 +661,48 @@ CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
 CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y
 CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
 # end of Sleep Config
 
 #
 # RTC Clock Config
 #
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
-CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
-CONFIG_ESP_IPC_ISR_ENABLE=y
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# Main XTAL Config
+#
+# CONFIG_XTAL_FREQ_26 is not set
+CONFIG_XTAL_FREQ_40=y
+# CONFIG_XTAL_FREQ_AUTO is not set
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -538,40 +712,158 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
 #
-# PHY
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
+#
+# PHY
+#
+CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP_PHY_MAX_TX_POWER=20
+CONFIG_ESP_PHY_REDUCE_TX_POWER=y
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
+# end of PHY
+
+#
+# Power Management
+#
+# CONFIG_PM_ENABLE is not set
+# end of Power Management
+
+#
+# ESP PSRAM
+#
+CONFIG_SPIRAM=y
+
+#
+# SPI RAM config
+#
+CONFIG_SPIRAM_MODE_QUAD=y
+CONFIG_SPIRAM_TYPE_AUTO=y
+# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
+CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED=40
+CONFIG_SPIRAM_BOOT_INIT=y
+CONFIG_SPIRAM_IGNORE_NOTFOUND=y
+# CONFIG_SPIRAM_USE_MEMMAP is not set
+# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
+CONFIG_SPIRAM_USE_MALLOC=y
+CONFIG_SPIRAM_MEMTEST=y
+CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
+# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
+CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
+# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
+# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set
+CONFIG_SPIRAM_CACHE_WORKAROUND=y
+
+#
+# SPIRAM cache workaround debugging
+#
+CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW=y
+# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST is not set
+# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS is not set
+# end of SPIRAM cache workaround debugging
+
+#
+# SPIRAM workaround libraries placement
+#
+CONFIG_SPIRAM_CACHE_LIBJMP_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBMATH_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBIO_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBTIME_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBCHAR_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBMEM_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBSTR_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBRAND_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBENV_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBFILE_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBMISC_IN_IRAM=y
+# end of SPIRAM workaround libraries placement
+
+CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
+CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
+# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
+
+#
+# PSRAM clock and cs IO for ESP32-DOWD
+#
+CONFIG_D0WD_PSRAM_CLK_IO=17
+CONFIG_D0WD_PSRAM_CS_IO=16
+# end of PSRAM clock and cs IO for ESP32-DOWD
+
+#
+# PSRAM clock and cs IO for ESP32-D2WD
+#
+CONFIG_D2WD_PSRAM_CLK_IO=9
+CONFIG_D2WD_PSRAM_CS_IO=10
+# end of PSRAM clock and cs IO for ESP32-D2WD
+
+#
+# PSRAM clock and cs IO for ESP32-PICO
+#
+CONFIG_PICO_PSRAM_CS_IO=10
+# end of PSRAM clock and cs IO for ESP32-PICO
+
+# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set
+CONFIG_SPIRAM_SPIWP_SD3_PIN=7
+# CONFIG_SPIRAM_2T_MODE is not set
+# end of SPI RAM config
+# end of ESP PSRAM
+
+#
+# ESP Ringbuf
+#
+# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
+# end of ESP Ringbuf
+
+#
+# ESP System Settings
 #
-CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
-# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
-CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
-CONFIG_ESP_PHY_MAX_TX_POWER=20
-CONFIG_ESP_PHY_REDUCE_TX_POWER=y
-# end of PHY
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240
 
 #
-# Power Management
+# Memory
 #
-# CONFIG_PM_ENABLE is not set
-# end of Power Management
+# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
 
 #
-# ESP Ringbuf
+# Non-backward compatible options
 #
-# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
-# end of ESP Ringbuf
+# CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM is not set
+# end of Non-backward compatible options
+# end of Memory
 
 #
-# ESP System Settings
+# Trace memory
 #
+# CONFIG_ESP32_TRAX is not set
+CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 
 #
 # Memory protection
@@ -596,17 +888,46 @@ CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
 CONFIG_ESP_INT_WDT_CHECK_CPU1=y
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 CONFIG_ESP_TASK_WDT_PANIC=y
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=15
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 # CONFIG_ESP_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP_DEBUG_OCDAWARE=y
 # CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is not set
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_0=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=0
+# end of Brownout Detector
+
+# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
+CONFIG_ESP_IPC_ISR_ENABLE=y
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -615,41 +936,68 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
-# CONFIG_ESP_TIMER_IMPL_FRC2 is not set
 CONFIG_ESP_TIMER_IMPL_TG0_LAC=y
 # end of High resolution timer (esp_timer)
 
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=16
-# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
-# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=16
+# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
 # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+# CONFIG_ESP_WIFI_NAN_ENABLE is not set
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -665,6 +1013,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=32
 CONFIG_ESP_COREDUMP_UART_DELAY=0
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 CONFIG_ESP_COREDUMP_DECODE_INFO=y
 # CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set
 CONFIG_ESP_COREDUMP_DECODE="info"
@@ -673,6 +1022,12 @@ CONFIG_ESP_COREDUMP_DECODE="info"
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+CONFIG_FATFS_LFN_NONE=y
+# CONFIG_FATFS_LFN_HEAP is not set
+# CONFIG_FATFS_LFN_STACK is not set
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -696,90 +1051,70 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-CONFIG_FATFS_LFN_NONE=y
-# CONFIG_FATFS_LFN_HEAP is not set
-# CONFIG_FATFS_LFN_STACK is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=2048
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-# CONFIG_FMB_PORT_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_FMB_PORT_TASK_AFFINITY_CPU0=y
-# CONFIG_FMB_PORT_TASK_AFFINITY_CPU1 is not set
-CONFIG_FMB_PORT_TASK_AFFINITY=0x0
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_FMB_TIMER_PORT_ENABLED=y
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 # CONFIG_FREERTOS_UNICORE is not set
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
-CONFIG_FREERTOS_CORETIMER_0=y
-# CONFIG_FREERTOS_CORETIMER_1 is not set
-CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_HZ=1000
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=8
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
 CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
 CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
+# end of Kernel
+
+#
+# Port
+#
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+# CONFIG_FREERTOS_FPU_IN_ISR is not set
+CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
+CONFIG_FREERTOS_CORETIMER_0=y
+# CONFIG_FREERTOS_CORETIMER_1 is not set
+CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
 # CONFIG_FREERTOS_RUN_TIME_STATS_USING_CPU_CLK is not set
-CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-# CONFIG_FREERTOS_FPU_IN_ISR is not set
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -787,9 +1122,11 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -801,20 +1138,13 @@ CONFIG_HEAP_POISONING_DISABLED=y
 CONFIG_HEAP_TRACING_OFF=y
 # CONFIG_HEAP_TRACING_STANDALONE is not set
 # CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -842,6 +1172,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 CONFIG_LWIP_IRAM_OPTIMIZATION=y
@@ -857,17 +1188,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 CONFIG_LWIP_IP4_REASSEMBLY=y
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -878,6 +1213,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 # CONFIG_LWIP_IPV6_AUTOCONFIG is not set
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -903,7 +1239,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -957,6 +1292,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -974,6 +1310,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -993,13 +1332,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -1021,6 +1362,7 @@ CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -1037,7 +1379,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -1046,16 +1387,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -1064,9 +1400,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -1086,6 +1419,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -1110,27 +1444,11 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1152,6 +1470,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1160,21 +1482,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
-# CONFIG_OPENSSL_ASSERT_EXIT is not set
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1188,6 +1509,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1197,7 +1526,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
 # CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
@@ -1208,9 +1536,21 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1267,9 +1607,16 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
+#
+# Ultra Low Power (ULP) Co-processor
+#
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
+
 #
 # Unity unit testing library
 #
@@ -1282,6 +1629,11 @@ CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
 # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
 # end of Unity unit testing library
 
+#
+# Root Hub configuration
+#
+# end of Root Hub configuration
+
 #
 # Virtual file system
 #
@@ -1312,22 +1664,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1402,14 +1742,14 @@ CONFIG_UDNS=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
+# CONFIG_ESP32_NO_BLOBS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1423,16 +1763,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=3
 # CONFIG_FLASHMODE_QOUT is not set
 # CONFIG_FLASHMODE_DIO is not set
 CONFIG_FLASHMODE_DOUT=y
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1445,55 +1779,56 @@ CONFIG_STACK_CHECK_NORM=y
 # CONFIG_STACK_CHECK_ALL is not set
 CONFIG_STACK_CHECK=y
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
 CONFIG_ADC2_DISABLE_DAC=y
-CONFIG_SPIRAM_SUPPORT=y
-# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ULP_COPROC_ENABLED is not set
-CONFIG_ULP_COPROC_RESERVE_MEM=0
-CONFIG_BROWNOUT_DET=y
-CONFIG_BROWNOUT_DET_LVL_SEL_0=y
-# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set
-CONFIG_BROWNOUT_DET_LVL=0
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
-# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_NO_BLOBS is not set
-# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+CONFIG_OTA_ALLOW_HTTP=y
 # CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set
 CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
 CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
+# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
+CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
+# CONFIG_ESP32_XTAL_FREQ_26 is not set
+CONFIG_ESP32_XTAL_FREQ_40=y
+# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
+CONFIG_ESP32_XTAL_FREQ=40
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+CONFIG_REDUCE_PHY_TX_POWER=y
 CONFIG_ESP32_REDUCE_PHY_TX_POWER=y
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
+CONFIG_SPIRAM_SUPPORT=y
+CONFIG_ESP32_SPIRAM_SUPPORT=y
+# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
+CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
+CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
+CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+# CONFIG_ESP32_PANIC_PRINT_HALT is not set
+CONFIG_ESP32_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP32_PANIC_GDBSTUB is not set
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 CONFIG_CONSOLE_UART_DEFAULT=y
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART=y
 CONFIG_CONSOLE_UART_NUM=0
@@ -1502,12 +1837,72 @@ CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
 CONFIG_INT_WDT_CHECK_CPU1=y
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 CONFIG_TASK_WDT_PANIC=y
 CONFIG_TASK_WDT_TIMEOUT_S=15
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
+CONFIG_ESP32_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_0=y
+CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set
+CONFIG_BROWNOUT_DET_LVL=0
+CONFIG_ESP32_BROWNOUT_DET_LVL=0
+# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_IPC_TASK_STACK_SIZE=1024
 CONFIG_TIMER_TASK_STACK_SIZE=4096
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1518,28 +1913,16 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=32
 CONFIG_ESP32_CORE_DUMP_UART_DELAY=0
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y
 # CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set
 CONFIG_ESP32_CORE_DUMP_DECODE="info"
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_MB_TIMER_PORT_ENABLED=y
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1551,7 +1934,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1562,6 +1944,12 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_HRT=y
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
@@ -1573,6 +1961,7 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
+# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
 CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
 CONFIG_SUPPORT_TERMIOS=y
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
diff --git a/projects/esp32_8m_full b/projects/esp32_8m_full
index 3e16967..bb9a663 100644
--- a/projects/esp32_8m_full
+++ b/projects/esp32_8m_full
@@ -1,40 +1,235 @@
 #
 # Automatically generated file. DO NOT EDIT.
-# Espressif IoT Development Framework (ESP-IDF) Project Configuration
-#
+# Espressif IoT Development Framework (ESP-IDF) 5.1.0 Project Configuration
+#
+CONFIG_SOC_BROWNOUT_RESET_SUPPORTED="Not determined"
+CONFIG_SOC_TWAI_BRP_DIV_SUPPORTED="Not determined"
+CONFIG_SOC_DPORT_WORKAROUND="Not determined"
+CONFIG_SOC_CAPS_ECO_VER_MAX=301
+CONFIG_SOC_ADC_SUPPORTED=y
+CONFIG_SOC_DAC_SUPPORTED=y
+CONFIG_SOC_UART_SUPPORTED=y
+CONFIG_SOC_MCPWM_SUPPORTED=y
+CONFIG_SOC_GPTIMER_SUPPORTED=y
+CONFIG_SOC_SDMMC_HOST_SUPPORTED=y
+CONFIG_SOC_BT_SUPPORTED=y
+CONFIG_SOC_PCNT_SUPPORTED=y
+CONFIG_SOC_WIFI_SUPPORTED=y
+CONFIG_SOC_SDIO_SLAVE_SUPPORTED=y
+CONFIG_SOC_TWAI_SUPPORTED=y
+CONFIG_SOC_EMAC_SUPPORTED=y
+CONFIG_SOC_ULP_SUPPORTED=y
+CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y
+CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y
+CONFIG_SOC_RTC_MEM_SUPPORTED=y
+CONFIG_SOC_I2S_SUPPORTED=y
+CONFIG_SOC_RMT_SUPPORTED=y
+CONFIG_SOC_SDM_SUPPORTED=y
+CONFIG_SOC_GPSPI_SUPPORTED=y
+CONFIG_SOC_LEDC_SUPPORTED=y
+CONFIG_SOC_I2C_SUPPORTED=y
+CONFIG_SOC_SUPPORT_COEXISTENCE=y
+CONFIG_SOC_AES_SUPPORTED=y
+CONFIG_SOC_MPI_SUPPORTED=y
+CONFIG_SOC_SHA_SUPPORTED=y
+CONFIG_SOC_FLASH_ENC_SUPPORTED=y
+CONFIG_SOC_SECURE_BOOT_SUPPORTED=y
+CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y
+CONFIG_SOC_BOD_SUPPORTED=y
+CONFIG_SOC_ULP_FSM_SUPPORTED=y
+CONFIG_SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL=5
+CONFIG_SOC_XTAL_SUPPORT_26M=y
+CONFIG_SOC_XTAL_SUPPORT_40M=y
+CONFIG_SOC_XTAL_SUPPORT_AUTO_DETECT=y
+CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y
+CONFIG_SOC_ADC_DMA_SUPPORTED=y
+CONFIG_SOC_ADC_PERIPH_NUM=2
+CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10
+CONFIG_SOC_ADC_ATTEN_NUM=4
+CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2
+CONFIG_SOC_ADC_PATT_LEN_MAX=16
+CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12
+CONFIG_SOC_ADC_DIGI_RESULT_BYTES=2
+CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=2
+CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=20
+CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=9
+CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12
+CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y
+CONFIG_SOC_CPU_CORES_NUM=2
+CONFIG_SOC_CPU_INTR_NUM=32
+CONFIG_SOC_CPU_HAS_FPU=y
+CONFIG_SOC_CPU_BREAKPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINTS_NUM=2
+CONFIG_SOC_CPU_WATCHPOINT_SIZE=64
+CONFIG_SOC_DAC_CHAN_NUM=2
+CONFIG_SOC_DAC_RESOLUTION=8
+CONFIG_SOC_DAC_DMA_16BIT_ALIGN=y
+CONFIG_SOC_GPIO_PORT=1
+CONFIG_SOC_GPIO_PIN_COUNT=40
+CONFIG_SOC_GPIO_VALID_GPIO_MASK=0xFFFFFFFFFF
+CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0xEF0FEA
+CONFIG_SOC_I2C_NUM=2
+CONFIG_SOC_I2C_FIFO_LEN=32
+CONFIG_SOC_I2C_SUPPORT_SLAVE=y
+CONFIG_SOC_I2C_SUPPORT_APB=y
+CONFIG_SOC_I2S_NUM=2
+CONFIG_SOC_I2S_HW_VERSION_1=y
+CONFIG_SOC_I2S_SUPPORTS_APLL=y
+CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y
+CONFIG_SOC_I2S_SUPPORTS_PDM=y
+CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y
+CONFIG_SOC_I2S_PDM_MAX_TX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y
+CONFIG_SOC_I2S_PDM_MAX_RX_LINES=1
+CONFIG_SOC_I2S_SUPPORTS_ADC_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_ADC=y
+CONFIG_SOC_I2S_SUPPORTS_DAC=y
+CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA=y
+CONFIG_SOC_I2S_TRANS_SIZE_ALIGN_WORD=y
+CONFIG_SOC_I2S_LCD_I80_VARIANT=y
+CONFIG_SOC_LCD_I80_SUPPORTED=y
+CONFIG_SOC_LCD_I80_BUSES=2
+CONFIG_SOC_LCD_I80_BUS_WIDTH=24
+CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX=y
+CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y
+CONFIG_SOC_LEDC_SUPPORT_REF_TICK=y
+CONFIG_SOC_LEDC_SUPPORT_HS_MODE=y
+CONFIG_SOC_LEDC_CHANNEL_NUM=8
+CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=20
+CONFIG_SOC_MCPWM_GROUPS=2
+CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3
+CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3
+CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2
+CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3
+CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y
+CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3
+CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3
+CONFIG_SOC_MMU_PERIPH_NUM=2
+CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=3
+CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000
+CONFIG_SOC_MPU_REGIONS_MAX_NUM=8
+CONFIG_SOC_PCNT_GROUPS=1
+CONFIG_SOC_PCNT_UNITS_PER_GROUP=8
+CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2
+CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2
+CONFIG_SOC_RMT_GROUPS=1
+CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=8
+CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8
+CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=64
+CONFIG_SOC_RMT_SUPPORT_REF_TICK=y
+CONFIG_SOC_RMT_SUPPORT_APB=y
+CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT=y
+CONFIG_SOC_RTCIO_PIN_COUNT=18
+CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y
+CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y
+CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y
+CONFIG_SOC_SDM_GROUPS=1
+CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8
+CONFIG_SOC_SDM_CLK_SUPPORT_APB=y
+CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED=y
+CONFIG_SOC_SPI_AS_CS_SUPPORTED=y
+CONFIG_SOC_SPI_PERIPH_NUM=3
+CONFIG_SOC_SPI_DMA_CHAN_NUM=2
+CONFIG_SOC_SPI_MAX_CS_NUM=3
+CONFIG_SOC_SPI_SUPPORT_CLK_APB=y
+CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64
+CONFIG_SOC_SPI_MAX_PRE_DIVIDER=8192
+CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y
+CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y
+CONFIG_SOC_TIMER_GROUPS=2
+CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2
+CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=64
+CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4
+CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y
+CONFIG_SOC_TOUCH_VERSION_1=y
+CONFIG_SOC_TOUCH_SENSOR_NUM=10
+CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF
+CONFIG_SOC_TWAI_CONTROLLER_NUM=1
+CONFIG_SOC_TWAI_BRP_MIN=2
+CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y
+CONFIG_SOC_TWAI_SUPPORT_MULTI_ADDRESS_LAYOUT=y
+CONFIG_SOC_UART_NUM=3
+CONFIG_SOC_UART_SUPPORT_APB_CLK=y
+CONFIG_SOC_UART_SUPPORT_REF_TICK=y
+CONFIG_SOC_UART_FIFO_LEN=128
+CONFIG_SOC_UART_BITRATE_MAX=5000000
+CONFIG_SOC_SPIRAM_SUPPORTED=y
+CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y
+CONFIG_SOC_SHA_SUPPORT_PARALLEL_ENG=y
+CONFIG_SOC_SHA_SUPPORT_SHA1=y
+CONFIG_SOC_SHA_SUPPORT_SHA256=y
+CONFIG_SOC_SHA_SUPPORT_SHA384=y
+CONFIG_SOC_SHA_SUPPORT_SHA512=y
+CONFIG_SOC_RSA_MAX_BIT_LEN=4096
+CONFIG_SOC_AES_SUPPORT_AES_128=y
+CONFIG_SOC_AES_SUPPORT_AES_192=y
+CONFIG_SOC_AES_SUPPORT_AES_256=y
+CONFIG_SOC_SECURE_BOOT_V1=y
+CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=y
+CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32
+CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21
+CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y
+CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD=y
+CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y
+CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y
+CONFIG_SOC_PM_SUPPORT_MODEM_PD=y
+CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y
+CONFIG_SOC_CLK_APLL_SUPPORTED=y
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MIN_HZ=350000000
+CONFIG_SOC_APLL_MULTIPLIER_OUT_MAX_HZ=500000000
+CONFIG_SOC_APLL_MIN_HZ=5303031
+CONFIG_SOC_APLL_MAX_HZ=125000000
+CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y
+CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y
+CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y
+CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y
+CONFIG_SOC_SDMMC_USE_IOMUX=y
+CONFIG_SOC_SDMMC_NUM_SLOTS=2
+CONFIG_SOC_WIFI_WAPI_SUPPORT=y
+CONFIG_SOC_WIFI_CSI_SUPPORT=y
+CONFIG_SOC_WIFI_MESH_SUPPORT=y
+CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y
+CONFIG_SOC_WIFI_NAN_SUPPORT=y
+CONFIG_SOC_BLE_SUPPORTED=y
+CONFIG_SOC_BLE_MESH_SUPPORTED=y
+CONFIG_SOC_BT_CLASSIC_SUPPORTED=y
+CONFIG_SOC_BLUFI_SUPPORTED=y
+CONFIG_SOC_ULP_HAS_ADC=y
 CONFIG_IDF_CMAKE=y
 CONFIG_IDF_TARGET_ARCH_XTENSA=y
+CONFIG_IDF_TARGET_ARCH="xtensa"
 CONFIG_IDF_TARGET="esp32"
 CONFIG_IDF_TARGET_ESP32=y
 CONFIG_IDF_FIRMWARE_CHIP_ID=0x0000
 
-#
-# SDK tool configuration
-#
-CONFIG_SDK_TOOLPREFIX="xtensa-esp32-elf-"
-# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set
-# end of SDK tool configuration
-
 #
 # Build type
 #
 CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y
-# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_APP_BUILD_TYPE_RAM is not set
 CONFIG_APP_BUILD_GENERATE_BINARIES=y
 CONFIG_APP_BUILD_BOOTLOADER=y
 CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y
+# CONFIG_APP_REPRODUCIBLE_BUILD is not set
+# CONFIG_APP_NO_BLOBS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # end of Build type
 
-#
-# Application manager
-#
-CONFIG_APP_COMPILE_TIME_DATE=y
-# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
-# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
-# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
-CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
-# end of Application manager
-
 #
 # Bootloader config
 #
@@ -70,15 +265,33 @@ CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y
 #
 # Security features
 #
+CONFIG_SECURE_BOOT_V1_SUPPORTED=y
 # CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set
 # CONFIG_SECURE_BOOT is not set
 # CONFIG_SECURE_FLASH_ENC_ENABLED is not set
 # end of Security features
 
+#
+# Application manager
+#
+CONFIG_APP_COMPILE_TIME_DATE=y
+# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set
+# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set
+# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set
+CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16
+# end of Application manager
+
+CONFIG_ESP_ROM_HAS_CRC_LE=y
+CONFIG_ESP_ROM_HAS_CRC_BE=y
+CONFIG_ESP_ROM_HAS_MZ_CRC32=y
+CONFIG_ESP_ROM_HAS_JPEG_DECODE=y
+CONFIG_ESP_ROM_HAS_UART_BUF_SWITCH=y
+CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y
+CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y
+
 #
 # Serial flasher config
 #
-CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200
 # CONFIG_ESPTOOLPY_NO_STUB is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set
 # CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set
@@ -100,22 +313,13 @@ CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y
 # CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set
 # CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set
 CONFIG_ESPTOOLPY_FLASHSIZE="8MB"
-CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y
+# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set
 CONFIG_ESPTOOLPY_BEFORE_RESET=y
 # CONFIG_ESPTOOLPY_BEFORE_NORESET is not set
 CONFIG_ESPTOOLPY_BEFORE="default_reset"
 CONFIG_ESPTOOLPY_AFTER_RESET=y
 # CONFIG_ESPTOOLPY_AFTER_NORESET is not set
 CONFIG_ESPTOOLPY_AFTER="hard_reset"
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B=y
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set
-# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set
-CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_ESPTOOLPY_MONITOR_BAUD=115200
 # end of Serial flasher config
 
@@ -142,6 +346,7 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set
 # CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set
+CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2
 # CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set
 CONFIG_COMPILER_HIDE_PATHS_MACROS=y
@@ -153,7 +358,7 @@ CONFIG_COMPILER_STACK_CHECK_MODE_NORM=y
 # CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set
 CONFIG_COMPILER_STACK_CHECK=y
 # CONFIG_COMPILER_WARN_WRITE_STRINGS is not set
-# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set
+# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set
 # CONFIG_COMPILER_DUMP_RTL_FILES is not set
 # end of Compiler options
 
@@ -166,15 +371,13 @@ CONFIG_COMPILER_STACK_CHECK=y
 #
 # CONFIG_APPTRACE_DEST_JTAG is not set
 CONFIG_APPTRACE_DEST_NONE=y
+# CONFIG_APPTRACE_DEST_UART1 is not set
+# CONFIG_APPTRACE_DEST_UART2 is not set
+CONFIG_APPTRACE_DEST_UART_NONE=y
+CONFIG_APPTRACE_UART_TASK_PRIO=1
 CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Application Level Tracing
 
-#
-# ESP-ASIO
-#
-# CONFIG_ASIO_SSL_SUPPORT is not set
-# end of ESP-ASIO
-
 #
 # Bluetooth
 #
@@ -182,235 +385,163 @@ CONFIG_APPTRACE_LOCK_ENABLE=y
 # end of Bluetooth
 
 #
-# CoAP Configuration
+# Driver Configurations
 #
-CONFIG_COAP_MBEDTLS_PSK=y
-# CONFIG_COAP_MBEDTLS_PKI is not set
-# CONFIG_COAP_MBEDTLS_DEBUG is not set
-CONFIG_COAP_LOG_DEFAULT_LEVEL=0
-# end of CoAP Configuration
 
 #
-# Driver configurations
+# Legacy ADC Configuration
 #
-
-#
-# ADC configuration
-#
-# CONFIG_ADC_FORCE_XPD_FSM is not set
 CONFIG_ADC_DISABLE_DAC=y
-# end of ADC configuration
+# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set
 
 #
-# MCPWM configuration
+# Legacy ADC Calibration Configuration
 #
-# CONFIG_MCPWM_ISR_IN_IRAM is not set
-# end of MCPWM configuration
+CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CAL_LUT_ENABLE=y
+# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set
+# end of Legacy ADC Calibration Configuration
+# end of Legacy ADC Configuration
 
 #
-# SPI configuration
+# SPI Configuration
 #
 # CONFIG_SPI_MASTER_IN_IRAM is not set
 CONFIG_SPI_MASTER_ISR_IN_IRAM=y
 # CONFIG_SPI_SLAVE_IN_IRAM is not set
 CONFIG_SPI_SLAVE_ISR_IN_IRAM=y
-# end of SPI configuration
+# end of SPI Configuration
 
 #
-# TWAI configuration
+# TWAI Configuration
 #
 # CONFIG_TWAI_ISR_IN_IRAM is not set
 # CONFIG_TWAI_ERRATA_FIX_BUS_OFF_REC is not set
 # CONFIG_TWAI_ERRATA_FIX_TX_INTR_LOST is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FRAME_INVALID is not set
 # CONFIG_TWAI_ERRATA_FIX_RX_FIFO_CORRUPT is not set
-# end of TWAI configuration
+CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y
+# end of TWAI Configuration
 
 #
-# UART configuration
+# UART Configuration
 #
 # CONFIG_UART_ISR_IN_IRAM is not set
-# end of UART configuration
-
-#
-# RTCIO configuration
-#
-# CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC is not set
-# end of RTCIO configuration
+# end of UART Configuration
 
 #
 # GPIO Configuration
 #
 # CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL is not set
+# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set
 # end of GPIO Configuration
 
 #
-# GDMA Configuration
+# Sigma Delta Modulator Configuration
 #
-# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set
-# CONFIG_GDMA_ISR_IRAM_SAFE is not set
-# end of GDMA Configuration
-# end of Driver configurations
+# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_SDM_ENABLE_DEBUG_LOG is not set
+# end of Sigma Delta Modulator Configuration
 
 #
-# eFuse Bit Manager
+# GPTimer Configuration
 #
-# CONFIG_EFUSE_CUSTOM_TABLE is not set
-# CONFIG_EFUSE_VIRTUAL is not set
-# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set
-CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
-# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set
-CONFIG_EFUSE_MAX_BLK_LEN=192
-# end of eFuse Bit Manager
+# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set
+# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set
+# end of GPTimer Configuration
 
 #
-# ESP-TLS
+# PCNT Configuration
 #
-CONFIG_ESP_TLS_USING_MBEDTLS=y
-# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
-# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
-# CONFIG_ESP_TLS_SERVER is not set
-# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
-# CONFIG_ESP_TLS_INSECURE is not set
-# end of ESP-TLS
+# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_PCNT_ISR_IRAM_SAFE is not set
+# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set
+# end of PCNT Configuration
 
 #
-# ESP32-specific
+# RMT Configuration
 #
-CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y
-CONFIG_ESP32_REV_MIN_0=y
-# CONFIG_ESP32_REV_MIN_1 is not set
-# CONFIG_ESP32_REV_MIN_2 is not set
-# CONFIG_ESP32_REV_MIN_3 is not set
-CONFIG_ESP32_REV_MIN=0
-CONFIG_ESP32_DPORT_WORKAROUND=y
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
-# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
-CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
-CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
-CONFIG_ESP32_SPIRAM_SUPPORT=y
+# CONFIG_RMT_ISR_IRAM_SAFE is not set
+# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_RMT_ENABLE_DEBUG_LOG is not set
+# end of RMT Configuration
 
 #
-# SPI RAM config
+# MCPWM Configuration
 #
-CONFIG_SPIRAM_TYPE_AUTO=y
-# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
-# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
-CONFIG_SPIRAM_SIZE=-1
-CONFIG_SPIRAM_SPEED_40M=y
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_BOOT_INIT=y
-CONFIG_SPIRAM_IGNORE_NOTFOUND=y
-# CONFIG_SPIRAM_USE_MEMMAP is not set
-# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
-CONFIG_SPIRAM_USE_MALLOC=y
-CONFIG_SPIRAM_MEMTEST=y
-CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
-# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
-CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
-# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
-# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set
-CONFIG_SPIRAM_CACHE_WORKAROUND=y
+# CONFIG_MCPWM_ISR_IRAM_SAFE is not set
+# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set
+# end of MCPWM Configuration
 
 #
-# SPIRAM cache workaround debugging
+# I2S Configuration
 #
-CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW=y
-# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST is not set
-# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS is not set
-# end of SPIRAM cache workaround debugging
+# CONFIG_I2S_ISR_IRAM_SAFE is not set
+# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_I2S_ENABLE_DEBUG_LOG is not set
+# end of I2S Configuration
 
 #
-# SPIRAM workaround libraries placement
+# DAC Configuration
 #
-# CONFIG_SPIRAM_CACHE_LIBJMP_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBMATH_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBIO_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBTIME_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBCHAR_IN_IRAM is not set
-CONFIG_SPIRAM_CACHE_LIBMEM_IN_IRAM=y
-CONFIG_SPIRAM_CACHE_LIBSTR_IN_IRAM=y
-# CONFIG_SPIRAM_CACHE_LIBRAND_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBENV_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBFILE_IN_IRAM is not set
-# CONFIG_SPIRAM_CACHE_LIBMISC_IN_IRAM is not set
-# end of SPIRAM workaround libraries placement
-
-CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
-CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
-# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
+# CONFIG_DAC_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_DAC_ISR_IRAM_SAFE is not set
+# CONFIG_DAC_SUPPRESS_DEPRECATE_WARN is not set
+# CONFIG_DAC_ENABLE_DEBUG_LOG is not set
+CONFIG_DAC_DMA_AUTO_16BIT_ALIGN=y
+# end of DAC Configuration
+# end of Driver Configurations
 
 #
-# PSRAM clock and cs IO for ESP32-DOWD
+# eFuse Bit Manager
 #
-CONFIG_D0WD_PSRAM_CLK_IO=17
-CONFIG_D0WD_PSRAM_CS_IO=16
-# end of PSRAM clock and cs IO for ESP32-DOWD
+# CONFIG_EFUSE_CUSTOM_TABLE is not set
+# CONFIG_EFUSE_VIRTUAL is not set
+# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set
+CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y
+# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set
+CONFIG_EFUSE_MAX_BLK_LEN=192
+# end of eFuse Bit Manager
 
 #
-# PSRAM clock and cs IO for ESP32-D2WD
+# ESP-TLS
 #
-CONFIG_D2WD_PSRAM_CLK_IO=9
-CONFIG_D2WD_PSRAM_CS_IO=10
-# end of PSRAM clock and cs IO for ESP32-D2WD
+CONFIG_ESP_TLS_USING_MBEDTLS=y
+# CONFIG_ESP_TLS_USE_SECURE_ELEMENT is not set
+# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set
+# CONFIG_ESP_TLS_SERVER is not set
+# CONFIG_ESP_TLS_PSK_VERIFICATION is not set
+# CONFIG_ESP_TLS_INSECURE is not set
+# end of ESP-TLS
 
 #
-# PSRAM clock and cs IO for ESP32-PICO
+# ADC and ADC Calibration
 #
-CONFIG_PICO_PSRAM_CS_IO=10
-# end of PSRAM clock and cs IO for ESP32-PICO
+# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set
+# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set
 
-# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set
-CONFIG_SPIRAM_SPIWP_SD3_PIN=7
-# CONFIG_SPIRAM_2T_MODE is not set
-# end of SPI RAM config
+#
+# ADC Calibration Configurations
+#
+CONFIG_ADC_CALI_EFUSE_TP_ENABLE=y
+CONFIG_ADC_CALI_EFUSE_VREF_ENABLE=y
+CONFIG_ADC_CALI_LUT_ENABLE=y
+# end of ADC Calibration Configurations
 
-# CONFIG_ESP32_TRAX is not set
-CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
-CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0
-CONFIG_ESP32_DEBUG_OCDAWARE=y
-CONFIG_ESP32_BROWNOUT_DET=y
-CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set
-CONFIG_ESP32_BROWNOUT_DET_LVL=0
-CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
-# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
-# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
-CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
-# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
-# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
-CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
-CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
-CONFIG_ESP32_XTAL_FREQ_40=y
-# CONFIG_ESP32_XTAL_FREQ_26 is not set
-# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
-CONFIG_ESP32_XTAL_FREQ=40
-# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_ESP32_NO_BLOBS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
-# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
-# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
-CONFIG_ESP32_DPORT_DIS_INTERRUPT_LVL=5
-# end of ESP32-specific
+CONFIG_ADC_DISABLE_DAC_OUTPUT=y
+# end of ADC and ADC Calibration
 
 #
-# ADC-Calibration
+# Wireless Coexistence
 #
-CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y
-CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y
-CONFIG_ADC_CAL_LUT_ENABLE=y
-# end of ADC-Calibration
+# end of Wireless Coexistence
 
 #
 # Common ESP-related
@@ -435,6 +566,7 @@ CONFIG_ETH_USE_SPI_ETHERNET=y
 # CONFIG_ETH_SPI_ETHERNET_W5500 is not set
 # CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set
 # CONFIG_ETH_USE_OPENETH is not set
+# CONFIG_ETH_TRANSMIT_MUTEX is not set
 # end of Ethernet
 
 #
@@ -467,12 +599,14 @@ CONFIG_HTTPD_ERR_RESP_NO_DELAY=y
 CONFIG_HTTPD_PURGE_BUF_LEN=32
 # CONFIG_HTTPD_LOG_PURGE_DATA is not set
 # CONFIG_HTTPD_WS_SUPPORT is not set
+# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set
 # end of HTTP Server
 
 #
 # ESP HTTPS OTA
 #
-CONFIG_OTA_ALLOW_HTTP=y
+# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set
+CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP=y
 # end of ESP HTTPS OTA
 
 #
@@ -485,6 +619,26 @@ CONFIG_OTA_ALLOW_HTTP=y
 # Hardware Settings
 #
 
+#
+# Chip revision
+#
+CONFIG_ESP32_REV_MIN_0=y
+# CONFIG_ESP32_REV_MIN_1 is not set
+# CONFIG_ESP32_REV_MIN_1_1 is not set
+# CONFIG_ESP32_REV_MIN_2 is not set
+# CONFIG_ESP32_REV_MIN_3 is not set
+# CONFIG_ESP32_REV_MIN_3_1 is not set
+CONFIG_ESP32_REV_MIN=0
+CONFIG_ESP32_REV_MIN_FULL=0
+CONFIG_ESP_REV_MIN_FULL=0
+
+#
+# Maximum Supported ESP32 Revision (Rev v3.99)
+#
+CONFIG_ESP32_REV_MAX_FULL=399
+CONFIG_ESP_REV_MAX_FULL=399
+# end of Chip revision
+
 #
 # MAC Config
 #
@@ -492,9 +646,11 @@ CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y
 CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y
+CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 # CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_TWO is not set
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR=y
 CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES=4
+# CONFIG_ESP_MAC_IGNORE_MAC_CRC_ERROR is not set
 # end of MAC Config
 
 #
@@ -505,30 +661,48 @@ CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y
 CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y
 CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y
 # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set
+CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000
 # end of Sleep Config
 
 #
 # RTC Clock Config
 #
+CONFIG_RTC_CLK_SRC_INT_RC=y
+# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set
+CONFIG_RTC_CLK_CAL_CYCLES=1024
 # end of RTC Clock Config
-# end of Hardware Settings
 
 #
-# IPC (Inter-Processor Call)
+# Peripheral Control
 #
-CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
-CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
-CONFIG_ESP_IPC_ISR_ENABLE=y
-# end of IPC (Inter-Processor Call)
+CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y
+# end of Peripheral Control
+
+#
+# Main XTAL Config
+#
+# CONFIG_XTAL_FREQ_26 is not set
+CONFIG_XTAL_FREQ_40=y
+# CONFIG_XTAL_FREQ_AUTO is not set
+CONFIG_XTAL_FREQ=40
+# end of Main XTAL Config
+# end of Hardware Settings
 
 #
 # LCD and Touch Panel
 #
 
+#
+# LCD Touch Drivers are maintained in the IDF Component Registry
+#
+
 #
 # LCD Peripheral Configuration
 #
 CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
+# CONFIG_LCD_ENABLE_DEBUG_LOG is not set
 # end of LCD Peripheral Configuration
 # end of LCD and Touch Panel
 
@@ -538,40 +712,158 @@ CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32
 CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120
 CONFIG_ESP_NETIF_TCPIP_LWIP=y
 # CONFIG_ESP_NETIF_LOOPBACK is not set
-CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER=y
+CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y
+# CONFIG_ESP_NETIF_L2_TAP is not set
+# CONFIG_ESP_NETIF_BRIDGE_EN is not set
 # end of ESP NETIF Adapter
 
 #
-# PHY
+# Partition API Configuration
+#
+# end of Partition API Configuration
+
+#
+# PHY
+#
+CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
+# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
+CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
+CONFIG_ESP_PHY_MAX_TX_POWER=20
+CONFIG_ESP_PHY_REDUCE_TX_POWER=y
+CONFIG_ESP_PHY_RF_CAL_PARTIAL=y
+# CONFIG_ESP_PHY_RF_CAL_NONE is not set
+# CONFIG_ESP_PHY_RF_CAL_FULL is not set
+CONFIG_ESP_PHY_CALIBRATION_MODE=0
+# end of PHY
+
+#
+# Power Management
+#
+# CONFIG_PM_ENABLE is not set
+# end of Power Management
+
+#
+# ESP PSRAM
+#
+CONFIG_SPIRAM=y
+
+#
+# SPI RAM config
+#
+CONFIG_SPIRAM_MODE_QUAD=y
+CONFIG_SPIRAM_TYPE_AUTO=y
+# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set
+# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set
+CONFIG_SPIRAM_SPEED_40M=y
+CONFIG_SPIRAM_SPEED=40
+CONFIG_SPIRAM_BOOT_INIT=y
+CONFIG_SPIRAM_IGNORE_NOTFOUND=y
+# CONFIG_SPIRAM_USE_MEMMAP is not set
+# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set
+CONFIG_SPIRAM_USE_MALLOC=y
+CONFIG_SPIRAM_MEMTEST=y
+CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384
+# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
+CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768
+# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
+# CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY is not set
+CONFIG_SPIRAM_CACHE_WORKAROUND=y
+
+#
+# SPIRAM cache workaround debugging
+#
+CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW=y
+# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_DUPLDST is not set
+# CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_NOPS is not set
+# end of SPIRAM cache workaround debugging
+
+#
+# SPIRAM workaround libraries placement
+#
+# CONFIG_SPIRAM_CACHE_LIBJMP_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBMATH_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBNUMPARSER_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBIO_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBTIME_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBCHAR_IN_IRAM is not set
+CONFIG_SPIRAM_CACHE_LIBMEM_IN_IRAM=y
+CONFIG_SPIRAM_CACHE_LIBSTR_IN_IRAM=y
+# CONFIG_SPIRAM_CACHE_LIBRAND_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBENV_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBFILE_IN_IRAM is not set
+# CONFIG_SPIRAM_CACHE_LIBMISC_IN_IRAM is not set
+# end of SPIRAM workaround libraries placement
+
+CONFIG_SPIRAM_BANKSWITCH_ENABLE=y
+CONFIG_SPIRAM_BANKSWITCH_RESERVE=8
+# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set
+
+#
+# PSRAM clock and cs IO for ESP32-DOWD
+#
+CONFIG_D0WD_PSRAM_CLK_IO=17
+CONFIG_D0WD_PSRAM_CS_IO=16
+# end of PSRAM clock and cs IO for ESP32-DOWD
+
+#
+# PSRAM clock and cs IO for ESP32-D2WD
+#
+CONFIG_D2WD_PSRAM_CLK_IO=9
+CONFIG_D2WD_PSRAM_CS_IO=10
+# end of PSRAM clock and cs IO for ESP32-D2WD
+
+#
+# PSRAM clock and cs IO for ESP32-PICO
+#
+CONFIG_PICO_PSRAM_CS_IO=10
+# end of PSRAM clock and cs IO for ESP32-PICO
+
+# CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN is not set
+CONFIG_SPIRAM_SPIWP_SD3_PIN=7
+# CONFIG_SPIRAM_2T_MODE is not set
+# end of SPI RAM config
+# end of ESP PSRAM
+
+#
+# ESP Ringbuf
+#
+# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
+# end of ESP Ringbuf
+
+#
+# ESP System Settings
 #
-CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y
-# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set
-CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20
-CONFIG_ESP_PHY_MAX_TX_POWER=20
-CONFIG_ESP_PHY_REDUCE_TX_POWER=y
-# end of PHY
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set
+# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 is not set
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y
+CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=240
 
 #
-# Power Management
+# Memory
 #
-# CONFIG_PM_ENABLE is not set
-# end of Power Management
+# CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE is not set
 
 #
-# ESP Ringbuf
+# Non-backward compatible options
 #
-# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set
-# CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH is not set
-# end of ESP Ringbuf
+# CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM is not set
+# end of Non-backward compatible options
+# end of Memory
 
 #
-# ESP System Settings
+# Trace memory
 #
+# CONFIG_ESP32_TRAX is not set
+CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0
+# end of Trace memory
+
 # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set
 CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y
 # CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set
 # CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set
 # CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set
+CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0
 
 #
 # Memory protection
@@ -596,17 +888,46 @@ CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200
 CONFIG_ESP_INT_WDT=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=300
 CONFIG_ESP_INT_WDT_CHECK_CPU1=y
-CONFIG_ESP_TASK_WDT=y
+CONFIG_ESP_TASK_WDT_EN=y
+CONFIG_ESP_TASK_WDT_INIT=y
 CONFIG_ESP_TASK_WDT_PANIC=y
 CONFIG_ESP_TASK_WDT_TIMEOUT_S=15
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 # CONFIG_ESP_PANIC_HANDLER_IRAM is not set
 CONFIG_ESP_DEBUG_STUBS_ENABLE=y
+CONFIG_ESP_DEBUG_OCDAWARE=y
 # CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is not set
 CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y
+
+#
+# Brownout Detector
+#
+CONFIG_ESP_BROWNOUT_DET=y
+CONFIG_ESP_BROWNOUT_DET_LVL_SEL_0=y
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 is not set
+CONFIG_ESP_BROWNOUT_DET_LVL=0
+# end of Brownout Detector
+
+# CONFIG_ESP32_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_ESP32_ECO3_CACHE_LOCK_FIX=y
+CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y
 # end of ESP System Settings
 
+#
+# IPC (Inter-Processor Call)
+#
+CONFIG_ESP_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y
+CONFIG_ESP_IPC_ISR_ENABLE=y
+# end of IPC (Inter-Processor Call)
+
 #
 # High resolution timer (esp_timer)
 #
@@ -615,41 +936,68 @@ CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y
 CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y
 CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096
 CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1
+# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set
+CONFIG_ESP_TIMER_TASK_AFFINITY=0x0
+CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y
+CONFIG_ESP_TIMER_ISR_AFFINITY=0x1
+CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y
 # CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set
-# CONFIG_ESP_TIMER_IMPL_FRC2 is not set
 CONFIG_ESP_TIMER_IMPL_TG0_LAC=y
 # end of High resolution timer (esp_timer)
 
 #
 # Wi-Fi
 #
-CONFIG_ESP32_WIFI_ENABLED=y
-CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
-CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
-CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
-CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
-CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
-# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
-CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
-CONFIG_ESP32_WIFI_TX_BA_WIN=6
-CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
-CONFIG_ESP32_WIFI_RX_BA_WIN=16
-# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
-CONFIG_ESP32_WIFI_NVS_ENABLED=y
-CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
-# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
-CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
-CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
-CONFIG_ESP32_WIFI_IRAM_OPT=y
-CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
-CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLED=y
+CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP_WIFI_CSI_ENABLED is not set
+CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP_WIFI_TX_BA_WIN=6
+CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP_WIFI_RX_BA_WIN=16
+# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP_WIFI_NVS_ENABLED=y
+CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP_WIFI_IRAM_OPT=y
+CONFIG_ESP_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP_WIFI_ENABLE_SAE_PK=y
+CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y
+CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y
 # CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set
 # CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set
 # CONFIG_ESP_WIFI_GMAC_SUPPORT is not set
 CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y
 # CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set
 CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7
+# CONFIG_ESP_WIFI_NAN_ENABLE is not set
+CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y
+CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y
+# CONFIG_ESP_WIFI_WAPI_PSK is not set
+# CONFIG_ESP_WIFI_SUITE_B_192 is not set
+# CONFIG_ESP_WIFI_11KV_SUPPORT is not set
+# CONFIG_ESP_WIFI_MBO_SUPPORT is not set
+# CONFIG_ESP_WIFI_DPP_SUPPORT is not set
+# CONFIG_ESP_WIFI_11R_SUPPORT is not set
+# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set
+
+#
+# WPS Configuration Options
+#
+# CONFIG_ESP_WIFI_WPS_STRICT is not set
+# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set
+# end of WPS Configuration Options
+
+# CONFIG_ESP_WIFI_DEBUG_PRINT is not set
+# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set
 # end of Wi-Fi
 
 #
@@ -665,6 +1013,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP_COREDUMP_ENABLE=y
 CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=32
 CONFIG_ESP_COREDUMP_UART_DELAY=0
+CONFIG_ESP_COREDUMP_STACK_SIZE=0
 CONFIG_ESP_COREDUMP_DECODE_INFO=y
 # CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set
 CONFIG_ESP_COREDUMP_DECODE="info"
@@ -673,6 +1022,12 @@ CONFIG_ESP_COREDUMP_DECODE="info"
 #
 # FAT Filesystem support
 #
+CONFIG_FATFS_VOLUME_COUNT=2
+CONFIG_FATFS_LFN_NONE=y
+# CONFIG_FATFS_LFN_HEAP is not set
+# CONFIG_FATFS_LFN_STACK is not set
+# CONFIG_FATFS_SECTOR_512 is not set
+CONFIG_FATFS_SECTOR_4096=y
 # CONFIG_FATFS_CODEPAGE_DYNAMIC is not set
 CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_720 is not set
@@ -696,90 +1051,70 @@ CONFIG_FATFS_CODEPAGE_437=y
 # CONFIG_FATFS_CODEPAGE_949 is not set
 # CONFIG_FATFS_CODEPAGE_950 is not set
 CONFIG_FATFS_CODEPAGE=437
-CONFIG_FATFS_LFN_NONE=y
-# CONFIG_FATFS_LFN_HEAP is not set
-# CONFIG_FATFS_LFN_STACK is not set
 CONFIG_FATFS_FS_LOCK=0
 CONFIG_FATFS_TIMEOUT_MS=10000
 CONFIG_FATFS_PER_FILE_CACHE=y
 CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y
 # CONFIG_FATFS_USE_FASTSEEK is not set
+CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0
 # end of FAT Filesystem support
 
 #
-# Modbus configuration
-#
-CONFIG_FMB_COMM_MODE_TCP_EN=y
-CONFIG_FMB_TCP_PORT_DEFAULT=502
-CONFIG_FMB_TCP_PORT_MAX_CONN=5
-CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20
-CONFIG_FMB_COMM_MODE_RTU_EN=y
-CONFIG_FMB_COMM_MODE_ASCII_EN=y
-CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_FMB_QUEUE_LENGTH=20
-CONFIG_FMB_PORT_TASK_STACK_SIZE=2048
-CONFIG_FMB_SERIAL_BUF_SIZE=256
-CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8
-CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000
-CONFIG_FMB_PORT_TASK_PRIO=10
-# CONFIG_FMB_PORT_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_FMB_PORT_TASK_AFFINITY_CPU0=y
-# CONFIG_FMB_PORT_TASK_AFFINITY_CPU1 is not set
-CONFIG_FMB_PORT_TASK_AFFINITY=0x0
-CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_FMB_CONTROLLER_STACK_SIZE=4096
-CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_FMB_TIMER_PORT_ENABLED=y
-# CONFIG_FMB_TIMER_USE_ISR_DISPATCH_METHOD is not set
-# end of Modbus configuration
+# FreeRTOS
+#
 
 #
-# FreeRTOS
+# Kernel
 #
+# CONFIG_FREERTOS_SMP is not set
 # CONFIG_FREERTOS_UNICORE is not set
-CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
-CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
-CONFIG_FREERTOS_CORETIMER_0=y
-# CONFIG_FREERTOS_CORETIMER_1 is not set
-CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_HZ=1000
-CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set
 # CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set
 CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y
-# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
-CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
 CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1
-CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y
-# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set
-# CONFIG_FREERTOS_ASSERT_DISABLE is not set
 CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536
-CONFIG_FREERTOS_ISR_STACKSIZE=2096
-# CONFIG_FREERTOS_LEGACY_HOOKS is not set
+# CONFIG_FREERTOS_USE_IDLE_HOOK is not set
+# CONFIG_FREERTOS_USE_TICK_HOOK is not set
 CONFIG_FREERTOS_MAX_TASK_NAME_LEN=8
-CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
-# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set
 CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1
 CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10
 CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0
+CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1
 CONFIG_FREERTOS_USE_TRACE_FACILITY=y
 CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y
 CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y
 CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y
+# end of Kernel
+
+#
+# Port
+#
+CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y
+# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set
+CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y
+# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set
+CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
+CONFIG_FREERTOS_ISR_STACKSIZE=2096
+CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y
+# CONFIG_FREERTOS_FPU_IN_ISR is not set
+CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER=y
+CONFIG_FREERTOS_CORETIMER_0=y
+# CONFIG_FREERTOS_CORETIMER_1 is not set
+CONFIG_FREERTOS_SYSTICK_USES_CCOUNT=y
 CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y
 # CONFIG_FREERTOS_RUN_TIME_STATS_USING_CPU_CLK is not set
-CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y
-# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
 # CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set
-CONFIG_FREERTOS_DEBUG_OCDAWARE=y
-# CONFIG_FREERTOS_FPU_IN_ISR is not set
-CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 # CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set
+# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set
+CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
+# end of Port
+
+CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF
+CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y
+CONFIG_FREERTOS_DEBUG_OCDAWARE=y
 # end of FreeRTOS
 
 #
@@ -787,9 +1122,11 @@ CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y
 #
 CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y
 # CONFIG_HAL_ASSERTION_DISABLE is not set
-# CONFIG_HAL_ASSERTION_SILIENT is not set
+# CONFIG_HAL_ASSERTION_SILENT is not set
 # CONFIG_HAL_ASSERTION_ENABLE is not set
 CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2
+CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y
+CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y
 # end of Hardware Abstraction Layer (HAL) and Low Level (LL)
 
 #
@@ -801,20 +1138,13 @@ CONFIG_HEAP_POISONING_DISABLED=y
 CONFIG_HEAP_TRACING_OFF=y
 # CONFIG_HEAP_TRACING_STANDALONE is not set
 # CONFIG_HEAP_TRACING_TOHOST is not set
+# CONFIG_HEAP_USE_HOOKS is not set
 # CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set
+# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set
 # end of Heap memory debugging
 
-#
-# jsmn
-#
-# CONFIG_JSMN_PARENT_LINKS is not set
-# CONFIG_JSMN_STRICT is not set
-# end of jsmn
-
-#
-# libsodium
-#
-# end of libsodium
+CONFIG_IEEE802154_CCA_THRESHOLD=-60
+CONFIG_IEEE802154_PENDING_TABLE_SIZE=20
 
 #
 # Log output
@@ -842,6 +1172,7 @@ CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
 CONFIG_LWIP_LOCAL_HOSTNAME="espressif"
 # CONFIG_LWIP_NETIF_API is not set
 # CONFIG_LWIP_TCPIP_CORE_LOCKING is not set
+# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set
 CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y
 # CONFIG_LWIP_L2_TO_L3_COPY is not set
 CONFIG_LWIP_IRAM_OPTIMIZATION=y
@@ -857,17 +1188,21 @@ CONFIG_LWIP_IP4_FRAG=y
 CONFIG_LWIP_IP6_FRAG=y
 CONFIG_LWIP_IP4_REASSEMBLY=y
 # CONFIG_LWIP_IP6_REASSEMBLY is not set
+CONFIG_LWIP_IP_REASS_MAX_PBUFS=10
 # CONFIG_LWIP_IP_FORWARD is not set
 # CONFIG_LWIP_STATS is not set
-# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set
 CONFIG_LWIP_ESP_GRATUITOUS_ARP=y
 CONFIG_LWIP_GARP_TMR_INTERVAL=60
+CONFIG_LWIP_ESP_MLDV6_REPORT=y
+CONFIG_LWIP_MLDV6_TMR_INTERVAL=40
 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y
 # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set
 CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y
 # CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set
 CONFIG_LWIP_DHCP_OPTIONS_LEN=68
+CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0
+CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1
 
 #
 # DHCP server
@@ -878,6 +1213,7 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8
 # end of DHCP server
 
 # CONFIG_LWIP_AUTOIP is not set
+CONFIG_LWIP_IPV4=y
 CONFIG_LWIP_IPV6=y
 # CONFIG_LWIP_IPV6_AUTOCONFIG is not set
 CONFIG_LWIP_IPV6_NUM_ADDRESSES=3
@@ -903,7 +1239,6 @@ CONFIG_LWIP_TCP_WND_DEFAULT=5744
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=6
 CONFIG_LWIP_TCP_QUEUE_OOSEQ=y
 # CONFIG_LWIP_TCP_SACK_OUT is not set
-# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_LWIP_TCP_OVERSIZE_MSS=y
 # CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set
@@ -957,6 +1292,7 @@ CONFIG_LWIP_SNTP_MAX_SERVERS=1
 CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000
 # end of SNTP
 
+CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7
 CONFIG_LWIP_ESP_LWIP_ASSERT=y
 
 #
@@ -974,6 +1310,9 @@ CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y
 CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set
 # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set
+CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y
+# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set
+# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set
 # end of Hooks
 
 # CONFIG_LWIP_DEBUG is not set
@@ -993,13 +1332,15 @@ CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096
 # CONFIG_MBEDTLS_DEBUG is not set
 
 #
-# mbedTLS v2.28.x related
+# mbedTLS v3.x related
 #
+# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set
 # CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set
 # CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set
 # CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set
 CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y
-# end of mbedTLS v2.28.x related
+CONFIG_MBEDTLS_PKCS7_C=y
+# end of mbedTLS v3.x related
 
 #
 # Certificate Bundle
@@ -1021,6 +1362,7 @@ CONFIG_MBEDTLS_ROM_MD5=y
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set
 # CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set
 CONFIG_MBEDTLS_HAVE_TIME=y
+# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set
 # CONFIG_MBEDTLS_HAVE_TIME_DATE is not set
 CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y
 CONFIG_MBEDTLS_SHA512_C=y
@@ -1037,7 +1379,6 @@ CONFIG_MBEDTLS_TLS_ENABLED=y
 #
 # CONFIG_MBEDTLS_PSK_MODES is not set
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y
@@ -1046,16 +1387,11 @@ CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y
 # end of TLS Key Exchange Methods
 
 CONFIG_MBEDTLS_SSL_RENEGOTIATION=y
-# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set
-CONFIG_MBEDTLS_SSL_PROTO_TLS1=y
-CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y
 CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y
 # CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set
 # CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set
 CONFIG_MBEDTLS_SSL_ALPN=y
 CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y
-CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y
-CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y
 CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 
 #
@@ -1064,9 +1400,6 @@ CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y
 CONFIG_MBEDTLS_AES_C=y
 # CONFIG_MBEDTLS_CAMELLIA_C is not set
 # CONFIG_MBEDTLS_DES_C is not set
-CONFIG_MBEDTLS_RC4_DISABLED=y
-# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set
-# CONFIG_MBEDTLS_RC4_ENABLED is not set
 # CONFIG_MBEDTLS_BLOWFISH_C is not set
 # CONFIG_MBEDTLS_XTEA_C is not set
 CONFIG_MBEDTLS_CCM_C=y
@@ -1086,6 +1419,7 @@ CONFIG_MBEDTLS_X509_CSR_PARSE_C=y
 # end of Certificates
 
 CONFIG_MBEDTLS_ECP_C=y
+# CONFIG_MBEDTLS_DHM_C is not set
 CONFIG_MBEDTLS_ECDH_C=y
 CONFIG_MBEDTLS_ECDSA_C=y
 # CONFIG_MBEDTLS_ECJPAKE_C is not set
@@ -1110,27 +1444,11 @@ CONFIG_MBEDTLS_ECP_NIST_OPTIM=y
 # CONFIG_MBEDTLS_SECURITY_RISKS is not set
 # end of mbedTLS
 
-#
-# mDNS
-#
-CONFIG_MDNS_MAX_SERVICES=10
-CONFIG_MDNS_TASK_PRIORITY=1
-CONFIG_MDNS_TASK_STACK_SIZE=4096
-# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set
-CONFIG_MDNS_TASK_AFFINITY_CPU0=y
-# CONFIG_MDNS_TASK_AFFINITY_CPU1 is not set
-CONFIG_MDNS_TASK_AFFINITY=0x0
-CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000
-# CONFIG_MDNS_STRICT_MODE is not set
-CONFIG_MDNS_TIMER_PERIOD_MS=100
-# CONFIG_MDNS_NETWORKING_SOCKET is not set
-CONFIG_MDNS_MULTIPLE_INSTANCE=y
-# end of mDNS
-
 #
 # ESP-MQTT Configurations
 #
 CONFIG_MQTT_PROTOCOL_311=y
+# CONFIG_MQTT_PROTOCOL_5 is not set
 CONFIG_MQTT_TRANSPORT_SSL=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET=y
 CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y
@@ -1152,6 +1470,10 @@ CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y
 # CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set
 CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NEWLIB_NANO_FORMAT is not set
+CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set
 # end of Newlib
 
 #
@@ -1160,21 +1482,20 @@ CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y
 # CONFIG_NVS_ASSERT_ERROR_CHECK is not set
 # end of NVS
 
-#
-# OpenSSL
-#
-# CONFIG_OPENSSL_DEBUG is not set
-CONFIG_OPENSSL_ERROR_STACK=y
-CONFIG_OPENSSL_ASSERT_DO_NOTHING=y
-# CONFIG_OPENSSL_ASSERT_EXIT is not set
-# end of OpenSSL
-
 #
 # OpenThread
 #
 # CONFIG_OPENTHREAD_ENABLED is not set
 # end of OpenThread
 
+#
+# Protocomm
+#
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y
+CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y
+# end of Protocomm
+
 #
 # PThreads
 #
@@ -1188,6 +1509,14 @@ CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1
 CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread"
 # end of PThreads
 
+#
+# MMU Config
+#
+CONFIG_MMU_PAGE_SIZE_64KB=y
+CONFIG_MMU_PAGE_MODE="64KB"
+CONFIG_MMU_PAGE_SIZE=0x10000
+# end of MMU Config
+
 #
 # SPI Flash driver
 #
@@ -1197,7 +1526,6 @@ CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y
 CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set
 # CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set
-# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set
 # CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set
 # CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set
 CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y
@@ -1208,9 +1536,21 @@ CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192
 # CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set
 # CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set
 
+#
+# SPI Flash behavior when brownout
+#
+CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y
+CONFIG_SPI_FLASH_BROWNOUT_RESET=y
+# end of SPI Flash behavior when brownout
+
 #
 # Auto-detect flash chips
 #
+CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y
+CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y
 CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y
 CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y
@@ -1267,9 +1607,16 @@ CONFIG_SPIFFS_USE_MTIME=y
 #
 CONFIG_WS_TRANSPORT=y
 CONFIG_WS_BUFFER_SIZE=1024
+# CONFIG_WS_DYNAMIC_BUFFER is not set
 # end of Websocket
 # end of TCP Transport
 
+#
+# Ultra Low Power (ULP) Co-processor
+#
+# CONFIG_ULP_COPROC_ENABLED is not set
+# end of Ultra Low Power (ULP) Co-processor
+
 #
 # Unity unit testing library
 #
@@ -1282,6 +1629,11 @@ CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y
 # CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set
 # end of Unity unit testing library
 
+#
+# Root Hub configuration
+#
+# end of Root Hub configuration
+
 #
 # Virtual file system
 #
@@ -1312,22 +1664,10 @@ CONFIG_WL_SECTOR_SIZE=4096
 CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16
 CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30
 CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y
+CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y
+# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set
 # end of Wi-Fi Provisioning Manager
 
-#
-# Supplicant
-#
-CONFIG_WPA_MBEDTLS_CRYPTO=y
-# CONFIG_WPA_WAPI_PSK is not set
-# CONFIG_WPA_SUITE_B_192 is not set
-# CONFIG_WPA_DEBUG_PRINT is not set
-# CONFIG_WPA_TESTING_OPTIONS is not set
-# CONFIG_WPA_WPS_STRICT is not set
-# CONFIG_WPA_11KV_SUPPORT is not set
-# CONFIG_WPA_MBO_SUPPORT is not set
-# CONFIG_WPA_DPP_SUPPORT is not set
-# end of Supplicant
-
 #
 # Atrium
 #
@@ -1379,6 +1719,7 @@ CONFIG_ROMFS_VFS_NUMFDS=4
 # hardware support
 #
 CONFIG_GPIOS=y
+# CONFIG_CORETEMP is not set
 CONFIG_IOEXTENDERS=y
 CONFIG_LEDS=y
 CONFIG_BUTTON=y
@@ -1400,6 +1741,7 @@ CONFIG_PCF8574=y
 CONFIG_TCA9555=y
 CONFIG_MCP2300X=y
 CONFIG_MCP2301X=y
+# CONFIG_OPT3001 is not set
 CONFIG_INA2XX=y
 CONFIG_SI7021=y
 CONFIG_BMX280=y
@@ -1413,6 +1755,7 @@ CONFIG_SPI=y
 CONFIG_SX1276=y
 CONFIG_SSD1309=y
 CONFIG_ILI9341=y
+# CONFIG_SDCARD is not set
 CONFIG_XPT2046=y
 CONFIG_HCSR04=y
 CONFIG_DIMMER=y
@@ -1431,14 +1774,14 @@ CONFIG_FUNCTION_TIMING=y
 # end of Atrium
 # end of Component config
 
-#
-# Compatibility options
-#
-# CONFIG_LEGACY_INCLUDE_COMMON_HEADERS is not set
-# end of Compatibility options
+# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set
 
 # Deprecated options for backward compatibility
-CONFIG_TOOLPREFIX="xtensa-esp32-elf-"
+# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set
+# CONFIG_NO_BLOBS is not set
+# CONFIG_ESP32_NO_BLOBS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_ESP32_COMPATIBLE_PRE_V3_1_BOOTLOADERS is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set
 # CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set
@@ -1452,16 +1795,10 @@ CONFIG_LOG_BOOTLOADER_LEVEL=3
 # CONFIG_FLASHMODE_QOUT is not set
 # CONFIG_FLASHMODE_DIO is not set
 CONFIG_FLASHMODE_DOUT=y
-# CONFIG_MONITOR_BAUD_9600B is not set
-# CONFIG_MONITOR_BAUD_57600B is not set
-CONFIG_MONITOR_BAUD_115200B=y
-# CONFIG_MONITOR_BAUD_230400B is not set
-# CONFIG_MONITOR_BAUD_921600B is not set
-# CONFIG_MONITOR_BAUD_2MB is not set
-# CONFIG_MONITOR_BAUD_OTHER is not set
-CONFIG_MONITOR_BAUD_OTHER_VAL=115200
 CONFIG_MONITOR_BAUD=115200
+# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set
 # CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y
 CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y
 # CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set
@@ -1474,55 +1811,56 @@ CONFIG_STACK_CHECK_NORM=y
 # CONFIG_STACK_CHECK_ALL is not set
 CONFIG_STACK_CHECK=y
 # CONFIG_WARN_WRITE_STRINGS is not set
-# CONFIG_DISABLE_GCC8_WARNINGS is not set
 # CONFIG_ESP32_APPTRACE_DEST_TRAX is not set
 CONFIG_ESP32_APPTRACE_DEST_NONE=y
 CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
 CONFIG_ADC2_DISABLE_DAC=y
-CONFIG_SPIRAM_SUPPORT=y
-# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set
-CONFIG_TRACEMEM_RESERVE_DRAM=0x0
-# CONFIG_ULP_COPROC_ENABLED is not set
-CONFIG_ULP_COPROC_RESERVE_MEM=0
-CONFIG_BROWNOUT_DET=y
-CONFIG_BROWNOUT_DET_LVL_SEL_0=y
-# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
-# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set
-CONFIG_BROWNOUT_DET_LVL=0
-CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
-# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
-# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
-# CONFIG_NO_BLOBS is not set
-# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set
+# CONFIG_MCPWM_ISR_IN_IRAM is not set
 # CONFIG_EVENT_LOOP_PROFILING is not set
 CONFIG_POST_EVENTS_FROM_ISR=y
 CONFIG_POST_EVENTS_FROM_IRAM_ISR=y
+CONFIG_OTA_ALLOW_HTTP=y
 # CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set
 CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y
 CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4
-# CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND is not set
-CONFIG_IPC_TASK_STACK_SIZE=1024
+CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000
+CONFIG_ESP32_RTC_CLK_SRC_INT_RC=y
+CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set
+# CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set
+# CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256 is not set
+# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set
+CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024
+# CONFIG_ESP32_XTAL_FREQ_26 is not set
+CONFIG_ESP32_XTAL_FREQ_40=y
+# CONFIG_ESP32_XTAL_FREQ_AUTO is not set
+CONFIG_ESP32_XTAL_FREQ=40
 CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y
 # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set
 CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20
 CONFIG_ESP32_PHY_MAX_TX_POWER=20
+CONFIG_REDUCE_PHY_TX_POWER=y
 CONFIG_ESP32_REDUCE_PHY_TX_POWER=y
-# CONFIG_ESP32S2_PANIC_PRINT_HALT is not set
-CONFIG_ESP32S2_PANIC_PRINT_REBOOT=y
-# CONFIG_ESP32S2_PANIC_SILENT_REBOOT is not set
-# CONFIG_ESP32S2_PANIC_GDBSTUB is not set
+CONFIG_SPIRAM_SUPPORT=y
+CONFIG_ESP32_SPIRAM_SUPPORT=y
+# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set
+# CONFIG_ESP32_DEFAULT_CPU_FREQ_160 is not set
+CONFIG_ESP32_DEFAULT_CPU_FREQ_240=y
+CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=240
+CONFIG_TRACEMEM_RESERVE_DRAM=0x0
+# CONFIG_ESP32_PANIC_PRINT_HALT is not set
+CONFIG_ESP32_PANIC_PRINT_REBOOT=y
+# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set
+# CONFIG_ESP32_PANIC_GDBSTUB is not set
 CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32
 CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304
 CONFIG_MAIN_TASK_STACK_SIZE=3584
 CONFIG_CONSOLE_UART_DEFAULT=y
 # CONFIG_CONSOLE_UART_CUSTOM is not set
+# CONFIG_CONSOLE_UART_NONE is not set
 # CONFIG_ESP_CONSOLE_UART_NONE is not set
 CONFIG_CONSOLE_UART=y
 CONFIG_CONSOLE_UART_NUM=0
@@ -1531,12 +1869,72 @@ CONFIG_INT_WDT=y
 CONFIG_INT_WDT_TIMEOUT_MS=300
 CONFIG_INT_WDT_CHECK_CPU1=y
 CONFIG_TASK_WDT=y
+CONFIG_ESP_TASK_WDT=y
 CONFIG_TASK_WDT_PANIC=y
 CONFIG_TASK_WDT_TIMEOUT_S=15
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
 CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
+CONFIG_ESP32_DEBUG_OCDAWARE=y
+CONFIG_BROWNOUT_DET=y
+CONFIG_ESP32_BROWNOUT_DET=y
+CONFIG_BROWNOUT_DET_LVL_SEL_0=y
+CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_0=y
+# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_1 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_2 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_3 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_4 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_5 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6 is not set
+# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set
+# CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7 is not set
+CONFIG_BROWNOUT_DET_LVL=0
+CONFIG_ESP32_BROWNOUT_DET_LVL=0
+# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set
+CONFIG_IPC_TASK_STACK_SIZE=1024
 CONFIG_TIMER_TASK_STACK_SIZE=4096
+CONFIG_ESP32_WIFI_ENABLED=y
+CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
+CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y
+CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0
+CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16
+CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32
+# CONFIG_ESP32_WIFI_CSI_ENABLED is not set
+CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y
+CONFIG_ESP32_WIFI_TX_BA_WIN=6
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+CONFIG_ESP32_WIFI_RX_BA_WIN=16
+# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set
+CONFIG_ESP32_WIFI_NVS_ENABLED=y
+CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y
+# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set
+CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752
+CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32
+CONFIG_ESP32_WIFI_IRAM_OPT=y
+CONFIG_ESP32_WIFI_RX_IRAM_OPT=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y
+CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y
+CONFIG_WPA_MBEDTLS_CRYPTO=y
+CONFIG_WPA_MBEDTLS_TLS_CLIENT=y
+# CONFIG_WPA_WAPI_PSK is not set
+# CONFIG_WPA_SUITE_B_192 is not set
+# CONFIG_WPA_11KV_SUPPORT is not set
+# CONFIG_WPA_MBO_SUPPORT is not set
+# CONFIG_WPA_DPP_SUPPORT is not set
+# CONFIG_WPA_11R_SUPPORT is not set
+# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set
+# CONFIG_WPA_WPS_STRICT is not set
+# CONFIG_WPA_DEBUG_PRINT is not set
+# CONFIG_WPA_TESTING_OPTIONS is not set
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
 CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y
 # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set
@@ -1547,28 +1945,16 @@ CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y
 CONFIG_ESP32_ENABLE_COREDUMP=y
 CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=32
 CONFIG_ESP32_CORE_DUMP_UART_DELAY=0
+CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0
 CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y
 # CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set
 CONFIG_ESP32_CORE_DUMP_DECODE="info"
-CONFIG_MB_MASTER_TIMEOUT_MS_RESPOND=150
-CONFIG_MB_MASTER_DELAY_MS_CONVERT=200
-CONFIG_MB_QUEUE_LENGTH=20
-CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048
-CONFIG_MB_SERIAL_BUF_SIZE=256
-CONFIG_MB_SERIAL_TASK_PRIO=10
-CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT=y
-CONFIG_MB_CONTROLLER_SLAVE_ID=0x00112233
-CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20
-CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20
-CONFIG_MB_CONTROLLER_STACK_SIZE=4096
-CONFIG_MB_EVENT_QUEUE_TIMEOUT=20
-CONFIG_MB_TIMER_PORT_ENABLED=y
-# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
 CONFIG_TIMER_TASK_PRIORITY=1
 CONFIG_TIMER_TASK_STACK_DEPTH=2048
 CONFIG_TIMER_QUEUE_LENGTH=10
+# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set
+# CONFIG_HAL_ASSERTION_SILIENT is not set
 # CONFIG_L2_TO_L3_COPY is not set
-# CONFIG_USE_ONLY_LWIP_SELECT is not set
 CONFIG_ESP_GRATUITOUS_ARP=y
 CONFIG_GARP_TMR_INTERVAL=60
 CONFIG_TCPIP_RECVMBOX_SIZE=32
@@ -1580,7 +1966,6 @@ CONFIG_TCP_SND_BUF_DEFAULT=5744
 CONFIG_TCP_WND_DEFAULT=5744
 CONFIG_TCP_RECVMBOX_SIZE=6
 CONFIG_TCP_QUEUE_OOSEQ=y
-# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set
 CONFIG_TCP_OVERSIZE_MSS=y
 # CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set
 # CONFIG_TCP_OVERSIZE_DISABLE is not set
@@ -1591,6 +1976,12 @@ CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y
 # CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set
 CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF
 # CONFIG_PPP_SUPPORT is not set
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_HRT=y
+CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y
+# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_HRT is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set
+# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set
 CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5
 CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072
 CONFIG_ESP32_PTHREAD_STACK_MIN=768
@@ -1602,6 +1993,7 @@ CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"
 CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set
 # CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set
+# CONFIG_ESP32_ULP_COPROC_ENABLED is not set
 CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y
 CONFIG_SUPPORT_TERMIOS=y
 CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1
diff --git a/setupenv.sh b/setupenv.sh
index 071e4b4..0139dd7 100755
--- a/setupenv.sh
+++ b/setupenv.sh
@@ -258,17 +258,17 @@ if [ "$IDF_ESP32" == "" ]; then
 fi
 pushd $IDF_ESP32
 git pull --recurse-submodule
-git reset --hard v4.4.4
+git reset --hard v5.1
 git submodule deinit -f --all
 #git switch -c v4.4.4
 git submodule update --init
 IDF_PATH="$IDF_ESP32" bash install.sh
 IDF_PATH="$IDF_ESP32" python3 tools/idf_tools.py install
 echo patching IDF for ESP32
-patch -t -p1 < $patchdir/idf-esp32-v4.4.diff || echo PATCHING FAILED!
+patch -t -p1 < $patchdir/idf-esp32-v5.1.diff || echo PATCHING FAILED!
 echo patching lwip of ESP32
 cd components/lwip/lwip
-patch -t -p1 < $patchdir/esp32-lwip-v4.4.4.diff || echo PATCHING FAILED!
+patch -t -p1 < $patchdir/esp32-lwip-v5.1.diff || echo PATCHING FAILED!
 popd > /dev/null
 
 echo ===================
diff --git a/swcfg.wfc b/swcfg.wfc
index a382ec8..77ba6aa 100644
--- a/swcfg.wfc
+++ b/swcfg.wfc
@@ -200,8 +200,8 @@ bitset uartcfg_t
 
 message UartSettings
 {
-	uint8 port = 1;
-	unsigned baudrate = 2;
+	sint8 port = 1			[ unset = -1 ];
+	unsigned baudrate = 2		[ default = 115200 ];
 	uartcfg_t config = 3		[ default = 5, encoding = fixed16 ];
 	fixed8 rx_thresh = 4		[ unset = 0 ];
 	unsigned tx_bufsize = 6;