From 30a48ce99ffa9c4c02b70a1e9bc7c250bef9f16d Mon Sep 17 00:00:00 2001 From: Thomas Maier-Komor Date: Thu, 26 Oct 2023 21:55:40 +0200 Subject: [PATCH] release R2310 --- ChangeLog | 10 + components/logging/modules.c | 67 +- components/logging/modules.h | 6 +- components/logging/profiling.cpp | 4 +- components/netsvc/lwtcp.cpp | 2 +- components/streams/estring.h | 5 +- components/wfc/hwcfg_esp32.cpp | 12 +- components/wfc/hwcfg_esp32.h | 4 +- components/wfc/hwcfg_esp8266.cpp | 12 +- components/wfc/hwcfg_esp8266.h | 4 +- components/wfc/hwcfg_esp8285.cpp | 12 +- components/wfc/hwcfg_esp8285.h | 4 +- components/wfc/hwcfg_pc.cpp | 6 +- components/wfc/hwcfg_pc.h | 4 +- components/wfc/swcfg_esp32.cpp | 2 +- components/wfc/swcfg_esp32.h | 2 +- components/wfc/swcfg_esp8266.cpp | 2 +- components/wfc/swcfg_esp8266.h | 2 +- components/wfc/swcfg_esp8285.cpp | 2 +- components/wfc/swcfg_esp8285.h | 2 +- components/wfc/swcfg_pc.cpp | 2 +- components/wfc/swcfg_pc.h | 2 +- components/wfc/wfccore_esp32.cpp | 2 +- components/wfc/wfccore_esp32.h | 2 +- components/wfc/wfccore_esp8266.cpp | 2 +- components/wfc/wfccore_esp8266.h | 2 +- components/wfc/wfccore_esp8285.cpp | 2 +- components/wfc/wfccore_esp8285.h | 2 +- components/wfc/wfccore_pc.cpp | 2 +- components/wfc/wfccore_pc.h | 2 +- data/lua/rgbcct.lua | 1 - drv/display/display.cpp | 2 +- drv/display/ssd130x.cpp | 84 +- drv/i2c/CMakeLists.txt | 2 + drv/i2c/bmp388.cpp | 476 +++++++ drv/i2c/bmp388.h | 66 + drv/i2c/hdc1000.cpp | 4 +- drv/i2c/i2cdrv.cpp | 7 +- drv/i2c/opt3001.cpp | 65 +- drv/i2c/opt3001.h | 17 +- drv/i2c/sgp30.cpp | 6 + drv/i2c/sh1106.cpp | 384 +++++ drv/i2c/sh1106.h | 69 + drv/i2c/ssd1306.cpp | 424 +----- drv/i2c/ssd1306.h | 46 - drv/i2c/ti.cpp | 6 +- drv/spi/ssd1309.cpp | 777 ++-------- drv/spi/ssd1309.h | 78 +- drv/spi/sx1276.cpp | 304 ++-- drv/spi/sx1276.h | 14 +- hwcfg.wfc | 2 + main/Kconfig | 18 +- main/adc.cpp | 6 +- main/displays.cpp | 8 + main/fs.cpp | 4 + main/ftpd.cpp | 101 +- main/gpios.cpp | 49 +- main/i2c.cpp | 9 + main/leds.cpp | 37 +- main/ping.cpp | 2 +- main/screen.cpp | 21 +- main/shell.cpp | 15 +- main/shell.h | 3 +- main/spi.cpp | 18 + mkatrium.sh | 2 + projects/esp32-c3_4m | 11 +- projects/esp32-c3_4m_dev | 1879 +++++++++++++++++++++++++ projects/esp32-c6_4m | 70 +- projects/esp32-s2_4m | 13 +- projects/esp32-s3_4m | 90 +- projects/esp32-s3_4m_dev | 2086 +++++++++++++++++++++++++++ projects/esp32-s3_8m | 15 +- projects/esp32-s3_8m_dev | 2101 ++++++++++++++++++++++++++++ projects/esp32_4m | 17 +- projects/esp32_8m_full | 2 + projects/esp8266_2m | 2 + projects/esp8266_4m | 6 +- projects/esp8266_4m_full | 2 + projects/esp8266_4m_min | 51 +- projects/esp8285 | 1 + tools/atriumcfg.cpp | 2 +- 81 files changed, 8059 insertions(+), 1600 deletions(-) create mode 100644 drv/i2c/bmp388.cpp create mode 100644 drv/i2c/bmp388.h create mode 100644 drv/i2c/sh1106.cpp create mode 100644 drv/i2c/sh1106.h create mode 100644 projects/esp32-c3_4m_dev create mode 100644 projects/esp32-s3_4m_dev create mode 100644 projects/esp32-s3_8m_dev diff --git a/ChangeLog b/ChangeLog index af409d4..58dd18f 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,13 @@ +R2310: +====== +- fixes for SGP30: re-initialize after error, false detection +- FTPd fixes +- bugfixes for SSD1309 +- fixes for ESP32-C6 +- added hold/unhold actions for GPIOs and LEDs +- added OPT3001 driver +- added SH1106 driver + R2309: ====== - fix SNTP for IDFv5.1 64bit timeval struct diff --git a/components/logging/modules.c b/components/logging/modules.c index 0f90039..c47dc76 100644 --- a/components/logging/modules.c +++ b/components/logging/modules.c @@ -19,7 +19,7 @@ #include "modules.h" const char ModNames[] = - "\0action\0adc\0alarms\0apds\0bh1750\0bmx\0button\0cam\0ccs811b\0cfg\0con\0cyclic\0dht\0dim\0disp\0ds18b20\0event\0fs\0ftpd\0gpio\0hcsr04\0hd44780u\0hdc1000\0hlw8012\0ht16k33\0http\0i2c\0ili9341\0ina219\0influx\0init\0led\0ledc\0log\0lua\0lwtcp\0max7219\0mcp230xx\0mqtt\0nightsky\0ns\0nvm\0ota\0owb\0pca9685\0pcf8574\0relay\0rgbleds\0romfs\0screen\0sgp30\0shell\0si7021\0sm\0sntp\0spi\0ssd130x\0sx1276\0tca9555\0telnet\0ti\0timefuse\0tlc5916\0tlc5947\0tp\0uart\0udns\0udpctrl\0usb\0wlan\0ws2812\0www\0xio\0xpt2046\0"; + "\0action\0adc\0alarms\0apds\0bh1750\0bmx\0button\0cam\0ccs811b\0cfg\0con\0cyclic\0dht\0dim\0disp\0ds18b20\0event\0fs\0ftpd\0gpio\0hcsr04\0hd44780u\0hdc1000\0hlw8012\0ht16k33\0http\0i2c\0ili9341\0ina219\0influx\0init\0led\0ledc\0log\0lua\0lwtcp\0max7219\0mcp230xx\0mqtt\0nightsky\0ns\0nvm\0opt3001\0ota\0owb\0pca9685\0pcf8574\0relay\0rgbleds\0romfs\0screen\0sgp30\0shell\0si7021\0sm\0sntp\0spi\0ssd130x\0sx1276\0tca9555\0telnet\0ti\0timefuse\0tlc5916\0tlc5947\0tp\0uart\0udns\0udpctrl\0usb\0wlan\0ws2812\0www\0xio\0xpt2046\0"; const uint16_t ModNameOff[] = { 0, @@ -65,36 +65,37 @@ const uint16_t ModNameOff[] = { 237, // nightsky 246, // ns 249, // nvm - 253, // ota - 257, // owb - 261, // pca9685 - 269, // pcf8574 - 277, // relay - 283, // rgbleds - 291, // romfs - 297, // screen - 304, // sgp30 - 310, // shell - 316, // si7021 - 323, // sm - 326, // sntp - 331, // spi - 335, // ssd130x - 343, // sx1276 - 350, // tca9555 - 358, // telnet - 365, // ti - 368, // timefuse - 377, // tlc5916 - 385, // tlc5947 - 393, // tp - 396, // uart - 401, // udns - 406, // udpctrl - 414, // usb - 418, // wlan - 423, // ws2812 - 430, // www - 434, // xio - 438, // xpt2046 + 253, // opt3001 + 261, // ota + 265, // owb + 269, // pca9685 + 277, // pcf8574 + 285, // relay + 291, // rgbleds + 299, // romfs + 305, // screen + 312, // sgp30 + 318, // shell + 324, // si7021 + 331, // sm + 334, // sntp + 339, // spi + 343, // ssd130x + 351, // sx1276 + 358, // tca9555 + 366, // telnet + 373, // ti + 376, // timefuse + 385, // tlc5916 + 393, // tlc5947 + 401, // tp + 404, // uart + 409, // udns + 414, // udpctrl + 422, // usb + 426, // wlan + 431, // ws2812 + 438, // www + 442, // xio + 446, // xpt2046 }; diff --git a/components/logging/modules.h b/components/logging/modules.h index 2537daa..b708e57 100644 --- a/components/logging/modules.h +++ b/components/logging/modules.h @@ -71,6 +71,7 @@ typedef enum logmod_e { logmod_nightsky, logmod_ns, logmod_nvm, + logmod_opt3001, logmod_ota, logmod_owb, logmod_pca9685, @@ -148,6 +149,7 @@ typedef enum logmod_e { #define MODULE_NIGHTSKY logmod_nightsky #define MODULE_NS logmod_ns #define MODULE_NVM logmod_nvm +#define MODULE_OPT3001 logmod_opt3001 #define MODULE_OTA logmod_ota #define MODULE_OWB logmod_owb #define MODULE_PCA9685 logmod_pca9685 @@ -180,8 +182,8 @@ typedef enum logmod_e { #define MODULE_WWW logmod_www #define MODULE_XIO logmod_xio #define MODULE_XPT2046 logmod_xpt2046 -#define MAX_MODULE_ID 74 -#define NUM_MODULES 75 +#define MAX_MODULE_ID 75 +#define NUM_MODULES 76 #ifdef USE_MODULE #define TAG USE_MODULE diff --git a/components/logging/profiling.cpp b/components/logging/profiling.cpp index f71c108..68dcc23 100644 --- a/components/logging/profiling.cpp +++ b/components/logging/profiling.cpp @@ -30,11 +30,11 @@ TimeStats *TimeStats::First = 0; int prof(Terminal &term, int argc, const char *args[]) { - term.printf("%8s %9s %10s %8s %5s %s\n","low","avg","high","total","calls","function"); + term.printf("%8s %9s %10s %10s %5s %s\n","low","avg","high","total","calls","function"); TimeStats *s = TimeStats::First; while (s) { if (s->count) - term.printf("%8lu %9lu %10lu %8lu %5lu %s\n",s->low,(long unsigned)(s->total/s->count),(long unsigned)s->high,(long unsigned)s->total,(long unsigned)s->count,s->name); + term.printf("%8lu %9lu %10lu %10lu %5lu %s\n",s->low,(long unsigned)(s->total/s->count),(long unsigned)s->high,(long unsigned)s->total,(long unsigned)s->count,s->name); s = s->next; } return 0; diff --git a/components/netsvc/lwtcp.cpp b/components/netsvc/lwtcp.cpp index 7168da5..1ccb9d0 100644 --- a/components/netsvc/lwtcp.cpp +++ b/components/netsvc/lwtcp.cpp @@ -355,7 +355,6 @@ err_t LwTcp::handle_connect(void *arg, struct tcp_pcb *pcb, err_t x) int LwTcp::read(char *buf, size_t l, unsigned timeout) { - PROFILE_FUNCTION(); int r; struct pbuf *tofree = 0; if ((m_pcb == 0) && (m_pbuf == 0)) { @@ -365,6 +364,7 @@ int LwTcp::read(char *buf, size_t l, unsigned timeout) log_local(TAG,"read@%u(%u,%u) fill=%u,pbuf=%u",m_port,l,timeout,m_fill,m_pbuf?m_pbuf->tot_len:0); if (pdTRUE != xSemaphoreTakeRecursive(m_mtx,MUTEX_ABORT_TIMEOUT)) abort_on_mutex(m_mtx,__FUNCTION__); + PROFILE_FUNCTION(); if (m_pbuf) { unsigned avail = m_pbuf->tot_len - m_taken; unsigned copy = l > avail ? avail : l; diff --git a/components/streams/estring.h b/components/streams/estring.h index cdf0753..0aff0ea 100644 --- a/components/streams/estring.h +++ b/components/streams/estring.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2020-2021, Thomas Maier-Komor + * Copyright (C) 2020-2023, Thomas Maier-Komor * * This source file belongs to Wire-Format-Compiler. * @@ -82,6 +82,9 @@ class estring { if (len == 0) return 0; else return str[len-1]; } void push_back(char c); + + void pop_back() + { if (len) --len; } const char *data() const { return str; } diff --git a/components/wfc/hwcfg_esp32.cpp b/components/wfc/hwcfg_esp32.cpp index b092fc2..dfe1542 100644 --- a/components/wfc/hwcfg_esp32.cpp +++ b/components/wfc/hwcfg_esp32.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -292,6 +292,7 @@ static const char *i2cdrv_t_names[] = { "i2cdrv_pca9685_xclk_npn", "i2cdrv_pca9685_xclk_pnp", "i2cdrv_pcf8574", + "i2cdrv_sh1106", "i2cdrv_si7021", "i2cdrv_ssd1306", "i2cdrv_tca9555", @@ -310,6 +311,7 @@ static i2cdrv_t i2cdrv_t_values[] = { i2cdrv_pca9685_xclk_npn, i2cdrv_pca9685_xclk_pnp, i2cdrv_pcf8574, + i2cdrv_sh1106, i2cdrv_si7021, i2cdrv_ssd1306, i2cdrv_tca9555, @@ -332,6 +334,7 @@ size_t parse_ascii_i2cdrv_t(i2cdrv_t *v, const char *s) { "i2cdrv_pca9685_xclk_npn", i2cdrv_pca9685_xclk_npn}, { "i2cdrv_pca9685_xclk_pnp", i2cdrv_pca9685_xclk_pnp}, { "i2cdrv_pcf8574", i2cdrv_pcf8574}, + { "i2cdrv_sh1106", i2cdrv_sh1106}, { "i2cdrv_si7021", i2cdrv_si7021}, { "i2cdrv_ssd1306", i2cdrv_ssd1306}, { "i2cdrv_tca9555", i2cdrv_tca9555}, @@ -396,6 +399,8 @@ const char *i2cdrv_t_str(i2cdrv_t e) return "i2cdrv_tca9555"; case i2cdrv_ssd1306: return "i2cdrv_ssd1306"; + case i2cdrv_sh1106: + return "i2cdrv_sh1106"; } #endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB #ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB @@ -414,6 +419,7 @@ static const char *disp_t_names[] = { "dt_pcf8574_hd44780u", "dt_sd_14seg", "dt_sd_7seg", + "dt_sh1106", "dt_ssd1306", "dt_ssd1309", }; @@ -424,6 +430,7 @@ static disp_t disp_t_values[] = { dt_pcf8574_hd44780u, dt_sd_14seg, dt_sd_7seg, + dt_sh1106, dt_ssd1306, dt_ssd1309, }; @@ -438,6 +445,7 @@ size_t parse_ascii_disp_t(disp_t *v, const char *s) { "dt_pcf8574_hd44780u", dt_pcf8574_hd44780u}, { "dt_sd_14seg", dt_sd_14seg}, { "dt_sd_7seg", dt_sd_7seg}, + { "dt_sh1106", dt_sh1106}, { "dt_ssd1306", dt_ssd1306}, { "dt_ssd1309", dt_ssd1309}, }; @@ -483,6 +491,8 @@ const char *disp_t_str(disp_t e) return "dt_ssd1306"; case dt_ssd1309: return "dt_ssd1309"; + case dt_sh1106: + return "dt_sh1106"; case dt_ili9341: return "dt_ili9341"; } diff --git a/components/wfc/hwcfg_esp32.h b/components/wfc/hwcfg_esp32.h index 27a8de1..a6be31b 100644 --- a/components/wfc/hwcfg_esp32.h +++ b/components/wfc/hwcfg_esp32.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -175,6 +175,7 @@ typedef enum { i2cdrv_si7021 = 12, i2cdrv_tca9555 = 13, i2cdrv_ssd1306 = 14, + i2cdrv_sh1106 = 15, } i2cdrv_t; //! Function to get an ASCII string from a value of a i2cdrv_t. const char *i2cdrv_t_str(i2cdrv_t e); @@ -188,6 +189,7 @@ typedef enum { dt_pcf8574_hd44780u = 16, dt_ssd1306 = 32, dt_ssd1309 = 33, + dt_sh1106 = 34, dt_ili9341 = 64, } disp_t; //! Function to get an ASCII string from a value of a disp_t. diff --git a/components/wfc/hwcfg_esp8266.cpp b/components/wfc/hwcfg_esp8266.cpp index b6e9b13..8c15e35 100644 --- a/components/wfc/hwcfg_esp8266.cpp +++ b/components/wfc/hwcfg_esp8266.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -292,6 +292,7 @@ static const char *i2cdrv_t_names[] = { "i2cdrv_pca9685_xclk_npn", "i2cdrv_pca9685_xclk_pnp", "i2cdrv_pcf8574", + "i2cdrv_sh1106", "i2cdrv_si7021", "i2cdrv_ssd1306", "i2cdrv_tca9555", @@ -310,6 +311,7 @@ static i2cdrv_t i2cdrv_t_values[] = { i2cdrv_pca9685_xclk_npn, i2cdrv_pca9685_xclk_pnp, i2cdrv_pcf8574, + i2cdrv_sh1106, i2cdrv_si7021, i2cdrv_ssd1306, i2cdrv_tca9555, @@ -332,6 +334,7 @@ size_t parse_ascii_i2cdrv_t(i2cdrv_t *v, const char *s) { "i2cdrv_pca9685_xclk_npn", i2cdrv_pca9685_xclk_npn}, { "i2cdrv_pca9685_xclk_pnp", i2cdrv_pca9685_xclk_pnp}, { "i2cdrv_pcf8574", i2cdrv_pcf8574}, + { "i2cdrv_sh1106", i2cdrv_sh1106}, { "i2cdrv_si7021", i2cdrv_si7021}, { "i2cdrv_ssd1306", i2cdrv_ssd1306}, { "i2cdrv_tca9555", i2cdrv_tca9555}, @@ -396,6 +399,8 @@ const char *i2cdrv_t_str(i2cdrv_t e) return "i2cdrv_tca9555"; case i2cdrv_ssd1306: return "i2cdrv_ssd1306"; + case i2cdrv_sh1106: + return "i2cdrv_sh1106"; } #endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB #ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB @@ -414,6 +419,7 @@ static const char *disp_t_names[] = { "dt_pcf8574_hd44780u", "dt_sd_14seg", "dt_sd_7seg", + "dt_sh1106", "dt_ssd1306", "dt_ssd1309", }; @@ -424,6 +430,7 @@ static disp_t disp_t_values[] = { dt_pcf8574_hd44780u, dt_sd_14seg, dt_sd_7seg, + dt_sh1106, dt_ssd1306, dt_ssd1309, }; @@ -438,6 +445,7 @@ size_t parse_ascii_disp_t(disp_t *v, const char *s) { "dt_pcf8574_hd44780u", dt_pcf8574_hd44780u}, { "dt_sd_14seg", dt_sd_14seg}, { "dt_sd_7seg", dt_sd_7seg}, + { "dt_sh1106", dt_sh1106}, { "dt_ssd1306", dt_ssd1306}, { "dt_ssd1309", dt_ssd1309}, }; @@ -483,6 +491,8 @@ const char *disp_t_str(disp_t e) return "dt_ssd1306"; case dt_ssd1309: return "dt_ssd1309"; + case dt_sh1106: + return "dt_sh1106"; case dt_ili9341: return "dt_ili9341"; } diff --git a/components/wfc/hwcfg_esp8266.h b/components/wfc/hwcfg_esp8266.h index fb372e2..4ab11f9 100644 --- a/components/wfc/hwcfg_esp8266.h +++ b/components/wfc/hwcfg_esp8266.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -176,6 +176,7 @@ typedef enum { i2cdrv_si7021 = 12, i2cdrv_tca9555 = 13, i2cdrv_ssd1306 = 14, + i2cdrv_sh1106 = 15, } i2cdrv_t; //! Function to get an ASCII string from a value of a i2cdrv_t. const char *i2cdrv_t_str(i2cdrv_t e); @@ -189,6 +190,7 @@ typedef enum { dt_pcf8574_hd44780u = 16, dt_ssd1306 = 32, dt_ssd1309 = 33, + dt_sh1106 = 34, dt_ili9341 = 64, } disp_t; //! Function to get an ASCII string from a value of a disp_t. diff --git a/components/wfc/hwcfg_esp8285.cpp b/components/wfc/hwcfg_esp8285.cpp index a1ec5a2..5556fa4 100644 --- a/components/wfc/hwcfg_esp8285.cpp +++ b/components/wfc/hwcfg_esp8285.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -294,6 +294,7 @@ static const char *i2cdrv_t_names[] = { "i2cdrv_pca9685_xclk_npn", "i2cdrv_pca9685_xclk_pnp", "i2cdrv_pcf8574", + "i2cdrv_sh1106", "i2cdrv_si7021", "i2cdrv_ssd1306", "i2cdrv_tca9555", @@ -312,6 +313,7 @@ static i2cdrv_t i2cdrv_t_values[] = { i2cdrv_pca9685_xclk_npn, i2cdrv_pca9685_xclk_pnp, i2cdrv_pcf8574, + i2cdrv_sh1106, i2cdrv_si7021, i2cdrv_ssd1306, i2cdrv_tca9555, @@ -334,6 +336,7 @@ size_t parse_ascii_i2cdrv_t(i2cdrv_t *v, const char *s) { "i2cdrv_pca9685_xclk_npn", i2cdrv_pca9685_xclk_npn}, { "i2cdrv_pca9685_xclk_pnp", i2cdrv_pca9685_xclk_pnp}, { "i2cdrv_pcf8574", i2cdrv_pcf8574}, + { "i2cdrv_sh1106", i2cdrv_sh1106}, { "i2cdrv_si7021", i2cdrv_si7021}, { "i2cdrv_ssd1306", i2cdrv_ssd1306}, { "i2cdrv_tca9555", i2cdrv_tca9555}, @@ -398,6 +401,8 @@ const char *i2cdrv_t_str(i2cdrv_t e) return "i2cdrv_tca9555"; case i2cdrv_ssd1306: return "i2cdrv_ssd1306"; + case i2cdrv_sh1106: + return "i2cdrv_sh1106"; } #endif // !CONFIG_ESPTOOLPY_FLASHSIZE_1MB #ifdef CONFIG_ESPTOOLPY_FLASHSIZE_1MB @@ -416,6 +421,7 @@ static const char *disp_t_names[] = { "dt_pcf8574_hd44780u", "dt_sd_14seg", "dt_sd_7seg", + "dt_sh1106", "dt_ssd1306", "dt_ssd1309", }; @@ -426,6 +432,7 @@ static disp_t disp_t_values[] = { dt_pcf8574_hd44780u, dt_sd_14seg, dt_sd_7seg, + dt_sh1106, dt_ssd1306, dt_ssd1309, }; @@ -440,6 +447,7 @@ size_t parse_ascii_disp_t(disp_t *v, const char *s) { "dt_pcf8574_hd44780u", dt_pcf8574_hd44780u}, { "dt_sd_14seg", dt_sd_14seg}, { "dt_sd_7seg", dt_sd_7seg}, + { "dt_sh1106", dt_sh1106}, { "dt_ssd1306", dt_ssd1306}, { "dt_ssd1309", dt_ssd1309}, }; @@ -485,6 +493,8 @@ const char *disp_t_str(disp_t e) return "dt_ssd1306"; case dt_ssd1309: return "dt_ssd1309"; + case dt_sh1106: + return "dt_sh1106"; case dt_ili9341: return "dt_ili9341"; } diff --git a/components/wfc/hwcfg_esp8285.h b/components/wfc/hwcfg_esp8285.h index 2aac1b4..c92c2a0 100644 --- a/components/wfc/hwcfg_esp8285.h +++ b/components/wfc/hwcfg_esp8285.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -177,6 +177,7 @@ typedef enum { i2cdrv_si7021 = 12, i2cdrv_tca9555 = 13, i2cdrv_ssd1306 = 14, + i2cdrv_sh1106 = 15, } i2cdrv_t; //! Function to get an ASCII string from a value of a i2cdrv_t. const char *i2cdrv_t_str(i2cdrv_t e); @@ -190,6 +191,7 @@ typedef enum { dt_pcf8574_hd44780u = 16, dt_ssd1306 = 32, dt_ssd1309 = 33, + dt_sh1106 = 34, dt_ili9341 = 64, } disp_t; //! Function to get an ASCII string from a value of a disp_t. diff --git a/components/wfc/hwcfg_pc.cpp b/components/wfc/hwcfg_pc.cpp index ec30aa6..9b5ceda 100644 --- a/components/wfc/hwcfg_pc.cpp +++ b/components/wfc/hwcfg_pc.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -204,6 +204,7 @@ static const char *i2cdrv_t_names[] = { "i2cdrv_pca9685_xclk_npn", "i2cdrv_pca9685_xclk_pnp", "i2cdrv_pcf8574", + "i2cdrv_sh1106", "i2cdrv_si7021", "i2cdrv_ssd1306", "i2cdrv_tca9555", @@ -222,6 +223,7 @@ static i2cdrv_t i2cdrv_t_values[] = { i2cdrv_pca9685_xclk_npn, i2cdrv_pca9685_xclk_pnp, i2cdrv_pcf8574, + i2cdrv_sh1106, i2cdrv_si7021, i2cdrv_ssd1306, i2cdrv_tca9555, @@ -259,6 +261,7 @@ static const char *disp_t_names[] = { "dt_pcf8574_hd44780u", "dt_sd_14seg", "dt_sd_7seg", + "dt_sh1106", "dt_ssd1306", "dt_ssd1309", }; @@ -269,6 +272,7 @@ static disp_t disp_t_values[] = { dt_pcf8574_hd44780u, dt_sd_14seg, dt_sd_7seg, + dt_sh1106, dt_ssd1306, dt_ssd1309, }; diff --git a/components/wfc/hwcfg_pc.h b/components/wfc/hwcfg_pc.h index 53aabb5..df61448 100644 --- a/components/wfc/hwcfg_pc.h +++ b/components/wfc/hwcfg_pc.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -177,6 +177,7 @@ typedef enum { i2cdrv_si7021 = 12, i2cdrv_tca9555 = 13, i2cdrv_ssd1306 = 14, + i2cdrv_sh1106 = 15, } i2cdrv_t; //! Function to get an ASCII string from a value of a i2cdrv_t. const char *i2cdrv_t_str(i2cdrv_t e); @@ -190,6 +191,7 @@ typedef enum { dt_pcf8574_hd44780u = 16, dt_ssd1306 = 32, dt_ssd1309 = 33, + dt_sh1106 = 34, dt_ili9341 = 64, } disp_t; //! Function to get an ASCII string from a value of a disp_t. diff --git a/components/wfc/swcfg_esp32.cpp b/components/wfc/swcfg_esp32.cpp index a5a1216..b0ab263 100644 --- a/components/wfc/swcfg_esp32.cpp +++ b/components/wfc/swcfg_esp32.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_esp32.h b/components/wfc/swcfg_esp32.h index d375cce..aebfe88 100644 --- a/components/wfc/swcfg_esp32.h +++ b/components/wfc/swcfg_esp32.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_esp8266.cpp b/components/wfc/swcfg_esp8266.cpp index 16ae018..0501df1 100644 --- a/components/wfc/swcfg_esp8266.cpp +++ b/components/wfc/swcfg_esp8266.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_esp8266.h b/components/wfc/swcfg_esp8266.h index ae8f5ee..3b77d9e 100644 --- a/components/wfc/swcfg_esp8266.h +++ b/components/wfc/swcfg_esp8266.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_esp8285.cpp b/components/wfc/swcfg_esp8285.cpp index bf78dff..6ab6ba2 100644 --- a/components/wfc/swcfg_esp8285.cpp +++ b/components/wfc/swcfg_esp8285.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_esp8285.h b/components/wfc/swcfg_esp8285.h index f602572..89f20f2 100644 --- a/components/wfc/swcfg_esp8285.h +++ b/components/wfc/swcfg_esp8285.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_pc.cpp b/components/wfc/swcfg_pc.cpp index 7d7440d..f4cebf9 100644 --- a/components/wfc/swcfg_pc.cpp +++ b/components/wfc/swcfg_pc.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/swcfg_pc.h b/components/wfc/swcfg_pc.h index fa38bdc..6415558 100644 --- a/components/wfc/swcfg_pc.h +++ b/components/wfc/swcfg_pc.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp32.cpp b/components/wfc/wfccore_esp32.cpp index c04d6f1..252769b 100644 --- a/components/wfc/wfccore_esp32.cpp +++ b/components/wfc/wfccore_esp32.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp32.h b/components/wfc/wfccore_esp32.h index 4a66d1f..12c7775 100644 --- a/components/wfc/wfccore_esp32.h +++ b/components/wfc/wfccore_esp32.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp8266.cpp b/components/wfc/wfccore_esp8266.cpp index 1085453..51fa0ea 100644 --- a/components/wfc/wfccore_esp8266.cpp +++ b/components/wfc/wfccore_esp8266.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp8266.h b/components/wfc/wfccore_esp8266.h index d3a8f97..1b71ecf 100644 --- a/components/wfc/wfccore_esp8266.h +++ b/components/wfc/wfccore_esp8266.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:41 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp8285.cpp b/components/wfc/wfccore_esp8285.cpp index 7f2ce1c..73c0f68 100644 --- a/components/wfc/wfccore_esp8285.cpp +++ b/components/wfc/wfccore_esp8285.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_esp8285.h b/components/wfc/wfccore_esp8285.h index 07d5c3c..dca26d9 100644 --- a/components/wfc/wfccore_esp8285.h +++ b/components/wfc/wfccore_esp8285.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_pc.cpp b/components/wfc/wfccore_pc.cpp index 855d43a..6b0dd26 100644 --- a/components/wfc/wfccore_pc.cpp +++ b/components/wfc/wfccore_pc.cpp @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/components/wfc/wfccore_pc.h b/components/wfc/wfccore_pc.h index ce30c37..8198fcd 100644 --- a/components/wfc/wfccore_pc.h +++ b/components/wfc/wfccore_pc.h @@ -10,7 +10,7 @@ * Copyright: 2018-2023 * Author : Thomas Maier-Komor * - * Code generated on 2023-07-31, 21:35:41 (CET). + * Code generated on 2023-10-24, 21:26:42 (CET). * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/data/lua/rgbcct.lua b/data/lua/rgbcct.lua index 9eaeef2..2f1f63f 100644 --- a/data/lua/rgbcct.lua +++ b/data/lua/rgbcct.lua @@ -78,7 +78,6 @@ for k,v in pairs(colors) do numcolors = numcolors + 1 colornames[numcolors] = k end -h,m = time() function color_set(arg) diff --git a/drv/display/display.cpp b/drv/display/display.cpp index 8275cbc..2b719c5 100644 --- a/drv/display/display.cpp +++ b/drv/display/display.cpp @@ -567,7 +567,7 @@ unsigned MatrixDisplay::drawChar(uint16_t x, uint16_t y, char c, int32_t fg, int log_dbug(TAG,"drawChar(%d,%d,'%c') = %u",x,y,c,a); // log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l); if (bg != -1) - fillRect(x,y,dx,a,bg); + fillRect(x,y,a,m_font->yAdvance,bg); drawBitmap(x+dx,y+dy+m_font->yAdvance-1,w,h,data,fg,bg); return a; } diff --git a/drv/display/ssd130x.cpp b/drv/display/ssd130x.cpp index d3c0830..8997218 100644 --- a/drv/display/ssd130x.cpp +++ b/drv/display/ssd130x.cpp @@ -124,14 +124,6 @@ uint16_t SSD130X::fontHeight() const } -/* -void SSD130X::clrEol() -{ - clearRect(m_posx,m_posy,m_width-m_posx,fontHeight()); -} -*/ - - uint16_t SSD130X::charsPerLine() const { /* @@ -392,35 +384,15 @@ unsigned SSD130X::drawChar(uint16_t x, uint16_t y, char c, int32_t fg, int32_t b uint16_t a = m_font->glyph[ch].xAdvance; log_dbug(TAG,"drawChar(%u,%u,'%c') with %ux%u",x,y,c,w,h); // log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l); - clearRect(x,y,dx+w,m_font->yAdvance); -// drawBitmap(x+dx,y+dy+font->yAdvance,w,h,off,1,0); + clearRect(x,y,a,m_font->yAdvance); drawBitmapNative(x+dx,y+dy+m_font->yAdvance-1,w,h,off); return a; } -/* -void SSD130X::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) -{ - unsigned len = w*h; - log_dbug(TAG,"drawBitmap(%u,%u,%u,%u,%d,%d)",x,y,w,h,fg,bg); - unsigned idx = 0; - uint8_t b = 0; - while (idx != len) { - if ((idx & 7) == 0) - b = data[idx>>3]; - int32_t col = b & 0x80 ? fg : bg; - if (col != -2) - setPixel(x+idx%w,y+idx/w,col); - b<<=1; - ++idx; - } -} -*/ - - void SSD130X::drawHLine(uint16_t x, uint16_t y, uint16_t n, int32_t col) { + PROFILE_FUNCTION(); if ((x + n > m_width) || (y >= m_height) || (col != 1)) return; if ((x + n) > m_width) @@ -442,6 +414,7 @@ void SSD130X::drawHLine(uint16_t x, uint16_t y, uint16_t n, int32_t col) void SSD130X::drawVLine(uint16_t x, uint16_t y, uint16_t n, int32_t col) { + PROFILE_FUNCTION(); if ((x >= m_width) || (y >= m_height) || (col != 1)) return; if ((y + n) > m_height) @@ -490,6 +463,7 @@ static inline uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb) void SSD130X::drawBitmapNative(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data) { + PROFILE_FUNCTION(); static const uint8_t masks[] = {0x1,0x3,0x7,0xf,0x1f,0x3f,0x7f}; unsigned len = w*h; uint16_t bitoff = 0; @@ -528,7 +502,7 @@ void SSD130X::drawBitmapNative(uint16_t x, uint16_t y, uint16_t w, uint16_t h, c } -void SSD130X::pClrPixel(uint16_t x, uint16_t y) +inline void SSD130X::pClrPixel(uint16_t x, uint16_t y) { // log_dbug(TAG,"clrPixel(%u,%u)",(unsigned)x,(unsigned)y); if ((x < m_width) && (y < m_height)) { @@ -594,6 +568,7 @@ void SSD130X::setPixel(uint16_t x, uint16_t y, int32_t col) int SSD130X::clearRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h) { + PROFILE_FUNCTION(); log_dbug(TAG,"clearRect(%u,%u,%u,%u)",x,y,w,h); if ((x > m_width) || (y >= m_height)) return 1; @@ -616,19 +591,6 @@ int SSD130X::clearRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h) } -/* -int SSD130X::drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col) -{ - log_dbug(TAG,"drawRect(%u,%u,%u,%u)",x,y,w,h); - drawHLine(x,y,w,col); - drawHLine(x,y+h-1,w,col); - drawVLine(x,y,h,col); - drawVLine(x+w-1,y,h,col); - return 0; -} -*/ - - int SSD130X::writeHex(uint8_t h, bool comma) { log_dbug(TAG,"writeHex %x",h); @@ -644,37 +606,3 @@ int SSD130X::writeHex(uint8_t h, bool comma) } -/* -int SSD130X::setPos(uint16_t x, uint16_t y) -{ - log_dbug(TAG,"setPos(%u/%u)",x,y); - x *= CHAR_WIDTH; - y *= fontHeight(); - if ((x >= m_width-(CHAR_WIDTH)) || (y > m_height-fontHeight())) { - log_dbug(TAG,"invalid pos %u/%u",x,y); - return 1; - } - log_dbug(TAG,"setPos %u/%u",x,y); - m_posx = x; - m_posy = y; - return 0; -} -*/ - - -/* -void SSD130X::write(const char *text, int len) -{ - log_dbug(TAG,"write %s",text); - size_t n = 0; - while (len) { - char c = *text++; - if (c == 0) - return n; - drawChar(c); - ++n; - --len; - } - return n; -} -*/ diff --git a/drv/i2c/CMakeLists.txt b/drv/i2c/CMakeLists.txt index d598c67..04f9560 100644 --- a/drv/i2c/CMakeLists.txt +++ b/drv/i2c/CMakeLists.txt @@ -3,6 +3,7 @@ idf_component_register( apds9930.cpp bh1750.cpp bme680.c + bmp388.cpp bmx.cpp ccs811b.cpp hdc1000.cpp @@ -15,6 +16,7 @@ idf_component_register( pca9685.cpp pcf8574.cpp sgp30.cpp + sh1106.cpp si7021.cpp ssd1306.cpp tca9555.cpp diff --git a/drv/i2c/bmp388.cpp b/drv/i2c/bmp388.cpp new file mode 100644 index 0000000..5524ee1 --- /dev/null +++ b/drv/i2c/bmp388.cpp @@ -0,0 +1,476 @@ +/* + * Copyright (C) 2023, Thomas Maier-Komor + * Atrium Firmware Package for ESP + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +// This drivers operates the BMP388 in I2C mode. +// Connect CSB to 3.3V to enable I2C mode. +// Connect SDO to either GND or VCC to select the base address. + +#ifdef CONFIG_BMP388 + +#include +#include + +#include "actions.h" +#include "bmp388.h" +#include "cyclic.h" +#include "event.h" +#include "i2cdrv.h" +#include "log.h" +#include "stream.h" +#include "terminal.h" +#include "xio.h" + +#include +#include + +#define BMP388_ADDR 0x58 + +#define ADDR_MIN (0x76<<1) +#define ADDR_MAX (0x77<<1) + +#define REG_ID 0x00 +#define REG_ERROR 0x02 +#define REG_STATUS 0x03 +#define REG_EVENT 0x10 +#define REG_INT_CTRL 0x19 +#define REG_PWR_CTRL 0x1b +#define REG_OSR 0x1c +#define REG_ODR 0x1d +#define REG_CONFIG 0x1f // IIR filter +#define REG_CMD 0x7e +#define REG_BASE 0x2 + +#define CMD_FIFO_FLUSH 0xb0 +#define CMD_RESET 0xb6 +#define CMD_EXTMODE_EN 0x34 + +#define BIT_ERR_FATAL 0x1 +#define BIT_ERR_CMD 0x2 +#define BIT_ERR_CONF 0x4 + +#define BIT_ST_CRDY 0x10 +#define BIT_ST_PRDY 0x20 +#define BIT_ST_TRDY 0x40 + +#define BIT_PWR_PON 0x1 +#define BIT_PWR_TON 0x2 +#define BIT_PWR_FORCE 0x10 +#define BIT_PWR_NORM 0x30 + +#define BIT_INT_OD 0x1 // open-drain port +#define BIT_INT_AHI 0x2 // active high interrupts +#define BIT_INT_LATCH 0x4 // latch interrupts in status reg +#define BIT_INT_FIFO 0x8 // FIFO watermark interrupt +#define BIT_INT_FULL 0x10 // FIFO full interrupt +#define BIT_INT_DRDY 0x40 // data ready + +#define T1 0 +#define T2 1 +#define T3 2 +#define P1 3 +#define P2 4 +#define P3 5 +#define P4 6 +#define P5 7 +#define P6 8 +#define P7 9 +#define P8 10 +#define P9 11 +#define P10 12 +#define P11 13 + +#define CALIB_DATA 0x31 +#define BMX280_REG_BASE 0xf7 + +#define TAG MODULE_BMX + + +BMP388::BMP388(uint8_t port, uint8_t addr, const char *n) +: I2CDevice(port,addr,n ? n : drvName()) +, m_temp("temperature","\u00b0C","%4.1f") +, m_press("pressure","hPa","%4.1f") +{ +} + + +void BMP388::addIntr(uint8_t intr) +{ + m_irqev = event_register(m_name,"`irq"); + xio_cfg_t cfg = XIOCFG_INIT; + cfg.cfg_io = xio_cfg_io_in; + cfg.cfg_pull = xio_cfg_pull_none; + cfg.cfg_intr = xio_cfg_intr_edges; + if (0 > xio_config(intr,cfg)) { + log_warn(TAG,"config interrupt error"); + } else if (esp_err_t e = xio_set_intr(intr,intr_handler,this)) { + log_warn(TAG,"error attaching interrupt: %s",esp_err_to_name(e)); + } else { + log_info(TAG,"BMP388@%u,0x%x: interrupt on GPIO%u",m_bus,m_addr,intr); + } +} + + +void BMP388::trigger(void *arg) +{ + BMP388 *dev = (BMP388 *)arg; + if (dev->m_state == st_idle) + dev->m_state = st_sample; +} + + +unsigned BMP388::cyclic(void *arg) +{ + BMP388 *drv = (BMP388 *) arg; + switch (drv->m_state) { + case st_idle: + return 20; + case st_sample: + if (drv->sample()) + break; + drv->m_state = st_measure; + return 85; // conversion time depends on oversampling + // 85ms covers all cases + case st_measure: + if (drv->status()) + break; + return 5; + case st_read: + if (drv->read()) + break; + drv->m_state = st_idle; + return 50; + default: + abort(); + } + drv->handle_error(); + return 1000; +} + + +void BMP388::attach(EnvObject *root) +{ + root->add(&m_temp); + root->add(&m_press); + cyclic_add_task(m_name,BMP388::cyclic,this,0); + action_add(concat(m_name,"!sample"),trigger,(void*)this,"BMP388 sample data"); +} + + +void BMP388::intr_handler(void *arg) +{ + BMP388 *drv = (BMP388 *) arg; + event_isr_trigger(drv->m_irqev); +} + + +#ifdef CONFIG_I2C_XCMD + +int osr_value(uint8_t v) +{ + if (v == 0) + return -1; + int r = 0; + while ((v & 1) == 0) { + ++r; + v >>= 1; + } + if (v & ~1) + return -1; + return r; +} + + +const char *BMP388::exeCmd(Terminal &term, int argc, const char **args) +{ + static const uint8_t coef[] = {0,1,3,7,15,31,63,127}; + + if (argc == 1) { + if (0 == strcmp(args[0],"iir")) { + uint8_t iir; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_CONFIG,&iir,sizeof(iir))) + return esp_err_to_name(e); + iir >>= 1; + if (iir >= sizeof(coef)/sizeof(coef[0])) { +// term.printf("IIR register value %d\n",iir); + return "Unexpted register value."; + } else { + term.printf("IIR filter cofficient %d\n",coef[iir]); + } + } else if (0 == strcmp(args[0],"osr")) { + uint8_t osr; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_OSR,&osr,sizeof(osr))) + return esp_err_to_name(e); + term.printf("oversampling: temperatur x%u, pressure x%u\n",1<<((osr>>3)&7),1<<(osr&7)); + } else { + return "Invalid argument #1."; + } + } else if (argc == 2) { + if (0 == strcmp(args[0],"iir")) { + char *e; + long l = strtol(args[1],&e,0); + if (*e) + return "Invalid argument #2."; + int c = -1; + for (int x = 0; x < sizeof(coef)/sizeof(coef[0]); ++x) { + if (l == coef[x]) { + c = x; + break; + } + } + if (c == -1) + return "Invalid argument #2."; + if (esp_err_t e = i2c_write2(m_bus,m_addr,REG_CONFIG,c<<1)) + return esp_err_to_name(e); + } else if (0 == strcmp(args[0],"osrp")) { + char *e; + long l = strtol(args[1],&e,0); + if ((*e != 0) || (l <= 0) || (l > 32)) + return "Invalid argument #2."; + int v = osr_value(l); + if (v < 0) + return "Invalid argument #2."; + uint8_t osr; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_OSR,&osr,sizeof(osr))) + return esp_err_to_name(e); + osr &= 0x38; + osr |= v; + if (esp_err_t e = i2c_write2(m_bus,m_addr,REG_OSR,osr)) + return esp_err_to_name(e); + } else if (0 == strcmp(args[0],"osrt")) { + char *e; + long l = strtol(args[1],&e,0); + if ((*e != 0) || (l <= 0) || (l > 32)) + return "Invalid argument #2."; + int v = osr_value(l); + if (v < 0) + return "Invalid argument #2."; + uint8_t osr; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_OSR,&osr,sizeof(osr))) + return esp_err_to_name(e); + osr &= 0x7; + osr |= v << 3; + if (esp_err_t e = i2c_write2(m_bus,m_addr,REG_OSR,osr)) + return esp_err_to_name(e); + } else { + return "Invalid argument #1."; + } + } else { + return "Invalid number of arguments."; + } + return 0; +} +#endif + + +int BMP388::get_error() +{ + uint8_t err = 0; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_ERROR,&err,sizeof(err))) + return -e; + if (err) + log_warn(TAG,"device error %d",err); + return err; +} + + +int BMP388::get_status() +{ + uint8_t status = 0; + if (esp_err_t e = i2c_w1rd(m_bus,m_addr,REG_ERROR,&status,sizeof(status))) + return -e; + log_dbug(TAG,"device status %d",status); + return status; +} + + +void BMP388::handle_error() +{ + m_temp.set(NAN); + m_press.set(NAN); +} + + +void BMP388::calc_tfine(uint32_t uncomp_temp) +{ +#if 1 + float partial_data1 = (float)(uncomp_temp - D[T1]); + float partial_data2 = (float)(partial_data1 * D[T2]); + m_temp.set(partial_data2 + (partial_data1 * partial_data1) * D[T3]); +#else + uint64_t partial_data1 = (float)(uncomp_temp - D[T1]); + uint64_t partial_data2 = (float)(partial_data1 * D[T2]); + uint64_t comp_temp = partial_data2 + (partial_data1 * partial_data1) * D[T3]; + m_temp.set((float)comp_temp/100); + +#endif +} + + +void BMP388::calc_press(uint32_t uncomp_press) +{ + float temp = m_temp.get(); + float temp_2 = temp * temp; + float temp_3 = temp_2 * temp; + float partial_data1 = D[P6] * temp; + float partial_data2 = D[P7] * temp_2; + float partial_data3 = D[P8] * temp_3; + float partial_out1 = D[P5] + partial_data1 + partial_data2 + partial_data3; + partial_data1 = D[P2] * temp; + partial_data2 = D[P3] * temp_2; + partial_data3 = D[P4] * temp_3; + float partial_out2 = (float)uncomp_press * (D[P1] + partial_data1 + partial_data2 + partial_data3); + partial_data1 = (float)uncomp_press * (float)uncomp_press; + partial_data2 = D[P9] + D[P10] * temp; + partial_data3 = partial_data1 * partial_data2; + float partial_data4 = partial_data3 + ((float)uncomp_press * (float)uncomp_press * (float)uncomp_press) * D[P11]; + float comp_press = partial_out1 + partial_out2 + partial_data4; + m_press.set(comp_press/100.0); +} + + +int BMP388::sample() +{ + log_dbug(TAG,"sample"); + uint8_t cmd[] = { m_addr, REG_PWR_CTRL, BIT_PWR_FORCE|BIT_PWR_TON|BIT_PWR_PON}; + return i2c_write(m_bus, cmd, sizeof(cmd), true, true); +} + + +int BMP388::read() +{ + uint8_t data[8]; + if (int r = i2c_w1rd(m_bus,m_addr,REG_BASE,data,sizeof(data))) + return r; + log_dbug(TAG,"status: temp %s, press %s, conf %s, cmd %s, %s" + ,data[1]&0x40?"ready":"busy" + ,data[1]&0x20?"ready":"busy" + ,data[0]&0x4?"err":"ok" + ,data[0]&0x2?"err":"ok" + ,data[0]&0x1?"fatal":"ok" + ); + log_hex(TAG,data,sizeof(data),"data read:"); + uint32_t tempraw = (data[7]<<16) | (data[6]<<8) | data[5]; + log_dbug(TAG,"tempraw = %u",tempraw); + calc_tfine(tempraw); + uint32_t pressraw = (data[4]<<16) | (data[3]<<8) | data[2]; + calc_press(pressraw); +#ifdef CONFIG_NEWLIB_LIBRARY_LEVEL_FLOAT_NANO + log_dbug(TAG,"t=%G, p=%G",m_temp.get(),m_press.get()); +#else + if (log_module_enabled(TAG)) { + char ts[16],ps[16]; + float_to_str(ts,m_temp.get()); + float_to_str(ps,m_press.get()); + log_dbug(TAG,"t=%s,p=%s",ts,ps); + } +#endif + i2c_write2(m_bus,m_addr,REG_PWR_CTRL,0); + return 0; +} + + +int BMP388::flush_fifo() +{ + return i2c_write2(m_bus,m_addr,REG_CMD,CMD_FIFO_FLUSH); +} + + +bool BMP388::status() +{ + uint8_t status = 0; + if (i2c_w1rd(m_bus,m_addr,REG_STATUS,&status,1)) + return true; + if ((status & 0x8) == 0) + m_state = st_read; + return false; +} + + +int BMP388::init() +{ + if (esp_err_t r = i2c_write2(m_bus, m_addr, REG_CMD, CMD_RESET)) + log_warn(TAG,"failed to reset BMP388@%u,0x%x: %s",m_bus,m_addr,esp_err_to_name(r)); + uint8_t calib[21]; + + if (esp_err_t r = i2c_w1rd(m_bus,m_addr,CALIB_DATA,calib,sizeof(calib))) { + log_warn(TAG,"failed to read calibration of BMP388@%u,0x%x: %s",m_bus,m_addr,esp_err_to_name(r)); + return r; + } + log_hex(TAG,calib,sizeof(calib),"calib:"); + uint16_t t1 = ((uint16_t)calib[1] << 8) | calib[0]; + D[T1] = (float)t1 / powf(2,-8); + log_dbug(TAG,"t1 = %d, T1 = %g",t1,D[T1]); + + uint16_t t2 = ((uint16_t)calib[3] << 8) | calib[2]; + D[T2] = (float)t2 / powf(2,30); + log_dbug(TAG,"t2 = %d, T2 = %g",t2,D[T2]); + + int8_t t3 = (int8_t)calib[4]; + D[T3] = (float)t3 / powf(2,48); + log_dbug(TAG,"t3 = %d, T3 = %g",t3,D[T3]); + + int16_t p1 = (calib[6] << 8) | calib[5]; + D[P1] = ((float)p1 - powf(2,14)) / powf(2,20); + int16_t p2 = (calib[8] << 8) | calib[7]; + D[P2] = ((float)p2 - powf(2,14)) / powf(2,29); + int8_t p3 = calib[9]; + D[P3] = (float)p3 / powf(2,32); + int8_t p4 = calib[10]; + D[P4] = (float)p4 / powf(2,37); + uint16_t p5 = (calib[12] << 8) | calib[11]; + D[P5] = (float)p5 / powf(2,-3); + uint16_t p6 = (calib[14] << 8) | calib[13]; + D[P6] = (float)p6 / powf(2,6); + int8_t p7 = calib[15]; + D[P7] = (float)p7 / powf(2,8); + int8_t p8 = calib[16]; + D[P8] = (float)p8 / powf(2,15); + int16_t p9 = (calib[18] << 8) | calib[17]; + D[P9] = (float)p9 / powf(2,48); + int8_t p10 = calib[19]; + D[P10] = (float)p10 / powf(2,48); + int8_t p11 = calib[20]; + D[P11] = (float)p11 / powf(2,65); + return 0; +} + + +unsigned bmp388_scan(uint8_t bus) +{ + unsigned num = 0; + uint8_t addr = ADDR_MIN; + do { + uint8_t id = 0; + int r = i2c_w1rd(bus,addr,REG_ID,&id,sizeof(id)); + // esp32 i2c stack has a bug and reports timeout + // although data was received correctly... + // so ignore return codes > 0 + log_dbug(TAG,"scan BMP388 at 0x%x: %d, id=0x%x",addr,r,id); + if ((r >= 0) && (id == 0x50)) { + I2CDevice *d = new BMP388(bus,addr); + d->init(); + num = 1; + } + addr += 2; + } while (addr <= ADDR_MAX); + return num; +} + +#endif // CONFIG_BMP388 diff --git a/drv/i2c/bmp388.h b/drv/i2c/bmp388.h new file mode 100644 index 0000000..a3bdf63 --- /dev/null +++ b/drv/i2c/bmp388.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2023, Thomas Maier-Komor + * Atrium Firmware Package for ESP + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef BMP388_H +#define BMP388_H + +#include "env.h" +#include "event.h" +#include "i2cdrv.h" + + +struct BMP388 : public I2CDevice +{ + BMP388(uint8_t port, uint8_t addr, const char *n = 0); + + const char *drvName() const + { return "bmp388"; } + + void addIntr(uint8_t intr) override; + int init() override; + void attach(class EnvObject *); +#ifdef CONFIG_I2C_XCMD + const char *exeCmd(struct Terminal &, int argc, const char **argv) override; +#endif + + protected: + float calc_press(int32_t adc_P, int32_t t_fine); + void calc_tfine(uint32_t); + void calc_press(uint32_t); + int flush_fifo(); + static void trigger(void *); + static void intr_handler(void *); + bool status(); + virtual int sample(); + virtual int read(); + virtual void handle_error(); + static unsigned cyclic(void *); + int get_error(); + int get_status(); + + EnvNumber m_temp, m_press; + float D[14]; + event_t m_irqev = 0; + typedef enum { st_idle, st_sample, st_measure, st_read } state_t; + state_t m_state = st_idle; +}; + + +unsigned bmp388_scan(uint8_t port); + +#endif diff --git a/drv/i2c/hdc1000.cpp b/drv/i2c/hdc1000.cpp index eab7284..4c2bcf9 100644 --- a/drv/i2c/hdc1000.cpp +++ b/drv/i2c/hdc1000.cpp @@ -121,8 +121,8 @@ unsigned HDC1000::cyclic() if (!m_cfgsynced) { // uint16_t cfg = (unsigned) m_tres | (unsigned) m_hres; uint8_t data[] = { m_addr, REG_CONFIG, (uint8_t)(m_cfg >> 8), (uint8_t)(m_cfg & 0xff) }; - if (i2c_write(m_bus,data,sizeof(data),1,1)) { - log_warn(TAG,"config sync failed"); + if (esp_err_t e = i2c_write(m_bus,data,sizeof(data),1,1)) { + log_warn(TAG,"config sync failed: %s",esp_err_to_name(e)); break; } m_cfgsynced = true; diff --git a/drv/i2c/i2cdrv.cpp b/drv/i2c/i2cdrv.cpp index 4cf8269..6b72dc9 100644 --- a/drv/i2c/i2cdrv.cpp +++ b/drv/i2c/i2cdrv.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2021, Thomas Maier-Komor + * Copyright (C) 2021-2023, Thomas Maier-Komor * Atrium Firmware Package for ESP * * This program is free software: you can redistribute it and/or modify @@ -21,6 +21,7 @@ #ifdef CONFIG_I2C #include "bmx.h" +#include "bmp388.h" #include "i2cdrv.h" #include "log.h" @@ -450,6 +451,10 @@ int i2c_init(uint8_t port, uint8_t sda, uint8_t scl, unsigned freq, uint8_t xpul log_info(TAG,"search bmx"); n += bmx_scan(port); #endif +#ifdef CONFIG_BMP388 + log_info(TAG,"search bmp388"); + n += bmp388_scan(port); +#endif #ifdef CONFIG_SGP30 log_info(TAG,"search sgp30"); n += sgp30_scan(port); diff --git a/drv/i2c/opt3001.cpp b/drv/i2c/opt3001.cpp index c6b86d7..521a021 100644 --- a/drv/i2c/opt3001.cpp +++ b/drv/i2c/opt3001.cpp @@ -20,8 +20,11 @@ #ifdef CONFIG_OPT3001 +#include "actions.h" +#include "cyclic.h" #include "opt3001.h" #include "log.h" +#include "xio.h" #define REG_RESULT 0x00 #define REG_CONFIG 0x01 @@ -61,21 +64,23 @@ static const float Ranges[] = OPT3001::OPT3001(unsigned bus, unsigned addr) -: I2CDevice(bus,addr) -, m_lux("luminance","lux") +: I2CDevice(bus,addr,drvName()) +, m_lum("luminance","lux") { + m_lum.set(NAN); } void OPT3001::addIntr(uint8_t gpio) { + m_isrev = event_register(m_name,"`isr"); xio_cfg_t cfg = XIOCFG_INIT; cfg.cfg_io = xio_cfg_io_in; cfg.cfg_pull = xio_cfg_pull_up; cfg.cfg_intr = xio_cfg_intr_fall; if (0 > xio_config(gpio,cfg)) { log_warn(TAG,"gpio %u as interrupt failed",gpio); - } else if (xio_set_intr(gpio,intr,b)) { + } else if (xio_set_intr(gpio,intrHandler,this)) { log_warn(TAG,"add handler for gpio %u interrupt failed",gpio); } } @@ -83,7 +88,6 @@ void OPT3001::addIntr(uint8_t gpio) void OPT3001::attach(EnvObject *root) { root->add(&m_lum); - root->add(&m_press); cyclic_add_task(m_name,OPT3001::cyclic,this,0); action_add(concat(m_name,"!sample"),sample,(void*)this,"OPT3001 sample data"); } @@ -91,13 +95,25 @@ void OPT3001::attach(EnvObject *root) unsigned OPT3001::cyclic(void *arg) { - read(); + OPT3001 *dev = (OPT3001 *) arg; + dev->read(); return 1000; } OPT3001 *OPT3001::create(unsigned bus, unsigned addr) { + uint8_t data[2]; + if (esp_err_t e = i2c_w1rd(bus,addr,REG_MANID,data,sizeof(data))) { + log_warn(TAG,"cannot read manufacturer id: %s",esp_err_to_name(e)); + return 0; + } + log_info(TAG,"manufacturer id 0x%x",data[0] | (data[1]<<8)); + if (esp_err_t e = i2c_w1rd(bus,addr,REG_DEVID,data,sizeof(data))) { + log_warn(TAG,"cannot read device id: %s",esp_err_to_name(e)); + return 0; + } + log_info(TAG,"device id 0x%x",data[0] | (data[1]<<8)); return new OPT3001(bus,addr); } @@ -111,24 +127,51 @@ const char *OPT3001::exeCmd(Terminal &term, int argc, const char **args) #endif -void OPT3001::intr(void *arg) +int OPT3001::init() +{ + // configure to contiuous sampling + // 800ms sampling time + uint8_t cfg[] = { m_addr, REG_CONFIG, 0xce, 0x00 }; + if (esp_err_t e = i2c_write(m_bus,cfg,sizeof(cfg),1,1)) { + log_warn(TAG,"failed to config device: %s",esp_err_to_name(e)); + return 1; + } + return 0; +} + + +void OPT3001::intrHandler(void *arg) { OPT3001 *dev = (OPT3001 *) arg; - // TODO + event_isr_trigger(dev->m_isrev); } int OPT3001::read() { - uint8_t data[2]; - if (int r = i2c_w1rd(m_bus,m_addr,REG_RESULT,data,sizeof(data))) + uint8_t data[2] = { 0, 0 }; + if (int r = i2c_w1rd(m_bus,m_addr,REG_CONFIG,data,sizeof(data))) { + log_warn(TAG,"read error: %s",esp_err_to_name(r)); + m_lum.set(NAN); + return r; + } + log_dbug(TAG,"status: %s%s%s" + , data[1]&0x80?" CRF":"" + , data[1]&0x40?" FH":"" + , data[1]&0x20?" FL":"" + ); + if (int r = i2c_w1rd(m_bus,m_addr,REG_RESULT,data,sizeof(data))) { + log_warn(TAG,"read error: %s",esp_err_to_name(r)); + m_lum.set(NAN); return r; + } + log_dbug(TAG,"read: %02x %02x",data[0],data[1]); uint16_t val = ((uint16_t)data[0] << 8) | data[1]; uint8_t exp = val >> 12; - uint16_t &= 0xfff; + val &= 0xfff; float scale = ((float)(1< #include "env.h" +#include "event.h" #include "i2cdrv.h" struct OPT3001 : public I2CDevice { - static unsigned scan(unsigned bus); + static OPT3001 *create(unsigned bus, unsigned addr); + + const char *drvName() const override + { return "opt3001"; } void attach(EnvObject *root) override; void addIntr(uint8_t intr) override; - unsigned cyclic(void *arg); #ifdef CONFIG_I2C_XCMD const char *exeCmd(Terminal &term, int argc, const char **args) override; #endif - int read(); + int init() override; private: OPT3001(unsigned bus, unsigned addr); - void sample(void *arg); + static void sample(void *arg); + static void intrHandler(void *); + static unsigned cyclic(void *arg); + int read(); - EnvNumber m_lux; + EnvNumber m_lum; + event_t m_isrev = 0; }; #endif diff --git a/drv/i2c/sgp30.cpp b/drv/i2c/sgp30.cpp index dc4c687..6a8021b 100644 --- a/drv/i2c/sgp30.cpp +++ b/drv/i2c/sgp30.cpp @@ -229,11 +229,14 @@ unsigned SGP30::cyclic() } break; case st_error: + m_state = st_init; return 3000; } log_dbug(TAG,"had error"); m_err = e; m_state = st_error; + m_tvoc.set(NAN); + m_co2.set(NAN); return 5000; } @@ -480,6 +483,9 @@ int SGP30::read() unsigned sgp30_scan(uint8_t bus) { + uint8_t vercmd[] = { SGP30_ADDR, REG_BASE, REG_GET_VERS }; + if (0 != i2c_write(bus,vercmd,sizeof(vercmd),false,true)) + return 0; return SGP30::create(bus) != 0; } diff --git a/drv/i2c/sh1106.cpp b/drv/i2c/sh1106.cpp new file mode 100644 index 0000000..5785999 --- /dev/null +++ b/drv/i2c/sh1106.cpp @@ -0,0 +1,384 @@ +/* + * Copyright (C) 2023, Thomas Maier-Komor + * Atrium Firmware Package for ESP + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#ifdef CONFIG_SH1106 + +#include "sh1106.h" +#include "log.h" +#include "profiling.h" + +//#include "fonts.h" +#include +#include + +#include +#include + +#define CHAR_WIDTH 6 +#define CHAR_HEIGHT 8 + +#define CTRL_CMD1 0x00 // command and data +#define CTRL_CMDN 0x80 // command with more commands +#define CTRL_CMDC 0xc0 // continuation command +#define CTRL_DATA 0x00 // data only + +#define SH1106_ADDR0 0x3c +#define SH1106_ADDR1 0x3d + +#define CMD_NOP 0xe3 + +#define TAG MODULE_SSD130X + + + +SH1106 *SH1106::Instance = 0; + + +SH1106::SH1106(uint8_t bus, uint8_t addr) +: I2CDevice(bus,addr,drvName()) +{ + Instance = this; + log_info(TAG,"ssd1306 at %u,0x%x",bus,addr); +} + + +int SH1106::init(uint8_t maxx, uint8_t maxy, uint8_t hwcfg) +{ + log_info(TAG,"init(%u,%u)",maxx,maxy); + m_width = maxx; + m_height = maxy; + uint32_t dsize = maxx * maxy; + m_disp = (uint8_t *) malloc(dsize); // two dimensional array of n pages each of n columns. + if (m_disp == 0) { + log_error(TAG,"out of memory"); + return 1; + } + /* + uint8_t setup[] = { + m_addr, + 0xae, // display off + 0xa4, // output RAM + 0xaf, + 0x00, // set lower column start address + 0xd5, 0x80, // oszi freq (default), clock div=1 (optional) + 0xa8, (uint8_t)(m_height-1), // MUX + 0xd3, 0x00, // display offset (optional) + 0x40, // display start line (optional) + 0x8d, 0x14, // enable charge pump + 0x20, 0x00, // address mode: horizontal + 0xa0, // map address 0 to seg0 + (uint8_t) (0xc0 | (hwcfg&hwc_iscan)), // scan 0..n + 0xda, // COM hardware config + (uint8_t) (hwcfg&(hwc_rlmap|hwc_altm)), + 0x81, 0x80, // medium contrast + 0xd9, 0x22, // default pre-charge (optional) + 0xa6, // normal mode, a7=inverse + 0x2e, // no scrolling + }; + if (i2c_write(m_bus,setup,sizeof(setup),1,1)) + return 1; + */ + xmitCmd(0xae); + xmitCmd(0xa4); + vTaskDelay(100); + clear(); + flush(); + setOn(true); + initOK(); + log_info(TAG,"ready"); + return 0; +} + + +void SH1106::xmitCmds(uint8_t *cmd, unsigned n) +{ + do { + xmitCmd(*cmd); + ++cmd; + --n; + } while (n); +} + + +int SH1106::xmitCmd(uint8_t cmd) +{ + log_dbug(TAG,"xmitCmd(0x%x)",cmd); + return i2c_write2(m_bus,m_addr,0x00,cmd); +} + + +int SH1106::setOn(bool on) +{ + log_dbug(TAG,"setOn(%d)",on); + return xmitCmd(0xae|on); + /* + uint8_t cmd_on[] = { m_addr, 0x00, 0xaf }; + uint8_t cmd_off[] = { m_addr, 0x00, 0xae }; + return i2c_write(m_bus,on ? cmd_on : cmd_off,sizeof(cmd_on),1,1); + */ +} + +int SH1106::setInvert(bool inv) +{ + log_dbug(TAG,"invert(%d)",inv); + return xmitCmd(0xa6|inv); + /* + uint8_t cmd[3] = { m_addr, 0x00, 0xa6 }; + if (inv) + cmd[2] |= 1; + return i2c_write(m_bus,cmd,sizeof(cmd),1,1); + */ +} + + +int SH1106::setBrightness(uint8_t contrast) +{ + uint8_t cmd[] = { m_addr, 0x00, 0x81, contrast }; + return i2c_write(m_bus,cmd,sizeof(cmd),1,1); +} + + +void SH1106::flush() +{ + if (m_dirty == 0) + return; + PROFILE_FUNCTION(); + uint8_t cmd[] = { m_addr, 0x00, 0x00, 0x10, 0xb0 }; + uint8_t pfx[] = { m_addr, 0x40 }; + uint8_t numpg = m_height / 8 + ((m_height & 7) != 0); + unsigned pgs = m_width; + if (m_dirty) { + for (uint8_t p = 0; p < numpg; p++) { + if (m_dirty & (1<= m_width) || (y >= m_height)) { + log_dbug(TAG,"off display %u,%u",x,y); + return 1; + } + uint8_t shift = y & 7; + uint8_t pg = y >> 3; + uint16_t idx = pg * m_width + x; + uint8_t b0 = m_disp[idx]; + if (shift) { + b0 >>= shift; + idx += m_width; + if (idx < (m_width*m_height)) { + uint8_t b1 = m_disp[idx]; + b1 <<= (8-shift); + b0 |= b1; + } + } + *b = b0; + return 0; +} + + +int SH1106::drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m) +{ + uint8_t o; + if (readByte(x,y,&o)) + return 1; + o &= ~m; + o |= (b & m); + return drawByte(x,y,o); +} + + +/* +static uint16_t scaleDouble(uint8_t byte) +{ + uint16_t r = 0; + uint16_t m = 1; + for (uint8_t b = 0; b < 8; ++b) { + if (byte & (1<> 3; + unsigned off = pg * m_width + x; + uint8_t shl = y & 7; + uint16_t b0 = (uint16_t)b << shl; + uint8_t b1 = (uint8_t)(b0 >> 8); + if (b1) + m_disp[off+m_width] |= b1; + m_disp[off] |= (uint8_t)(b0&0xff); +// log_dbug(TAG,"drawBits %x at %u",b0,off); + return 0; +} + + +int SH1106::drawByte(uint8_t x, uint8_t y, uint8_t b) +{ + uint8_t pg = y >> 3; + uint16_t idx = pg * m_width + x; + if ((x >= m_width) || (y >= m_height)) { + log_dbug(TAG,"off display %u,%u=%u pg=%u",(unsigned)x,(unsigned)y,(unsigned)idx,(unsigned)pg); + return 1; + } + uint8_t shift = y & 7; + if (shift != 0) { + uint16_t idx2 = idx + m_width; + if (idx2 >= (m_width*m_height)) + return 1; + m_dirty |= 1<<(pg+1); + uint16_t w = (uint16_t) b << shift; + uint16_t m = 0xff << shift; + m = ~m; + uint8_t b0 = (m_disp[idx] & m) | (w & 0xFF); + if (b0 != m_disp[idx]) { + m_disp[idx] = b0; + m_dirty |= 1<> 8)) | (w >> 8); + idx = idx2; + } + if (m_disp[idx] != b) { + m_dirty |= 1<> 3; + uint8_t byte = data[b]; + unsigned bitst = off & 7; + uint8_t got = 8-bitst; + byte >>= bitst; + if (got < numb) + byte |= data[b+1] << got; +// log_dbug(TAG,"getBits(%u,%u): %x",off,numb,byte); + return byte; +} + + +void SH1106::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) +{ + static const uint8_t masks[] = {0x1,0x3,0x7,0xf,0x1f,0x3f,0x7f}; + unsigned len = w*h; + uint16_t bitoff = 0; + log_dbug(TAG,"SH1106::drawBitmap(%u,%u,%u,%u) %u/%u",x,y,w,h,len,len/8); + for (uint8_t x0 = x; x0 < x+w; ++x0) { + uint8_t yoff = y; + uint8_t numb = h; + while (numb) { +// log_dbug(TAG,"numb=%u",numb); + uint8_t byte = getBits(data,bitoff,numb); + if (numb >= 8) { +// log_dbug(TAG,"byte %x at %u/%u",byte,x0,y+yoff); + if (byte) + drawByte(x0,yoff,byte); + numb -= 8; + yoff += 8; + bitoff += 8; + } else { + byte &= masks[numb-1]; + if (byte) { +// drawBits(x0,yoff,byte,numb); + uint8_t pg = yoff >> 3; + unsigned off = pg * m_width + x0; + uint8_t shl = yoff & 7; + uint16_t b0 = (uint16_t)byte << shl; + m_disp[off] |= (uint8_t)(b0&0xff); + uint8_t b1 = (uint8_t)(b0 >> 8); + if (b1) + m_disp[off+m_width] |= b1; + } + bitoff += numb; + break; + } + } + } +} + + + +SH1106 *SH1106::create(uint8_t bus, uint8_t addr) +{ + addr <<= 1; + uint8_t cmd[] = { (uint8_t)addr, 0x00, CMD_NOP }; + if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) { + return new SH1106(bus,addr); + } + return 0; +} + + +unsigned sh1106_scan(uint8_t bus) +{ + log_dbug(TAG,"searching for SH1106"); + uint8_t addrs[] = { 0x3c, 0x3d }; + for (uint8_t addr : addrs) { + if (SH1106::create(bus,addr)) + return 1; + } + return 0; +} + +#endif diff --git a/drv/i2c/sh1106.h b/drv/i2c/sh1106.h new file mode 100644 index 0000000..8ba10b9 --- /dev/null +++ b/drv/i2c/sh1106.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2023, Thomas Maier-Komor + * Atrium Firmware Package for ESP + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef SH1106_H +#define SH1106_H + +#include "ssd130x.h" +#include "i2cdrv.h" + +class SH1106 : public SSD130X, public I2CDevice +{ + public: + enum hwcfg_t : uint8_t { + hwc_iscan = 0x8, // inverted scan + hwc_altm = 0x10, // alternating rows (non-sequential) + hwc_rlmap = 0x20, // right-to-left mapping + }; + + SH1106(uint8_t bus, uint8_t addr); + + static SH1106 *create(uint8_t bus, uint8_t addr); + int init(uint8_t maxx, uint8_t maxy, uint8_t options); + void drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override; + + void flush() override; + int setBrightness(uint8_t contrast) override; + int setInvert(bool inv) override; + int setOn(bool on) override; + + const char *drvName() const + { return "sh1106"; } + + static SH1106 *getInstance() + { return Instance; } + + uint8_t maxBrightness() const override + { return 255; } + + private: + int drawByte(uint8_t x, uint8_t y, uint8_t b); + int drawBits(uint8_t x, uint8_t y, uint8_t b, uint8_t n); + int drawChar(char c); + int readByte(uint8_t x, uint8_t y, uint8_t *b); + int drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m); + int xmitCmd(uint8_t cmd); + void xmitCmds(uint8_t *cmd, unsigned n); + + static SH1106 *Instance; +}; + +unsigned sh1106_scan(uint8_t bus); + +#endif + diff --git a/drv/i2c/ssd1306.cpp b/drv/i2c/ssd1306.cpp index b3c54d6..21fd5d0 100644 --- a/drv/i2c/ssd1306.cpp +++ b/drv/i2c/ssd1306.cpp @@ -39,6 +39,9 @@ #define CTRL_CMDC 0xc0 // continuation command #define CTRL_DATA 0x00 // data only +#define SSD1306_ADDR0 0x3c +#define SSD1306_ADDR1 0x3d + #define CMD_NOP 0xe3 #define TAG MODULE_SSD130X @@ -52,17 +55,10 @@ SSD1306::SSD1306(uint8_t bus, uint8_t addr) : I2CDevice(bus,addr,drvName()) { Instance = this; + log_info(TAG,"ssd1306 at %u,0x%x",bus,addr); } -/* -SSD130X::~SSD130X() -{ - free(m_disp); -} -*/ - - int SSD1306::init(uint8_t maxx, uint8_t maxy, uint8_t hwcfg) { log_info(TAG,"init(%u,%u)",maxx,maxy); @@ -129,85 +125,6 @@ int SSD1306::setBrightness(uint8_t contrast) } -/* -void SSD1306::clear() -{ - uint8_t numpg = m_height >> 3; - uint8_t pg = 0; - do { - uint8_t *at = m_disp + m_width * pg; - uint8_t *pge = at + m_width; - do { - if (*at) - break; - ++at; - } while (at != pge); - if (at != pge) { - bzero(at, pge-at); - m_dirty |= 1 << pg; - } - } while (++pg != numpg); - m_posx = 0; - m_posy = 0; - log_dbug(TAG,"clear: dirty %x",m_dirty); -} -*/ - -/* -uint8_t SSD1306::fontHeight() const -{ - switch (m_font) { - case -1: return 8; - case -2: return 16; - default: - return Fonts[m_font].yAdvance; - } -} -*/ - - -/* -int SSD1306::clrEol() -{ - return fillRect(m_posx,m_posy,m_width-m_posx,fontHeight(),m_colbg); -} - - -uint16_t SSD1306::charsPerLine() const -{ - if (m_font == font_nativedbl) - return m_width/CHAR_WIDTH<<1; - return m_width/CHAR_WIDTH; -} - - -uint16_t SSD1306::numLines() const -{ - return m_height/fontHeight(); -} - - -int SSD1306::setFont(const char *fn) -{ - if (0 == strcasecmp(fn,"native")) { - m_font = (fontid_t)-1; - return 0; - } - if (0 == strcasecmp(fn,"nativedbl")) { - m_font = (fontid_t)-2; - return 0; - } - for (int i = 0; i < font_numfonts; ++i) { - if (0 == strcasecmp(Fonts[i].name,fn)) { - m_font = (fontid_t)i; - return 0; - } - } - return -1; -} -*/ - - void SSD1306::flush() { if (m_dirty == 0) @@ -372,118 +289,6 @@ int SSD1306::drawByte(uint8_t x, uint8_t y, uint8_t b) } -/* -int SSD1306::drawChar(char c) -{ - PROFILE_FUNCTION(); - switch ((unsigned char) c) { - case '\r': - m_posx = 0; - return 0; - case '\n': - m_posx = 0; - m_posy += fontHeight(); - return 0; - case 176: // '°' - c = 133; - break; - case 196: // 'Ä' - c = 130; - break; - case 220: // 'Ü' - c = 128; - break; - case 214: // 'Ö' - c = 132; - break; - case 223: // 'ß' - c = 134; - break; - case 228: // 'ä' - c = 129; - break; - case 246: // 'ö' - c = 131; - break; - case 252: // 'ü' - c = 127; - break; - default: - break; - } - uint8_t x = m_posx; - if (m_font == -1) { - if (c < 32) - return 1; - uint16_t idx = (c - 32)*6; - if (idx >= SizeofFont6x8) - return 1; - for (int c = 0; c < 6; ++c) - drawByte(x++, m_posy, Font6x8[idx+c]); - m_posx = x; - return 0; - } else if (m_font == -2) { - if (c < 32) - return 1; - uint16_t idx = (c - 32)*6; - if (idx >= SizeofFont6x8) - return 1; - for (int c = 0; c < 6; ++c) { - uint16_t w = scaleDouble(Font6x8[idx+c]); - drawByte(x, m_posy, w & 0xff); - drawByte(x, m_posy+8, w >> 8); - ++x; - drawByte(x, m_posy, w & 0xff); - drawByte(x, m_posy+8, w >> 8); - ++x; - } - m_posx = x; - return 0; - } - const Font *font = Fonts+(int)m_font; - if ((font < Fonts) || (font >= Fonts+(int)font_numfonts)) { - log_dbug(TAG,"invalid font"); - return 1; - } - if ((c < font->first) || (c > font->last)) - return 1; - uint8_t ch = c - font->first; - const uint8_t *off = font->bitmap + font->glyph[ch].bitmapOffset; - uint8_t w = font->glyph[ch].width; - uint8_t h = font->glyph[ch].height; - int8_t dx = font->glyph[ch].xOffset; - int8_t dy = font->glyph[ch].yOffset; - uint8_t a = font->glyph[ch].xAdvance; - log_dbug(TAG,"drawChar('%c') at %u/%u %ux%u",c,m_posx,m_posy,w,h); -// log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l); -// clearRect(m_posx,m_posy,dx+w,a); -// drawBitmap(m_posx+dx,m_posy+dy+font->yAdvance,w,h,off); - drawBitmap_ssd1306(m_posx+dx,m_posy+dy+font->yAdvance-1,w,h,off); - m_posx += a; - - return 0; -} - - -void SSD1306::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) -{ - unsigned len = w*h; - log_dbug(TAG,"drawBitmap(%u,%u,%u,%u,%d,%d)",x,y,w,h,fg,bg); - unsigned idx = 0; - uint8_t b = 0; - while (idx != len) { - if ((idx & 7) == 0) - b = data[idx>>3]; - int32_t col = b & 0x80 ? fg : bg; - if (col != -1) - setPixel(x+idx%w,y+idx/w,col); - b<<=1; - ++idx; - } -} -*/ - - static uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb) { unsigned b = off >> 3; @@ -498,7 +303,6 @@ static uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb) } -//int SSD1306::drawBitmap_ssd1306(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data) void SSD1306::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) { static const uint8_t masks[] = {0x1,0x3,0x7,0xf,0x1f,0x3f,0x7f}; @@ -539,213 +343,26 @@ void SSD1306::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const u // return 0; } -/* -int SSD1306::pClrPixel(uint16_t x, uint16_t y) -{ -// log_dbug(TAG,"clrPixel(%u,%u)",(unsigned)x,(unsigned)y); - if ((x < m_width) && (y < m_height)) { - uint8_t pg = y >> 3; - uint8_t *p = m_disp + pg * m_width + x; - uint8_t bit = 1 << (y & 7); - uint8_t b = *p; - if ((b & bit) != 0) { - *p = b & ~bit; - m_dirty |= (1 << pg); - } - return 0; - } - return -1; -} -int SSD1306::pSetPixel(uint16_t x, uint16_t y) -{ -// log_dbug(TAG,"setPixel(%u,%u)",(unsigned)x,(unsigned)y); - if ((x < m_width) && (y < m_height)) { - uint8_t pg = y >> 3; - uint8_t *p = m_disp + pg * m_width + x; - uint8_t bit = 1 << (y & 7); - uint8_t b = *p; - if ((b & bit) == 0) { - *p = b | bit; - m_dirty |= (1 << pg); - } - return 0; - } - return -1; -} - - -int SSD1306::setPixel(uint16_t x, uint16_t y, int32_t col) -{ -// log_dbug(TAG,"setPixel(%u,%u)",(unsigned)x,(unsigned)y); - if ((x < m_width) && (y < m_height)) { - uint8_t pg = y >> 3; - uint8_t *p = m_disp + pg * m_width + x; - uint8_t bit = 1 << (y & 7); - uint8_t b = *p; - if (col) { - if ((b & bit) == 0) { - *p = b | bit; - m_dirty |= (1 << pg); - } - } else { - if ((b & bit) != 0) { - *p = b & ~bit; - m_dirty |= (1 << pg); - } - } - return 0; - } - return -1; -} - - -void SSD1306::drawHLine(uint8_t x, uint8_t y, uint8_t n, int32_t col) -{ - if ((x + n > m_width) || (y >= m_height) || (col != 1)) - return; - uint8_t pg = y >> 3; - uint16_t off = x + pg * m_width; - uint8_t m = 1 << (y & 7); - uint8_t *p = m_disp+off; - do { - m |= *p; - if (*p != m) { - *p = m; - m_dirty |= (1 << pg); - } - ++p; - } while (--n); -} - - -void SSD1306::drawVLine(uint8_t x, uint8_t y, uint8_t n, int32_t col) -{ - if ((x >= m_width) || (y >= m_height) || (col != 1)) - return; - while (n) { - uint8_t pg = y >> 3; - uint16_t off = x + pg * m_width; - uint8_t shift = y & 7; - uint8_t m = 0; - if ((shift == 0) && (n >= 8)) { - m = 0xff; - n -= 8; - y += 8; - } else { - m = 0; - do { - m |= (1 << shift); - --n; - ++y; - ++shift; - } while ((shift < 8) && (n != 0)); - } - uint8_t *p = m_disp + off; - uint8_t v = *p | m; - if (v != *p) { - *p = v; - m_dirty |= (1< m_width) || (y >= m_height)) - return 1; - for (int i = x; i < x+w; ++i) { - uint16_t y0 = y; - uint16_t h0 = h; - do { - if (((y & 7) == 0) && (h0 >= 8)) { - drawByte(i,y0,0); - y0 += 8; - h0 -= 8; - } else { - clrPixel(i,y0); - ++y0; - --h0; - } - } while (h0 > 0); - } - return 0; -} -*/ - - -/* -int SSD1306::drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col) -{ - log_dbug(TAG,"drawRect(%u,%u,%u,%u)",x,y,w,h); - drawHLine(x,y,w,col); - drawHLine(x,y+h-1,w,col); - drawVLine(x,y,h,col); - drawVLine(x+w-1,y,h,col); - return 0; -} - - -int SSD1306::writeHex(uint8_t h, bool comma) +SSD1306 *SSD1306::create(uint8_t bus, uint8_t addr) { - log_dbug(TAG,"writeHex %x",h); - char c = h; - if (h < 10) - c += '0'; - else - c += 'A' - 10; - if (drawChar(c)) - return 1; - if (comma) { - if (drawChar('.')) - return 1; + addr <<= 1; + uint8_t cmd[] = { (uint8_t)addr, CMD_NOP }; + if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) { + return new SSD1306(bus,addr); } return 0; } -int SSD1306::setPos(uint16_t x, uint16_t y) +static int ssd1306_test(uint8_t bus, uint8_t addr) { - log_dbug(TAG,"setPos(%u/%u)",x,y); - x *= CHAR_WIDTH; - y *= fontHeight(); - if ((x >= m_width-(CHAR_WIDTH)) || (y > m_height-fontHeight())) { - log_dbug(TAG,"invalid pos %u/%u",x,y); + if (0 == i2c_write1(bus,addr,CMD_NOP)) { + new SSD1306(bus,addr); return 1; - } - log_dbug(TAG,"setPos %u/%u",x,y); - m_posx = x; - m_posy = y; - return 0; -} - - -int SSD1306::write(const char *text, int len) -{ - log_dbug(TAG,"write %s",text); - size_t n = 0; - while (len) { - char c = *text++; - if (c == 0) - return n; - drawChar(c); - ++n; - --len; - } - return n; -} -*/ - - -SSD1306 *SSD1306::create(uint8_t bus, uint8_t addr) -{ - addr <<= 1; - uint8_t cmd[] = { (uint8_t)addr, CMD_NOP }; - if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) { - return new SSD1306(bus,addr); + } else { + log_dbug(TAG,"no SSD1306 at 0x%x",addr); } return 0; } @@ -754,15 +371,10 @@ SSD1306 *SSD1306::create(uint8_t bus, uint8_t addr) unsigned ssd1306_scan(uint8_t bus) { log_dbug(TAG,"searching for SSD1306"); - uint8_t cmd[] = { (0x3c << 1), CMD_NOP }; - if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) { - new SSD1306(bus,cmd[0]); - return 1; - } - cmd[0] += 2; - if (0 == i2c_write(bus,cmd,sizeof(cmd),1,1)) { - new SSD1306(bus,cmd[0]); - return 1; + uint8_t addrs[] = { 0x3c, 0x3d }; + for (uint8_t addr : addrs) { + if (ssd1306_test(bus,addr<<1)) + return 1; } return 0; } diff --git a/drv/i2c/ssd1306.h b/drv/i2c/ssd1306.h index b5a312d..433e811 100644 --- a/drv/i2c/ssd1306.h +++ b/drv/i2c/ssd1306.h @@ -20,7 +20,6 @@ #define SSD1306_H #include "ssd130x.h" -//#include "fonts.h" #include "i2cdrv.h" class SSD1306 : public SSD130X, public I2CDevice @@ -37,48 +36,11 @@ class SSD1306 : public SSD130X, public I2CDevice static SSD1306 *create(uint8_t bus, uint8_t addr); int init(uint8_t maxx, uint8_t maxy, uint8_t options); void drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override; -// int drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col) override; - - /* - int write(const char *t, int n) override; - int writeHex(uint8_t, bool) override; - int clear() override; - int clrEol() override; - - uint16_t maxX() const override - { return m_maxx; } - - uint16_t maxY() const override - { return m_maxy; } - - int setXY(uint16_t x, uint16_t y) override - { - if (x >= m_maxx) - return -1; - if (y >= m_maxy) - return -1; - m_posx = x; - m_posy = y; - return 0; - } - - int setFont(unsigned f) override - { - m_font = (fontid_t) f; - return 0; - } - */ void flush() override; -// int setFont(const char *) override; int setBrightness(uint8_t contrast) override; -// int setPos(uint16_t x, uint16_t y) override; int setInvert(bool inv) override; int setOn(bool on) override; -// uint16_t numLines() const override; -// uint16_t charsPerLine() const override; - -// void setPixel(uint16_t x, uint16_t y, int32_t col) override; const char *drvName() const { return "ssd1306"; } @@ -90,21 +52,13 @@ class SSD1306 : public SSD130X, public I2CDevice { return 255; } private: -// int drawBitmap_ssd1306(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data); int drawByte(uint8_t x, uint8_t y, uint8_t b); int drawBits(uint8_t x, uint8_t y, uint8_t b, uint8_t n); -// void drawHLine(uint16_t x, uint16_t y, uint16_t n); -// void drawVLine(uint8_t x, uint8_t y, uint8_t n); int drawChar(char c); int readByte(uint8_t x, uint8_t y, uint8_t *b); int drawMasked(uint8_t x, uint8_t y, uint8_t b, uint8_t m); -// uint8_t fontHeight() const; static SSD1306 *Instance; -// uint8_t m_maxx = 0, m_maxy = 0, m_posx = 0, m_posy = 0; -// uint8_t *m_disp = 0; -// uint8_t m_dirty = 0xff; -// fontid_t m_font = font_native; }; unsigned ssd1306_scan(uint8_t bus); diff --git a/drv/i2c/ti.cpp b/drv/i2c/ti.cpp index 1e539f1..4dc3d38 100644 --- a/drv/i2c/ti.cpp +++ b/drv/i2c/ti.cpp @@ -21,6 +21,7 @@ #ifdef CONFIG_I2C #include "hdc1000.h" +#include "opt3001.h" #include "log.h" #define DEV_ADDR (0x40<<1) @@ -42,9 +43,9 @@ static unsigned scan_addr(uint8_t bus, uint8_t addr) if (i2c_w1rd(bus,addr,REG_DEV_ID,data,sizeof(data))) return 0; uint16_t id = (data[0] << 8) | data[1]; - log_dbug(TAG,"found TI device 0x%04x",id); + log_info(TAG,"found TI device 0x%04x",id); #ifdef CONFIG_HDC1000 - if ((id = 0x1000) || (id == 0x1050)) { + if ((id == 0x1000) || (id == 0x1050)) { if (I2CDevice *s = HDC1000::create(bus,addr,id)) { s->init(); return 1; @@ -59,6 +60,7 @@ static unsigned scan_addr(uint8_t bus, uint8_t addr) } } #endif + log_warn(TAG,"no driver for device id 0x%04x",id); return 0; } diff --git a/drv/spi/ssd1309.cpp b/drv/spi/ssd1309.cpp index a736666..a16a193 100644 --- a/drv/spi/ssd1309.cpp +++ b/drv/spi/ssd1309.cpp @@ -24,7 +24,6 @@ #include "log.h" #include "profiling.h" -//#include "fonts.h" #include #include @@ -47,37 +46,44 @@ #define TAG MODULE_SSD130X - +#if 1 +#define log_devel log_dbug +#else +#define log_devel(...) +#endif SSD1309 *SSD1309::Instance = 0; -SSD1309::SSD1309(spi_host_t host, int8_t cs, uint8_t dc, int8_t reset, struct spi_device_t *hdl) -: SpiDevice(drvName(), cs) -, m_sem(xSemaphoreCreateBinary()) -, m_dc((gpio_num_t)dc) -, m_reset((gpio_num_t)reset) +static IRAM_ATTR void ssd1309_preop(spi_transaction_t *t) { -#ifndef CONFIG_IDF_TARGET_ESP8266 - m_hdl = hdl; -#endif - if (cs >= 0) { - if (esp_err_t e = gpio_set_direction((gpio_num_t)cs,GPIO_MODE_OUTPUT)) - log_warn(TAG,"cannot set gpio%d to output: %s",cs,esp_err_to_name(e)); + if (ssd1309_trans_t *a = (ssd1309_trans_t *) t->user) { + if (a->set) + if (esp_err_t e = gpio_set_level(a->gpio,a->lvl)) + log_warn(TAG,"set DC: %s",esp_err_to_name(e)); } - gpio_set_level(m_dc,0); } -inline void SSD1309::setC() +static IRAM_ATTR void ssd1309_postop(spi_transaction_t *t) { - gpio_set_level(m_dc,0); + if (ssd1309_trans_t *a = (ssd1309_trans_t *) t->user) { + if (a->sem) + xSemaphoreGive(a->sem); + } } -inline void SSD1309::setD() +SSD1309::SSD1309(spi_host_t host, int8_t cs, uint8_t dc, int8_t reset, struct spi_device_t *hdl) +: SpiDevice(drvName(), cs) +, m_dc((gpio_num_t)dc) +, m_reset((gpio_num_t)reset) { - gpio_set_level(m_dc,1); +#ifndef CONFIG_IDF_TARGET_ESP8266 + m_hdl = hdl; +#endif + gpio_set_level(m_reset,1); + gpio_set_level(m_dc,0); } @@ -87,37 +93,47 @@ SSD1309 *SSD1309::create(spi_host_device_t host, int8_t cs, int8_t dc, int8_t re SSD1309 *SSD1309::create(spi_host_device_t host, spi_device_interface_config_t &cfg, int8_t dc, int8_t reset) #endif { + if (Instance) { + log_warn(TAG,"instance already exists"); + return Instance; + } if ((dc < 0) || (reset < 0)) return 0; + int8_t cs = cfg.spics_io_num; if (esp_err_t e = gpio_set_direction((gpio_num_t)dc,GPIO_MODE_OUTPUT)) { - log_warn(TAG,"cannot set gpio%d to output: %s",dc,esp_err_to_name(e)); + log_warn(TAG,"set DC/gpio%d to output: %s",dc,esp_err_to_name(e)); + return 0; + } + gpio_set_level((gpio_num_t)dc,1); + if (esp_err_t e = gpio_set_pull_mode((gpio_num_t)reset,GPIO_PULLUP_ONLY)) { + log_warn(TAG,"set RST/gpio%d pull-up: %s",reset,esp_err_to_name(e)); return 0; } if (esp_err_t e = gpio_set_direction((gpio_num_t)reset,GPIO_MODE_OUTPUT)) { - log_warn(TAG,"cannot set gpio%d to output: %s",reset,esp_err_to_name(e)); + log_warn(TAG,"set RST/gpio%d to output: %s",reset,esp_err_to_name(e)); + return 0; + } + if (esp_err_t e = gpio_set_direction((gpio_num_t)cs,GPIO_MODE_OUTPUT)) { + log_warn(TAG,"set CS/gpio%d to output: %s",cs,esp_err_to_name(e)); return 0; } #ifdef CONFIG_IDF_TARGET_ESP8266 void *hdl = 0; #else + cfg.mode = 2; cfg.command_bits = 0; cfg.address_bits = 0; cfg.cs_ena_pretrans = 0; cfg.clock_speed_hz = SPI_MASTER_FREQ_8M; - cfg.queue_size = 1; - cfg.post_cb = postCallback; - int8_t cs = cfg.spics_io_num; + cfg.queue_size = 8; + cfg.pre_cb = ssd1309_preop; + cfg.post_cb = ssd1309_postop; spi_device_handle_t hdl; -#endif - if (Instance) { - log_warn(TAG,"instance already exists"); -#ifndef CONFIG_IDF_TARGET_ESP8266 - } else if (esp_err_t e = spi_bus_add_device(host,&cfg,&hdl)) { + if (esp_err_t e = spi_bus_add_device(host,&cfg,&hdl)) log_warn(TAG,"device add failed: %s",esp_err_to_name(e)); + else #endif - } else { Instance = new SSD1309(host, cs, dc, reset, hdl); - } return Instance; } @@ -125,11 +141,21 @@ SSD1309 *SSD1309::create(spi_host_device_t host, spi_device_interface_config_t & int SSD1309::init(uint16_t maxx, uint16_t maxy, uint8_t hwcfg) { log_info(TAG,"init(%u,%u)",maxx,maxy); + if ((maxx > 128) || (maxx < 1)) { + log_warn(TAG,"invalid x resolution"); + return 1; + } + gpio_set_level(m_dc,1); if (m_reset >= 0) { + gpio_set_level(m_reset,1); + ets_delay_us(100); + vTaskDelay(2); gpio_set_level(m_reset,0); ets_delay_us(100); + vTaskDelay(2); gpio_set_level(m_reset,1); ets_delay_us(100); + vTaskDelay(2); } m_width = maxx; m_height = maxy; @@ -139,103 +165,36 @@ int SSD1309::init(uint16_t maxx, uint16_t maxy, uint8_t hwcfg) log_error(TAG,"Out of memory."); return 1; } - /* works, but column 127 is at offset 0. Related to a1 command? - * display options = 24 - uint8_t setup[] = { + static const uint8_t setup[] = { 0xae, // display off - 0xd5, 0x80, // oszi freq (default), clock div=1 (optional) - 0xa8, (uint8_t)(m_height-1), // MUX - 0xd3, 0x00, // display offset (optional) - 0x40, // display start line (optional) - 0x8d, 0x14, // enable charge pump + 0x00, 0x10, // low CSA in PAM 0x20, 0x00, // address mode: horizontal - 0xa1, // map address 0 to seg0 - (uint8_t) (0xc0 | (hwcfg&hwc_iscan)), // scan 0..n - 0xda, // COM hardware config - (uint8_t) (hwcfg&(hwc_rlmap|hwc_altm)), 0x81, 0x80, // medium contrast + 0xa6, // normal mode, a7=inverse + 0xa8, (uint8_t)(m_height-1), // MUX + 0xd3, 0x00, // display offset (optional) + 0xd5, 0x80, // oszi freq (default), clock div=1 (optional) 0xd9, 0x22, // default pre-charge (optional) -// 0x21, 0x0, 0x7f, -// 0x00, 0x10, - 0x22, 0x0, 0x7, + 0xda, 0x12, // COM hardware config + // (uint8_t) ((hwcfg&(hwc_rlmap|hwc_altm))|0x2), 0xa4, // output RAM - 0xa6, // normal mode, a7=inverse - 0x2e, // no scrolling 0xaf, // display on - }; - */ - uint8_t setup[] = { - 0xae, // display off - 0xd5, 0x80, // oszi freq (default), clock div=1 (optional) - 0xa8, (uint8_t)(m_height-1), // MUX - 0xd3, 0x00, // display offset (optional) + /* 0x40, // display start line (optional) 0x8d, 0x14, // enable charge pump - 0x20, 0x00, // address mode: horizontal - //0x20, 0x02, // address mode: page +// 0x20, 0x02, // address mode: page 0xa0, // map address 0 to seg0 (uint8_t) (0xc0 | (hwcfg&hwc_iscan)), // scan 0..n - 0xda, // COM hardware config - (uint8_t) ((hwcfg&(hwc_rlmap|hwc_altm))|0x2), - 0x81, 0x80, // medium contrast - 0xd9, 0x22, // default pre-charge (optional) 0x21, 0x0, 0x7f, // column address range -// 0x00, 0x10, 0x22, 0x0, 0x7, // page address range - 0xa4, // output RAM - 0xa6, // normal mode, a7=inverse 0x2e, // no scrolling - 0xaf, // display on - }; - - /* something is broken here - uint8_t setup[] = { - // display off - 0xae, - // MUX - 0xa8, (uint8_t)(m_height-1), - // display offset (optional) - 0xd3, 0x00, - // display start line (optional) - 0x40, - // map address 0 to seg0 - 0xa0, - (uint8_t) (0xc0 | (hwcfg&hwc_iscan)), // scan 0..n - // COM hardware config - 0xda, (uint8_t) ((hwcfg&(hwc_rlmap|hwc_altm))|0x2), - // medium contrast - 0x81, 0x80, - // output RAM - 0xa4, - // normal mode, a7=inverse - 0xa6, - // oszi freq (default), clock div=1 (optional) - 0xd5, 0x80, - // enable charge pump - 0x8d, 0x14, - // display on - 0xaf, - // from here on custom stuff - // default pre-charge (optional) - 0xd9, 0x22, - // address mode: horizontal - 0x20, 0x00, -// 0x21, 0x0, 0x7f, -// 0x00, 0x10, -// 0x22, 0x0, 0x7, -// 0x2e, // no scrolling + */ }; - */ - setC(); - if (esp_err_t e = writeBytes(setup,sizeof(setup))) { - log_warn(TAG,"SPI write error: %s",esp_err_to_name(e)); - return 1; - } + writeBytes(setup,sizeof(setup),pre_c); clear(); flush(); - setOn(true); initOK(); log_info(TAG,"ready"); return 0; @@ -244,180 +203,68 @@ int SSD1309::init(uint16_t maxx, uint16_t maxy, uint8_t hwcfg) int SSD1309::setOn(bool on) { log_dbug(TAG,"setOn(%d)",on); - return writeByte(0xae|on); + uint8_t d[] = { (uint8_t)(0xae|on) }; + return writeBytes(d,sizeof(d),pre_c); } int SSD1309::setInvert(bool inv) { log_dbug(TAG,"invert(%d)",inv); - return writeByte(0xa6|inv); + uint8_t d[] = { (uint8_t)(0xa6|inv) }; + return writeBytes(d,sizeof(d),pre_c); } int SSD1309::setBrightness(uint8_t contrast) { - return writeWord(0x81,contrast); + uint8_t d[] = {0x81,contrast}; + return writeBytes(d,sizeof(d),pre_c); } -/* -void SSD1309::clear() -{ - uint8_t numpg = m_height >> 3; - uint8_t pg = 0; - do { - uint8_t *at = m_disp + m_width * pg; - uint8_t *pge = at + m_width; - do { - if (*at) - break; - ++at; - } while (at != pge); - if (at != pge) { - bzero(at, pge-at); - m_dirty |= 1 << pg; - } - } while (++pg != numpg); - m_posx = 0; - m_posy = 0; - log_dbug(TAG,"clear: dirty %x",m_dirty); -} - - -uint8_t SSD1309::fontHeight() const -{ - switch (m_font) { - case -1: return 8; - case -2: return 16; - default: - return FontsCM[m_font].yAdvance; - } -} - - -int SSD1309::clrEol() -{ - clearRect(m_posx,m_posy,m_width-m_posx,fontHeight()); - return 0; -} - - -uint8_t SSD1309::charsPerLine() const -{ - if (m_font == font_nativedbl) - return m_width/CHAR_WIDTH<<1; - return m_width/CHAR_WIDTH; -} - - -uint8_t SSD1309::numLines() const -{ - return m_height/fontHeight(); -} - - -int SSD1309::setFont(const char *fn) -{ - if (0 == strcasecmp(fn,"native")) { - m_font = (fontid_t)-1; - return 0; - } - if (0 == strcasecmp(fn,"nativedbl")) { - m_font = (fontid_t)-2; - return 0; - } - for (int i = 0; i < font_numfonts; ++i) { - if (0 == strcasecmp(Fonts[i].name,fn)) { - m_font = (fontid_t)i; - return 0; - } - } - return -1; -} -*/ - - void SSD1309::flush() { if (m_dirty == 0) return; PROFILE_FUNCTION(); - //writeByte(0xb0); -// uint8_t cmd[] = { 0x22, 0x00, (uint8_t)(m_width-1) }; - uint8_t cmd[] = { 0x00, 0x01, 0xb0 }; + uint8_t cmd[] = { 0x00, 0x10, 0xb0, }; uint8_t numpg = m_height / 8 + ((m_height & 7) != 0); unsigned pgs = m_width; if (pgs == 128) { if (m_dirty == 0xff) { - writeBytes(cmd,sizeof(cmd)); - setD(); - writeBytes(m_disp,128*8); - setC(); -// log_dbug(TAG,"flush 0-7"); + writeBytes(cmd,sizeof(cmd),pre_c); + writeBytes(m_disp,m_width*8,pre_d); + log_dbug(TAG,"sync 0-7"); m_dirty = 0; } else if (m_dirty == 0xf) { - writeBytes(cmd,sizeof(cmd)); - setD(); - writeBytes(m_disp,128*4); - setC(); -// log_dbug(TAG,"flush 0-3"); + writeBytes(cmd,sizeof(cmd),pre_c); + writeBytes(m_disp,m_width*4,pre_d); + log_dbug(TAG,"sync 0-3"); m_dirty = 0; } } if (m_dirty) { - for (uint8_t p = 0; p < numpg; p++) { - if (m_dirty & (1<> 3; uint16_t idx = pg * m_width + x; + log_devel(TAG,"drawByte(%u,%u,%u)",x,y,b); if ((x >= m_width) || (y >= m_height)) { log_dbug(TAG,"off display %u,%u=%u pg=%u",(unsigned)x,(unsigned)y,(unsigned)idx,(unsigned)pg); return 1; @@ -470,420 +318,69 @@ int SSD1309::drawByte(uint16_t x, uint16_t y, uint8_t b) } -/* -int SSD1309::drawChar(char c) -{ - PROFILE_FUNCTION(); - switch ((unsigned char) c) { - case '\r': - m_posx = 0; - return 0; - case '\n': - m_posx = 0; - m_posy += fontHeight(); - return 0; - case 176: // '°' - c = 133; - break; - case 196: // 'Ä' - c = 130; - break; - case 220: // 'Ü' - c = 128; - break; - case 214: // 'Ö' - c = 132; - break; - case 223: // 'ß' - c = 134; - break; - case 228: // 'ä' - c = 129; - break; - case 246: // 'ö' - c = 131; - break; - case 252: // 'ü' - c = 127; - break; - default: - break; - } - uint8_t x = m_posx; - if (m_font == -1) { - if (c < 32) - return 1; - uint16_t idx = (c - 32)*6; - if (idx >= SizeofFont6x8) - return 1; - for (int c = 0; c < 6; ++c) - drawByte(x++, m_posy, Font6x8[idx+c]); - m_posx = x; - return 0; - } else if (m_font == -2) { - if (c < 32) - return 1; - uint16_t idx = (c - 32)*6; - if (idx >= SizeofFont6x8) - return 1; - for (int c = 0; c < 6; ++c) { - uint16_t w = scaleDouble(Font6x8[idx+c]); - drawByte(x, m_posy, w & 0xff); - drawByte(x, m_posy+8, w >> 8); - ++x; - drawByte(x, m_posy, w & 0xff); - drawByte(x, m_posy+8, w >> 8); - ++x; - } - m_posx = x; - return 0; - } - const Font *font = Fonts+(int)m_font; - if ((font < Fonts) || (font >= Fonts+(int)font_numfonts)) { - log_dbug(TAG,"invalid font"); - return 1; - } - if ((c < font->first) || (c > font->last)) - return 1; - uint8_t ch = c - font->first; - const uint8_t *off = font->bitmap + font->glyph[ch].bitmapOffset; - uint8_t w = font->glyph[ch].width; - uint8_t h = font->glyph[ch].height; - int8_t dx = font->glyph[ch].xOffset; - int8_t dy = font->glyph[ch].yOffset; - uint8_t a = font->glyph[ch].xAdvance; - log_dbug(TAG,"drawChar('%c') at %u/%u %ux%u",c,m_posx,m_posy,w,h); -// log_info(TAG,"%d/%d %+d/%+d, adv %u len %u",(int)w,(int)h,(int)dx,(int)dy,a,l); -// clearRect(m_posx,m_posy,dx+w,a); -// drawBitmap(m_posx+dx,m_posy+dy+font->yAdvance,w,h,off); - drawBitmapNative(m_posx+dx,m_posy+dy+font->yAdvance-1,w,h,off); - m_posx += a; - - return 0; -} - - -int SSD1309::drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) -{ - unsigned len = w*h; - log_dbug(TAG,"drawBitmap(%u,%u,%u,%u) %u/%u",x,y,w,h,len,len/8); - unsigned idx = 0; - uint8_t b = 0; - while (idx != len) { - if ((idx & 7) == 0) - b = data[idx>>3]; - setPixel(x+idx%w,y+idx/w,b&0x80?fg:bg); - b<<=1; - ++idx; - } - return 0; -} -*/ - - -static uint8_t getBits(const uint8_t *data, unsigned off, uint8_t numb) -{ - unsigned b = off >> 3; - uint8_t byte = data[b]; - unsigned bitst = off & 7; - uint8_t got = 8-bitst; - byte >>= bitst; - if (got < numb) - byte |= data[b+1] << got; -// log_dbug(TAG,"getBits(%u,%u): %x",off,numb,byte); - return byte; -} - - -int SSD1309::drawBitmap_ssd1309(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data) -{ - static const uint8_t masks[] = {0x1,0x3,0x7,0xf,0x1f,0x3f,0x7f}; - unsigned len = w*h; - uint16_t bitoff = 0; - log_dbug(TAG,"drawBitmap_fast(%u,%u,%u,%u) %u/%u",x,y,w,h,len,len/8); - for (uint8_t x0 = x; x0 < x+w; ++x0) { - uint8_t yoff = y; - uint8_t numb = h; - while (numb) { -// log_dbug(TAG,"numb=%u",numb); - uint8_t byte = getBits(data,bitoff,numb); - if (numb >= 8) { -// log_dbug(TAG,"byte %x at %u/%u",byte,x0,y+yoff); - if (byte) - drawByte(x0,yoff,byte); - numb -= 8; - yoff += 8; - bitoff += 8; - } else { - byte &= masks[numb-1]; - if (byte) { -// drawBits(x0,yoff,byte,numb); - uint8_t pg = yoff >> 3; - unsigned off = pg * m_width + x0; - uint8_t shl = yoff & 7; - uint16_t b0 = (uint16_t)byte << shl; - m_disp[off] |= (uint8_t)(b0&0xff); - uint8_t b1 = (uint8_t)(b0 >> 8); - if (b1) - m_disp[off+m_width] |= b1; - } - bitoff += numb; - break; - } - } - } - return 0; -} - - -/* -int SSD1309::clrPixel(uint16_t x, uint16_t y) -{ -// log_dbug(TAG,"setPixel(%u,%u)",(unsigned)x,(unsigned)y); - if ((x < m_width) && (y < m_height)) { - uint8_t pg = y >> 3; - uint8_t *p = m_disp + pg * m_width + x; - uint8_t bit = 1 << (y & 7); - uint8_t b = *p; - if ((b & bit) != 0) { - *p = b & ~bit; - m_dirty |= (1 << pg); - } - return 0; - } - return -1; -} - - -int SSD1309::setPixel(uint16_t x, uint16_t y) -{ -// log_dbug(TAG,"setPixel(%u,%u)",(unsigned)x,(unsigned)y); - if ((x < m_width) && (y < m_height)) { - uint8_t pg = y >> 3; - uint8_t *p = m_disp + pg * m_width + x; - uint8_t bit = 1 << (y & 7); - uint8_t b = *p; - if ((b & bit) == 0) { - *p = b | bit; - m_dirty |= (1 << pg); - } - return 0; - } - return -1; -} - - -void SSD1309::drawHLine(uint16_t x, uint16_t y, uint16_t n) -{ - if ((x + n > m_width) || (y >= m_height)) - return; - uint8_t pg = y >> 3; - uint16_t off = x + pg * m_width; - uint8_t m = 1 << (y & 7); - uint8_t *p = m_disp+off; - do { - m |= *p; - if (*p != m) { - *p = m; - m_dirty |= (1 << pg); - } - ++p; - } while (--n); -} - - -void SSD1309::drawVLine(uint16_t x, uint16_t y, uint16_t n) +spi_transaction_t *SSD1309::getTransaction(pre_t pre) { - while (n) { - uint8_t pg = y >> 3; - uint16_t off = x + pg * m_width; - uint8_t shift = y & 7; - uint8_t m = 0; - if ((shift == 0) && (n >= 8)) { - m = 0xff; - n -= 8; - y += 8; - } else { - m = 0; - do { - m |= (1 << shift); - --n; - ++y; - ++shift; - } while ((shift < 8) && (n != 0)); - } - uint8_t *p = m_disp + off; - uint8_t v = *p | m; - if (v != *p) { - *p = v; - m_dirty |= (1<= 0) && (id < sizeof(m_trans)/sizeof(m_trans[0]))); + break; } } -} - - -int SSD1309::clearRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h) -{ - log_dbug(TAG,"clearRect(%u,%u,%u,%u)",x,y,w,h); - if ((x > m_width) || (y >= m_height)) - return 1; - for (int i = x; i < x+w; ++i) { - uint16_t y0 = y; - uint16_t h0 = h; - do { - if (((y & 7) == 0) && (h0 >= 8)) { - drawByte(i,y0,0); - y0 += 8; - h0 -= 8; - } else { - clrPixel(i,y0); - ++y0; - --h0; - } - } while (h0 > 0); - } - return 0; -} - - -int SSD1309::drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h) -{ - log_dbug(TAG,"drawRect(%u,%u,%u,%u)",x,y,w,h); - drawHLine(x,y,w); - drawHLine(x,y+h-1,w); - // why x offset??? - // x=127 is visible at x=0 - // x=0 is visible at x=1 - drawVLine(x,y,h); - drawVLine(x+w-1,y,h); -// log_hex(TAG,m_disp,m_width*m_height/8,"frame"); - return 0; -} - - -int SSD1309::writeHex(uint8_t h, bool comma) -{ -// log_dbug(TAG,"writeHex %x",h); - char c = h; - if (h < 10) - c += '0'; - else - c += 'A' - 10; - if (drawChar(c)) - return 1; - if (comma) { - if (drawChar('.')) - return 1; + if (t == 0) { + unsigned x = 0; + while (m_xtrans & (1 << x)) + ++x; + m_xtrans |= (1<= m_width-(CHAR_WIDTH)) || (y > m_height-fontHeight())) { - log_dbug(TAG,"invalid pos %u/%u",x,y); - return 1; + bzero(t,sizeof(ssd1309_trans_t)); + t->trans.user = t; + t->gpio = m_dc; + if (pre == pre_c) { + t->set = true; + t->lvl = false; + } else if (pre == pre_d) { + t->set = true; + t->lvl = true; } - log_dbug(TAG,"setPos %u/%u",x,y); - m_posx = x; - m_posy = y; - return 0; + return &t->trans; } -int SSD1309::write(const char *text, int len) +int SSD1309::writeBytes(const uint8_t *data, unsigned len, pre_t pre) { - log_dbug(TAG,"write '%s'",text); - size_t n = 0; - while (len) { - char c = *text++; - if (c == 0) - return n; - drawChar(c); - ++n; - --len; + log_hex(TAG,data,len,"writeBytes %u",pre); + spi_transaction_t *t = getTransaction(pre); + if (len > sizeof(t->tx_data)) { + t->tx_buffer = data; + } else { + memcpy(t->tx_data,data,len); + t->flags = SPI_TRANS_USE_TXDATA; } - return n; -} -*/ - - -IRAM_ATTR void SSD1309::postCallback(spi_transaction_t *t) -{ - SSD1309 *dev = (SSD1309 *) t->user; - xSemaphoreGive(dev->m_sem); -} - - -int SSD1309::writeBytes(uint8_t *data, unsigned len) -{ - spi_transaction_t t; - bzero(&t,sizeof(t)); - t.user = this; - t.length = len<<3; - t.rxlength = 0; - t.rx_buffer = 0; - t.tx_buffer = data; - if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) { + t->length = len<<3; + if (esp_err_t e = spi_device_queue_trans(m_hdl,t,portMAX_DELAY)) { log_warn(TAG,"error queuing read: %s",esp_err_to_name(e)); return -1; } - if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) - abort_on_mutex(m_sem,"ssd1309"); -// log_hex(TAG,data,len,"writeBytes"); return 0; -// spi_transaction_t *r = &t; -// return spi_device_get_trans_result(m_hdl,&r,1); } -int SSD1309::writeByte(uint8_t v) +int SSD1309::writeByte(uint8_t v, pre_t pre) { -#ifdef CONFIG_IDF_TARGET_ESP8266 - spi_trans_t t = {0}; - trans.mosi = &v; - trans.bits.mosi = 8; - return spi_trans(host,&trans); -#else - spi_transaction_t t; - bzero(&t,sizeof(t)); - t.flags = SPI_TRANS_USE_TXDATA; - t.user = this; - t.length = 1<<3; - t.tx_data[0] = v; - if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) { - log_warn(TAG,"error queuing read: %s",esp_err_to_name(e)); - return -1; - } - if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) - abort_on_mutex(m_sem,"ssd1309"); - log_dbug(TAG,"writeB 0x%02x",v); - return 0; -#endif + return writeBytes(&v,1,pre); } -int SSD1309::writeWord(uint8_t b0, uint8_t b1) +int SSD1309::writeWord(uint8_t l, uint8_t h, pre_t pre) { - spi_transaction_t t; - bzero(&t,sizeof(t)); - t.flags = SPI_TRANS_USE_TXDATA; - t.user = this; - t.length = 2<<3; - t.tx_data[0] = b0; - t.tx_data[1] = b1; - if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) { - log_warn(TAG,"error queuing read: %s",esp_err_to_name(e)); - return -1; - } - if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) - abort_on_mutex(m_sem,"ssd1309"); - log_dbug(TAG,"writeW 0x%02x, 0x%02x",b0,b1); - return 0; + uint8_t d[] = {l,h}; + return writeBytes(d,sizeof(d),pre); } diff --git a/drv/spi/ssd1309.h b/drv/spi/ssd1309.h index 5564ac7..0c14b09 100644 --- a/drv/spi/ssd1309.h +++ b/drv/spi/ssd1309.h @@ -19,16 +19,21 @@ #ifndef SSD1309_H #define SSD1309_H +#ifdef ESP32 #include "ssd130x.h" -//#include "fonts.h" #include "spidrv.h" -#include -#include - #include +struct ssd1309_trans_t { + spi_transaction_t trans; + SemaphoreHandle_t sem; + gpio_num_t gpio; + bool set,lvl; +}; + + class SSD1309 : public SSD130X, public SpiDevice { public: @@ -45,45 +50,8 @@ class SSD1309 : public SSD130X, public SpiDevice static SSD1309 *create(spi_host_t host, spi_device_interface_config_t &cfg, int8_t dc, int8_t reset); #endif int init(uint16_t maxx, uint16_t maxy, uint8_t options); - /* - int drawBitmap(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data, int32_t fg, int32_t bg) override; - void drawRect(uint16_t x, uint16_t y, uint16_t w, uint16_t h, int32_t col) override; - - int write(const char *t, int n) override; - int writeHex(uint8_t, bool) override; - int clear() override; -// int clrEol() override; - int flush() override; - - uint16_t maxX() const override - { return m_maxx; } - - uint16_t maxY() const override - { return m_maxy; } - - int setXY(uint16_t x, uint16_t y) override - { - if (x >= m_maxx) - return -1; - if (y >= m_maxy) - return -1; - m_posx = x; - m_posy = y; - return 0; - } - - int setFont(int f) override - { - m_font = (fontid_t) f; - return 0; - } - - int setFont(const char *) override; - */ - void flush() override; int setBrightness(uint8_t contrast) override; - //int setPos(uint16_t x, uint16_t y) override; int setInvert(bool inv) override; int setOn(bool on) override; const char *drvName() const @@ -95,43 +63,31 @@ class SSD1309 : public SSD130X, public SpiDevice bool hasChar(char) const override { return true; } -// uint16_t numLines() const override; -// uint16_t charsPerLine() const override; - static SSD1309 *getInstance() { return Instance; } -// void setPixel(uint16_t x, uint16_t y, int32_t v) override; -// int setPixel(uint16_t x, uint16_t y); -// int clrPixel(uint16_t x, uint16_t y); - private: SSD1309(spi_host_t host, int8_t cs, uint8_t cd, int8_t r, struct spi_device_t *); - int drawBitmap_ssd1309(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t *data); int drawByte(uint16_t x, uint16_t y, uint8_t b); int drawBits(uint16_t x, uint16_t y, uint8_t b, uint8_t n); void drawHLine(uint16_t x, uint16_t y, uint16_t n); void drawVLine(uint16_t x, uint16_t y, uint16_t n); int drawChar(char c); -// uint8_t fontHeight() const; #ifndef CONFIG_IDF_TARGET_ESP8266 static void postCallback(spi_transaction_t *t); #endif - void setC(); - void setD(); - int writeByte(uint8_t); - int writeWord(uint8_t, uint8_t); - int writeBytes(uint8_t *data, unsigned len); + typedef enum { pre_0, pre_c, pre_d } pre_t; + spi_transaction_t *getTransaction(pre_t); + int writeByte(uint8_t, pre_t = pre_c); + int writeWord(uint8_t, uint8_t, pre_t = pre_c); + int writeBytes(const uint8_t *data, unsigned len, pre_t pre); static SSD1309 *Instance; -// uint8_t *m_disp = 0; - SemaphoreHandle_t m_sem = 0; + ssd1309_trans_t m_trans[8]; + uint8_t m_xtrans = 0; gpio_num_t m_dc, m_reset; -// uint8_t m_maxx = 0, m_maxy = 0, m_posx = 0, m_posy = 0, m_dirty = 0xff; -// uint8_t m_dirty = 0xff; -// fontid_t m_font = font_native; }; - +#endif // ESP32 #endif diff --git a/drv/spi/sx1276.cpp b/drv/spi/sx1276.cpp index 0a7c9bb..97b81a9 100644 --- a/drv/spi/sx1276.cpp +++ b/drv/spi/sx1276.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, Thomas Maier-Komor + * Copyright (C) 2023, Thomas Maier-Komor * Atrium Firmware Package for ESP * * This program is free software: you can redistribute it and/or modify @@ -24,6 +24,7 @@ #include "env.h" #include "event.h" #include "log.h" +#include "shell.h" #include "sx1276.h" #include "terminal.h" #include "xio.h" @@ -101,10 +102,13 @@ #define FSKOOK_AFC_LSB 0x1c #define FSKOOK_FEI_MSB 0x1d #define FSKOOK_FEI_LSB 0x1e +#define FSKOOK_PREEMBLE_DETECT 0x1f +#define FSKOOK_OSC 0x24 #define FSKOOK_PACKET_CONFIG 0x30 #define FSKOOK_PAYLOAD_LENGTH 0x32 #define FSKOOK_NODE_ADRS 0x33 #define FSKOOK_BROADCAST_ADRS 0x34 +#define FSKOOK_FIFO_THRESH 0x35 #define FSKOOK_TEMP 0x3c #define FSKOOK_IRQ_FLAGS1 0x3e #define FSKOOK_IRQ_FLAGS2 0x3f @@ -141,7 +145,7 @@ // RX_CONFIG #define BIT_RESTART_RX_ON_COLLISSION (1<<7) #define BIT_RESTART_WITHOUT_PLL_LOCK (1<<6) -#define BIT_RESTART_WITH_PLL_LOCK (1<<5) +#define BIT_RESTART_RX_WPLL (1<<5) #define BIT_AFC_AUTO_ON (1<<4) #define BIT_AGC_AUTO_ON (1<<3) #define MODE_INTR_NONE 0 @@ -150,8 +154,9 @@ #define MODE_INTR_RX_PREAMBLE 7 // PACKET_CONFIG -#define BIT_FIXED_LENGTH (1<<7) +#define BIT_VARIABLE_LENGTH (1<<7) #define BIT_CRC_ON (1<<4) +#define BIT_CRC_AUTOCLEAROFF (1<<3) #define BIT_CRC_ON_PAYLOAD (1<<6) #define BIT_PLL_TIMEOUT (1<<7) @@ -159,7 +164,9 @@ #define BIT_RX_DONE (1<<6) #define BIT_PAYLOAD_CRC_ERROR (1<<5) #define BIT_VALID_HEADER (1<<4) -#define BIT_TX_DONE (1<<3) +#define BIT_TX_DONE (1<<3) // LORA +#define BIT_TX_READY (1<<5) // OOK/FSK +#define BIT_PACKET_SENT (1<<3) // OOK/FSK #define BIT_CAD_DONE (1<<2) #define BIT_FHSS_CHANGE_CHANEL (1<<1) #define BIT_CAD_DETECTED (1<<0) @@ -184,13 +191,50 @@ #define TAG MODULE_SX1276 -struct PaConfig +struct RegPaConfig { uint8_t output_power : 4; uint8_t max_power : 3; uint8_t pa_select : 1; }; +struct RegPaRamp // 0x0a +{ + uint8_t ramp:4; + uint8_t reserved:1; + uint8_t shaping:2; +}; + +struct RegOcp // 0x0b +{ + uint8_t trim:5; + uint8_t on:1; +}; + +struct RegLna // 0x0c +{ + uint8_t boosthf:2; + uint8_t reserved:1; + uint8_t boostlf:2; + uint8_t lnagain:3; +}; + +struct RegRxConfig // 0x0d +{ + uint8_t rxtrigger:3; + uint8_t agcautoon:1; + uint8_t afcautoon:1; + uint8_t restart_w_pll:1; + uint8_t restart_wo_pll:1; + uint8_t restart_on_coll:1; +}; + +struct RegRssiConfig // 0x0e +{ + uint8_t smoothing:3; + uint8_t offset:5; +}; + SX1276 *SX1276::m_inst = 0; @@ -204,6 +248,22 @@ static const char *ModeStrs[] = { "SLEEP", "STDBY", "FSTX", "TX", "FSRX", "RXCONT", "RXSINGLE", "CAD" }; +static const char *RegNames[] = { + "FIFO", "OpMode", "BitRateMsb", "BitRateLsb", "FdevMsb", + "FdevLsb", "FrFMsb", "FrfMid", "FrfLsb", "PaConfig", + "PaRamp", "Ocp", "Lna", "RxConfig", "RssiConfig", "RssiColl", + "RssiThresh", "RssiValue", "RxBw", "AfcBw", "OokPeak", "OokFix", + "OokAfg", "Res17", "Res18", "Res19", "AfcFei", "AfcMsb", "AfcLsb", + "FeiMsb", "FeiLsb", "PreambleDet", "RxTimeout1", "RxTimeout2", "RxTimeout3", + "RxDelay", "Osc", "PreambleMsb", "PreambleLsb", "SyncConfig", "SyncVal1", + "SyncVal2", "SyncVal3", "SyncVal4", "SyncVal5", "SyncVal6", "SyncVal7", + "SyncVal8", "PacketCfg1", "PacketCfg2", "PayloadLen", "NodeAdrs", "BcastAdrs", + "FifoThresh", "SeqConfig1", "SeqConfig2", "TimerRes", "Timer1Coef", "Timer2Coef", + "ImageCal", "Temp", "LowBat", "IrqFlags1", "IrqFlags2", "DioMap1", "DioMap2", + "Version", "Reserve43", "PllHop" +}; + + // heltec wireless stick: // reset 14 // dio1 35 @@ -230,14 +290,23 @@ SX1276::SX1276(spi_host_device_t host, spi_device_interface_config_t &cfg, int8_ cfg.clock_speed_hz = SPI_MASTER_FREQ_10M; cfg.queue_size = 1; cfg.post_cb = postCallback; -// cfg.flags = ESP_INTR_FLAG_IRAM; + cfg.flags = ESP_INTR_FLAG_IRAM; cfg.flags = SPI_DEVICE_HALFDUPLEX; - /* if (-1 != intr) { - if (esp_err_t e = xio_set_intr(intr,intrHandler,this)) + xio_cfg_t cfg = XIOCFG_INIT; + cfg.cfg_io = xio_cfg_io_in; + cfg.cfg_pull = xio_cfg_pull_none; + cfg.cfg_intr = xio_cfg_intr_edges; + if (0 > xio_config(intr,cfg)) { + log_warn(TAG,"config interrupt error"); + } else if (esp_err_t e = xio_set_intr(intr,intr_handler,this)) log_warn(TAG,"error attaching interrupt: %s",esp_err_to_name(e)); + else + log_info(TAG,"interrupt on %u",intr); } - */ + Action *irqac = action_add("sx1276!irqh",intr_action,this,0); + m_irqev = event_register(concat(m_name,"`irq")); + event_callback(m_irqev,irqac); if (esp_err_t e = spi_bus_add_device(host,&cfg,&m_hdl)) log_warn(TAG,"device add failed: %s",esp_err_to_name(e)); else @@ -391,15 +460,18 @@ int SX1276::init() log_info(TAG,"version: %u",ver); log_info(TAG,"freq: %dMHz",getFreq()); - writeReg(REG_PA_CONFIG,0); + writeReg(REG_PA_CONFIG,0x4f); float pmax,pout; - getMaxPower(pmax); - getPower(pout); +// getMaxPower(pmax); + getPower(pout,pmax); log_info(TAG,"power: max: %g, output %g",pmax,pout); - log_info(TAG,"Imax: %dmA, %sabled" - , getImax() - , getOCP() ? "en" : "dis"); + unsigned imax; + bool ocp; + if (0 == getImax(imax,ocp)) + log_info(TAG,"Imax: %dmA, %sabled", imax, ocp ? "en" : "dis"); + else + log_warn(TAG,"cannot get Imax/OCP"); setFreq(433); log_info(TAG,"freq: %dMHz",getFreq()); @@ -432,12 +504,20 @@ int SX1276::init() writeReg(LORA_IRQ_FLAGS,0xff); setLora(false); m_rev = event_register(concat(m_name,"`recv")); - action_add(concat(m_name,"!send"),send_action,0,"set "); + action_add(concat(m_name,"!send"),send_action,0,"send data"); return 0; } -void SX1276::intr_action(void *arg) +void IRAM_ATTR SX1276::intr_handler(void *arg) +{ + SX1276 *dev = (SX1276 *) arg; + con_printf("intr\n"); + event_isr_trigger(dev->m_irqev); +} + + +void IRAM_ATTR SX1276::intr_action(void *arg) { SX1276 *dev = (SX1276 *) arg; dev->processIntr(); @@ -469,7 +549,10 @@ void SX1276::processIntr() readRegs(FSKOOK_IRQ_FLAGS1,sizeof(r),r); log_dbug(TAG,"irq flags 0x%02x 0x%02x",r[0],r[1]); if (r[1] & BIT_PAYLOAD_READY) { - // TODO + log_dbug(TAG,"payload ready"); + uint8_t data[64], st; + readRegs(0,sizeof(data),data); + // TODO: handle data } } } @@ -492,29 +575,65 @@ bool SX1276::isLora() int SX1276::setLora(bool lora) { - uint8_t r; - if (readReg(REG_OP_MODE,&r)) + uint8_t m; + if (readReg(REG_OP_MODE,&m)) return -1; - if (((r&BIT_LORA) != 0) == lora) { - return 0; + if (((m&BIT_LORA) != 0) == lora) { + log_dbug(TAG,"LORA mode already %sactive",lora?"":"in"); +// return 0; } - uint8_t m = r & MASK_MODE; - r &= ~BIT_LORA; - r &= ~MASK_MODE; + log_dbug(TAG,"set modem %s",lora?"LORA":"OOK/FSK"); if (lora) - r |= BIT_LORA; + m |= BIT_LORA; else - r &= ~BIT_LORA; - if (writeReg(REG_OP_MODE,r)) + m &= ~BIT_LORA; + if (writeReg(REG_OP_MODE,m)) return -1; - writeReg(REG_OP_MODE,r|m); if (lora) { getBitRate(); - } else { - writeReg(FSKOOK_RX_CONFIG,BIT_AFC_AUTO_ON|BIT_AGC_AUTO_ON|MODE_INTR_RX_PREAMBLE); - writeReg(FSKOOK_PACKET_CONFIG,BIT_CRC_ON); // variable-length, no address filter - writeReg(FSKOOK_PAYLOAD_LENGTH,0xff); // maximum payload lenght getBandwidth(); + } else { + uint8_t r; + uint8_t v = BIT_RESTART_RX_WPLL|BIT_AFC_AUTO_ON|BIT_AGC_AUTO_ON|MODE_INTR_RX_PREAMBLE; + writeReg(FSKOOK_RX_CONFIG,v); + v &= ~BIT_RESTART_RX_WPLL; // remove trigger bit + r = 0; + readReg(FSKOOK_RX_CONFIG,&r); + assert(r == v); + + v = BIT_VARIABLE_LENGTH|BIT_CRC_ON|BIT_CRC_AUTOCLEAROFF; // variable-length, no address filter + v |= 3<<5; // DC Free: whitening encoding enable + writeReg(FSKOOK_PACKET_CONFIG,v); + readReg(FSKOOK_PACKET_CONFIG,&r); + assert(r == v); + + // maximum payload length + // absolute max is 255, but some devices are limited to 0x7f + // why_ + v = 0x60; + writeReg(FSKOOK_PAYLOAD_LENGTH,v); + readReg(FSKOOK_PAYLOAD_LENGTH,&r); + assert(r == v); + + // preemble detect on 1<<7 + // detector size 2 (3bytes) 2<<5 + // detector tolerance 0xa (default) + // TODO preamble detect is not a trigger but not accepted, should be 0xaa + // v = 0xaa; + v = 0x2a; + writeReg(FSKOOK_PREEMBLE_DETECT,v); + readReg(FSKOOK_PREEMBLE_DETECT,&r); + assert(r == v); + + v = 0x15; // default value + writeReg(FSKOOK_RX_BW,v); + readReg(FSKOOK_RX_BW,&r); + assert(r == v); + + v = 0x08; // start directly + writeReg(FSKOOK_FIFO_THRESH,v); + readReg(FSKOOK_FIFO_THRESH,&r); + assert(r == v); } return 0; } @@ -542,9 +661,10 @@ int SX1276::setOOK(bool ook) } +/* int SX1276::getMaxPower(float &pmax) { - PaConfig pac; + RegPaConfig pac; if (readRegs(REG_PA_CONFIG,sizeof(pac),(uint8_t*)&pac)) return -1; pmax = (float) pac.max_power * 0.6 + 10.8; @@ -555,6 +675,7 @@ int SX1276::getMaxPower(float &pmax) ); return 0; } +*/ int SX1276::setMaxPower(float pmax) @@ -563,7 +684,7 @@ int SX1276::setMaxPower(float pmax) log_warn(TAG,"valid maximum power range 10.8..20dBm"); return -1; } - PaConfig pac; + RegPaConfig pac; if (readRegs(REG_PA_CONFIG,sizeof(pac),(uint8_t*)&pac)) return -1; float pout; @@ -589,12 +710,12 @@ int SX1276::setMaxPower(float pmax) } -int SX1276::getPower(float &pout) +int SX1276::getPower(float &pout, float &pmax) { - PaConfig pac; + RegPaConfig pac; if (readRegs(REG_PA_CONFIG,sizeof(pac),(uint8_t*)&pac)) return -1; - float pmax = (float) pac.max_power * 0.6 + 10.8; + pmax = (float) pac.max_power * 0.6 + 10.8; pout = pac.pa_select ? (2.0+pac.output_power) : pmax-(15-pac.output_power); // negative value plausible? // pout = pac.pa_select ? (2.0+pac.output_power) : (pmax-pac.output_power); @@ -609,9 +730,11 @@ int SX1276::getPower(float &pout) int SX1276::setPower(float pout) { - if (pout > 20) + if (pout > 20) { + log_warn(TAG,"invalid power %g",pout); return -1; - PaConfig pac; + } + RegPaConfig pac; if (readRegs(REG_PA_CONFIG,sizeof(pac),(uint8_t*)&pac)) return -1; if (pac.pa_select) { @@ -619,6 +742,7 @@ int SX1276::setPower(float pout) return -1; pac.output_power = pout-2; } else if (pout > (pac.max_power*0.6+10.8)) { + log_warn(TAG,"power %g: out of range",pout); return -1; } else { float pmax = (float) pac.max_power * 0.6 + 10.8; @@ -635,7 +759,7 @@ int SX1276::getFreq() if (0 == readRegs(REG_FRF_MSB,sizeof(freq),freq)) { uint32_t f = (freq[0]<<16)|(freq[1]<<8)|freq[0]; r = (f<<5)/(1<<19); - log_dbug(TAG,"freq: %uMHz",r); +// log_dbug(TAG,"freq: %uMHz",r); } return r; } @@ -681,23 +805,23 @@ int SX1276::setImax(unsigned imax) } -int SX1276::getImax() +int SX1276::getImax(unsigned &imax, bool &ocp) { - uint8_t ocp; - if (readReg(REG_OCP,&ocp)) + uint8_t v; + if (readReg(REG_OCP,&v)) return -1; - unsigned imax; - if ((ocp & 0x1f) <= 15) - imax = 45+5*(ocp&0x1f); - else if ((ocp & 0x1f) <= 27) - imax = -30 + 10 * (ocp&0x1f); + if ((v & 0x1f) <= 15) + imax = 45+5*(v&0x1f); + else if ((v & 0x1f) <= 27) + imax = -30 + 10 * (v&0x1f); else imax = 240; + ocp = v & (1<<5); log_dbug(TAG,"OCP %sabled, Imax %u mA" - , ocp & (1<<5) ? "en" : "dis" + , ocp ? "en" : "dis" , imax ); - return imax; + return 0; } @@ -793,7 +917,7 @@ int SX1276::getBitRate() return -1; float br = (float)((v[0] << 8) | v[1]) + ((float)f/16); float r = rintf(32.0E6 / br); - log_dbug(TAG,"bit-rate %dB/s",(int)r); +// log_dbug(TAG,"bit-rate %dB/s",(int)r); return (int)r; } @@ -947,6 +1071,7 @@ IRAM_ATTR void SX1276::postCallback(spi_transaction_t *t) } +/* void SX1276::readRegsSync(uint8_t reg, uint8_t num) { uint8_t data[num]; @@ -963,12 +1088,14 @@ void SX1276::readRegsSync(uint8_t reg, uint8_t num) } if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) abort_on_mutex(m_sem,"sx1276"); - log_hex(TAG,data,sizeof(data),"read regs %u@%u:",num,reg); + log_hex(TAG,data,sizeof(data),"readRegs %u@%u:",num,reg); } +*/ int SX1276::readRegs(uint8_t reg, uint8_t num, uint8_t *data) { + bzero(data,num); spi_transaction_t t; bzero(&t,sizeof(t)); t.user = this; @@ -982,7 +1109,7 @@ int SX1276::readRegs(uint8_t reg, uint8_t num, uint8_t *data) } if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) abort_on_mutex(m_sem,"sx1276"); - log_hex(TAG,data,num,"read regs %u@%u:",num,reg); + log_hex(TAG,data,num,"readRegs %u of %s(0x%x):",num,(reg < (sizeof(RegNames)/sizeof(RegNames[0])) ? RegNames[reg] : ""),reg,*data); return 0; } @@ -1002,7 +1129,7 @@ int SX1276::readReg(uint8_t reg, uint8_t *data) } if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) abort_on_mutex(m_sem,"sx1276"); - log_dbug(TAG,"read reg 0x%x: 0x%x",reg,*data); + log_dbug(TAG,"readReg %s(0x%02x): 0x%02x",(reg < (sizeof(RegNames)/sizeof(RegNames[0])) ? RegNames[reg] : ""),reg,*data); return 0; } @@ -1013,37 +1140,36 @@ int SX1276::writeReg(uint8_t r, uint8_t v) bzero(&t,sizeof(t)); t.cmd = 1; t.user = this; - t.addr = r; + t.addr = r | 0x80; t.length = 1<<3; - t.rxlength = 0; - t.rx_buffer = 0; - t.tx_buffer = &v; -// if (esp_err_t e = spi_device_transmit(m_hdl,&t)) -// log_warn(TAG,"error writing reg 0x%x: %s",r,esp_err_to_name(e)); + t.tx_data[0] = v; + t.flags = SPI_TRANS_USE_TXDATA; if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) { log_warn(TAG,"error queuing read: %s",esp_err_to_name(e)); return -1; } if (pdTRUE != xSemaphoreTake(m_sem,MUTEX_ABORT_TIMEOUT)) abort_on_mutex(m_sem,"sx1276"); - log_dbug(TAG,"write 0x%02x, 0x%02x",r,v); + log_dbug(TAG,"writeReg %s(0x%02x), 0x%02x",(r < (sizeof(RegNames)/sizeof(RegNames[0])) ? RegNames[r] : ""),r,v); return 0; } int SX1276::writeRegs(uint8_t r, uint8_t n, uint8_t *v) { + log_hex(TAG,v,n,"write regs 0x%x",r); spi_transaction_t t; bzero(&t,sizeof(t)); t.cmd = 1; t.user = this; - t.addr = r; + t.addr = r | 0x80; t.length = n<<3; - t.rxlength = 0; - t.rx_buffer = 0; - t.tx_buffer = v; -// if (esp_err_t e = spi_device_transmit(m_hdl,&t)) -// log_warn(TAG,"error writing reg 0x%x: %s",r,esp_err_to_name(e)); + if (n > sizeof(t.tx_data)) { + t.tx_buffer = v; + } else { + memcpy(t.tx_data,v,n); + t.flags = SPI_TRANS_USE_TXDATA; + } if (esp_err_t e = spi_device_queue_trans(m_hdl,&t,1)) { log_warn(TAG,"error queuing read: %s",esp_err_to_name(e)); return -1; @@ -1063,8 +1189,9 @@ int SX1276::send(const char *buf, int s) } if (readReg(REG_OP_MODE,&opm)) return -1; - if (((opm & MASK_MODE) != mode_stdb) && ((opm & MASK_MODE) != mode_sleep)) { - log_warn(TAG,"cannot send from mode %s",ModeStrs[opm&MASK_MODE]); + uint8_t mode = opm & MASK_MODE; + if ((mode != mode_stdb) && (mode != mode_sleep) && (mode != mode_tx)) { + log_warn(TAG,"cannot send from mode %s",ModeStrs[mode]); return -1; } opm &= ~MASK_MODE; @@ -1105,14 +1232,12 @@ int SX1276::send(const char *buf, int s) opm |= mode_tx; writeReg(REG_OP_MODE,opm); log_dbug(TAG,"send started"); - uint8_t irqf; + uint8_t flags[2]; do { ets_delay_us(10000); - readReg(REG_OP_MODE,&opm); - readReg(LORA_IRQ_FLAGS,&irqf); - } while ((irqf & BIT_TX_DONE) == 0); + readRegs(FSKOOK_IRQ_FLAGS1,sizeof(flags),flags); + } while ((flags[1]& BIT_PACKET_SENT) == 0); log_dbug(TAG,"send done"); - writeReg(LORA_IRQ_FLAGS,BIT_TX_DONE); opm &= ~MASK_MODE; opm |= mode_stdb; writeReg(REG_OP_MODE,opm); @@ -1126,6 +1251,7 @@ const char *SX1276::exeCmd(Terminal &t, int argc, const char **args) if ((argc == 0) || ((argc == 1) && (0 == strcmp(args[0],"-h")))) { t.println( "info : print current settings\n" + "mode : set mode (rx/rx1/recv/tx/standby)\n" "addr : 8bit node address (only FSK/OOK)\n" "bca : 8bit broadcast address (only FSK/OOK)\n" "modem : switch modem to FSK, OOK, LORA\n" @@ -1163,6 +1289,20 @@ const char *SX1276::exeCmd(Terminal &t, int argc, const char **args) t.printf("%02x %02x\n",flags[0],flags[1]); if (flags[0] & 0x80) t.println("mode ready"); + if (flags[0] & 0x40) + t.println("rx ready"); + if (flags[0] & 0x20) + t.println("tx ready"); + if (flags[0] & 0x10) + t.println("pll lock"); + if (flags[0] & 0x8) + t.println("rssi"); + if (flags[0] & 0x4) + t.println("timeout"); + if (flags[0] & 0x2) + t.println("preamble detect"); + if (flags[0] & 0x1) + t.println("address match"); if (flags[1] & 0x80) t.println("fifo full"); if (flags[1] & 0x40) @@ -1201,9 +1341,17 @@ const char *SX1276::exeCmd(Terminal &t, int argc, const char **args) setMode(mode_stdb); setMode(mode_cad); } else if (0 == strcmp(args[0],"regs")) { - uint8_t r[32]; - readRegs(1,sizeof(r),r); - log_hex(TAG,r,sizeof(r),"regs:"); + uint8_t r0[0x28]; + r0[0] = 0; // address 0 is the FIFO + readRegs(1,sizeof(r0)-1,r0+1); + t.println("regs:"); + for (unsigned i = 1; i < sizeof(r0); ++i) + printf("0x%02x %-12s 0x%02x\n",i,RegNames[i],r0[i]); + uint8_t r1[0x1b]; + readRegs(sizeof(r0),sizeof(r1),r1); + for (unsigned i = 0; i < sizeof(r1); ++i) + printf("0x%02x %-12s 0x%02x\n",i+sizeof(r0),RegNames[i+sizeof(r0)],r1[i]); +// print_hex(t,r,sizeof(r)); } else { return "Invalid argument #1."; } diff --git a/drv/spi/sx1276.h b/drv/spi/sx1276.h index ccd3569..e08fc54 100644 --- a/drv/spi/sx1276.h +++ b/drv/spi/sx1276.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, Thomas Maier-Komor + * Copyright (C) 2023, Thomas Maier-Komor * Atrium Firmware Package for ESP * * This program is free software: you can redistribute it and/or modify @@ -21,6 +21,7 @@ #include "spidrv.h" + struct Packet { uint16_t len; @@ -70,13 +71,13 @@ class SX1276 : public SpiDevice int getOCP(); int setOCP(bool en); int setImax(unsigned imax); - int getImax(); + int getImax(unsigned &, bool &); int getFreq(); int setFreq(unsigned f); int setPower(float pmax); - int getPower(float &pmax); + int getPower(float &pout, float &pmax); int setMaxPower(float pmax); - int getMaxPower(float &pmax); +// int getMaxPower(float &pmax); // LORA only int getBandwidth(); @@ -100,20 +101,21 @@ class SX1276 : public SpiDevice static void dio3Handler(void *); static void dio4Handler(void *); static void dio5Handler(void *); - void readRegsSync(uint8_t reg, uint8_t num); +// void readRegsSync(uint8_t reg, uint8_t num); int readRegs(uint8_t reg, uint8_t num, uint8_t *); int readReg(uint8_t reg, uint8_t *); int writeReg(uint8_t r, uint8_t v); int writeRegs(uint8_t r, uint8_t num, uint8_t *v); static void send_action(void *); static void intr_action(void *); // used internally - static void intrHandler(void *); + static void intr_handler(void *); void processIntr(); class EnvObject *m_env = 0; SemaphoreHandle_t m_sem; uint8_t m_opmode = 0; int8_t m_reset = -1; + event_t m_irqev = 0; event_t m_rev = 0; // receive event event_t m_iev[6]; uint8_t m_rcvbuf[64]; diff --git a/hwcfg.wfc b/hwcfg.wfc index 8671626..2ab7eee 100644 --- a/hwcfg.wfc +++ b/hwcfg.wfc @@ -240,6 +240,7 @@ enum i2cdrv_t { i2cdrv_si7021 = 12; i2cdrv_tca9555 = 13; i2cdrv_ssd1306 = 14; + i2cdrv_sh1106 = 15; } @@ -399,6 +400,7 @@ enum disp_t // monochrom displays dt_ssd1306 = 32; // I2C dt_ssd1309 = 33; // 4-wire spi + dt_sh1106 = 34; // TFT displays dt_ili9341 = 64; diff --git a/main/Kconfig b/main/Kconfig index 201bc01..e5e4386 100644 --- a/main/Kconfig +++ b/main/Kconfig @@ -232,7 +232,7 @@ config USB_DIAGLOG config USB_CONSOLE depends on ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG || TINYUSB_CDC_ENABLED - bool "diag output to USB serial" + bool "console on USB serial" default true help Console on USB serial connections. Uses serial JTAG on @@ -326,6 +326,12 @@ config SSD1306 help "OLED displays based on SSD1306" +config SH1106 + depends on DISPLAY && I2C_XDEV + bool "SH1106 driver" + help + "OLED displays based on SH1106" + config DHT bool "DHT-xx sensor" default false @@ -395,7 +401,7 @@ config MCP2301X I2C driver for MCP2301x devices (16-port GPIO expander) config OPT3001 - depends on I2C && DEVEL + depends on I2C bool "opt3001" default true help @@ -422,6 +428,13 @@ config BMX280 help I2C driver for BME280 and BMP280 air sensor (temperature, humidity, pressure) +config BMP388 + depends on I2C && DEVEL + bool "BMP388" + default false + help + I2C driver for BMP388 air sensor (temperature, pressure) + config BME680 depends on I2C bool "BME680" @@ -481,6 +494,7 @@ config SX1276 config SSD1309 bool "SSD1309" + depends on DEVEL default false depends on SPI help diff --git a/main/adc.cpp b/main/adc.cpp index 3c1e2d3..ac54799 100644 --- a/main/adc.cpp +++ b/main/adc.cpp @@ -35,7 +35,7 @@ #ifdef CONFIG_CORETEMP #include #include -//#include +#include #include #endif #else @@ -317,6 +317,7 @@ static int8_t s_temperature_regval_2_celsius(temperature_sensor_handle_t tsens, } // END of import from IDF private header for BUG workaround +#if 0 // IDF BUG workaround by NoNullptr from github static inline uint32_t temperature_sensor_ll_get_raw_value_bugfix(void) { @@ -346,11 +347,12 @@ s: SENS.sar_peri_clk_gate_conf.tsens_clk_en = true; SENS.sar_tctrl.tsens_dump_out = 0; return SENS.sar_tctrl.tsens_out; } +#endif static unsigned temp_cyclic(void *arg) { PROFILE_FUNCTION(); -#if 1 // IDF still buggy? +#if 0 // IDF still buggy? uint32_t raw = temperature_sensor_ll_get_raw_value_bugfix(); EnvNumber *t = (EnvNumber *) arg; t->set(s_temperature_regval_2_celsius(TSensHdl,raw)); diff --git a/main/displays.cpp b/main/displays.cpp index cc6d517..86cae51 100644 --- a/main/displays.cpp +++ b/main/displays.cpp @@ -28,6 +28,7 @@ #include "MAX7219.h" #include "pcf8574.h" #include "hd44780u.h" +#include "sh1106.h" #include "ssd1306.h" #include "ssd1309.h" @@ -70,6 +71,13 @@ void display_setup() if (!ok) log_warn(TAG,"no pcf8574/hd44780u found"); #endif +#ifdef CONFIG_SH1106 + } else if (t == dt_sh1106) { + if (SH1106 *dev = SH1106::getInstance()) + dev->init(maxx,maxy,c.options()); + else + log_warn(TAG,"no ssd1306 found"); +#endif #ifdef CONFIG_SSD1306 } else if (t == dt_ssd1306) { if (SSD1306 *dev = SSD1306::getInstance()) diff --git a/main/fs.cpp b/main/fs.cpp index 9d7370d..64fec32 100644 --- a/main/fs.cpp +++ b/main/fs.cpp @@ -64,6 +64,7 @@ void rootfs_add(const char *entr) log_error(TAG,"rootfs out of entries"); } +#if defined ESP32 || defined CONFIG_USING_ESP_VFS static int rootfs_vfs_closedir(DIR *d) { if (d) { @@ -117,6 +118,7 @@ static struct dirent *rootfs_vfs_readdir(DIR *d) return r; return 0; } +#endif #if 0 // not needed, as stat is directed to child filesystem @@ -137,6 +139,7 @@ static int rootfs_vfs_stat(const char *p, struct stat *st) void rootfs_init() { +#if defined ESP32 || defined CONFIG_USING_ESP_VFS esp_vfs_t vfs; bzero(&vfs,sizeof(vfs)); vfs.flags = ESP_VFS_FLAG_DEFAULT; @@ -148,6 +151,7 @@ void rootfs_init() log_warn(TAG,"VFS register rootfs: %s",esp_err_to_name(e)); else log_info(TAG,"rootfs mounted"); +#endif } #endif diff --git a/main/ftpd.cpp b/main/ftpd.cpp index 272e95e..aef2422 100644 --- a/main/ftpd.cpp +++ b/main/ftpd.cpp @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2022, Thomas Maier-Komor + * Copyright (C) 2018-2023, Thomas Maier-Komor * Atrium Firmware Package for ESP * * This program is free software: you can redistribute it and/or modify @@ -54,11 +54,13 @@ extern "C" { #define BUFSIZE 1024 #define FTPD_PORT 21 +using namespace std; + typedef struct ftpctx { - const char *root; - char *wd; + const char *root; // always no slash-termination (wd has a leading slash) + char *wd; // always slash-terminated char *rnfr; LwTcp *con, *dcon; uint8_t login; // 2 = ftp, 4 = root, 1 = unlocked @@ -92,6 +94,27 @@ static char *arg2fn(ftpctx_t *ctx, const char *arg) } +static int valid_path(const char *p, const char *r = 0) +{ + struct stat st; + size_t l = strlen(p); + if (l == 0) { + log_warn(TAG,"empty path"); + } else if (p[l-1] != '/') { + log_warn(TAG,"path is not / terminated"); + } else if (stat(p,&st)) { + log_warn(TAG,"failed to stat %s: %s",p,strerror(errno)); + } else if (0 == S_ISDIR(st.st_mode) ) { + log_warn(TAG,"%s is not a directory",p); + } else if ((r != 0) && (strncmp(p,r,strlen(r)))) { + log_warn(TAG,"%s not in ftpd-root",p); + } else { + return 1; + } + return 0; +} + + static void answer(ftpctx_t *ctx, const char *fmt, ...) { char buf[96], *b = buf; @@ -129,12 +152,17 @@ static char *up_slash(char *str, char *at) static void fold_path(char *path) { log_dbug(TAG,"folding %s",path); - while (0 == memcmp(path,"/../",4)) - memmove(path,path+3,strlen(path+3)+1); + char *ds = strstr(path,"//"); + while (ds) { + size_t l = strlen(ds); + memmove(ds,ds+1,l); + ds = strstr(path,"//"); + } char *dd = strstr(path,"/../"); while (dd) { - char *sl = up_slash(path,dd-1); - if (sl) { + if (dd == path) { + memmove(path,path+3,strlen(path+3)+1); + } else if (char *sl = up_slash(path,dd-1)) { memmove(sl+1,dd+4,strlen(dd+4)+1); } else { memmove(dd,dd+3,strlen(dd+3)+1); @@ -147,7 +175,7 @@ static void fold_path(char *path) static void pwd(ftpctx_t *ctx, const char *arg) { - answer(ctx,"200: %s",ctx->wd); + answer(ctx,"257 \"%s\"",ctx->wd); } @@ -214,14 +242,14 @@ static void mkd(ftpctx_t *ctx, const char *arg) answer(ctx,"501 missing argument"); return; } +#ifdef ESP8266 + answer(ctx,"452 operation not supported"); +#else char buf[256]; strcpy(buf,ctx->root); strcat(buf,ctx->wd); strcat(buf,arg); fold_path(buf); -#ifdef ESP8266 - answer(ctx,"452 operation not supported"); -#else log_dbug(TAG,"mkdir %s",buf); if (-1 == mkdir(buf,0777)) { log_warn(TAG,"failed to create %s: %s",arg,strerror(errno)); @@ -495,19 +523,30 @@ static void cwd(ftpctx_t *ctx, const char *arg) answer(ctx,"501 missing argument",4,0); return; } - if (arg[0] == '/') { - ctx->wd = (char*)realloc(ctx->wd,strlen(arg)+1); - strcpy(ctx->wd,arg); + size_t al = strlen(arg); + size_t wl = strlen(ctx->wd); + size_t rl = strlen(ctx->root); + char path[al+wl+rl+2]; + memcpy(path,ctx->root,rl); + char *at = path+rl; + if (arg[0] != '/') { + memcpy(at,ctx->wd,wl); + at += wl; + } + memcpy(at,arg,al+1); + if (at[al-1] != '/') { + at[al] = '/'; + at[al+1] = 0; + } + fold_path(path); + if (valid_path(path,ctx->root)) { + free(ctx->wd); + ctx->wd = strdup(path+rl); + answer(ctx,"200 %s",ctx->wd); + log_dbug(TAG,"cwd %s",ctx->wd); } else { - ctx->wd = (char*)realloc(ctx->wd,strlen(ctx->wd)+strlen(arg)+2); - strcat(ctx->wd,arg); - size_t al = strlen(arg); - if (arg[al-1] != '/') - strcat(ctx->wd,"/"); + answer(ctx,"501 invalid argument",4,0); } - fold_path(ctx->wd); - answer(ctx,"200 %s",ctx->wd); - log_dbug(TAG,"cwd %s",ctx->wd); } @@ -517,14 +556,14 @@ static void cdup(ftpctx_t *ctx, const char *arg) char *sl = strrchr(ctx->wd,'/'); if (sl == ctx->wd) { answer(ctx,"200 %s",ctx->wd); - log_dbug(TAG,"cwd %s",ctx->wd); + log_dbug(TAG,"cdup %s",ctx->wd); return; } assert(sl[1] == 0); sl = up_slash(ctx->wd,sl-1); sl[1] = 0; answer(ctx,"200 %s",ctx->wd); - log_dbug(TAG,"cwd %s",ctx->wd); + log_dbug(TAG,"cdup %s",ctx->wd); } @@ -669,7 +708,7 @@ static void passive(ftpctx_t *ctx, const char *arg) { // TODO // 202: not implemented - answer(ctx,"202 not implemented"); + answer(ctx,"202 passive mode not implemented"); } @@ -830,9 +869,15 @@ void ftpd_setup() if (c->has_port()) p = c->port(); const char *r = "/flash"; - if (c->has_root()) - r = c->root().c_str(); - + if (c->has_root()) { + // ensure root is slash-terminated + auto *root = c->mutable_root(); + if (root->back() == '/') + root->pop_back(); + r = root->c_str(); + } else { + c->set_root(r); + } if (DIR *d = opendir(r)) { closedir(d); log_info(TAG,"port %hu, root '%s'",p,r); diff --git a/main/gpios.cpp b/main/gpios.cpp index 367ee56..533617b 100644 --- a/main/gpios.cpp +++ b/main/gpios.cpp @@ -37,6 +37,7 @@ #include #else #include +#include #endif #ifdef CONFIG_LUA @@ -70,7 +71,6 @@ class Gpio Gpio(const char *name, xio_t gpio, unsigned config) : m_env(name,false) , m_gpio(gpio) - , m_intrev(0) { init(config); } @@ -90,7 +90,10 @@ class Gpio { return m_env.name(); } void set_lvl(int lvl) - { xio_set_lvl(m_gpio,(xio_lvl_t)lvl); } + { + if (-1 != xio_set_lvl(m_gpio,(xio_lvl_t)lvl)) + m_env.set(lvl); + } void attach(EnvObject *r) { r->add(&m_env); } @@ -108,12 +111,17 @@ class Gpio static void action_set0(void *); static void action_set1(void *); static void action_toggle(void *); +#ifdef ESP32 + static void action_hold(void *); + static void action_unhold(void *); +#endif EnvBool m_env; xio_t m_gpio; - Gpio *m_next; // set in init() - bool m_intlvl; // level at time of interrupt - event_t m_intrev; + Gpio *m_next = 0; // set in init() + bool m_intlvl = false; // level at time of interrupt + bool hold = false; + event_t m_intrev = 0, m_fallev = 0, m_riseev = 0; static Gpio *First; }; @@ -186,6 +194,7 @@ void Gpio::action_sample(void *arg) { Gpio *gpio = (Gpio *)arg; int lvl = gpio->get_lvl(); + event_trigger(lvl != 0 ? gpio->m_riseev : gpio->m_fallev); log_dbug(TAG,"%s = %d",gpio->name(),lvl); } @@ -215,6 +224,24 @@ void Gpio::action_toggle(void *arg) } +#ifdef ESP32 +void Gpio::action_hold(void *arg) +{ + Gpio *gpio = (Gpio *)arg; + gpio_pad_hold(gpio->m_gpio); + log_dbug(TAG,"hold %s",gpio->name()); +} + + +void Gpio::action_unhold(void *arg) +{ + Gpio *gpio = (Gpio *)arg; + gpio_pad_unhold(gpio->m_gpio); + log_dbug(TAG,"unhold %s",gpio->name()); +} +#endif + + void Gpio::init(unsigned config) { log_info(TAG,"gpio%d named %s, config 0x%x",m_gpio,m_env.name(),config); @@ -246,11 +273,21 @@ void Gpio::init(unsigned config) action_add(concat(name,"!set_1"),Gpio::action_set1,(void*)this,"set gpio high"); action_add(concat(name,"!set_0"),Gpio::action_set0,(void*)this,"set gpio low"); action_add(concat(name,"!toggle"),Gpio::action_toggle,(void*)this,"toggle gpio"); +#ifdef ESP32 + if (GPIO_IS_VALID_OUTPUT_GPIO(m_gpio)) { + action_add(concat(name,"!hold"),Gpio::action_hold,(void*)this,"hold gpio"); + action_add(concat(name,"!unhold"),Gpio::action_unhold,(void*)this,"unhold gpio"); + } else { + log_dbug(TAG,"no hold feature for gpio%u",m_gpio); + } +#endif } if ((config >> 2) & 0x3) { // configure interrupts log_dbug(TAG,"gpio interrupts"); - m_intrev = event_register(concat(name,"`intr")); + m_intrev = event_register(name,"`intr"); + m_fallev = event_register(name,"`fall"); + m_riseev = event_register(name,"`rise"); if (a == 0) log_warn(TAG,"gpio%d: interrupts only work on inputs",m_gpio); else if (xio_set_intr(m_gpio,isr_handler,this)) diff --git a/main/i2c.cpp b/main/i2c.cpp index caff245..8f4bcf1 100644 --- a/main/i2c.cpp +++ b/main/i2c.cpp @@ -29,6 +29,7 @@ #include "pcf8574.h" #include "si7021.h" #include "ssd1306.h" +#include "sh1106.h" #include "tca9555.h" #include "log.h" #include "terminal.h" @@ -110,6 +111,14 @@ static inline void i2c_scan_device(uint8_t bus, uint8_t addr, i2cdrv_t drv, int8 else ssd1306_scan(bus); break; +#endif +#ifdef CONFIG_SH1106 + case i2cdrv_sh1106: + if (addr) + SH1106::create(bus,addr); + else + sh1106_scan(bus); + break; #endif default: log_warn(TAG,"unsupported I2C config %d at %u,0x%x",drv,bus,addr); diff --git a/main/leds.cpp b/main/leds.cpp index 630d082..2d4b76a 100644 --- a/main/leds.cpp +++ b/main/leds.cpp @@ -35,6 +35,9 @@ #include +#include +#include + #ifdef CONFIG_LUA #include "luaext.h" extern "C" { @@ -50,12 +53,6 @@ extern "C" { #define stacksize 1536 #endif -#if defined CONFIG_IDF_TARGET_ESP32 && IDF_VERSION >= 40 -#include -#else -#include -#endif - #define TAG MODULE_LED @@ -388,6 +385,26 @@ static void led_toggle(void *arg) } +#ifdef ESP32 +static void led_hold(void *arg) +{ + LedMode *m = (LedMode *)arg; + if (m) { + gpio_pad_hold(m->gpio); + } +} + + +static void led_unhold(void *arg) +{ + LedMode *m = (LedMode *)arg; + if (m) { + gpio_pad_unhold(m->gpio); + } +} +#endif + + extern "C" void statusled_set(ledmode_t m) { @@ -564,6 +581,14 @@ int leds_setup() action_add(concat(name,"!on"), led_set_on, (void*)ctx, "led on"); action_add(concat(name,"!off"), led_set_off, (void*)ctx, "led off"); action_add(concat(name,"!toggle"), led_toggle, (void*)ctx, "toggle led"); +#ifdef ESP32 + if (GPIO_IS_VALID_OUTPUT_GPIO(gpio)) { + action_add(concat(name,"!hold"), led_hold, (void*)ctx, "hold LED state over reset"); + action_add(concat(name,"!unhold"),led_unhold, (void*)ctx, "unhold LED"); + } else { + log_dbug(TAG,"no hold feature for gpio%u",gpio); + } +#endif } if (ctx) cyclic_add_task(name,ledmode_subtask,(void*)ctx); diff --git a/main/ping.cpp b/main/ping.cpp index 93f578d..454f264 100644 --- a/main/ping.cpp +++ b/main/ping.cpp @@ -18,7 +18,7 @@ #include -#ifndef CONFIG_ESPTOOLPY_FLASHSIZE_1MB +#if !defined ESP8266 || (defined CONFIG_LWIP_RAW && !defined CONFIG_ESPTOOLPY_FLASHSIZE_1MB) #include "globals.h" #include "log.h" diff --git a/main/screen.cpp b/main/screen.cpp index 1209e7e..4bd9189 100644 --- a/main/screen.cpp +++ b/main/screen.cpp @@ -216,12 +216,12 @@ void Screen::display_version() { if (MatrixDisplay *dm = disp->toMatrixDisplay()) { assert(dm->maxX()); - dm->drawRect(1,1,dm->maxX()-2,dm->maxY()-2); + dm->drawRect(4,1,dm->maxX()-5,dm->maxY()-3); dm->setFont(font_sanslight16); - dm->setPos(10,2); + dm->setPos(10,3); dm->write("Atrium"); dm->setFont(font_sanslight12); - dm->setPos(10,24); + dm->setPos(10,26); const char *sp = strchr(Version,' '); dm->write(Version,sp-Version); if (dm->maxY() >= 48) { @@ -300,15 +300,6 @@ void Screen::display_sw() } -/* -static EnvElement *getNextEnv(EnvElement *e) -{ - if (e == 0) - return RTData-> -} -*/ - - static unsigned clock_iter(void *arg) { bool alpha = Ctx->disp->hasAlpha(); @@ -322,7 +313,7 @@ static unsigned clock_iter(void *arg) uint8_t nextFont = font_sans12; switch (Ctx->mode) { case cm_time: - text = "time of day"; + text = "local time"; // nextFont = 4; break; case cm_date: @@ -353,7 +344,7 @@ static unsigned clock_iter(void *arg) if (text) { log_dbug(TAG,"mode %s",text); if (dm) { - dm->setFont(font_sanslight10); + dm->setFont(font_sanslight12); dm->setPos(3,4); } else { Ctx->disp->setPos(0,0); @@ -377,7 +368,7 @@ static unsigned clock_iter(void *arg) unsigned d = 100; // Ctx->disp->setPos(0,Ctx->disp->numLines() > 1 ? 1 : 0); if (dm) { - dm->setPos(10,20); + dm->setPos(5,22); } else { Ctx->disp->write("\r"); Ctx->disp->clrEol(); diff --git a/main/shell.cpp b/main/shell.cpp index a725060..bb3b154 100644 --- a/main/shell.cpp +++ b/main/shell.cpp @@ -695,7 +695,7 @@ static const char *shell_cp(Terminal &term, int argc, const char *args[]) #endif -void print_hex(Terminal &term, const uint8_t *b, size_t s, size_t off = 0) +void print_hex(Terminal &term, const uint8_t *b, size_t s, size_t off) { const uint8_t *a = b, *e = b + s; while (a != e) { @@ -1777,16 +1777,6 @@ static const char *nslookup(Terminal &term, int argc, const char *args[]) } -#ifdef CONFIG_DEVEL -static const char *segv(Terminal &term, int argc, const char *args[]) -{ - term.printf("triggering segment violoation\n"); - *(char*)0 = 1; - return 0; -} -#endif - - static const char *sntp(Terminal &term, int argc, const char *args[]) { if (argc > 3) @@ -2665,9 +2655,6 @@ ExeName ExeNames[] = { #ifdef CONFIG_SMARTCONFIG {"sc",1,sc,"SmartConfig actions",0}, #endif -#ifdef CONFIG_DEVEL - {"segv",1,segv,"trigger a segmentation violation",0}, -#endif #ifdef CONFIG_SPI {"spi",0,spicmd,"list/configure/operate SPI devices",0}, #endif diff --git a/main/shell.h b/main/shell.h index 9d06fa7..7acc84e 100644 --- a/main/shell.h +++ b/main/shell.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017-2022, Thomas Maier-Komor + * Copyright (C) 2017-2023, Thomas Maier-Komor * Atrium Firmware Package for ESP * * This program is free software: you can redistribute it and/or modify @@ -28,6 +28,7 @@ int exe_flags(char *cmd); const char *shellexe(Terminal &, char *cmd); void shell(Terminal &term, bool prompt = true); const char *help_cmd(Terminal &term, const char *arg); +void print_hex(Terminal &term, const uint8_t *b, size_t s, size_t off = 0); extern "C" #endif diff --git a/main/spi.cpp b/main/spi.cpp index 5498d56..af033ed 100644 --- a/main/spi.cpp +++ b/main/spi.cpp @@ -222,18 +222,30 @@ void spi_setup() if (c.has_miso()) { cfg.miso_io_num = c.miso(); cfg.flags |= SPICOMMON_BUSFLAG_MISO; +#ifdef CONFIG_IDF_TARGET_ESP32C3 + if (cfg.miso_io_num != 2) + cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; +#endif } else { cfg.miso_io_num = -1; } if (c.has_mosi()) { cfg.mosi_io_num = c.mosi(); cfg.flags |= SPICOMMON_BUSFLAG_MOSI; +#ifdef CONFIG_IDF_TARGET_ESP32C3 + if (cfg.mosi_io_num != 7) + cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; +#endif } else { cfg.mosi_io_num = -1; } if (c.has_sclk()) { cfg.sclk_io_num = c.sclk(); cfg.flags |= SPICOMMON_BUSFLAG_SCLK; +#ifdef CONFIG_IDF_TARGET_ESP32C3 + if (cfg.sclk_io_num != 6) + cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; +#endif } else { cfg.sclk_io_num = -1; } @@ -241,6 +253,12 @@ void spi_setup() cfg.quadwp_io_num = c.wp(); cfg.quadhd_io_num = c.hold(); cfg.flags |= SPICOMMON_BUSFLAG_WPHD; +#ifdef CONFIG_IDF_TARGET_ESP32C3 + if (cfg.quadwp_io_num != 5) + cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; + if (cfg.quadhd_io_num != 4) + cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; +#endif } else { cfg.quadwp_io_num = -1; cfg.quadhd_io_num = -1; diff --git a/mkatrium.sh b/mkatrium.sh index 43e4a8a..8fad72e 100755 --- a/mkatrium.sh +++ b/mkatrium.sh @@ -103,6 +103,8 @@ elif [ "$CONFIG_IDF_TARGET_ESP32S3" == "y" ]; then IDF_TARGET=esp32s3 elif [ "$CONFIG_IDF_TARGET_ESP32C3" == "y" ]; then IDF_TARGET=esp32c3 +elif [ "$CONFIG_IDF_TARGET_ESP32C6" == "y" ]; then + IDF_TARGET=esp32c6 fi ATRIUM_VER=`cat "$BUILD_DIR/version.txt"` diff --git a/projects/esp32-c3_4m b/projects/esp32-c3_4m index e2a9bdd..d002409 100644 --- a/projects/esp32-c3_4m +++ b/projects/esp32-c3_4m @@ -1642,7 +1642,6 @@ CONFIG_USB_HOST_FS=y CONFIG_USB_DIAGLOG=y CONFIG_USB_CONSOLE=y CONFIG_GPIOS=y -# CONFIG_CORETEMP is not set CONFIG_IOEXTENDERS=y CONFIG_LEDS=y CONFIG_BUTTON=y @@ -1653,8 +1652,8 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y CONFIG_DHT=y -# CONFIG_HLW8012 is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y @@ -1663,7 +1662,7 @@ CONFIG_PCF8574=y CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y -# CONFIG_OPT3001 is not set +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1674,10 +1673,8 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -# CONFIG_SX1276 is not set -CONFIG_SSD1309=y CONFIG_ILI9341=y -# CONFIG_SDCARD is not set +CONFIG_SDCARD=y CONFIG_XPT2046=y CONFIG_HCSR04=y CONFIG_DIMMER=y @@ -1688,7 +1685,7 @@ CONFIG_TLC5947=y # # development tools and experimental/alpha drivers (disable all) # -CONFIG_DEVEL=y +# CONFIG_DEVEL is not set # CONFIG_VERIFY_HEAP is not set # CONFIG_FUNCTION_TIMING is not set # end of development tools and experimental/alpha drivers (disable all) diff --git a/projects/esp32-c3_4m_dev b/projects/esp32-c3_4m_dev new file mode 100644 index 0000000..6573322 --- /dev/null +++ b/projects/esp32-c3_4m_dev @@ -0,0 +1,1879 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.1.1 Project Configuration +# +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_EFUSE_HAS_EFUSE_RST_BUG=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=5 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=1 +CONFIG_SOC_ADC_PATT_LEN_MAX=8 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_DIGI_MONITOR_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_SHARED_IDCACHE_SUPPORTED=y +CONFIG_SOC_CACHE_MEMORY_IBANK_SIZE=0x4000 +CONFIG_SOC_CPU_CORES_NUM=1 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FLEXIBLE_INTC=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=8 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=8 +CONFIG_SOC_CPU_WATCHPOINT_SIZE=0x80000000 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=3072 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_GDMA_GROUPS=1 +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=3 +CONFIG_SOC_GDMA_TX_RX_SHARE_INTERRUPT=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=22 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP=y +CONFIG_SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK=0 +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x00000000003FFFC0 +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_PERIPH_ALWAYS_ENABLE=y +CONFIG_SOC_I2C_NUM=1 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2S_NUM=1 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=6 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=2 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=2 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=4 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=108 +CONFIG_SOC_RTCIO_PIN_COUNT=0 +CONFIG_SOC_RSA_MAX_BIT_LEN=3072 +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SDM_GROUPS=1 +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=4 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=2 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_IDLE_INTR=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_CHECK_SUS=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=1 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=2 +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_PAD_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=32 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=512 +CONFIG_SOC_UART_NUM=2 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_REQUIRE_CORE_RESET=y +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_WIFI_PD=y +CONFIG_SOC_PM_SUPPORT_BT_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_RISCV=y +CONFIG_IDF_TARGET_ARCH="riscv" +CONFIG_IDF_TARGET="esp32c3" +CONFIG_IDF_TARGET_ESP32C3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_LOG_LEVEL=3 +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=3 +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_NO_STUB=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="ptables/esp32_4m-ptable.csv" +CONFIG_PARTITION_TABLE_FILENAME="ptables/esp32_4m-ptable.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS is not set +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# Driver Configurations +# + +# +# Legacy ADC Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Configuration + +# +# SPI Configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI Configuration + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Temperature sensor Configuration +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of Temperature sensor Configuration + +# +# UART Configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART Configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of GPIO Configuration + +# +# Sigma Delta Modulator Configuration +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of Sigma Delta Modulator Configuration + +# +# GPTimer Configuration +# +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of GPTimer Configuration + +# +# RMT Configuration +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of RMT Configuration + +# +# I2S Configuration +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of I2S Configuration + +# +# USB Serial/JTAG Configuration +# +# end of USB Serial/JTAG Configuration +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3 is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +# CONFIG_ESP32C3_REV_MIN_0 is not set +# CONFIG_ESP32C3_REV_MIN_1 is not set +# CONFIG_ESP32C3_REV_MIN_2 is not set +CONFIG_ESP32C3_REV_MIN_3=y +# CONFIG_ESP32C3_REV_MIN_4 is not set +CONFIG_ESP32C3_REV_MIN_FULL=3 +CONFIG_ESP_REV_MIN_FULL=3 + +# +# Maximum Supported ESP32-C3 Revision (Rev v0.99) +# +CONFIG_ESP32C3_REV_MAX_FULL=99 +CONFIG_ESP_REV_MAX_FULL=99 +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +# CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES=4 +# end of MAC Config + +# +# Sleep Config +# +# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set +CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND=y +# end of Sleep Config + +CONFIG_ESP_SLEEP_SYSTIMER_STALL_WORKAROUND=y + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configuration + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +# CONFIG_ESP_SYSTEM_USE_EH_FRAME is not set + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +# CONFIG_ESP_CONSOLE_UART_DEFAULT is not set +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_NONE=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1536 +# end of IPC (Inter-Processor Call) + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY=0x1 +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +# end of Wi-Fi + +# +# Core dump +# +CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_NONE is not set +# CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP_COREDUMP_CHECK_BOOT=y +CONFIG_ESP_COREDUMP_ENABLE=y +CONFIG_ESP_COREDUMP_LOGS=y +CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64 +CONFIG_ESP_COREDUMP_STACK_SIZE=0 +CONFIG_ESP_COREDUMP_SUMMARY_STACKDUMP_SIZE=1024 +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +# CONFIG_FATFS_LFN_NONE is not set +# CONFIG_FATFS_LFN_HEAP is not set +CONFIG_FATFS_LFN_STACK=y +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_MAX_LFN=63 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +# CONFIG_FATFS_API_ENCODING_UTF_8 is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +CONFIG_FREERTOS_UNICORE=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y +# CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID is not set +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=2096 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +# end of Port + +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +# CONFIG_HEAP_POISONING_DISABLED is not set +# CONFIG_HEAP_POISONING_LIGHT is not set +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +# CONFIG_HEAP_TRACING_OFF is not set +CONFIG_HEAP_TRACING_STANDALONE=y +# CONFIG_HEAP_TRACING_TOHOST is not set +CONFIG_HEAP_TRACING=y +CONFIG_HEAP_TRACING_STACK_DEPTH=0 +# CONFIG_HEAP_USE_HOOKS is not set +CONFIG_HEAP_TASK_TRACKING=y +# CONFIG_HEAP_TRACE_HASH_MAP is not set +CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS=y +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +CONFIG_IEEE802154_CCA_THRESHOLD=-60 +CONFIG_IEEE802154_PENDING_TABLE_SIZE=20 + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_CORE_LOCKING=y +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +CONFIG_LWIP_IPV6_AUTOCONFIG=y +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +CONFIG_LWIP_IPV6_RDNSS_MAX_DNS_SERVERS=0 +# CONFIG_LWIP_IPV6_DHCP6 is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI=y +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +# CONFIG_SPI_FLASH_AUTO_SUSPEND is not set +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Root Hub configuration +# +# end of Root Hub configuration + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +# CONFIG_VFS_SUPPORT_SELECT is not set +# CONFIG_VFS_SUPPORT_TERMIOS is not set +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager + +# +# Atrium +# +CONFIG_WFC_TARGET="esp32" + +# +# software services +# +CONFIG_CONSOLE_UART_TX=-1 +CONFIG_CONSOLE_UART_RX=-1 +CONFIG_UART_CONSOLE=y +CONFIG_HWCONF_DYNAMIC=y +CONFIG_LUA=y +CONFIG_THRESHOLDS=y +CONFIG_INTEGRATED_HELP=y +CONFIG_AT_ACTIONS=y +CONFIG_HOLIDAYS=y +CONFIG_TERMSERV=y +CONFIG_STATEMACHINES=y +# CONFIG_APP_PARAMS is not set +# end of software services + +# +# networking services +# +CONFIG_OTA=y +CONFIG_UDNS=y +CONFIG_MQTT=y +CONFIG_HTTP=y +CONFIG_FTP=y +CONFIG_TELNET=y +CONFIG_SYSLOG=y +CONFIG_INFLUX=y +CONFIG_UDPCTRL=y +CONFIG_WPS=y +# CONFIG_SMARTCONFIG is not set +# end of networking services + +# +# filesystem support +# +CONFIG_FATFS=y +CONFIG_ROMFS=y +CONFIG_ROMFS_VFS=y +CONFIG_ROMFS_VFS_NUMFDS=4 +CONFIG_USB_HOST_FS=y +# end of filesystem support + +# +# hardware support +# +CONFIG_USB_DIAGLOG=y +CONFIG_USB_CONSOLE=y +CONFIG_GPIOS=y +# CONFIG_CORETEMP is not set +CONFIG_IOEXTENDERS=y +CONFIG_LEDS=y +CONFIG_BUTTON=y +CONFIG_ROTARYENCODER=y +CONFIG_RELAY=y +CONFIG_ONEWIRE=y +CONFIG_DISPLAY=y +CONFIG_MAX7219=y +CONFIG_HT16K33=y +CONFIG_SSD1306=y +CONFIG_SH1106=y +CONFIG_DHT=y +CONFIG_HLW8012=y +CONFIG_I2C=y +CONFIG_I2C_XCMD=y +CONFIG_I2C_XDEV=y +CONFIG_PCA9685=y +CONFIG_PCF8574=y +CONFIG_TCA9555=y +CONFIG_MCP2300X=y +CONFIG_MCP2301X=y +CONFIG_OPT3001=y +CONFIG_INA2XX=y +CONFIG_SI7021=y +CONFIG_BMX280=y +CONFIG_BMP388=y +CONFIG_BME680=y +CONFIG_HDC1000=y +CONFIG_APDS9930=y +CONFIG_SGP30=y +CONFIG_CCS811B=y +CONFIG_BH1750=y +CONFIG_SPI=y +CONFIG_SX1276=y +CONFIG_SSD1309=y +CONFIG_ILI9341=y +CONFIG_SDCARD=y +CONFIG_XPT2046=y +CONFIG_HCSR04=y +CONFIG_DIMMER=y +CONFIG_RGBLEDS=y +CONFIG_TLC5947=y +# end of hardware support + +# +# development tools and experimental/alpha drivers (disable all) +# +CONFIG_DEVEL=y +CONFIG_VERIFY_HEAP=y +CONFIG_FUNCTION_TIMING=y +# end of development tools and experimental/alpha drivers (disable all) +# end of Atrium +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set +CONFIG_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP_SYSTEM_PD_FLASH is not set +CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND=y +CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +# CONFIG_ESP32C3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_ESP32C3_MEMPROT_FEATURE=y +CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK=y +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +# CONFIG_CONSOLE_UART_DEFAULT is not set +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32C3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32C3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1536 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set +# CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP32_ENABLE_COREDUMP=y +CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64 +CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0 +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +# CONFIG_SUPPORT_TERMIOS is not set +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/projects/esp32-c6_4m b/projects/esp32-c6_4m index a9273f5..21195eb 100644 --- a/projects/esp32-c6_4m +++ b/projects/esp32-c6_4m @@ -1021,20 +1021,18 @@ CONFIG_ESP_WIFI_ENABLE_WIFI_RX_MU_STATS=y # # Core dump # -# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set -CONFIG_ESP_COREDUMP_ENABLE_TO_UART=y +CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set # CONFIG_ESP_COREDUMP_ENABLE_TO_NONE is not set -CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN=y -# CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF is not set +# CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=y CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP_COREDUMP_CHECK_BOOT=y CONFIG_ESP_COREDUMP_ENABLE=y CONFIG_ESP_COREDUMP_LOGS=y CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64 -CONFIG_ESP_COREDUMP_UART_DELAY=0 CONFIG_ESP_COREDUMP_STACK_SIZE=0 -CONFIG_ESP_COREDUMP_DECODE_INFO=y -# CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set -CONFIG_ESP_COREDUMP_DECODE="info" +CONFIG_ESP_COREDUMP_SUMMARY_STACKDUMP_SIZE=1024 # end of Core dump # @@ -1115,7 +1113,7 @@ CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y # CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y -CONFIG_FREERTOS_ISR_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=2096 CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y @@ -1216,12 +1214,16 @@ CONFIG_LWIP_SO_REUSE_RXTOALL=y # CONFIG_LWIP_SO_RCVBUF is not set # CONFIG_LWIP_NETBUF_RECVINFO is not set CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y # CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 # CONFIG_LWIP_IP_FORWARD is not set # CONFIG_LWIP_STATS is not set CONFIG_LWIP_ESP_GRATUITOUS_ARP=y CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y # CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set @@ -1239,9 +1241,17 @@ CONFIG_LWIP_DHCPS_LEASE_UNIT=60 CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 # end of DHCP server -# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_AUTOIP=y +CONFIG_LWIP_AUTOIP_TRIES=2 +CONFIG_LWIP_AUTOIP_MAX_CONFLICTS=9 +CONFIG_LWIP_AUTOIP_RATE_LIMIT_INTERVAL=20 CONFIG_LWIP_IPV4=y -# CONFIG_LWIP_IPV6 is not set +CONFIG_LWIP_IPV6=y +CONFIG_LWIP_IPV6_AUTOCONFIG=y +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +CONFIG_LWIP_IPV6_RDNSS_MAX_DNS_SERVERS=0 +CONFIG_LWIP_IPV6_DHCP6=y # CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set CONFIG_LWIP_NETIF_LOOPBACK=y CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 @@ -1289,6 +1299,8 @@ CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y # CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF # CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 # CONFIG_LWIP_SLIP_SUPPORT is not set # @@ -1322,9 +1334,21 @@ CONFIG_LWIP_ESP_LWIP_ASSERT=y # CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y # CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set # CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set # end of Hooks # CONFIG_LWIP_DEBUG is not set @@ -1621,7 +1645,10 @@ CONFIG_SPIFFS_USE_MTIME=y # # Ultra Low Power (ULP) Co-processor # -# CONFIG_ULP_COPROC_ENABLED is not set +CONFIG_ULP_COPROC_ENABLED=y +CONFIG_ULP_COPROC_TYPE_LP_CORE=y +CONFIG_ULP_COPROC_RESERVE_MEM=4096 +CONFIG_ULP_SHARED_MEM=0x8 # end of Ultra Low Power (ULP) Co-processor # @@ -1738,6 +1765,7 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y # CONFIG_DHT is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y @@ -1747,6 +1775,7 @@ CONFIG_PCF8574=y CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1757,10 +1786,9 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -# CONFIG_SSD1309 is not set -# CONFIG_ILI9341 is not set +CONFIG_ILI9341=y CONFIG_SDCARD=y -# CONFIG_XPT2046 is not set +CONFIG_XPT2046=y CONFIG_HCSR04=y CONFIG_DIMMER=y CONFIG_RGBLEDS=y @@ -1892,19 +1920,15 @@ CONFIG_WPA_MBEDTLS_TLS_CLIENT=y # CONFIG_WPA_WPS_STRICT is not set # CONFIG_WPA_DEBUG_PRINT is not set # CONFIG_WPA_TESTING_OPTIONS is not set -# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set -CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set # CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set -CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN=y -# CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF is not set +# CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF=y CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y CONFIG_ESP32_ENABLE_COREDUMP=y CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64 -CONFIG_ESP32_CORE_DUMP_UART_DELAY=0 CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0 -CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y -# CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set -CONFIG_ESP32_CORE_DUMP_DECODE="info" CONFIG_TIMER_TASK_PRIORITY=1 CONFIG_TIMER_TASK_STACK_DEPTH=2048 CONFIG_TIMER_QUEUE_LENGTH=10 diff --git a/projects/esp32-s2_4m b/projects/esp32-s2_4m index ef7aced..6b4fa99 100644 --- a/projects/esp32-s2_4m +++ b/projects/esp32-s2_4m @@ -1675,7 +1675,7 @@ CONFIG_OTA=y CONFIG_UDNS=y CONFIG_MQTT=y CONFIG_HTTP=y -# CONFIG_FTP is not set +CONFIG_FTP=y CONFIG_TELNET=y CONFIG_SYSLOG=y CONFIG_INFLUX=y @@ -1698,7 +1698,6 @@ CONFIG_USB_HOST_FS=y # hardware support # CONFIG_GPIOS=y -# CONFIG_CORETEMP is not set CONFIG_IOEXTENDERS=y CONFIG_LEDS=y CONFIG_BUTTON=y @@ -1709,8 +1708,8 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y CONFIG_DHT=y -# CONFIG_HLW8012 is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y @@ -1719,7 +1718,7 @@ CONFIG_PCF8574=y CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y -# CONFIG_OPT3001 is not set +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1730,9 +1729,7 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -# CONFIG_SX1276 is not set -CONFIG_SSD1309=y -# CONFIG_SDCARD is not set +CONFIG_SDCARD=y CONFIG_XPT2046=y CONFIG_HCSR04=y CONFIG_DIMMER=y @@ -1743,7 +1740,7 @@ CONFIG_TLC5947=y # # development tools and experimental/alpha drivers (disable all) # -CONFIG_DEVEL=y +# CONFIG_DEVEL is not set # CONFIG_VERIFY_HEAP is not set # CONFIG_FUNCTION_TIMING is not set # end of development tools and experimental/alpha drivers (disable all) diff --git a/projects/esp32-s3_4m b/projects/esp32-s3_4m index 92b6e61..bb87cad 100644 --- a/projects/esp32-s3_4m +++ b/projects/esp32-s3_4m @@ -756,8 +756,8 @@ CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 # # Sleep Config # -# CONFIG_ESP_SLEEP_POWER_DOWN_FLASH is not set CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y # CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set @@ -838,7 +838,7 @@ CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 CONFIG_ESP_PHY_MAX_TX_POWER=20 # CONFIG_ESP_PHY_REDUCE_TX_POWER is not set -# CONFIG_ESP_PHY_ENABLE_USB is not set +CONFIG_ESP_PHY_ENABLE_USB=y # CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set CONFIG_ESP_PHY_RF_CAL_PARTIAL=y # CONFIG_ESP_PHY_RF_CAL_NONE is not set @@ -857,7 +857,37 @@ CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y # # ESP PSRAM # -# CONFIG_SPIRAM is not set +CONFIG_SPIRAM=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_MODE_QUAD=y +# CONFIG_SPIRAM_MODE_OCT is not set +CONFIG_SPIRAM_TYPE_AUTO=y +# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_SPIRAM_CLK_IO=30 +CONFIG_SPIRAM_CS_IO=26 +# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set +# CONFIG_SPIRAM_RODATA is not set +# CONFIG_SPIRAM_SPEED_120M is not set +# CONFIG_SPIRAM_SPEED_80M is not set +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_SPEED=40 +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +# CONFIG_SPIRAM_USE_MEMMAP is not set +# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set +# end of SPI RAM config # end of ESP PSRAM # @@ -1005,14 +1035,15 @@ CONFIG_ESP_WIFI_ENABLED=y CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y -# CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER is not set CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0 CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32 # CONFIG_ESP_WIFI_CSI_ENABLED is not set CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y CONFIG_ESP_WIFI_TX_BA_WIN=6 CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y CONFIG_ESP_WIFI_RX_BA_WIN=6 +# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set CONFIG_ESP_WIFI_NVS_ENABLED=y CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 @@ -1105,6 +1136,7 @@ CONFIG_FATFS_CODEPAGE=437 CONFIG_FATFS_FS_LOCK=0 CONFIG_FATFS_TIMEOUT_MS=10000 CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y # CONFIG_FATFS_USE_FASTSEEK is not set CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 # end of FAT Filesystem support @@ -1373,6 +1405,7 @@ CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y # mbedTLS # CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC is not set # CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set # CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y @@ -1775,6 +1808,7 @@ CONFIG_OTA=y CONFIG_UDNS=y CONFIG_MQTT=y CONFIG_HTTP=y +CONFIG_FTP=y CONFIG_TELNET=y CONFIG_SYSLOG=y CONFIG_INFLUX=y @@ -1786,19 +1820,19 @@ CONFIG_WPS=y # # filesystem support # -# CONFIG_FATFS is not set +CONFIG_FATFS=y CONFIG_ROMFS=y -# CONFIG_ROMFS_VFS is not set -# CONFIG_USB_HOST_FS is not set +CONFIG_ROMFS_VFS=y +CONFIG_ROMFS_VFS_NUMFDS=4 +CONFIG_USB_HOST_FS=y # end of filesystem support # # hardware support # -# CONFIG_USB_DIAGLOG is not set -# CONFIG_USB_CONSOLE is not set -# CONFIG_GPIOS is not set -# CONFIG_CORETEMP is not set +CONFIG_USB_DIAGLOG=y +CONFIG_USB_CONSOLE=y +CONFIG_GPIOS=y CONFIG_IOEXTENDERS=y CONFIG_LEDS=y CONFIG_BUTTON=y @@ -1809,17 +1843,17 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y CONFIG_DHT=y -# CONFIG_HLW8012 is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y -# CONFIG_PCA9685 is not set -# CONFIG_PCF8574 is not set -# CONFIG_TCA9555 is not set -# CONFIG_MCP2300X is not set -# CONFIG_MCP2301X is not set -# CONFIG_OPT3001 is not set +CONFIG_PCA9685=y +CONFIG_PCF8574=y +CONFIG_TCA9555=y +CONFIG_MCP2300X=y +CONFIG_MCP2301X=y +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1830,21 +1864,19 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -# CONFIG_SX1276 is not set -# CONFIG_SSD1309 is not set -# CONFIG_ILI9341 is not set -# CONFIG_SDCARD is not set +CONFIG_ILI9341=y +CONFIG_SDCARD=y CONFIG_XPT2046=y CONFIG_HCSR04=y CONFIG_DIMMER=y -# CONFIG_RGBLEDS is not set -# CONFIG_TLC5947 is not set +CONFIG_RGBLEDS=y +CONFIG_TLC5947=y # end of hardware support # # development tools and experimental/alpha drivers (disable all) # -CONFIG_DEVEL=y +# CONFIG_DEVEL is not set # CONFIG_VERIFY_HEAP is not set # CONFIG_FUNCTION_TIMING is not set # end of development tools and experimental/alpha drivers (disable all) @@ -1894,7 +1926,6 @@ CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y CONFIG_POST_EVENTS_FROM_ISR=y CONFIG_POST_EVENTS_FROM_IRAM_ISR=y # CONFIG_OTA_ALLOW_HTTP is not set -# CONFIG_ESP_SYSTEM_PD_FLASH is not set CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y # CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set @@ -1908,7 +1939,9 @@ CONFIG_ESP32_PHY_MAX_TX_POWER=20 # CONFIG_REDUCE_PHY_TX_POWER is not set # CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y -# CONFIG_ESP32S3_SPIRAM_SUPPORT is not set +CONFIG_ESP32S3_SPIRAM_SUPPORT=y +CONFIG_DEFAULT_PSRAM_CLK_IO=30 +CONFIG_DEFAULT_PSRAM_CS_IO=26 # CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y # CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set @@ -1955,9 +1988,9 @@ CONFIG_ESP32_WIFI_ENABLED=y CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y -# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32 # CONFIG_ESP32_WIFI_CSI_ENABLED is not set CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y CONFIG_ESP32_WIFI_TX_BA_WIN=6 @@ -1965,6 +1998,7 @@ CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y CONFIG_ESP32_WIFI_RX_BA_WIN=6 CONFIG_ESP32_WIFI_RX_BA_WIN=6 +# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set CONFIG_ESP32_WIFI_NVS_ENABLED=y CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 diff --git a/projects/esp32-s3_4m_dev b/projects/esp32-s3_4m_dev new file mode 100644 index 0000000..54c2c5e --- /dev/null +++ b/projects/esp32-s3_4m_dev @@ -0,0 +1,2086 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.1.1 Project Configuration +# +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_CACHE_SUPPORT_WRAP=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_ULP_FSM_SUPPORTED=y +CONFIG_SOC_RISCV_COPROC_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=24 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y +CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINT_SIZE=64 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_GDMA_GROUPS=y +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5 +CONFIG_SOC_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=49 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000 +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y +CONFIG_SOC_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2S_NUM=2 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_PCNT_GROUPS=1 +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCD_I80_BUSES=1 +CONFIG_SOC_LCD_RGB_PANELS=1 +CONFIG_SOC_LCD_I80_BUS_WIDTH=16 +CONFIG_SOC_LCD_RGB_DATA_WIDTH=16 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549 +CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTCIO_PIN_COUNT=22 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_SDM_GROUPS=y +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TOUCH_VERSION_2=y +CONFIG_SOC_TOUCH_SENSOR_NUM=15 +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF +CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_UART_NUM=3 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_REQUIRE_CORE_RESET=y +CONFIG_SOC_USB_PERIPH_NUM=y +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_SUPPORT_MODEM_PD=y +CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y +CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256 +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_SOC_ULP_HAS_ADC=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET_ARCH="xtensa" +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_INFO is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE=y +CONFIG_BOOTLOADER_LOG_LEVEL=5 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4 +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y +CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="ptables/esp32_4m-ptable.csv" +CONFIG_PARTITION_TABLE_FILENAME="ptables/esp32_4m-ptable.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART0 is not set +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# Driver Configurations +# + +# +# Legacy ADC Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Configuration + +# +# SPI Configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI Configuration + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Temperature sensor Configuration +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of Temperature sensor Configuration + +# +# UART Configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART Configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of GPIO Configuration + +# +# Sigma Delta Modulator Configuration +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of Sigma Delta Modulator Configuration + +# +# GPTimer Configuration +# +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of GPTimer Configuration + +# +# PCNT Configuration +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of PCNT Configuration + +# +# RMT Configuration +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of RMT Configuration + +# +# MCPWM Configuration +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of MCPWM Configuration + +# +# I2S Configuration +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of I2S Configuration + +# +# USB Serial/JTAG Configuration +# +# end of USB Serial/JTAG Configuration +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +CONFIG_ESP32S3_REV_MIN_0=y +# CONFIG_ESP32S3_REV_MIN_1 is not set +# CONFIG_ESP32S3_REV_MIN_2 is not set +CONFIG_ESP32S3_REV_MIN_FULL=0 +CONFIG_ESP_REV_MIN_FULL=0 + +# +# Maximum Supported ESP32-S3 Revision (Rev v0.99) +# +CONFIG_ESP32S3_REV_MAX_FULL=99 +CONFIG_ESP_REV_MAX_FULL=99 +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# end of MAC Config + +# +# Sleep Config +# +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y +# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +# CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configuration + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION=y +# CONFIG_ESP_PHY_DEFAULT_INIT_IF_INVALID is not set +# CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# +CONFIG_SPIRAM=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_MODE_QUAD=y +# CONFIG_SPIRAM_MODE_OCT is not set +CONFIG_SPIRAM_TYPE_AUTO=y +# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y +CONFIG_SPIRAM_CLK_IO=30 +CONFIG_SPIRAM_CS_IO=26 +# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set +# CONFIG_SPIRAM_RODATA is not set +# CONFIG_SPIRAM_SPEED_120M is not set +# CONFIG_SPIRAM_SPEED_80M is not set +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_SPEED=40 +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +# CONFIG_SPIRAM_USE_MEMMAP is not set +# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set +# end of SPI RAM config +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# end of Cache config + +# +# Memory +# +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of Memory + +# +# Trace memory +# +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# end of Trace memory + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +# CONFIG_ESP_CONSOLE_UART_DEFAULT is not set +# CONFIG_ESP_CONSOLE_USB_CDC is not set +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_NONE=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=-1 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1536 +# end of IPC (Inter-Processor Call) + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY=0x1 +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +# end of Wi-Fi + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_UART=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_NONE is not set +# CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP_COREDUMP_ENABLE=y +CONFIG_ESP_COREDUMP_LOGS=y +CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64 +CONFIG_ESP_COREDUMP_UART_DELAY=0 +CONFIG_ESP_COREDUMP_STACK_SIZE=0 +CONFIG_ESP_COREDUMP_DECODE_INFO=y +# CONFIG_ESP_COREDUMP_DECODE_DISABLE is not set +CONFIG_ESP_COREDUMP_DECODE="info" +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +CONFIG_FREERTOS_UNICORE=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +# CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=2096 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +# end of Port + +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_USE_HOOKS is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +CONFIG_IEEE802154_CCA_THRESHOLD=-60 +CONFIG_IEEE802154_PENDING_TABLE_SIZE=20 + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_CORE_LOCKING=y +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +CONFIG_LWIP_IPV6_AUTOCONFIG=y +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +CONFIG_LWIP_IPV6_RDNSS_MAX_DNS_SERVERS=0 +# CONFIG_LWIP_IPV6_DHCP6 is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC is not set +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_OTG_SUPPORTED=y +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set + +# +# Root Hub configuration +# +CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250 +CONFIG_USB_HOST_RESET_HOLD_MS=30 +CONFIG_USB_HOST_RESET_RECOVERY_MS=30 +CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10 +# end of Root Hub configuration +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager + +# +# Atrium +# +CONFIG_WFC_TARGET="esp32" + +# +# software services +# +CONFIG_CONSOLE_UART_TX=-1 +CONFIG_CONSOLE_UART_RX=-1 +CONFIG_UART_CONSOLE=y +CONFIG_HWCONF_DYNAMIC=y +CONFIG_LUA=y +# CONFIG_THRESHOLDS is not set +CONFIG_INTEGRATED_HELP=y +CONFIG_AT_ACTIONS=y +CONFIG_HOLIDAYS=y +CONFIG_TERMSERV=y +CONFIG_STATEMACHINES=y +# CONFIG_APP_PARAMS is not set +# end of software services + +# +# networking services +# +CONFIG_OTA=y +CONFIG_UDNS=y +CONFIG_MQTT=y +CONFIG_HTTP=y +CONFIG_FTP=y +CONFIG_TELNET=y +CONFIG_SYSLOG=y +CONFIG_INFLUX=y +CONFIG_UDPCTRL=y +CONFIG_WPS=y +# CONFIG_SMARTCONFIG is not set +# end of networking services + +# +# filesystem support +# +CONFIG_FATFS=y +CONFIG_ROMFS=y +CONFIG_ROMFS_VFS=y +CONFIG_ROMFS_VFS_NUMFDS=4 +CONFIG_USB_HOST_FS=y +# end of filesystem support + +# +# hardware support +# +CONFIG_USB_DIAGLOG=y +CONFIG_USB_CONSOLE=y +CONFIG_GPIOS=y +# CONFIG_CORETEMP is not set +CONFIG_IOEXTENDERS=y +CONFIG_LEDS=y +CONFIG_BUTTON=y +CONFIG_ROTARYENCODER=y +CONFIG_RELAY=y +CONFIG_ONEWIRE=y +CONFIG_DISPLAY=y +CONFIG_MAX7219=y +CONFIG_HT16K33=y +CONFIG_SSD1306=y +CONFIG_SH1106=y +CONFIG_DHT=y +CONFIG_HLW8012=y +CONFIG_I2C=y +CONFIG_I2C_XCMD=y +CONFIG_I2C_XDEV=y +CONFIG_PCA9685=y +CONFIG_PCF8574=y +CONFIG_TCA9555=y +CONFIG_MCP2300X=y +CONFIG_MCP2301X=y +CONFIG_OPT3001=y +CONFIG_INA2XX=y +CONFIG_SI7021=y +CONFIG_BMX280=y +CONFIG_BMP388=y +CONFIG_BME680=y +CONFIG_HDC1000=y +CONFIG_APDS9930=y +CONFIG_SGP30=y +CONFIG_CCS811B=y +CONFIG_BH1750=y +CONFIG_SPI=y +# CONFIG_SX1276 is not set +CONFIG_SSD1309=y +CONFIG_ILI9341=y +CONFIG_SDCARD=y +CONFIG_XPT2046=y +CONFIG_HCSR04=y +CONFIG_DIMMER=y +CONFIG_RGBLEDS=y +CONFIG_TLC5947=y +# end of hardware support + +# +# development tools and experimental/alpha drivers (disable all) +# +CONFIG_DEVEL=y +CONFIG_VERIFY_HEAP=y +CONFIG_FUNCTION_TIMING=y +# end of development tools and experimental/alpha drivers (disable all) +# end of Atrium +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_INFO is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=y +CONFIG_LOG_BOOTLOADER_LEVEL=5 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_OTA_ALLOW_HTTP is not set +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION=y +# CONFIG_ESP32_PHY_DEFAULT_INIT_IF_INVALID is not set +# CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +CONFIG_ESP32S3_SPIRAM_SUPPORT=y +CONFIG_DEFAULT_PSRAM_CLK_IO=30 +CONFIG_DEFAULT_PSRAM_CS_IO=26 +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +# CONFIG_CONSOLE_UART_DEFAULT is not set +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=-1 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1536 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_UART=y +# CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set +# CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP32_ENABLE_COREDUMP=y +CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64 +CONFIG_ESP32_CORE_DUMP_UART_DELAY=0 +CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0 +CONFIG_ESP32_CORE_DUMP_DECODE_INFO=y +# CONFIG_ESP32_CORE_DUMP_DECODE_DISABLE is not set +CONFIG_ESP32_CORE_DUMP_DECODE="info" +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/projects/esp32-s3_8m b/projects/esp32-s3_8m index f0d2907..cb85835 100644 --- a/projects/esp32-s3_8m +++ b/projects/esp32-s3_8m @@ -1839,16 +1839,15 @@ CONFIG_FATFS=y CONFIG_ROMFS=y CONFIG_ROMFS_VFS=y CONFIG_ROMFS_VFS_NUMFDS=4 -# CONFIG_USB_HOST_FS is not set +CONFIG_USB_HOST_FS=y # end of filesystem support # # hardware support # -# CONFIG_USB_DIAGLOG is not set +CONFIG_USB_DIAGLOG=y CONFIG_USB_CONSOLE=y CONFIG_GPIOS=y -# CONFIG_CORETEMP is not set CONFIG_IOEXTENDERS=y CONFIG_LEDS=y CONFIG_BUTTON=y @@ -1859,8 +1858,8 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y CONFIG_DHT=y -# CONFIG_HLW8012 is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y @@ -1869,7 +1868,7 @@ CONFIG_PCF8574=y CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y -# CONFIG_OPT3001 is not set +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1880,8 +1879,6 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -# CONFIG_SX1276 is not set -CONFIG_SSD1309=y CONFIG_ILI9341=y CONFIG_SDCARD=y CONFIG_XPT2046=y @@ -1894,9 +1891,9 @@ CONFIG_TLC5947=y # # development tools and experimental/alpha drivers (disable all) # -CONFIG_DEVEL=y +# CONFIG_DEVEL is not set # CONFIG_VERIFY_HEAP is not set -CONFIG_FUNCTION_TIMING=y +# CONFIG_FUNCTION_TIMING is not set # end of development tools and experimental/alpha drivers (disable all) # end of Atrium # end of Component config diff --git a/projects/esp32-s3_8m_dev b/projects/esp32-s3_8m_dev new file mode 100644 index 0000000..4155577 --- /dev/null +++ b/projects/esp32-s3_8m_dev @@ -0,0 +1,2101 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) 5.1.1 Project Configuration +# +CONFIG_SOC_MPU_MIN_REGION_SIZE=0x20000000 +CONFIG_SOC_MPU_REGIONS_MAX_NUM=8 +CONFIG_SOC_ADC_SUPPORTED=y +CONFIG_SOC_UART_SUPPORTED=y +CONFIG_SOC_PCNT_SUPPORTED=y +CONFIG_SOC_WIFI_SUPPORTED=y +CONFIG_SOC_TWAI_SUPPORTED=y +CONFIG_SOC_GDMA_SUPPORTED=y +CONFIG_SOC_GPTIMER_SUPPORTED=y +CONFIG_SOC_LCDCAM_SUPPORTED=y +CONFIG_SOC_MCPWM_SUPPORTED=y +CONFIG_SOC_DEDICATED_GPIO_SUPPORTED=y +CONFIG_SOC_CACHE_SUPPORT_WRAP=y +CONFIG_SOC_ULP_SUPPORTED=y +CONFIG_SOC_ULP_FSM_SUPPORTED=y +CONFIG_SOC_RISCV_COPROC_SUPPORTED=y +CONFIG_SOC_BT_SUPPORTED=y +CONFIG_SOC_USB_OTG_SUPPORTED=y +CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED=y +CONFIG_SOC_CCOMP_TIMER_SUPPORTED=y +CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED=y +CONFIG_SOC_SUPPORTS_SECURE_DL_MODE=y +CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD=y +CONFIG_SOC_SDMMC_HOST_SUPPORTED=y +CONFIG_SOC_RTC_FAST_MEM_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED=y +CONFIG_SOC_RTC_MEM_SUPPORTED=y +CONFIG_SOC_PSRAM_DMA_CAPABLE=y +CONFIG_SOC_XT_WDT_SUPPORTED=y +CONFIG_SOC_I2S_SUPPORTED=y +CONFIG_SOC_RMT_SUPPORTED=y +CONFIG_SOC_SDM_SUPPORTED=y +CONFIG_SOC_GPSPI_SUPPORTED=y +CONFIG_SOC_LEDC_SUPPORTED=y +CONFIG_SOC_I2C_SUPPORTED=y +CONFIG_SOC_SYSTIMER_SUPPORTED=y +CONFIG_SOC_SUPPORT_COEXISTENCE=y +CONFIG_SOC_TEMP_SENSOR_SUPPORTED=y +CONFIG_SOC_AES_SUPPORTED=y +CONFIG_SOC_MPI_SUPPORTED=y +CONFIG_SOC_SHA_SUPPORTED=y +CONFIG_SOC_HMAC_SUPPORTED=y +CONFIG_SOC_DIG_SIGN_SUPPORTED=y +CONFIG_SOC_FLASH_ENC_SUPPORTED=y +CONFIG_SOC_SECURE_BOOT_SUPPORTED=y +CONFIG_SOC_MEMPROT_SUPPORTED=y +CONFIG_SOC_TOUCH_SENSOR_SUPPORTED=y +CONFIG_SOC_BOD_SUPPORTED=y +CONFIG_SOC_XTAL_SUPPORT_40M=y +CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG=y +CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED=y +CONFIG_SOC_ADC_ARBITER_SUPPORTED=y +CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED=y +CONFIG_SOC_ADC_MONITOR_SUPPORTED=y +CONFIG_SOC_ADC_DMA_SUPPORTED=y +CONFIG_SOC_ADC_PERIPH_NUM=2 +CONFIG_SOC_ADC_MAX_CHANNEL_NUM=10 +CONFIG_SOC_ADC_ATTEN_NUM=4 +CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM=2 +CONFIG_SOC_ADC_PATT_LEN_MAX=24 +CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_DIGI_RESULT_BYTES=4 +CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV=4 +CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM=2 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH=83333 +CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW=611 +CONFIG_SOC_ADC_RTC_MIN_BITWIDTH=12 +CONFIG_SOC_ADC_RTC_MAX_BITWIDTH=12 +CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED=y +CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED=y +CONFIG_SOC_APB_BACKUP_DMA=y +CONFIG_SOC_BROWNOUT_RESET_SUPPORTED=y +CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED=y +CONFIG_SOC_CACHE_FREEZE_SUPPORTED=y +CONFIG_SOC_CPU_CORES_NUM=2 +CONFIG_SOC_CPU_INTR_NUM=32 +CONFIG_SOC_CPU_HAS_FPU=y +CONFIG_SOC_CPU_BREAKPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINTS_NUM=2 +CONFIG_SOC_CPU_WATCHPOINT_SIZE=64 +CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN=4096 +CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH=16 +CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US=1100 +CONFIG_SOC_GDMA_GROUPS=y +CONFIG_SOC_GDMA_PAIRS_PER_GROUP=5 +CONFIG_SOC_GDMA_SUPPORT_PSRAM=y +CONFIG_SOC_GPIO_PORT=1 +CONFIG_SOC_GPIO_PIN_COUNT=49 +CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER=y +CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB=y +CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT=y +CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD=y +CONFIG_SOC_GPIO_VALID_GPIO_MASK=0x1FFFFFFFFFFFF +CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK=0x0001FFFFFC000000 +CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM=8 +CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE=y +CONFIG_SOC_I2C_NUM=2 +CONFIG_SOC_I2C_FIFO_LEN=32 +CONFIG_SOC_I2C_CMD_REG_NUM=8 +CONFIG_SOC_I2C_SUPPORT_SLAVE=y +CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS=y +CONFIG_SOC_I2C_SUPPORT_XTAL=y +CONFIG_SOC_I2C_SUPPORT_RTC=y +CONFIG_SOC_I2S_NUM=2 +CONFIG_SOC_I2S_HW_VERSION_2=y +CONFIG_SOC_I2S_SUPPORTS_XTAL=y +CONFIG_SOC_I2S_SUPPORTS_PLL_F160M=y +CONFIG_SOC_I2S_SUPPORTS_PCM=y +CONFIG_SOC_I2S_SUPPORTS_PDM=y +CONFIG_SOC_I2S_SUPPORTS_PDM_TX=y +CONFIG_SOC_I2S_PDM_MAX_TX_LINES=2 +CONFIG_SOC_I2S_SUPPORTS_PDM_RX=y +CONFIG_SOC_I2S_PDM_MAX_RX_LINES=4 +CONFIG_SOC_I2S_SUPPORTS_TDM=y +CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK=y +CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_LEDC_CHANNEL_NUM=8 +CONFIG_SOC_LEDC_TIMER_BIT_WIDTH=14 +CONFIG_SOC_LEDC_SUPPORT_FADE_STOP=y +CONFIG_SOC_MCPWM_GROUPS=2 +CONFIG_SOC_MCPWM_TIMERS_PER_GROUP=3 +CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP=3 +CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR=2 +CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP=3 +CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP=y +CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER=3 +CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP=3 +CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE=y +CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM=1 +CONFIG_SOC_MMU_PERIPH_NUM=1 +CONFIG_SOC_PCNT_GROUPS=1 +CONFIG_SOC_PCNT_UNITS_PER_GROUP=4 +CONFIG_SOC_PCNT_CHANNELS_PER_UNIT=2 +CONFIG_SOC_PCNT_THRES_POINT_PER_UNIT=2 +CONFIG_SOC_RMT_GROUPS=1 +CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP=4 +CONFIG_SOC_RMT_CHANNELS_PER_GROUP=8 +CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL=48 +CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG=y +CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION=y +CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT=y +CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP=y +CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO=y +CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY=y +CONFIG_SOC_RMT_SUPPORT_XTAL=y +CONFIG_SOC_RMT_SUPPORT_RC_FAST=y +CONFIG_SOC_RMT_SUPPORT_APB=y +CONFIG_SOC_RMT_SUPPORT_DMA=y +CONFIG_SOC_LCD_I80_SUPPORTED=y +CONFIG_SOC_LCD_RGB_SUPPORTED=y +CONFIG_SOC_LCD_I80_BUSES=1 +CONFIG_SOC_LCD_RGB_PANELS=1 +CONFIG_SOC_LCD_I80_BUS_WIDTH=16 +CONFIG_SOC_LCD_RGB_DATA_WIDTH=16 +CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV=y +CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM=549 +CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH=128 +CONFIG_SOC_RTCIO_PIN_COUNT=22 +CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED=y +CONFIG_SOC_RTCIO_HOLD_SUPPORTED=y +CONFIG_SOC_RTCIO_WAKE_SUPPORTED=y +CONFIG_SOC_SDM_GROUPS=y +CONFIG_SOC_SDM_CHANNELS_PER_GROUP=8 +CONFIG_SOC_SDM_CLK_SUPPORT_APB=y +CONFIG_SOC_SPI_PERIPH_NUM=3 +CONFIG_SOC_SPI_MAX_CS_NUM=6 +CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE=64 +CONFIG_SOC_SPI_SUPPORT_DDRCLK=y +CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS=y +CONFIG_SOC_SPI_SUPPORT_CD_SIG=y +CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS=y +CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2=y +CONFIG_SOC_SPI_SUPPORT_CLK_APB=y +CONFIG_SOC_SPI_SUPPORT_CLK_XTAL=y +CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT=y +CONFIG_SOC_MEMSPI_IS_INDEPENDENT=y +CONFIG_SOC_SPI_MAX_PRE_DIVIDER=16 +CONFIG_SOC_SPI_SUPPORT_OCT=y +CONFIG_SOC_MEMSPI_SRC_FREQ_120M=y +CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED=y +CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED=y +CONFIG_SOC_SPIRAM_SUPPORTED=y +CONFIG_SOC_SPIRAM_XIP_SUPPORTED=y +CONFIG_SOC_SYSTIMER_COUNTER_NUM=2 +CONFIG_SOC_SYSTIMER_ALARM_NUM=3 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO=32 +CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI=20 +CONFIG_SOC_SYSTIMER_FIXED_DIVIDER=y +CONFIG_SOC_SYSTIMER_INT_LEVEL=y +CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE=y +CONFIG_SOC_TIMER_GROUPS=2 +CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP=2 +CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH=54 +CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL=y +CONFIG_SOC_TIMER_GROUP_SUPPORT_APB=y +CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS=4 +CONFIG_SOC_TOUCH_VERSION_2=y +CONFIG_SOC_TOUCH_SENSOR_NUM=15 +CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM=3 +CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED=y +CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX=0x1FFFFF +CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX=0xFF +CONFIG_SOC_TWAI_CONTROLLER_NUM=1 +CONFIG_SOC_TWAI_CLK_SUPPORT_APB=y +CONFIG_SOC_TWAI_BRP_MIN=2 +CONFIG_SOC_TWAI_BRP_MAX=16384 +CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS=y +CONFIG_SOC_UART_NUM=3 +CONFIG_SOC_UART_FIFO_LEN=128 +CONFIG_SOC_UART_BITRATE_MAX=5000000 +CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND=y +CONFIG_SOC_UART_SUPPORT_WAKEUP_INT=y +CONFIG_SOC_UART_SUPPORT_APB_CLK=y +CONFIG_SOC_UART_SUPPORT_RTC_CLK=y +CONFIG_SOC_UART_SUPPORT_XTAL_CLK=y +CONFIG_SOC_UART_REQUIRE_CORE_RESET=y +CONFIG_SOC_USB_PERIPH_NUM=y +CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE=3968 +CONFIG_SOC_SHA_SUPPORT_DMA=y +CONFIG_SOC_SHA_SUPPORT_RESUME=y +CONFIG_SOC_SHA_GDMA=y +CONFIG_SOC_SHA_SUPPORT_SHA1=y +CONFIG_SOC_SHA_SUPPORT_SHA224=y +CONFIG_SOC_SHA_SUPPORT_SHA256=y +CONFIG_SOC_SHA_SUPPORT_SHA384=y +CONFIG_SOC_SHA_SUPPORT_SHA512=y +CONFIG_SOC_SHA_SUPPORT_SHA512_224=y +CONFIG_SOC_SHA_SUPPORT_SHA512_256=y +CONFIG_SOC_SHA_SUPPORT_SHA512_T=y +CONFIG_SOC_RSA_MAX_BIT_LEN=4096 +CONFIG_SOC_AES_SUPPORT_DMA=y +CONFIG_SOC_AES_GDMA=y +CONFIG_SOC_AES_SUPPORT_AES_128=y +CONFIG_SOC_AES_SUPPORT_AES_256=y +CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_BT_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP=y +CONFIG_SOC_PM_SUPPORT_CPU_PD=y +CONFIG_SOC_PM_SUPPORT_TAGMEM_PD=y +CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD=y +CONFIG_SOC_PM_SUPPORT_RC_FAST_PD=y +CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD=y +CONFIG_SOC_PM_SUPPORT_MAC_BB_PD=y +CONFIG_SOC_PM_SUPPORT_MODEM_PD=y +CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED=y +CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY=y +CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL=y +CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA=y +CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED=y +CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256=y +CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION=y +CONFIG_SOC_CLK_XTAL32K_SUPPORTED=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE=y +CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE=y +CONFIG_SOC_EFUSE_HARD_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_USB_JTAG=y +CONFIG_SOC_EFUSE_SOFT_DIS_JTAG=y +CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT=y +CONFIG_SOC_EFUSE_DIS_ICACHE=y +CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK=y +CONFIG_SOC_SECURE_BOOT_V2_RSA=y +CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS=3 +CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS=y +CONFIG_SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY=y +CONFIG_SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX=64 +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128=y +CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256=y +CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE=16 +CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE=256 +CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE=21 +CONFIG_SOC_MAC_BB_PD_MEM_SIZE=192 +CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH=12 +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME=y +CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND=y +CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE=y +CONFIG_SOC_SPI_MEM_SUPPORT_TIME_TUNING=y +CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE=y +CONFIG_SOC_SPI_MEM_SUPPORT_WRAP=y +CONFIG_SOC_COEX_HW_PTI=y +CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE=y +CONFIG_SOC_SDMMC_USE_GPIO_MATRIX=y +CONFIG_SOC_SDMMC_NUM_SLOTS=2 +CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK=y +CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC=y +CONFIG_SOC_WIFI_HW_TSF=y +CONFIG_SOC_WIFI_FTM_SUPPORT=y +CONFIG_SOC_WIFI_GCMP_SUPPORT=y +CONFIG_SOC_WIFI_WAPI_SUPPORT=y +CONFIG_SOC_WIFI_CSI_SUPPORT=y +CONFIG_SOC_WIFI_MESH_SUPPORT=y +CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW=y +CONFIG_SOC_BLE_SUPPORTED=y +CONFIG_SOC_BLE_MESH_SUPPORTED=y +CONFIG_SOC_BLE_50_SUPPORTED=y +CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED=y +CONFIG_SOC_BLUFI_SUPPORTED=y +CONFIG_SOC_ULP_HAS_ADC=y +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_XTENSA=y +CONFIG_IDF_TARGET_ARCH="xtensa" +CONFIG_IDF_TARGET="esp32s3" +CONFIG_IDF_TARGET_ESP32S3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0009 + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# CONFIG_APP_REPRODUCIBLE_BUILD is not set +# CONFIG_APP_NO_BLOBS is not set +# end of Build type + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x0 +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_INFO is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE=y +CONFIG_BOOTLOADER_LOG_LEVEL=5 +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE=y +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT=y +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_V2_RSA_SUPPORTED=y +CONFIG_SECURE_BOOT_V2_PREFERRED=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +CONFIG_SECURE_ROM_DL_MODE_ENABLED=y +# end of Security features + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +CONFIG_ESP_ROM_HAS_CRC_LE=y +CONFIG_ESP_ROM_HAS_CRC_BE=y +CONFIG_ESP_ROM_HAS_MZ_CRC32=y +CONFIG_ESP_ROM_HAS_JPEG_DECODE=y +CONFIG_ESP_ROM_UART_CLK_IS_XTAL=y +CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING=y +CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM=4 +CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG=y +CONFIG_ESP_ROM_GET_CLK_FREQ=y +CONFIG_ESP_ROM_HAS_HAL_WDT=y +CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND=y +CONFIG_ESP_ROM_HAS_LAYOUT_TABLE=y +CONFIG_ESP_ROM_HAS_SPI_FLASH=y +CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG=y +CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT=y +CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE=y +CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT=y +CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG=y +CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG=y + +# +# Boot ROM Behavior +# +CONFIG_BOOT_ROM_LOG_ALWAYS_ON=y +# CONFIG_BOOT_ROM_LOG_ALWAYS_OFF is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_HIGH is not set +# CONFIG_BOOT_ROM_LOG_ON_GPIO_LOW is not set +# end of Boot ROM Behavior + +# +# Serial flasher config +# +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_OCT_FLASH is not set +CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT=y +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_120M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT=y +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_8MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_32MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_64MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_128MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="8MB" +# CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE is not set +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +CONFIG_ESPTOOLPY_MONITOR_BAUD=115200 +# end of Serial flasher config + +# +# Partition Table +# +# CONFIG_PARTITION_TABLE_SINGLE_APP is not set +# CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE is not set +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="ptables/esp32_8m-ptable.csv" +CONFIG_PARTITION_TABLE_FILENAME="ptables/esp32_8m-ptable.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set +# CONFIG_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_COMPILER_OPTIMIZATION_NONE is not set +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set +CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set +CONFIG_COMPILER_HIDE_PATHS_MACROS=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC12_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_JTAG is not set +CONFIG_APPTRACE_DEST_NONE=y +# CONFIG_APPTRACE_DEST_UART0 is not set +# CONFIG_APPTRACE_DEST_UART1 is not set +# CONFIG_APPTRACE_DEST_UART2 is not set +# CONFIG_APPTRACE_DEST_USB_CDC is not set +CONFIG_APPTRACE_DEST_UART_NONE=y +CONFIG_APPTRACE_UART_TASK_PRIO=1 +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# Bluetooth +# +# CONFIG_BT_ENABLED is not set +# end of Bluetooth + +# +# Driver Configurations +# + +# +# Legacy ADC Configuration +# +# CONFIG_ADC_SUPPRESS_DEPRECATE_WARN is not set + +# +# Legacy ADC Calibration Configuration +# +# CONFIG_ADC_CALI_SUPPRESS_DEPRECATE_WARN is not set +# end of Legacy ADC Calibration Configuration +# end of Legacy ADC Configuration + +# +# SPI Configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI Configuration + +# +# TWAI Configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +CONFIG_TWAI_ERRATA_FIX_LISTEN_ONLY_DOM=y +# end of TWAI Configuration + +# +# Temperature sensor Configuration +# +# CONFIG_TEMP_SENSOR_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG is not set +# end of Temperature sensor Configuration + +# +# UART Configuration +# +# CONFIG_UART_ISR_IN_IRAM is not set +# end of UART Configuration + +# +# GPIO Configuration +# +# CONFIG_GPIO_CTRL_FUNC_IN_IRAM is not set +# end of GPIO Configuration + +# +# Sigma Delta Modulator Configuration +# +# CONFIG_SDM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_SDM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_SDM_ENABLE_DEBUG_LOG is not set +# end of Sigma Delta Modulator Configuration + +# +# GPTimer Configuration +# +# CONFIG_GPTIMER_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GPTIMER_ISR_IRAM_SAFE is not set +# CONFIG_GPTIMER_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_GPTIMER_ENABLE_DEBUG_LOG is not set +# end of GPTimer Configuration + +# +# PCNT Configuration +# +# CONFIG_PCNT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_PCNT_ISR_IRAM_SAFE is not set +# CONFIG_PCNT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_PCNT_ENABLE_DEBUG_LOG is not set +# end of PCNT Configuration + +# +# RMT Configuration +# +# CONFIG_RMT_ISR_IRAM_SAFE is not set +# CONFIG_RMT_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_RMT_ENABLE_DEBUG_LOG is not set +# end of RMT Configuration + +# +# MCPWM Configuration +# +# CONFIG_MCPWM_ISR_IRAM_SAFE is not set +# CONFIG_MCPWM_CTRL_FUNC_IN_IRAM is not set +# CONFIG_MCPWM_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_MCPWM_ENABLE_DEBUG_LOG is not set +# end of MCPWM Configuration + +# +# I2S Configuration +# +# CONFIG_I2S_ISR_IRAM_SAFE is not set +# CONFIG_I2S_SUPPRESS_DEPRECATE_WARN is not set +# CONFIG_I2S_ENABLE_DEBUG_LOG is not set +# end of I2S Configuration + +# +# USB Serial/JTAG Configuration +# +# end of USB Serial/JTAG Configuration +# end of Driver Configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + +# +# ADC and ADC Calibration +# +# CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM is not set +# CONFIG_ADC_CONTINUOUS_ISR_IRAM_SAFE is not set +# CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3 is not set +# end of ADC and ADC Calibration + +# +# Wireless Coexistence +# +# CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE is not set +# end of Wireless Coexistence + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +# end of Common ESP-related + +# +# Ethernet +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_SPI_ETHERNET=y +# CONFIG_ETH_SPI_ETHERNET_DM9051 is not set +# CONFIG_ETH_SPI_ETHERNET_W5500 is not set +# CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL is not set +# CONFIG_ETH_USE_OPENETH is not set +# CONFIG_ETH_TRANSMIT_MUTEX is not set +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH=y +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# CONFIG_HTTPD_QUEUE_WORK_BLOCKING is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_ESP_HTTPS_OTA_DECRYPT_CB is not set +# CONFIG_ESP_HTTPS_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# Hardware Settings +# + +# +# Chip revision +# +CONFIG_ESP32S3_REV_MIN_0=y +# CONFIG_ESP32S3_REV_MIN_1 is not set +# CONFIG_ESP32S3_REV_MIN_2 is not set +CONFIG_ESP32S3_REV_MIN_FULL=0 +CONFIG_ESP_REV_MIN_FULL=0 + +# +# Maximum Supported ESP32-S3 Revision (Rev v0.99) +# +CONFIG_ESP32S3_REV_MAX_FULL=99 +CONFIG_ESP_REV_MAX_FULL=99 +# end of Chip revision + +# +# MAC Config +# +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_BT=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH=y +CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR=y +# CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO is not set +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR=y +CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES=4 +# end of MAC Config + +# +# Sleep Config +# +CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND=y +CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND=y +# CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU is not set +CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND=y +# CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set +CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY=2000 +# end of Sleep Config + +# +# RTC Clock Config +# +CONFIG_RTC_CLK_SRC_INT_RC=y +# CONFIG_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_RTC_CLK_CAL_CYCLES=1024 +# end of RTC Clock Config + +# +# Peripheral Control +# +CONFIG_PERIPH_CTRL_FUNC_IN_IRAM=y +# end of Peripheral Control + +# +# GDMA Configuration +# +# CONFIG_GDMA_CTRL_FUNC_IN_IRAM is not set +# CONFIG_GDMA_ISR_IRAM_SAFE is not set +# end of GDMA Configuration + +# +# Main XTAL Config +# +CONFIG_XTAL_FREQ_40=y +CONFIG_XTAL_FREQ=40 +# end of Main XTAL Config +# end of Hardware Settings + +# +# LCD and Touch Panel +# + +# +# LCD Touch Drivers are maintained in the IDF Component Registry +# + +# +# LCD Peripheral Configuration +# +CONFIG_LCD_PANEL_IO_FORMAT_BUF_SIZE=32 +# CONFIG_LCD_ENABLE_DEBUG_LOG is not set +# CONFIG_LCD_RGB_ISR_IRAM_SAFE is not set +# CONFIG_LCD_RGB_RESTART_IN_VSYNC is not set +# end of LCD Peripheral Configuration +# end of LCD and Touch Panel + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +CONFIG_ESP_NETIF_USES_TCPIP_WITH_BSD_API=y +# CONFIG_ESP_NETIF_RECEIVE_REPORT_ERRORS is not set +# CONFIG_ESP_NETIF_L2_TAP is not set +# CONFIG_ESP_NETIF_BRIDGE_EN is not set +# end of ESP NETIF Adapter + +# +# Partition API Configuration +# +# end of Partition API Configuration + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# CONFIG_ESP_PHY_REDUCE_TX_POWER is not set +CONFIG_ESP_PHY_ENABLE_USB=y +# CONFIG_ESP_PHY_ENABLE_CERT_TEST is not set +CONFIG_ESP_PHY_RF_CAL_PARTIAL=y +# CONFIG_ESP_PHY_RF_CAL_NONE is not set +# CONFIG_ESP_PHY_RF_CAL_FULL is not set +CONFIG_ESP_PHY_CALIBRATION_MODE=0 +# end of PHY + +# +# Power Management +# +# CONFIG_PM_ENABLE is not set +CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y +CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP=y +# end of Power Management + +# +# ESP PSRAM +# +CONFIG_SPIRAM=y + +# +# SPI RAM config +# +CONFIG_SPIRAM_MODE_QUAD=y +# CONFIG_SPIRAM_MODE_OCT is not set +CONFIG_SPIRAM_TYPE_AUTO=y +# CONFIG_SPIRAM_TYPE_ESPPSRAM16 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set +# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set +CONFIG_SPIRAM_CLK_IO=30 +CONFIG_SPIRAM_CS_IO=26 +# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set +# CONFIG_SPIRAM_RODATA is not set +# CONFIG_SPIRAM_SPEED_120M is not set +# CONFIG_SPIRAM_SPEED_80M is not set +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_SPEED=40 +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +# CONFIG_SPIRAM_USE_MEMMAP is not set +# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set +# end of SPI RAM config +# end of ESP PSRAM + +# +# ESP Ringbuf +# +# CONFIG_RINGBUF_PLACE_FUNCTIONS_INTO_FLASH is not set +# end of ESP Ringbuf + +# +# ESP System Settings +# +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y +# CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 is not set +CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160 + +# +# Cache config +# +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +# CONFIG_ESP32S3_INSTRUCTION_CACHE_32KB is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE=0x4000 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_4WAYS is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS=y +CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE=32 +# CONFIG_ESP32S3_DATA_CACHE_16KB is not set +CONFIG_ESP32S3_DATA_CACHE_32KB=y +# CONFIG_ESP32S3_DATA_CACHE_64KB is not set +CONFIG_ESP32S3_DATA_CACHE_SIZE=0x8000 +# CONFIG_ESP32S3_DATA_CACHE_4WAYS is not set +CONFIG_ESP32S3_DATA_CACHE_8WAYS=y +CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS=8 +# CONFIG_ESP32S3_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S3_DATA_CACHE_LINE_64B is not set +CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE=32 +# end of Cache config + +# +# Memory +# +# CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE is not set +# end of Memory + +# +# Trace memory +# +# CONFIG_ESP32S3_TRAX is not set +CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM=0x0 +# end of Trace memory + +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +# CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME is not set +CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS=0 +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection + +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y +# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set +# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_ESP_MAIN_TASK_AFFINITY=0x0 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +# CONFIG_ESP_CONSOLE_UART_DEFAULT is not set +# CONFIG_ESP_CONSOLE_USB_CDC is not set +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_NONE=y +CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=-1 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +CONFIG_ESP_INT_WDT_CHECK_CPU1=y +CONFIG_ESP_TASK_WDT_EN=y +CONFIG_ESP_TASK_WDT_INIT=y +# CONFIG_ESP_TASK_WDT_PANIC is not set +CONFIG_ESP_TASK_WDT_TIMEOUT_S=5 +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +# CONFIG_ESP_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP_DEBUG_OCDAWARE=y +CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4=y + +# +# Brownout Detector +# +CONFIG_ESP_BROWNOUT_DET=y +CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP_BROWNOUT_DET_LVL=7 +# end of Brownout Detector + +CONFIG_ESP_SYSTEM_BROWNOUT_INTR=y +# end of ESP System Settings + +# +# IPC (Inter-Processor Call) +# +CONFIG_ESP_IPC_TASK_STACK_SIZE=1536 +CONFIG_ESP_IPC_USES_CALLERS_PRIORITY=y +CONFIG_ESP_IPC_ISR_ENABLE=y +# end of IPC (Inter-Processor Call) + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_INTERRUPT_LEVEL=1 +# CONFIG_ESP_TIMER_SHOW_EXPERIMENTAL is not set +CONFIG_ESP_TIMER_TASK_AFFINITY=0x0 +CONFIG_ESP_TIMER_TASK_AFFINITY_CPU0=y +CONFIG_ESP_TIMER_ISR_AFFINITY=0x1 +CONFIG_ESP_TIMER_ISR_AFFINITY_CPU0=y +# CONFIG_ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD is not set +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP_WIFI_ENABLED=y +CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM=32 +# CONFIG_ESP_WIFI_CSI_ENABLED is not set +CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP_WIFI_TX_BA_WIN=6 +CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP_WIFI_RX_BA_WIN=6 +# CONFIG_ESP_WIFI_AMSDU_TX_ENABLED is not set +CONFIG_ESP_WIFI_NVS_ENABLED=y +CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP_WIFI_IRAM_OPT=y +CONFIG_ESP_WIFI_RX_IRAM_OPT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP_WIFI_ENABLE_SAE_PK=y +CONFIG_ESP_WIFI_SOFTAP_SAE_SUPPORT=y +CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# CONFIG_ESP_WIFI_GCMP_SUPPORT is not set +# CONFIG_ESP_WIFI_GMAC_SUPPORT is not set +CONFIG_ESP_WIFI_SOFTAP_SUPPORT=y +# CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT is not set +CONFIG_ESP_WIFI_ESPNOW_MAX_ENCRYPT_NUM=7 +CONFIG_ESP_WIFI_MBEDTLS_CRYPTO=y +CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT=y +# CONFIG_ESP_WIFI_WAPI_PSK is not set +# CONFIG_ESP_WIFI_SUITE_B_192 is not set +# CONFIG_ESP_WIFI_11KV_SUPPORT is not set +# CONFIG_ESP_WIFI_MBO_SUPPORT is not set +# CONFIG_ESP_WIFI_DPP_SUPPORT is not set +# CONFIG_ESP_WIFI_11R_SUPPORT is not set +# CONFIG_ESP_WIFI_WPS_SOFTAP_REGISTRAR is not set + +# +# WPS Configuration Options +# +# CONFIG_ESP_WIFI_WPS_STRICT is not set +# CONFIG_ESP_WIFI_WPS_PASSPHRASE is not set +# end of WPS Configuration Options + +# CONFIG_ESP_WIFI_DEBUG_PRINT is not set +# CONFIG_ESP_WIFI_TESTING_OPTIONS is not set +# end of Wi-Fi + +# +# Core dump +# +CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH=y +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_NONE is not set +# CONFIG_ESP_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP_COREDUMP_CHECK_BOOT=y +CONFIG_ESP_COREDUMP_ENABLE=y +CONFIG_ESP_COREDUMP_LOGS=y +CONFIG_ESP_COREDUMP_MAX_TASKS_NUM=64 +CONFIG_ESP_COREDUMP_STACK_SIZE=0 +# end of Core dump + +# +# FAT Filesystem support +# +CONFIG_FATFS_VOLUME_COUNT=2 +# CONFIG_FATFS_LFN_NONE is not set +# CONFIG_FATFS_LFN_HEAP is not set +CONFIG_FATFS_LFN_STACK=y +# CONFIG_FATFS_SECTOR_512 is not set +CONFIG_FATFS_SECTOR_4096=y +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_MAX_LFN=63 +CONFIG_FATFS_API_ENCODING_ANSI_OEM=y +# CONFIG_FATFS_API_ENCODING_UTF_8 is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y +# CONFIG_FATFS_USE_FASTSEEK is not set +CONFIG_FATFS_VFS_FSTAT_BLKSIZE=0 +# end of FAT Filesystem support + +# +# FreeRTOS +# + +# +# Kernel +# +# CONFIG_FREERTOS_SMP is not set +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_HZ=100 +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +# CONFIG_FREERTOS_USE_IDLE_HOOK is not set +# CONFIG_FREERTOS_USE_TICK_HOOK is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_FREERTOS_ENABLE_BACKWARD_COMPATIBILITY is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=1 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES=1 +CONFIG_FREERTOS_USE_TRACE_FACILITY=y +CONFIG_FREERTOS_USE_STATS_FORMATTING_FUNCTIONS=y +CONFIG_FREERTOS_VTASKLIST_INCLUDE_COREID=y +CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS=y +# end of Kernel + +# +# Port +# +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +CONFIG_FREERTOS_ISR_STACKSIZE=2096 +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER=y +CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1=y +# CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3 is not set +CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER=y +CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER=y +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +# CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH is not set +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_FREERTOS_ENABLE_TASK_SNAPSHOT=y +# end of Port + +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Hardware Abstraction Layer (HAL) and Low Level (LL) +# +CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y +# CONFIG_HAL_ASSERTION_DISABLE is not set +# CONFIG_HAL_ASSERTION_SILENT is not set +# CONFIG_HAL_ASSERTION_ENABLE is not set +CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2 +CONFIG_HAL_WDT_USE_ROM_IMPL=y +CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y +CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y +# end of Hardware Abstraction Layer (HAL) and Low Level (LL) + +# +# Heap memory debugging +# +# CONFIG_HEAP_POISONING_DISABLED is not set +# CONFIG_HEAP_POISONING_LIGHT is not set +CONFIG_HEAP_POISONING_COMPREHENSIVE=y +# CONFIG_HEAP_TRACING_OFF is not set +CONFIG_HEAP_TRACING_STANDALONE=y +# CONFIG_HEAP_TRACING_TOHOST is not set +CONFIG_HEAP_TRACING=y +CONFIG_HEAP_TRACING_STACK_DEPTH=2 +# CONFIG_HEAP_USE_HOOKS is not set +CONFIG_HEAP_TASK_TRACKING=y +# CONFIG_HEAP_TRACE_HASH_MAP is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH is not set +# end of Heap memory debugging + +CONFIG_IEEE802154_CCA_THRESHOLD=-60 +CONFIG_IEEE802154_PENDING_TABLE_SIZE=20 + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y +# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set +# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set +CONFIG_LOG_MAXIMUM_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="espressif" +# CONFIG_LWIP_NETIF_API is not set +CONFIG_LWIP_TCPIP_CORE_LOCKING=y +# CONFIG_LWIP_CHECK_THREAD_SAFETY is not set +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +# CONFIG_LWIP_SO_LINGER is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_ESP_MLDV6_REPORT=y +CONFIG_LWIP_MLDV6_TMR_INTERVAL=40 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=68 +CONFIG_LWIP_NUM_NETIF_CLIENT_DATA=0 +CONFIG_LWIP_DHCP_COARSE_TIMER_SECS=1 + +# +# DHCP server +# +CONFIG_LWIP_DHCPS=y +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_IPV4=y +CONFIG_LWIP_IPV6=y +CONFIG_LWIP_IPV6_AUTOCONFIG=y +CONFIG_LWIP_IPV6_NUM_ADDRESSES=3 +# CONFIG_LWIP_IPV6_FORWARD is not set +CONFIG_LWIP_IPV6_RDNSS_MAX_DNS_SERVERS=0 +# CONFIG_LWIP_IPV6_DHCP6 is not set +# CONFIG_LWIP_NETIF_STATUS_CALLBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_FIN_WAIT_TIMEOUT=20000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_SNTP_MAX_SERVERS=1 +# CONFIG_LWIP_DHCP_GET_NTP_SRV is not set +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_BRIDGEIF_MAX_PORTS=7 +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_ND6_GET_GW_NONE=y +# CONFIG_LWIP_HOOK_ND6_GET_GW_DEFAULT is not set +# CONFIG_LWIP_HOOK_ND6_GET_GW_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_NONE=y +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_INPUT_NONE=y +# CONFIG_LWIP_HOOK_IP6_INPUT_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_INPUT_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC is not set +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +# CONFIG_MBEDTLS_DYNAMIC_BUFFER is not set +# CONFIG_MBEDTLS_DEBUG is not set + +# +# mbedTLS v3.x related +# +# CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 is not set +# CONFIG_MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH is not set +# CONFIG_MBEDTLS_X509_TRUSTED_CERT_CALLBACK is not set +# CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION is not set +CONFIG_MBEDTLS_SSL_KEEP_PEER_CERTIFICATE=y +CONFIG_MBEDTLS_PKCS7_C=y +# end of mbedTLS v3.x related + +# +# Certificate Bundle +# +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE=y +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS=200 +# end of Certificate Bundle + +# CONFIG_MBEDTLS_ECP_RESTARTABLE is not set +# CONFIG_MBEDTLS_CMAC_C is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_MPI_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_PLATFORM_TIME_ALT is not set +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_GMTSSL1_1 is not set +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C is not set + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +# CONFIG_MBEDTLS_DHM_C is not set +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +# CONFIG_MQTT_PROTOCOL_5 is not set +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y +# CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_HRT is not set +# CONFIG_NEWLIB_TIME_SYSCALL_USE_NONE is not set +# end of Newlib + +# +# NVS +# +# CONFIG_NVS_ASSERT_ERROR_CHECK is not set +# end of NVS + +# +# OpenThread +# +# CONFIG_OPENTHREAD_ENABLED is not set + +# +# Thread Operational Dataset +# +CONFIG_OPENTHREAD_NETWORK_NAME="OpenThread-ESP" +CONFIG_OPENTHREAD_NETWORK_CHANNEL=15 +CONFIG_OPENTHREAD_NETWORK_PANID=0x1234 +CONFIG_OPENTHREAD_NETWORK_EXTPANID="dead00beef00cafe" +CONFIG_OPENTHREAD_NETWORK_MASTERKEY="00112233445566778899aabbccddeeff" +CONFIG_OPENTHREAD_NETWORK_PSKC="104810e2315100afd6bc9215a6bfac53" +# end of Thread Operational Dataset +# end of OpenThread + +# +# Protocomm +# +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_0=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_1=y +CONFIG_ESP_PROTOCOMM_SUPPORT_SECURITY_VERSION_2=y +# end of Protocomm + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_DEFAULT_CORE_NO_AFFINITY=y +# CONFIG_PTHREAD_DEFAULT_CORE_0 is not set +# CONFIG_PTHREAD_DEFAULT_CORE_1 is not set +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# MMU Config +# +CONFIG_MMU_PAGE_SIZE_64KB=y +CONFIG_MMU_PAGE_MODE="64KB" +CONFIG_MMU_PAGE_SIZE=0x10000 +# end of MMU Config + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +# CONFIG_SPI_FLASH_ROM_IMPL is not set +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set +# CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST is not set + +# +# SPI Flash behavior when brownout +# +CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC=y +CONFIG_SPI_FLASH_BROWNOUT_RESET=y +# end of SPI Flash behavior when brownout + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_VENDOR_XMC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_GD_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_ISSI_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_MXIC_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_WINBOND_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_BOYA_SUPPORTED=y +CONFIG_SPI_FLASH_VENDOR_TH_SUPPORTED=y +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_TH_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# CONFIG_WS_DYNAMIC_BUFFER is not set +# end of Websocket +# end of TCP Transport + +# +# Ultra Low Power (ULP) Co-processor +# +# CONFIG_ULP_COPROC_ENABLED is not set +# end of Ultra Low Power (ULP) Co-processor + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_64BIT is not set +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# USB-OTG +# +CONFIG_USB_OTG_SUPPORTED=y +CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE=256 +CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED=y +# CONFIG_USB_HOST_HW_BUFFER_BIAS_IN is not set +# CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT is not set + +# +# Root Hub configuration +# +CONFIG_USB_HOST_DEBOUNCE_DELAY_MS=250 +CONFIG_USB_HOST_RESET_HOLD_MS=30 +CONFIG_USB_HOST_RESET_RECOVERY_MS=30 +CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS=10 +# end of Root Hub configuration +# end of USB-OTG + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y +CONFIG_VFS_MAX_COUNT=8 + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION=y +CONFIG_WIFI_PROV_STA_ALL_CHANNEL_SCAN=y +# CONFIG_WIFI_PROV_STA_FAST_SCAN is not set +# end of Wi-Fi Provisioning Manager + +# +# Atrium +# +CONFIG_WFC_TARGET="esp32" + +# +# software services +# +CONFIG_CONSOLE_UART_TX=0 +CONFIG_CONSOLE_UART_RX=0 +CONFIG_UART_CONSOLE=y +CONFIG_HWCONF_DYNAMIC=y +CONFIG_LUA=y +CONFIG_THRESHOLDS=y +CONFIG_INTEGRATED_HELP=y +CONFIG_AT_ACTIONS=y +CONFIG_HOLIDAYS=y +CONFIG_TERMSERV=y +CONFIG_STATEMACHINES=y +# CONFIG_APP_PARAMS is not set +# end of software services + +# +# networking services +# +CONFIG_OTA=y +CONFIG_UDNS=y +CONFIG_MQTT=y +CONFIG_HTTP=y +CONFIG_FTP=y +CONFIG_TELNET=y +CONFIG_SYSLOG=y +CONFIG_INFLUX=y +CONFIG_UDPCTRL=y +CONFIG_WPS=y +CONFIG_SMARTCONFIG=y +# end of networking services + +# +# filesystem support +# +CONFIG_FATFS=y +CONFIG_ROMFS=y +CONFIG_ROMFS_VFS=y +CONFIG_ROMFS_VFS_NUMFDS=4 +CONFIG_USB_HOST_FS=y +# end of filesystem support + +# +# hardware support +# +CONFIG_USB_DIAGLOG=y +CONFIG_USB_CONSOLE=y +CONFIG_GPIOS=y +CONFIG_CORETEMP=y +CONFIG_IOEXTENDERS=y +CONFIG_LEDS=y +CONFIG_BUTTON=y +CONFIG_ROTARYENCODER=y +CONFIG_RELAY=y +CONFIG_ONEWIRE=y +CONFIG_DISPLAY=y +CONFIG_MAX7219=y +CONFIG_HT16K33=y +CONFIG_SSD1306=y +CONFIG_SH1106=y +CONFIG_DHT=y +# CONFIG_HLW8012 is not set +CONFIG_I2C=y +CONFIG_I2C_XCMD=y +CONFIG_I2C_XDEV=y +CONFIG_PCA9685=y +CONFIG_PCF8574=y +CONFIG_TCA9555=y +CONFIG_MCP2300X=y +CONFIG_MCP2301X=y +CONFIG_OPT3001=y +CONFIG_INA2XX=y +CONFIG_SI7021=y +CONFIG_BMX280=y +CONFIG_BMP388=y +CONFIG_BME680=y +CONFIG_HDC1000=y +CONFIG_APDS9930=y +CONFIG_SGP30=y +CONFIG_CCS811B=y +CONFIG_BH1750=y +CONFIG_SPI=y +CONFIG_SX1276=y +CONFIG_SSD1309=y +CONFIG_ILI9341=y +CONFIG_SDCARD=y +CONFIG_XPT2046=y +CONFIG_HCSR04=y +CONFIG_DIMMER=y +CONFIG_RGBLEDS=y +CONFIG_TLC5947=y +# end of hardware support + +# +# development tools and experimental/alpha drivers (disable all) +# +CONFIG_DEVEL=y +CONFIG_VERIFY_HEAP=y +CONFIG_FUNCTION_TIMING=y +# end of development tools and experimental/alpha drivers (disable all) +# end of Atrium +# end of Component config + +# CONFIG_IDF_EXPERIMENTAL_FEATURES is not set + +# Deprecated options for backward compatibility +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_INFO is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE=y +CONFIG_LOG_BOOTLOADER_LEVEL=5 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_MONITOR_BAUD=115200 +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2 +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_MCPWM_ISR_IN_IRAM is not set +# CONFIG_EXTERNAL_COEX_ENABLE is not set +# CONFIG_ESP_WIFI_EXTERNAL_COEXIST_ENABLE is not set +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_POST_EVENTS_FROM_ISR=y +CONFIG_POST_EVENTS_FROM_IRAM_ISR=y +# CONFIG_OTA_ALLOW_HTTP is not set +CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_REDUCE_PHY_TX_POWER is not set +# CONFIG_ESP32_REDUCE_PHY_TX_POWER is not set +CONFIG_ESP_SYSTEM_PM_POWER_DOWN_CPU=y +CONFIG_ESP32S3_SPIRAM_SUPPORT=y +CONFIG_DEFAULT_PSRAM_CLK_IO=30 +CONFIG_DEFAULT_PSRAM_CS_IO=26 +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32S3_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +# CONFIG_CONSOLE_UART_DEFAULT is not set +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +# CONFIG_ESP_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=-1 +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +CONFIG_ESP_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S3_DEBUG_OCDAWARE=y +CONFIG_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_ESP32S3_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_7=y +CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S3_BROWNOUT_DET_LVL=7 +CONFIG_IPC_TASK_STACK_SIZE=1536 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP32_WIFI_ENABLED=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +# CONFIG_ESP32_WIFI_AMSDU_TX_ENABLED is not set +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_OWE_STA=y +CONFIG_WPA_MBEDTLS_CRYPTO=y +CONFIG_WPA_MBEDTLS_TLS_CLIENT=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_SUITE_B_192 is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# CONFIG_WPA_MBO_SUPPORT is not set +# CONFIG_WPA_DPP_SUPPORT is not set +# CONFIG_WPA_11R_SUPPORT is not set +# CONFIG_WPA_WPS_SOFTAP_REGISTRAR is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH=y +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE is not set +# CONFIG_ESP32_COREDUMP_DATA_FORMAT_BIN is not set +CONFIG_ESP32_COREDUMP_DATA_FORMAT_ELF=y +CONFIG_ESP32_COREDUMP_CHECKSUM_CRC32=y +CONFIG_ESP32_ENABLE_COREDUMP=y +CONFIG_ESP32_CORE_DUMP_MAX_TASKS_NUM=64 +CONFIG_ESP32_CORE_DUMP_STACK_SIZE=0 +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +# CONFIG_HAL_ASSERTION_SILIENT is not set +# CONFIG_L2_TO_L3_COPY is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=12 +CONFIG_TCP_MSS=1440 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_ESP32_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +CONFIG_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +# End of deprecated options diff --git a/projects/esp32_4m b/projects/esp32_4m index fa9cdee..fb56f28 100644 --- a/projects/esp32_4m +++ b/projects/esp32_4m @@ -1600,7 +1600,7 @@ CONFIG_AT_ACTIONS=y CONFIG_HOLIDAYS=y CONFIG_TERMSERV=y CONFIG_STATEMACHINES=y -CONFIG_APP_PARAMS=y +# CONFIG_APP_PARAMS is not set # end of software services # @@ -1632,7 +1632,6 @@ CONFIG_ROMFS_VFS_NUMFDS=4 # hardware support # CONFIG_GPIOS=y -# CONFIG_CORETEMP is not set CONFIG_IOEXTENDERS=y CONFIG_LEDS=y CONFIG_BUTTON=y @@ -1644,17 +1643,17 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +# CONFIG_SH1106 is not set CONFIG_DHT=y -# CONFIG_HLW8012 is not set CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y CONFIG_PCA9685=y CONFIG_PCF8574=y -# CONFIG_TCA9555 is not set -# CONFIG_MCP2300X is not set -# CONFIG_MCP2301X is not set -# CONFIG_OPT3001 is not set +CONFIG_TCA9555=y +CONFIG_MCP2300X=y +CONFIG_MCP2301X=y +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y @@ -1665,8 +1664,6 @@ CONFIG_SGP30=y CONFIG_CCS811B=y CONFIG_BH1750=y CONFIG_SPI=y -CONFIG_SX1276=y -CONFIG_SSD1309=y CONFIG_ILI9341=y CONFIG_SDCARD=y CONFIG_XPT2046=y @@ -1680,7 +1677,7 @@ CONFIG_TLC5947=y # # development tools and experimental/alpha drivers (disable all) # -CONFIG_DEVEL=y +# CONFIG_DEVEL is not set # CONFIG_VERIFY_HEAP is not set CONFIG_FUNCTION_TIMING=y # end of development tools and experimental/alpha drivers (disable all) diff --git a/projects/esp32_8m_full b/projects/esp32_8m_full index a7b42e1..33124ac 100644 --- a/projects/esp32_8m_full +++ b/projects/esp32_8m_full @@ -1750,6 +1750,7 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +# CONFIG_SH1106 is not set CONFIG_DHT=y CONFIG_HLW8012=y CONFIG_I2C=y @@ -1764,6 +1765,7 @@ CONFIG_MCP2301X=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y +# CONFIG_BMP388 is not set CONFIG_BME680=y CONFIG_HDC1000=y CONFIG_APDS9930=y diff --git a/projects/esp8266_2m b/projects/esp8266_2m index 5d21de3..7ec5bb2 100644 --- a/projects/esp8266_2m +++ b/projects/esp8266_2m @@ -289,6 +289,7 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +# CONFIG_SH1106 is not set CONFIG_DHT=y CONFIG_I2C=y CONFIG_I2C_XCMD=y @@ -298,6 +299,7 @@ CONFIG_PCF8574=y # CONFIG_TCA9555 is not set CONFIG_MCP2300X=y CONFIG_MCP2301X=y +# CONFIG_OPT3001 is not set CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y diff --git a/projects/esp8266_4m b/projects/esp8266_4m index b8f427e..48bcc7c 100644 --- a/projects/esp8266_4m +++ b/projects/esp8266_4m @@ -262,7 +262,7 @@ CONFIG_AT_ACTIONS=y CONFIG_HOLIDAYS=y CONFIG_TERMSERV=y CONFIG_STATEMACHINES=y -CONFIG_APP_PARAMS=y +# CONFIG_APP_PARAMS is not set CONFIG_OTA=y CONFIG_UDNS=y CONFIG_MQTT=y @@ -289,15 +289,17 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +CONFIG_SH1106=y CONFIG_DHT=y CONFIG_I2C=y CONFIG_I2C_XCMD=y CONFIG_I2C_XDEV=y CONFIG_PCA9685=y CONFIG_PCF8574=y -# CONFIG_TCA9555 is not set +CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y +CONFIG_OPT3001=y CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y diff --git a/projects/esp8266_4m_full b/projects/esp8266_4m_full index 63c7f32..1582e4e 100644 --- a/projects/esp8266_4m_full +++ b/projects/esp8266_4m_full @@ -289,6 +289,7 @@ CONFIG_DISPLAY=y CONFIG_MAX7219=y CONFIG_HT16K33=y CONFIG_SSD1306=y +# CONFIG_SH1106 is not set CONFIG_DHT=y CONFIG_I2C=y CONFIG_I2C_XCMD=y @@ -298,6 +299,7 @@ CONFIG_PCF8574=y CONFIG_TCA9555=y CONFIG_MCP2300X=y CONFIG_MCP2301X=y +# CONFIG_OPT3001 is not set CONFIG_INA2XX=y CONFIG_SI7021=y CONFIG_BMX280=y diff --git a/projects/esp8266_4m_min b/projects/esp8266_4m_min index c3d0c7a..2ce27ed 100644 --- a/projects/esp8266_4m_min +++ b/projects/esp8266_4m_min @@ -121,10 +121,10 @@ CONFIG_ESP_PANIC_PRINT_REBOOT=y CONFIG_MAIN_TASK_STACK_SIZE=3584 CONFIG_TASK_WDT=y CONFIG_TASK_WDT_PANIC=y -CONFIG_TASK_WDT_TIMEOUT_13N=y +# CONFIG_TASK_WDT_TIMEOUT_13N is not set # CONFIG_TASK_WDT_TIMEOUT_14N is not set -# CONFIG_TASK_WDT_TIMEOUT_15N is not set -CONFIG_TASK_WDT_TIMEOUT_S=13 +CONFIG_TASK_WDT_TIMEOUT_15N=y +CONFIG_TASK_WDT_TIMEOUT_S=15 CONFIG_RESET_REASON=y CONFIG_WIFI_PPT_TASKSTACK_SIZE=2048 CONFIG_EVENT_LOOP_STACK_SIZE=2048 @@ -187,7 +187,7 @@ CONFIG_LOG_DEFAULT_LEVEL_WARN=y CONFIG_LOG_DEFAULT_LEVEL=2 CONFIG_LOG_COLORS=y # CONFIG_LOG_SET_LEVEL is not set -CONFIG_LWIP_USE_IRAM=y +# CONFIG_LWIP_USE_IRAM is not set # CONFIG_LWIP_HIGH_THROUGHPUT is not set CONFIG_LWIP_GLOBAL_DATA_LINK_IRAM=y # CONFIG_ESP_LWIP_RECV_REST_DATA is not set @@ -206,15 +206,15 @@ CONFIG_LWIP_SO_REUSE_RXTOALL=y # CONFIG_LWIP_SO_RCVBUF is not set CONFIG_LWIP_RECV_BUFSIZE_DEFAULT=11680 CONFIG_LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT=10000 -CONFIG_LWIP_IP_FRAG=y -CONFIG_LWIP_IP_REASSEMBLY=y +# CONFIG_LWIP_IP_FRAG is not set +# CONFIG_LWIP_IP_REASSEMBLY is not set CONFIG_LWIP_IP_REASS_MAX_PBUFS=10 -CONFIG_LWIP_IP_SOF_BROADCAST=y -CONFIG_LWIP_IP_SOF_BROADCAST_RECV=y +# CONFIG_LWIP_IP_SOF_BROADCAST is not set +# CONFIG_LWIP_IP_SOF_BROADCAST_RECV is not set CONFIG_LWIP_ICMP=y # CONFIG_LWIP_MULTICAST_PING is not set # CONFIG_LWIP_BROADCAST_PING is not set -CONFIG_LWIP_RAW=y +# CONFIG_LWIP_RAW is not set CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 CONFIG_LWIP_DHCPS_LEASE_UNIT=60 @@ -222,9 +222,9 @@ CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 CONFIG_LWIP_DHCP_DISCOVER_RETRANSMISSION_INTERVAL=250 # CONFIG_LWIP_ESP_DHCP_OPTION is not set # CONFIG_LWIP_AUTOIP is not set -# CONFIG_LWIP_IGMP is not set -# CONFIG_ESP_DNS is not set -CONFIG_DNS_MAX_SERVERS=2 +CONFIG_LWIP_IGMP=y +CONFIG_ESP_DNS=y +CONFIG_DNS_MAX_SERVERS=3 CONFIG_LWIP_NETIF_LOOPBACK=y CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 # CONFIG_TCP_HIGH_SPEED_RETRANSMISSION is not set @@ -269,7 +269,6 @@ CONFIG_WFC_TARGET="esp8266" # CONFIG_UDPCTRL is not set # CONFIG_WPS is not set # CONFIG_SMARTCONFIG is not set -# CONFIG_SPIFFS is not set # CONFIG_ROMFS is not set # CONFIG_GPIOS is not set # CONFIG_IOEXTENDERS is not set @@ -282,6 +281,7 @@ CONFIG_WFC_TARGET="esp8266" CONFIG_I2C=y # CONFIG_I2C_XCMD is not set # CONFIG_I2C_XDEV is not set +# CONFIG_OPT3001 is not set # CONFIG_BMX280 is not set # CONFIG_BME680 is not set # CONFIG_HDC1000 is not set @@ -377,26 +377,7 @@ CONFIG_NEWLIB_LIBRARY_LEVEL_FLOAT_NANO=y CONFIG_OPENSSL_ASSERT_DO_NOTHING=y # CONFIG_OPENSSL_ASSERT_EXIT is not set # CONFIG_ENABLE_PTHREAD is not set -CONFIG_USING_SPIFFS=y -CONFIG_SPIFFS_MAX_PARTITIONS=3 -CONFIG_SPIFFS_CACHE=y -CONFIG_SPIFFS_CACHE_WR=y -# CONFIG_SPIFFS_CACHE_STATS is not set -CONFIG_SPIFFS_PAGE_CHECK=y -CONFIG_SPIFFS_GC_MAX_RUNS=10 -# CONFIG_SPIFFS_GC_STATS is not set -CONFIG_SPIFFS_PAGE_SIZE=256 -CONFIG_SPIFFS_OBJ_NAME_LEN=32 -CONFIG_SPIFFS_USE_MAGIC=y -CONFIG_SPIFFS_USE_MAGIC_LENGTH=y -CONFIG_SPIFFS_META_LENGTH=4 -CONFIG_SPIFFS_USE_MTIME=y -# CONFIG_SPIFFS_DBG is not set -# CONFIG_SPIFFS_API_DBG is not set -# CONFIG_SPIFFS_GC_DBG is not set -# CONFIG_SPIFFS_CACHE_DBG is not set -# CONFIG_SPIFFS_CHECK_DBG is not set -# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# CONFIG_USING_SPIFFS is not set CONFIG_IP_LOST_TIMER_INTERVAL=120 CONFIG_TCPIP_ADAPTER_GLOBAL_DATA_LINK_IRAM=y # CONFIG_util_assert is not set @@ -404,9 +385,7 @@ CONFIG_ESP_SHA=y CONFIG_ESP_AES=y CONFIG_ESP_MD5=y CONFIG_ESP_ARC4=y -CONFIG_USING_ESP_VFS=y -CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y -CONFIG_SUPPORT_TERMIOS=y +# CONFIG_USING_ESP_VFS is not set # CONFIG_ENABLE_UNIFIED_PROVISIONING is not set CONFIG_LTM_FAST=y diff --git a/projects/esp8285 b/projects/esp8285 index 24b1b77..d3e8b4b 100644 --- a/projects/esp8285 +++ b/projects/esp8285 @@ -281,6 +281,7 @@ CONFIG_RELAY=y CONFIG_I2C=y # CONFIG_I2C_XCMD is not set # CONFIG_I2C_XDEV is not set +# CONFIG_OPT3001 is not set CONFIG_BMX280=y # CONFIG_BME680 is not set # CONFIG_HDC1000 is not set diff --git a/tools/atriumcfg.cpp b/tools/atriumcfg.cpp index dbcbdff..32c5bfa 100644 --- a/tools/atriumcfg.cpp +++ b/tools/atriumcfg.cpp @@ -996,7 +996,7 @@ int set_idf(const char *path) } char tmp[l+32]; memcpy(tmp,path,l); - strcpy(tmp[l-1] == '/' ? tmp+l-1 : tmp+l,"/components/esp32"); + strcpy(tmp[l-1] == '/' ? tmp+l-1 : tmp+l,"/components/esp_system"); ESP32 = (0 == isDir(tmp)); if (ESP32) { printf("ESP32 IDF\n");