Z80 CTCDART and Z80 DUALPIO almost ready to go

[lynchaj]

Hi,
Getting ready to send Z80 CTCDART and Z80 DUALPIO to PCB manufacturing. I've gone over them and I think they are ready. If anyone has an opportunity to review the designs before placing an order please look in these directories for the technical data

https://github.com/lynchaj/nhyodyne/tree/main/Z80CTCDART1

https://github.com/lynchaj/nhyodyne/tree/main/Z80DUALPIO1

Thanks and have a great day, Andrew Lynch

[lynchaj]

Hi
I have a question regarding Z80 CTCDART board. I have a bunch of Zilog IO chips in my collection and am planning to use them first. However I thought I remembered a CMOS version of DART but when I go to find such a thing they are nowhere to be found -- only the older NMOS ICs. There is a CMOS version of SIO/0 which for the Z80 CTCDART board is nearly pin-for-pin compatible and a drop in replacement for DART.

So are people planning on using SIO/0 instead of DART? Just using CMOS instead of NMOS will reduce power consumption by like an order of magnitude so definitely worth considering? What chip are you going to use on Z80 CTCDART? SIO/0 or DART?

I was planning on DART but if there is a CMOS version of SIO/0 then I am reconsidering. Would like to hear your thoughts of subject.

Thanks, Andrew Lynch

[wwarthen]

Honestly, I have never actually used a DART, always the SIO. I didn't remember why, but it may have been because there was no CMOS variant available. I already have SIOs in stock and that is what I am planning to use for the CTCDART build.

Thanks,

Wayne

[lynchaj]

Hi,
Last weekend I received the Z80 CTCDART V2 and Z80 DUALPIO V2 PCBs. I built and tested each board and they seem to work fine individually. However there seems to be a glitch in the IO port decoder/data_dir design so both boards do not share a common 16 byte IO address space as intended. I have a fairly minor fix planned and will try it this weekend. It is important that the patch be on both boards since they both share a common design. Hopefully that works and I'll post the results. If you'd like to go ahead and use the gerber files to obtain PCBs they are ready to go.

Thanks, Andrew Lynch

[lynchaj]

Hi
I made the patch fix and tested it on my Z80 CTCDART V2 and Z80 DUALPIO V2. It works just as intended and is a pretty easy patch to make. No trace cuts and just one jumper on copper side and another on the component side. Works great!

I placed the CTCDART at $B0-$B7 and DUALPIO at $B8-$BF and they seem to coexist peaceably. TIMER/C runs no problem as does 2PIOTST generates the right responses. No more annoying interference between the two boards.

The patch is the same for both boards:

U17, pin 2 (74LS138) to U5, pin 13 (74LS14); jumper on copper side
U5, pin 12 (74LS14) to U1A, pin 5 (74LS20); lift pins & jumper on component side

The board is close enough now for some extended testing to shake out any other possible bugs. I will definitely fix these problems in the next PCB respin.

Thanks, Andrew Lynch

[lynchaj]

Hi
More testing on Z80 CTCDART V2 and found another glitch but there is an easy fix. The DCDB pin needs to be grounded for the serial port channel B to receive data. Just add a short jumper between DCDB U9, pin 22 (DART or SIO) and Ground U9, pin 31 on the copper side of the PCB.

Serial port channel B transmits data just fine but due to a peculiar initialization of the DART or SIO pins DCDB has to be grounded for it to receive data. This change will be added to the upcoming PCB respin for Z80 CTCDART V3 when it comes out.

If you have any questions or comments please reply to this thread

Thanks, Andrew Lynch