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<!DOCTYPE html SYSTEM "about:legacy-compat">
<html lang="en-US" data-preset="contrast" data-primary-color="#6860F6" data-link-color="#307FFF" data-resizable-sidebar="true" data-sidebar-width="260"><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"><meta charset="UTF-8"><meta name="built-on" content="2024-12-10T15:14:05.5745668"><title>RISC-Ⅴ Architecture | Computer Science Study Notes</title><script type="application/json" id="virtual-toc-data">[{"id":"6-introduction-to-assembly-language-riscv","level":0,"title":"6 Introduction to Assembly Language","anchor":"#6-introduction-to-assembly-language-riscv"},{"id":"6-1-assembly-language-riscv","level":1,"title":"6.1 Assembly Language","anchor":"#6-1-assembly-language-riscv"},{"id":"6-2-registers-riscv","level":1,"title":"6.2 Registers","anchor":"#6-2-registers-riscv"},{"id":"6-3-riscv-instructions-riscv","level":1,"title":"6.3 RISC-Ⅴ Instructions","anchor":"#6-3-riscv-instructions-riscv"},{"id":"6-3-1-basic-arithmetic-instructions","level":2,"title":"6.3.1 Basic Arithmetic Instructions","anchor":"#6-3-1-basic-arithmetic-instructions"},{"id":"6-3-2-immediate-instructions","level":2,"title":"6.3.2 Immediate Instructions","anchor":"#6-3-2-immediate-instructions"},{"id":"6-3-3-data-transfer-instructions","level":2,"title":"6.3.3 Data Transfer Instructions","anchor":"#6-3-3-data-transfer-instructions"},{"id":"6-3-4-control-flow-instructions","level":2,"title":"6.3.4 Control Flow Instructions","anchor":"#6-3-4-control-flow-instructions"},{"id":"6-3-5-shifting-instructions","level":2,"title":"6.3.5 Shifting Instructions","anchor":"#6-3-5-shifting-instructions"},{"id":"6-4-c-assembly-machine-code-riscv","level":1,"title":"6.4 C, Assembly \u0026 Machine Code","anchor":"#6-4-c-assembly-machine-code-riscv"}]</script><script type="application/json" id="topic-shortcuts"></script><link href="https://resources.jetbrains.com/writerside/apidoc/6.10.0-b518/app.css" rel="stylesheet"><link href="static/custom.css" rel="stylesheet"><link rel="icon" type="image/png" sizes="16x16" href="Computer-Science-Study-Notes/photo.png"><meta name="image" content=""><!-- Open Graph --><meta property="og:title" content="RISC-Ⅴ Architecture | Computer Science Study Notes"><meta property="og:description" content=""><meta property="og:image" content=""><meta property="og:site_name" content="Computer Science Study Notes Help"><meta property="og:type" content="website"><meta property="og:locale" content="en_US"><meta property="og:url" content="writerside-documentation/computer-architecture-risc-v.html"><!-- End Open Graph --><!-- Twitter Card --><meta name="twitter:card" content="summary_large_image"><meta name="twitter:site" content=""><meta name="twitter:title" content="RISC-Ⅴ Architecture | Computer Science Study Notes"><meta name="twitter:description" content=""><meta name="twitter:creator" content=""><meta name="twitter:image:src" content=""><!-- End Twitter Card --><!-- Schema.org WebPage --><script type="application/ld+json">{
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}</script><!-- End Schema.org --></head><body data-id="Computer-Architecture-RISC-V" data-main-title="RISC-Ⅴ Architecture" data-article-props="{"seeAlsoStyle":"links"}" data-template="article" data-breadcrumbs="Computer-Architecture.topic|Computer Architecture"><div class="wrapper"><main class="panel _main"><header class="panel__header"><div class="container"><h3>Computer Science Study Notes Help</h3><div class="panel-trigger"></div></div></header><section class="panel__content"><div class="container"><article class="article" data-shortcut-switcher="inactive"><h1 data-toc="Computer-Architecture-RISC-V" id="Computer-Architecture-RISC-V.topic">RISC-Ⅴ Architecture</h1><section class="chapter"><h2 id="6-introduction-to-assembly-language-riscv" data-toc="6-introduction-to-assembly-language-riscv">6 Introduction to Assembly Language</h2><section class="chapter"><h3 id="6-1-assembly-language-riscv" data-toc="6-1-assembly-language-riscv">6.1 Assembly Language</h3><p id="z3katyp_9"><span id="z3katyp_18"><font style="color:#ff8c00">Assembly (also known as Assembly language, ASM):</font></span> A low-level programming language where the program instructions match a particular architecture's operations.</p><p id="z3katyp_10"><span id="z3katyp_19"><font style="color:#ff8c00">Architecture:</font></span> (also ISA: instruction set architecture) The parts of a processor design that one needs to understand for writing assembly/machine code.</p><p id="z3katyp_11"><span id="z3katyp_20"><font style="color:#8a2be2">Properties:</font></span></p><ul class="list _bullet" id="z3katyp_12"><li class="list__item" id="z3katyp_21"><p id="z3katyp_24">Splits a program into many small instructions that each do one single part of the process.</p></li><li class="list__item" id="z3katyp_22"><p id="z3katyp_25">Each architecture will have a different set of operations that it supports (although there are similarities).</p></li><li class="list__item" id="z3katyp_23"><p id="z3katyp_26">Assembly is not <span id="z3katyp_27"><i>portable</i></span> to other architectures.</p></li></ul><p id="z3katyp_13"><span id="z3katyp_28"><font style="color:#8a2be2">Complex/Reduced Instruction Set Computing</font></span></p><ol class="list _alpha-lower" id="z3katyp_14" type="a"><li class="list__item" id="z3katyp_29"><p id="z3katyp_31"><span id="z3katyp_33"><font style="color:#ff00ff">Complex Instruction Set Computing (CISC)</font></span></p><ul class="list _bullet" id="z3katyp_32"><li class="list__item" id="z3katyp_34"><p id="z3katyp_37">Difficult to learn and comprehend language.</p></li><li class="list__item" id="z3katyp_35"><p id="z3katyp_38">Less work for the compiler.</p></li><li class="list__item" id="z3katyp_36"><p id="z3katyp_39">Complicated hardware runs more slowly.</p></li></ul></li><li class="list__item" id="z3katyp_30"><p id="z3katyp_40"><span id="z3katyp_42"><font style="color:#ff00ff">Reduced Instruction Set Computing (RISC)</font></span></p><ul class="list _bullet" id="z3katyp_41"><li class="list__item" id="z3katyp_43"><p id="z3katyp_45">Simple (and smaller) instruction set makes it easier to build fast hardware.</p></li><li class="list__item" id="z3katyp_44"><p id="z3katyp_46">Let software do the complicated operations by composing simpler ones.</p></li></ul></li></ol><p id="z3katyp_15"><span id="z3katyp_47"><font style="color:#8a2be2">Code:</font></span></p><div class="code-block" data-lang="armasm">
op dst, src1, src2
</div><ul class="list _bullet" id="z3katyp_17"><li class="list__item" id="z3katyp_48"><p id="z3katyp_52"><code class="code" id="z3katyp_53">op</code>: operation name ("operator")</p></li><li class="list__item" id="z3katyp_49"><p id="z3katyp_54"><code class="code" id="z3katyp_55">dst</code>: register getting result ("destination")</p></li><li class="list__item" id="z3katyp_50"><p id="z3katyp_56"><code class="code" id="z3katyp_57">src1</code>: first register for operation ("source 1")</p></li><li class="list__item" id="z3katyp_51"><p id="z3katyp_58"><code class="code" id="z3katyp_59">src2</code>: second register for operation ("source 2")</p></li></ul></section><section class="chapter"><h3 id="6-2-registers-riscv" data-toc="6-2-registers-riscv">6.2 Registers</h3><p id="z3katyp_60">Assembly uses registers to store values. Registers are:</p><ul class="list _bullet" id="z3katyp_61"><li class="list__item" id="z3katyp_65"><p id="z3katyp_68">Small memories of a fixed size (in RV64, it is 64-bit wide).</p></li><li class="list__item" id="z3katyp_66"><p id="z3katyp_69">Can be read or written.</p></li><li class="list__item" id="z3katyp_67"><p id="z3katyp_70">Limited in number (in RV64, there are 32 registers), but very fast and low power to access.</p></li></ul><div class="table-wrapper"><table class="left_header wide" id="z3katyp_62"><thead><tr class="ijRowHead" id="z3katyp_71"><th id="z3katyp_75"></th><th id="z3katyp_76"><p>Registers</p></th><th id="z3katyp_77"><p>Memory</p></th></tr></thead><tbody><tr id="z3katyp_72"><th id="z3katyp_78"><p>Speed</p></th><td id="z3katyp_79"><p>Fast</p></td><td id="z3katyp_80"><p>Slow</p></td></tr><tr id="z3katyp_73"><th id="z3katyp_81"><p>Size</p></th><td id="z3katyp_82"><p id="z3katyp_84">Small</p><p id="z3katyp_85">e.g., 32 registers * 32 bit = 128 bytes</p></td><td id="z3katyp_83"><p id="z3katyp_86">Big</p><p id="z3katyp_87">4-32 GB</p></td></tr><tr id="z3katyp_74"><th id="z3katyp_88"><p>Connection</p></th><td id="z3katyp_89" colspan="2"><p id="z3katyp_90">More variables than registers?</p><p id="z3katyp_91">Keep most frequently used in registers and move the rest to memory</p></td></tr></tbody></table></div><figure id="z3katyp_63"><img alt="Registers" src="Computer-Science-Study-Notes/a6-2-1.png" title="Registers" width="2207" height="1307"></figure><aside class="prompt" data-type="warning" data-title="" id="z3katyp_64"><p id="z3katyp_92">Some important notes about registers:</p><ul class="list _bullet" id="z3katyp_93"><li class="list__item" id="z3katyp_94"><p id="z3katyp_98">Each ISA has a predetermined number of registers, registers are built in with hardware.</p></li><li class="list__item" id="z3katyp_95"><p id="z3katyp_99">Register denoted by 'x' can be referenced by number (x0 - x31) or by name (s0 - s11, t0 - t6).</p><div class="table-wrapper"><table class="wide" id="z3katyp_100"><thead><tr class="ijRowHead" id="z3katyp_101"><th id="z3katyp_113"><p>Number</p></th><th id="z3katyp_114"><p>Name</p></th><th id="z3katyp_115"><p>Function</p></th></tr></thead><tbody><tr id="z3katyp_102"><td id="z3katyp_116"><p>x0</p></td><td id="z3katyp_117"><p>zero</p></td><td id="z3katyp_118"><p>Always holds the value 0. Writing to it has no effect.</p></td></tr><tr id="z3katyp_103"><td id="z3katyp_119"><p>x1</p></td><td id="z3katyp_120"><p>ra</p></td><td id="z3katyp_121"><p><span id="z3katyp_122"><font style="color:#ff4500">Return Address</font></span>, used to store the return address when calling a subroutine or function.</p></td></tr><tr id="z3katyp_104"><td id="z3katyp_123"><p>x2</p></td><td id="z3katyp_124"><p>sp</p></td><td id="z3katyp_125"><p><span id="z3katyp_126"><font style="color:#ff4500">Stack Pointer</font></span>, points to the top of the stack.</p></td></tr><tr id="z3katyp_105"><td id="z3katyp_127"><p>x3</p></td><td id="z3katyp_128"><p>gp</p></td><td id="z3katyp_129"><p><span id="z3katyp_130"><font style="color:#ff4500">Global Pointer</font></span>, points to the global data area.</p></td></tr><tr id="z3katyp_106"><td id="z3katyp_131"><p>x4</p></td><td id="z3katyp_132"><p>tp</p></td><td id="z3katyp_133"><p><span id="z3katyp_134"><font style="color:#ff4500">Thread Pointer</font></span>, points to the thread-local storage.</p></td></tr><tr id="z3katyp_107"><td id="z3katyp_135"><p>x5 - x7</p></td><td id="z3katyp_136"><p>t0 - t2</p></td><td id="z3katyp_137"><p>Temporary/Caller-saved.</p></td></tr><tr id="z3katyp_108"><td id="z3katyp_138"><p>x8 - x9</p></td><td id="z3katyp_139"><p>s0/fp - s1</p></td><td id="z3katyp_140"><p><span id="z3katyp_141"><font style="color:#ff4500">Saved registers</font></span>, x8 is also used for frame pointer.</p></td></tr><tr id="z3katyp_109"><td id="z3katyp_142"><p>x10 - x11</p></td><td id="z3katyp_143"><p>a0 - a1</p></td><td id="z3katyp_144"><p><span id="z3katyp_145"><font style="color:#ff4500">Function arguments/Return values</font></span></p></td></tr><tr id="z3katyp_110"><td id="z3katyp_146"><p>x12 - x17</p></td><td id="z3katyp_147"><p>a2 - a7</p></td><td id="z3katyp_148"><p><span id="z3katyp_149"><font style="color:#ff4500">Function arguments</font></span></p></td></tr><tr id="z3katyp_111"><td id="z3katyp_150"><p>x18 - x27</p></td><td id="z3katyp_151"><p>s2 - s11</p></td><td id="z3katyp_152"><p><span id="z3katyp_153"><font style="color:#ff4500">Saved registers/Callee-Saved</font></span></p></td></tr><tr id="z3katyp_112"><td id="z3katyp_154"><p>x28 - x31</p></td><td id="z3katyp_155"><p>t3 - t6</p></td><td id="z3katyp_156"><p>Temporary/Caller-saved.</p></td></tr></tbody></table></div></li><li class="list__item" id="z3katyp_96"><p id="z3katyp_157">Registers have no type!</p></li><li class="list__item" id="z3katyp_97"><p id="z3katyp_158">In high-level languages, number of variables limited only by available memory.</p></li></ul></aside></section><section class="chapter"><h3 id="6-3-riscv-instructions-riscv" data-toc="6-3-riscv-instructions-riscv">6.3 RISC-Ⅴ Instructions</h3><p id="z3katyp_160">In high-level languages, variable types determine operation.</p><p id="z3katyp_161">In assembly, operation determines type, i.e., how register contents are treated.</p><p id="z3katyp_162"><span id="z3katyp_168"><font style="color:#8a2be2">Operations</font></span></p><section class="chapter"><h4 id="6-3-1-basic-arithmetic-instructions" data-toc="6-3-1-basic-arithmetic-instructions">6.3.1 Basic Arithmetic Instructions</h4><p id="z3katyp_169"><span id="z3katyp_172"><font style="color:#cd5c5c">Examples</font></span> (Assuming here that the variables <code class="code" id="z3katyp_173">a</code>, <code class="code" id="z3katyp_174">b</code> and <code class="code" id="z3katyp_175">c</code> are assigned to registers <code class="code" id="z3katyp_176">s1</code>, <code class="code" id="z3katyp_177">s2</code> and <code class="code" id="z3katyp_178">s3</code>, respectively)</p><ul class="list _bullet" id="z3katyp_170"><li class="list__item" id="z3katyp_179"><p id="z3katyp_181"><span id="z3katyp_183"><font style="color:#ff00ff">Integer Addition</font></span></p><div class="code-comparer" id="z3katyp_182" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
a = b + c;
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
add s1, s2, s3
</div></div></li><li class="list__item" id="z3katyp_180"><p id="z3katyp_186"><span id="z3katyp_188"><font style="color:#ff00ff">Integer Subtraction</font></span></p><div class="code-comparer" id="z3katyp_187" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
a = b - c;
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
sub s1, s2, s3
</div></div></li></ul><aside class="prompt" data-type="note" data-title="" id="z3katyp_171"><p id="z3katyp_191"><code class="code" id="z3katyp_193">add:</code> Perform addition.</p><p id="z3katyp_192"><code class="code" id="z3katyp_194">addw:</code> Addition with lower 32 bits of their values, then the result is sign-extended to 64 bits in the destination register.</p></aside></section><section class="chapter"><h4 id="6-3-2-immediate-instructions" data-toc="6-3-2-immediate-instructions">6.3.2 Immediate Instructions</h4><p id="z3katyp_195"><span id="z3katyp_202"><font style="color:#ff8c00">Immediates:</font></span> Numerical constants.</p><p id="z3katyp_196"><span id="z3katyp_203"><font style="color:#8a2be2">Syntax:</font></span></p><div class="code-block" data-lang="armasm">
opi dst, src, imm
</div><ul class="list _bullet" id="z3katyp_198"><li class="list__item" id="z3katyp_204"><p id="z3katyp_206">Operation names end with "i", replace <mjx-container class="MathJax" jax="SVG"><svg style="vertical-align: 0;" xmlns="http://www.w3.org/2000/svg" width="3.098ex" height="1.932ex" role="img" focusable="false" viewBox="0 -853.7 1369.3 853.7"><g stroke="currentColor" fill="currentColor" stroke-width="0" transform="scale(1,-1)"><g data-mml-node="math"><g data-mml-node="msup"><g data-mml-node="mn"><path data-c="32" d="M109 429Q82 429 66 447T50 491Q50 562 103 614T235 666Q326 666 387 610T449 465Q449 422 429 383T381 315T301 241Q265 210 201 149L142 93L218 92Q375 92 385 97Q392 99 409 186V189H449V186Q448 183 436 95T421 3V0H50V19V31Q50 38 56 46T86 81Q115 113 136 137Q145 147 170 174T204 211T233 244T261 278T284 308T305 340T320 369T333 401T340 431T343 464Q343 527 309 573T212 619Q179 619 154 602T119 569T109 550Q109 549 114 549Q132 549 151 535T170 489Q170 464 154 447T109 429Z"></path></g><g data-mml-node="TeXAtom" transform="translate(533,363) scale(0.707)" data-mjx-texclass="ORD"><g data-mml-node="mtext"><path data-c="6E" d="M41 46H55Q94 46 102 60V68Q102 77 102 91T102 122T103 161T103 203Q103 234 103 269T102 328V351Q99 370 88 376T43 385H25V408Q25 431 27 431L37 432Q47 433 65 434T102 436Q119 437 138 438T167 441T178 442H181V402Q181 364 182 364T187 369T199 384T218 402T247 421T285 437Q305 442 336 442Q450 438 463 329Q464 322 464 190V104Q464 66 466 59T477 49Q498 46 526 46H542V0H534L510 1Q487 2 460 2T422 3Q319 3 310 0H302V46H318Q379 46 379 62Q380 64 380 200Q379 335 378 343Q372 371 358 385T334 402T308 404Q263 404 229 370Q202 343 195 315T187 232V168V108Q187 78 188 68T191 55T200 49Q221 46 249 46H265V0H257L234 1Q210 2 183 2T145 3Q42 3 33 0H25V46H41Z"></path><path data-c="64" d="M376 495Q376 511 376 535T377 568Q377 613 367 624T316 637H298V660Q298 683 300 683L310 684Q320 685 339 686T376 688Q393 689 413 690T443 693T454 694H457V390Q457 84 458 81Q461 61 472 55T517 46H535V0Q533 0 459 -5T380 -11H373V44L365 37Q307 -11 235 -11Q158 -11 96 50T34 215Q34 315 97 378T244 442Q319 442 376 393V495ZM373 342Q328 405 260 405Q211 405 173 369Q146 341 139 305T131 211Q131 155 138 120T173 59Q203 26 251 26Q322 26 373 103V342Z" transform="translate(556,0)"></path></g></g></g></g></g></svg></mjx-container>source register with an immeidate.</p></li><li class="list__item" id="z3katyp_205"><p id="z3katyp_208">Immediates can up to 12 bits in size (-2048 to 2047, inclusive), and will be sign-extended to 64 bits before adding.</p></li></ul><p id="z3katyp_199"><span id="z3katyp_209"><font style="color:#cd5c5c">Example</font></span></p><div class="code-comparer" id="z3katyp_200" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
a = b - 10;
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
addi s1, s2, -10
</div></div><aside class="prompt" data-type="warning" data-title="" id="z3katyp_201"><p id="z3katyp_212">No <code class="code" id="z3katyp_213">subi</code> instruction, since RISC-Ⅴ is all about reducing # of instructions.</p></aside></section><section class="chapter"><h4 id="6-3-3-data-transfer-instructions" data-toc="6-3-3-data-transfer-instructions">6.3.3 Data Transfer Instructions</h4><p id="z3katyp_214">Specialized <span id="z3katyp_222"><font style="color:#ff4500">data transfer instructions</font></span> move data between registers and memory.</p><ul class="list _bullet" id="z3katyp_215"><li class="list__item" id="z3katyp_223"><p id="z3katyp_225"><span id="z3katyp_226"><font style="color:#ff00ff">Store:</font></span> register to memory</p></li><li class="list__item" id="z3katyp_224"><p id="z3katyp_227"><span id="z3katyp_228"><font style="color:#ff00ff">Load:</font></span> register FROM memory</p></li></ul><p id="z3katyp_216"><span id="z3katyp_229"><font style="color:#8a2be2">Syntax:</font></span></p><div class="code-block" data-lang="armasm">
memop reg, off (bAbbr)
</div><ul class="list _bullet" id="z3katyp_218"><li class="list__item" id="z3katyp_230"><p id="z3katyp_234"><code class="code" id="z3katyp_235">memop</code>: operation name (<code class="code" id="z3katyp_236">lw</code>, <code class="code" id="z3katyp_237">sw</code>, ...)</p></li><li class="list__item" id="z3katyp_231"><p id="z3katyp_238"><code class="code" id="z3katyp_239">reg</code>: Register for operation source or destination.</p></li><li class="list__item" id="z3katyp_232"><p id="z3katyp_240"><code class="code" id="z3katyp_241">bAbbr</code>: Register with pointer to memory ("base address")</p></li><li class="list__item" id="z3katyp_233"><p id="z3katyp_242"><code class="code" id="z3katyp_243">off</code>: Address offset (immediate) in bytes ("offset")</p></li></ul><p id="z3katyp_219"><span id="z3katyp_244"><font style="color:#cd5c5c">Example</font></span></p><ul class="list _bullet" id="z3katyp_220"><li class="list__item" id="z3katyp_245"><p id="z3katyp_247"><span id="z3katyp_249"><font style="color:#ff00ff">Load Doubleword</font></span></p><div class="code-comparer" id="z3katyp_248" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
a = array[3];
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
ld s1, 24(s2)
</div></div></li><li class="list__item" id="z3katyp_246"><p id="z3katyp_252"><span id="z3katyp_254"><font style="color:#ff00ff">Store Doubleword</font></span></p><div class="code-comparer" id="z3katyp_253" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
array[10] = 3;
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
sd s1, 80(s2)
</div></div></li></ul><aside class="prompt" data-type="note" data-title="" id="z3katyp_221"><p id="z3katyp_257">Other operations include <code class="code" id="z3katyp_258">lw</code> for load word (32 bits), <code class="code" id="z3katyp_259">lb</code> for load byte (8 bits), <code class="code" id="z3katyp_260">lbu</code> for load byte unsigned, <code class="code" id="z3katyp_261">lh</code> for load halfword (16 bits), <code class="code" id="z3katyp_262">lhu</code> for load halfword unsigned, <code class="code" id="z3katyp_263">sw</code> for store word, <code class="code" id="z3katyp_264">sb</code> for store byte, and <code class="code" id="z3katyp_265">sh</code> for store halfword.</p></aside></section><section class="chapter"><h4 id="6-3-4-control-flow-instructions" data-toc="6-3-4-control-flow-instructions">6.3.4 Control Flow Instructions</h4><p id="z3katyp_266"><span id="z3katyp_271"><font style="color:#ff8c00">Labels in RISC-Ⅴ:</font></span> Defined by a text and followed by a colon (e.g., main:) and refers to the instructions that follows; generate control flow by jumping to labels.</p><p id="z3katyp_267"><span id="z3katyp_272"><font style="color:#cd5c5c">Examples</font></span></p><ul class="list _bullet" id="z3katyp_268"><li class="list__item" id="z3katyp_273"><p id="z3katyp_280"><span id="z3katyp_281"><font style="color:#ff00ff">Jump</font></span></p></li><li class="list__item" id="z3katyp_274"><p id="z3katyp_282"><span id="z3katyp_284"><font style="color:#ff00ff">Branch If Equal</font></span></p><div class="code-comparer" id="z3katyp_283" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
if (i == j) {
a = b; /* then */
} else {
a = -b; /* else */
}
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
beq s0, s1, then
else:
sub s2, x0, s3
j end
then:
add s2, s3, x0
end:
</div></div></li><li class="list__item" id="z3katyp_275"><p id="z3katyp_287"><span id="z3katyp_289"><font style="color:#ff00ff">Branch If Not Equal</font></span></p><div class="code-comparer" id="z3katyp_288" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
if (i != j) {
a = b; /* then */
} else {
a = -b; /* else */
}
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
bne s0, s1, then
else:
sub s2, x0, s3
j end
then:
add s2, s3, x0
end:
</div></div></li><li class="list__item" id="z3katyp_276"><p id="z3katyp_292"><span id="z3katyp_294"><font style="color:#ff00ff">Branch Less Than</font></span></p><div class="code-comparer" id="z3katyp_293" data-comparing="vertically"><div class="code-block" data-lang="c" data-title="C">
if (i < j) {
a = b; /* then */
} else {
a = -b; /* else */
}
</div><div class="code-block" data-lang="armasm" data-title="RISC-V">
blt s0, s1, then
else:
sub s2, x0, s3
j end
then:
add s2, s3, x0
end:
</div></div></li><li class="list__item" id="z3katyp_277"><p id="z3katyp_297"><span id="z3katyp_298"><font style="color:#ff00ff">Branch Greater Than or Equal</font></span> (<code class="code" id="z3katyp_299">bge</code>)</p></li><li class="list__item" id="z3katyp_278"><p id="z3katyp_300"><span id="z3katyp_301"><font style="color:#ff00ff">Branch Less Than Unsigned</font></span> (<code class="code" id="z3katyp_302">bltu</code>, treat registers as unsigned integers)</p></li><li class="list__item" id="z3katyp_279"><p id="z3katyp_303"><span id="z3katyp_304"><font style="color:#ff00ff">Branch Greater Than or Equal Unsigned</font></span> (<code class="code" id="z3katyp_305">bgeu</code>)</p></li></ul><p id="z3katyp_269"><span id="z3katyp_306"><font style="color:#8a2be2">Program Counter:</font></span></p><ul class="list _bullet" id="z3katyp_270"><li class="list__item" id="z3katyp_307"><p id="z3katyp_310">Program Counter (PC): A special register that contains the current address of the code that is being executed, and not accessible as a part of 32 registers.</p></li><li class="list__item" id="z3katyp_308"><p id="z3katyp_311">Branches and Jumps change the flow of execution by modifying the PC.</p></li><li class="list__item" id="z3katyp_309"><p id="z3katyp_312">Instructions are stored as data in memory (code section) and have addresses! Labels get converted to instruction addresses.</p></li></ul></section><section class="chapter"><h4 id="6-3-5-shifting-instructions" data-toc="6-3-5-shifting-instructions">6.3.5 Shifting Instructions</h4><p id="z3katyp_313"><span id="z3katyp_316"><font style="color:#8a2be2">Instructions Table</font></span></p><div class="table-wrapper"><table class="wide" id="z3katyp_314"><thead><tr class="ijRowHead" id="z3katyp_317"><th id="z3katyp_327"><p>Logical Operations</p></th><th id="z3katyp_328"><p>C Operators</p></th><th id="z3katyp_329"><p>RISC-V Operators</p></th></tr></thead><tbody><tr id="z3katyp_318"><td id="z3katyp_330"><p>Bit-by-bit AND</p></td><td id="z3katyp_331"><p>&</p></td><td id="z3katyp_332"><p><code class="code" id="z3katyp_333">and</code></p></td></tr><tr id="z3katyp_319"><td id="z3katyp_334"><p>Bit-by-bit OR</p></td><td id="z3katyp_335"><p>|</p></td><td id="z3katyp_336"><p><code class="code" id="z3katyp_337">or</code></p></td></tr><tr id="z3katyp_320"><td id="z3katyp_338"><p>Bit-by-bit XOR</p></td><td id="z3katyp_339"><p>^</p></td><td id="z3katyp_340"><p><code class="code" id="z3katyp_341">xor</code></p></td></tr><tr id="z3katyp_321"><td id="z3katyp_342"><p>Shift Left Logical</p></td><td id="z3katyp_343"><p><<</p></td><td id="z3katyp_344"><p><code class="code" id="z3katyp_345">sll</code></p></td></tr><tr id="z3katyp_322"><td id="z3katyp_346"><p>Shift Left Logical Imm</p></td><td id="z3katyp_347"><p><<</p></td><td id="z3katyp_348"><p><code class="code" id="z3katyp_349">sll1</code></p></td></tr><tr id="z3katyp_323"><td id="z3katyp_350"><p>Shift Right Logical</p></td><td id="z3katyp_351"><p>>></p></td><td id="z3katyp_352"><p><code class="code" id="z3katyp_353">srl</code></p></td></tr><tr id="z3katyp_324"><td id="z3katyp_354"><p>Shift Right Logical Imm</p></td><td id="z3katyp_355"><p>>></p></td><td id="z3katyp_356"><p><code class="code" id="z3katyp_357">srli</code></p></td></tr><tr id="z3katyp_325"><td id="z3katyp_358"><p>Shift Right Arithmetic</p></td><td id="z3katyp_359"><p>>></p></td><td id="z3katyp_360"><p><code class="code" id="z3katyp_361">sra</code></p></td></tr><tr id="z3katyp_326"><td id="z3katyp_362"><p>Shift Right Arithmetic Imm</p></td><td id="z3katyp_363"><p>>></p></td><td id="z3katyp_364"><p><code class="code" id="z3katyp_365">srai</code></p></td></tr></tbody></table></div><aside class="prompt" data-type="note" data-title="" id="z3katyp_315"><p id="z3katyp_366">For a 64-bit RISC-Ⅴ system,</p><ul class="list _bullet" id="z3katyp_367"><li class="list__item" id="z3katyp_368"><p id="z3katyp_370">When using immediate, only values 0-63 are practical.</p></li><li class="list__item" id="z3katyp_369"><p id="z3katyp_371">When using variable, only lowest 6 bits are used.</p></li></ul></aside></section></section><section class="chapter"><h3 id="6-4-c-assembly-machine-code-riscv" data-toc="6-4-c-assembly-machine-code-riscv">6.4 C, Assembly & Machine Code</h3><p id="z3katyp_372">Compile with the following code (debugging-friendly):</p><div class="code-block" data-lang="none">
gcc –Og p1.c -o p
</div><figure id="z3katyp_374"><img alt="C, Assembly & Machine Code" src="Computer-Science-Study-Notes/a6-4-1.png" title="C, Assembly & Machine Code" width="2631" height="1242"></figure><p id="z3katyp_375">Use the following command to generate the assembly code:</p><div class="code-block" data-lang="none">
gcc –Og –S p1.c
</div><p id="z3katyp_377">Use the following command to disassembly the machine code:</p><div class="code-block" data-lang="none">
objdump –d p1
</div></section></section><div class="last-modified">Last modified: 10 December 2024</div><div data-feedback-placeholder="true"></div><div class="navigation-links _bottom"><a href="computer-architecture.html" class="navigation-links__prev">Computer Architecture</a><a href="computer-architecture-x86-64.html" class="navigation-links__next">x86-64 Architecture</a></div></article><div id="disqus_thread"></div></div></section></main></div><script src="https://resources.jetbrains.com/writerside/apidoc/6.10.0-b518/app.js"></script></body></html>