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fine_delay_core_config.m
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function fine_delay_core_config(this_block)
% Revision History:
%
% 08-Nov-2013 (14:02 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% /media/data/jack/ami/ami_correlator/fine_delay_core.vhd
%
%
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('fine_delay_core');
% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
this_block.tagAsCombinational;
this_block.addSimulinkInport('sync_in');
this_block.addSimulinkInport('en');
this_block.addSimulinkInport('phase');
this_block.addSimulinkInport('d_dt_phase');
this_block.addSimulinkInport('coarse_del');
this_block.addSimulinkInport('frac_delay');
this_block.addSimulinkInport('d_dt_delay');
this_block.addSimulinkInport('din');
this_block.addSimulinkOutport('sync_out');
this_block.addSimulinkOutport('dout');
dout_port = this_block.port('dout');
dout_port.setType('UFix_288_0');
sync_out_port = this_block.port('sync_out');
sync_out_port.setType('Bool');
sync_out_port.useHDLVector(false);
% -----------------------------
if (this_block.inputTypesKnown)
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('coarse_del').width ~= 15);
this_block.setError('Input data type for port "coarse_del" must have width=15.');
end
if (this_block.port('d_dt_delay').width ~= 16);
this_block.setError('Input data type for port "d_dt_delay" must have width=16.');
end
if (this_block.port('d_dt_phase').width ~= 16);
this_block.setError('Input data type for port "d_dt_phase" must have width=16.');
end
if (this_block.port('din').width ~= 288);
this_block.setError('Input data type for port "din" must have width=288.');
end
if (this_block.port('en').width ~= 1);
this_block.setError('Input data type for port "en" must have width=1.');
end
this_block.port('en').useHDLVector(false);
if (this_block.port('frac_delay').width ~= 16);
this_block.setError('Input data type for port "frac_delay" must have width=16.');
end
if (this_block.port('phase').width ~= 16);
this_block.setError('Input data type for port "phase" must have width=16.');
end
if (this_block.port('sync_in').width ~= 1);
this_block.setError('Input data type for port "sync_in" must have width=1.');
end
this_block.port('sync_in').useHDLVector(false);
end % if(inputTypesKnown)
% -----------------------------
% -----------------------------
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'clk_1','ce_1')
end % if(inputRatesKnown)
% -----------------------------
% (!) Set the inout port rate to be the same as the first input
% rate. Change the following code if this is untrue.
uniqueInputRates = unique(this_block.getInputRates);
% Add addtional source files as needed.
% |-------------
% | Add files in the order in which they should be compiled.
% | If two files "a.vhd" and "b.vhd" contain the entities
% | entity_a and entity_b, and entity_a contains a
% | component of type entity_b, the correct sequence of
% | addFile() calls would be:
% | this_block.addFile('b.vhd');
% | this_block.addFile('a.vhd');
% |-------------
% this_block.addFile('');
% this_block.addFile('');
this_block.addFile('fine_delay_core.vhd');
return;
% ------------------------------------------------------------
function setup_as_single_rate(block,clkname,cename)
inputRates = block.inputRates;
uniqueInputRates = unique(inputRates);
if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
block.addError('The inputs to this block cannot all be constant.');
return;
end
if (uniqueInputRates(end) == Inf)
hasConstantInput = true;
uniqueInputRates = uniqueInputRates(1:end-1);
end
if (length(uniqueInputRates) ~= 1)
block.addError('The inputs to this block must run at a single rate.');
return;
end
theInputRate = uniqueInputRates(1);
for i = 1:block.numSimulinkOutports
block.outport(i).setRate(theInputRate);
end
block.addClkCEPair(clkname,cename,theInputRate);
return;
% ------------------------------------------------------------