From 62b917c6a3e536605abd63c4caf5dd086ed6d74d Mon Sep 17 00:00:00 2001 From: "Sukhov, Egor" Date: Thu, 14 Nov 2024 20:59:59 +0000 Subject: [PATCH] XE2 compiles to SIMD16 in case of spilling XE2 compilation goes to SIMD16 route if we have spills during SIMD32 compilation. Test added & previous one that covered for kernels that exhaust PTSS changed. --- .../CISACodeGen/OpenCLKernelCodeGen.cpp | 21 ++++++++++++++++--- IGC/Compiler/CISACodeGen/Platform.hpp | 4 ++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp b/IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp index 0545e523155a..eeba6c4b4e45 100644 --- a/IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp +++ b/IGC/Compiler/CISACodeGen/OpenCLKernelCodeGen.cpp @@ -3446,7 +3446,8 @@ namespace IGC if (ctx->platform.getMinDispatchMode() == SIMDMode::SIMD16) { - AddCodeGenPasses(*ctx, shaders, Passes, SIMDMode::SIMD32, false); + bool abortOnSpills = ctx->platform.isCoreXE2() && (ctx->getModuleMetaData()->csInfo.forcedSIMDSize != 32); + AddCodeGenPasses(*ctx, shaders, Passes, SIMDMode::SIMD32, abortOnSpills); AddCodeGenPasses(*ctx, shaders, Passes, SIMDMode::SIMD16, false); ctx->SetSIMDInfo(SIMD_SKIP_HW, SIMDMode::SIMD8, ShaderDispatchMode::NOT_APPLICABLE); @@ -3751,9 +3752,23 @@ namespace IGC return SIMDStatus::SIMD_FUNC_FAIL; } - EP.m_canAbortOnSpill = false; // spill is always allowed since we don't do SIMD size lowering // Next we check if there is a required sub group size specified CodeGenContext* pCtx = GetContext(); + + CShader* simd16Program = m_parent->GetShader(SIMDMode::SIMD16); + CShader* simd32Program = m_parent->GetShader(SIMDMode::SIMD32); + + bool compileFunctionVariants = pCtx->m_enableSimdVariantCompilation && + (m_FGA && IGC::isIntelSymbolTableVoidProgram(m_FGA->getGroupHead(&F))); + + if((simd16Program && simd16Program->ProgramOutput()->m_programSize > 0) || + (simd32Program && simd32Program->ProgramOutput()->m_programSize > 0)) + { + bool canCompileMultipleSIMD = compileFunctionVariants; + if (!(canCompileMultipleSIMD && (pCtx->getModuleMetaData()->csInfo.forcedSIMDSize == 0))) + return SIMDStatus::SIMD_FUNC_FAIL; + } + MetaDataUtils* pMdUtils = EP.getAnalysis().getMetaDataUtils(); FunctionInfoMetaDataHandle funcInfoMD = pMdUtils->getFunctionsInfoItem(&F); uint32_t simd_size = getReqdSubGroupSize(F, pMdUtils); @@ -3856,7 +3871,7 @@ namespace IGC return SIMDStatus::SIMD_PASS; } - if (simdMode == SIMDMode::SIMD16 && !hasSubGroupForce && !forceLowestSIMDForStackCalls && !hasSubroutine) + if (simdMode == SIMDMode::SIMD16 && !pCtx->platform.isCoreXE2() && !hasSubGroupForce && !forceLowestSIMDForStackCalls && !hasSubroutine) { pCtx->SetSIMDInfo(SIMD_SKIP_PERF, simdMode, ShaderDispatchMode::NOT_APPLICABLE); return SIMDStatus::SIMD_FUNC_FAIL; diff --git a/IGC/Compiler/CISACodeGen/Platform.hpp b/IGC/Compiler/CISACodeGen/Platform.hpp index 41ff2f507768..ccc37e23e96a 100644 --- a/IGC/Compiler/CISACodeGen/Platform.hpp +++ b/IGC/Compiler/CISACodeGen/Platform.hpp @@ -203,6 +203,10 @@ bool isProductChildOf(PRODUCT_FAMILY product) const return m_platformInfo.eProductFamily >= product; } +bool isCoreXE2() const { + return ( m_platformInfo.eRenderCoreFamily == IGFX_XE2_HPG_CORE ); +} + // This function checks if core is child of another core bool isCoreChildOf(GFXCORE_FAMILY core) const {