From b96d958543811f7ceefdb1c54722e3ad5ba80468 Mon Sep 17 00:00:00 2001 From: Shane Passmore Date: Fri, 14 Dec 2012 15:03:45 -0600 Subject: [PATCH 1/2] msm8660: board-holiday-audio: workaround audience chip for AT&T in-call microphone --- arch/arm/mach-msm/board-holiday-audio.c | 78 ++++++++++--------------- 1 file changed, 32 insertions(+), 46 deletions(-) diff --git a/arch/arm/mach-msm/board-holiday-audio.c b/arch/arm/mach-msm/board-holiday-audio.c index 3dd2c17764df..348336981e05 100644 --- a/arch/arm/mach-msm/board-holiday-audio.c +++ b/arch/arm/mach-msm/board-holiday-audio.c @@ -192,54 +192,40 @@ void holiday_mic_enable(int en, int shift) void holiday_imic_pamp_on_with_audience(int en) { - int ret, call_state = 0; - pr_aud_info("%s %d\n", __func__, en); - - call_state = msm_get_call_state(); - if (en) { - ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_ALWAYS_ON); - if (ret) - pr_aud_err("%s: Enabling int mic power failed\n", __func__); - - /* select internal mic path */ - if (call_state) { - gpio_set_value(PM8058_GPIO_PM_TO_SYS(HOLIDAY_AUD_MIC_SEL2), 0); - ret = pm8058_micbias_enable(OTHC_MICBIAS_1, OTHC_SIGNAL_ALWAYS_ON); - if (ret) - pr_aud_err("%s: Enabling back mic power failed\n", __func__); - } else { - if (!force_a1026_on) - gpio_set_value(PM8058_GPIO_PM_TO_SYS(HOLIDAY_AUD_MIC_SEL2), 1); - } - } else { - ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_OFF); - if (ret) - pr_aud_err("%s: Enabling int mic power failed\n", __func__); - if (call_state) { - ret = pm8058_micbias_enable(OTHC_MICBIAS_1, OTHC_SIGNAL_OFF); - if (ret) - pr_aud_err("%s: Enabling back mic power failed\n", __func__); - } - } -} - + int ret; + + pr_aud_info("%s %d\n", __func__, en); + + holiday_snddev_bmic_pamp_on(en); + if (en) { + ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_ALWAYS_ON); + if (ret) + pr_aud_err("%s: Enabling int mic power failed\n", __func__); + + } else { + ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_OFF); + if (ret) + pr_aud_err("%s: Enabling int mic power failed\n", __func__); + } +} + void holiday_imic_pamp_on_without_audience(int en) { - int ret; - - pr_aud_info("%s %d\n", __func__, en); - - holiday_snddev_bmic_pamp_on(en); - if (en) { - ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_ALWAYS_ON); - if (ret) - pr_aud_err("%s: Enabling int mic power failed\n", __func__); - - } else { - ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_OFF); - if (ret) - pr_aud_err("%s: Enabling int mic power failed\n", __func__); - } + int ret; + + pr_aud_info("%s %d\n", __func__, en); + + holiday_snddev_bmic_pamp_on(en); + if (en) { + ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_ALWAYS_ON); + if (ret) + pr_aud_err("%s: Enabling int mic power failed\n", __func__); + + } else { + ret = pm8058_micbias_enable(OTHC_MICBIAS_0, OTHC_SIGNAL_OFF); + if (ret) + pr_aud_err("%s: Enabling int mic power failed\n", __func__); + } } void holiday_snddev_imic_pamp_on(int en) From 8c9af21ec8d1070bee7e27ab19e5c98932801858 Mon Sep 17 00:00:00 2001 From: homeslice976 Date: Tue, 8 Jan 2013 19:51:31 -0500 Subject: [PATCH 2/2] CPU freq now to 1512000, as it should be. Also a slight UV --- arch/arm/mach-msm/acpuclock-8x60.c | 44 +++++++++++++++++------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-msm/acpuclock-8x60.c b/arch/arm/mach-msm/acpuclock-8x60.c index 8107ca6dda83..74f64dc3a0b8 100644 --- a/arch/arm/mach-msm/acpuclock-8x60.c +++ b/arch/arm/mach-msm/acpuclock-8x60.c @@ -216,25 +216,31 @@ static struct clkctl_l2_speed l2_freq_tbl_v2[] = { #define L2(x) (&l2_freq_tbl_v2[(x)]) /* SCPLL frequencies = 2 * 27 MHz * L_VAL */ static struct clkctl_acpu_speed acpu_freq_tbl_1188mhz[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000}, + { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 937500, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 950000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 975000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 1000000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 1012500, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 1037500, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1062500, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1087500, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1125000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1137500, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1162500, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1187500, 0x03006000}, + { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, + { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, + { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, + { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, + { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, + { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, + { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, + { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, + { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, + { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 950000, 0x03006000}, + { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, + { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 975000, 0x03006000}, + { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1000000, 0x03006000}, + { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1000000, 0x03006000}, + { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1025000, 0x03006000}, + { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1025000, 0x03006000}, + { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1050000, 0x03006000}, + { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1075000, 0x03006000}, + { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1100000, 0x03006000}, + { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1125000, 0x03006000}, + { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1150000, 0x03006000}, + { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1150000, 0x03006000}, + { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1175000, 0x03006000}, { {0, 0}, 0 }, }; @@ -1032,7 +1038,7 @@ static __init struct clkctl_acpu_speed *select_freq_plan(void) break; } } else { - max_khz = 1188000; + max_khz = 1512000; acpu_freq_tbl = acpu_freq_tbl_1188mhz; }