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all.csv
We can make this file beautiful and searchable if this error is corrected: It looks like row 2 should actually have 1 column, instead of 3 in line 1.
163 lines (154 loc) · 4.85 KB
/
all.csv
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; clocks
OSC_50M, R10, IO_L29P_GCLK3_2
OSC_X3_NP, D9, IO_L34P_GCLK19_0 # Not placed R105, X3
; fx2_signal, connected_to
; slave fifo group
USB_D0, FX2.FD0, fpga.V15, IO_L5N_2
USB_D1, FX2.FD1, fpga.T14, IO_L12P_D1_MISO2_2
USB_D2, FX2.FD2, fpga.V14, IO_L12N_D2_MISO3_2
USB_D3, FX2.FD3, fpga.T12, IO_L19P_2
USB_D4, FX2.FD4, fpga.V12, IO_L19N_2
USB_D5, FX2.FD5, fpga.U11, IO_L23P_2
USB_D6, FX2.FD6, fpga.V11, IO_L23N_2
USB_D7, FX2.FD7, fpga.P12, IO_L13N_D10_2
USB_D8, FX2.FD8, fpga.V5, IO_L49N_D4_2
USB_D9, FX2.FD9, fpga.U5, IO_L49P_D3_2
USB_D10, FX2.FD10, fpga.V4, IO_L63N_2
USB_D11, FX2.FD11, fpga.T4, IO_L63P_2
USB_D12, FX2.FD12, fpga.T7, IO_L46N_2
USB_D13, FX2.FD13, fpga.P6, IO_L64N_D9_2
USB_D14, FX2.FD14, fpga.T5, IO_L48N_RDWR_B_VREF_2
USB_D15, FX2.FD15, fpga.R5, IO_L48P_D7_2
USB_CLK, FX2.IFCLK, U15, IO_L5P_2
USB_RD, FX2.SLRD, fpga.R3, IO_L62P_D5_2
USB_WR, FX2.SLWR, fpga.T3, IO_L62N_D6_2
USB_OE, FX2.SLOE, fpga.U11, IO_L23P_2
USB_A0, FX2.FIFOADDR0, fpga.V7, IO_L43N_2
USB_A1, FX2.FIFOADDR1, fpga.U7, IO_L43P_2
USB_PKTEND, FX2.PKTEND, fpga.V6, IO_L45N_2
USB_CSn, FX2.SLCS#, fpga.T6, IO_L45P_2
USB_FLAGA, FX2.FLAGA, fpga.T11, IO_L16N_VREF_2
USB_FLAGB, FX2.FLAGB, fpga.R11, IO_L16P_2
USB_FLAGC, FX2.FLAGC, fpga.P11, IO_L20N_2
; misc
FX2.TxD0, fpga.U13, IO_L14P_D11_2
FX2.RxD0, fpga.V13, IO_L14N_D12_2
FX2.CLKOUT, fpga.U10, IO_L30P_GCLK1_D13_2
ACQ_RSTn, FX2.PA0, fpga.V9, IO_L32N_GCLK28_2 # reset acquisition FPGA input
FX2.PA1, fpga.T9, IO_L32P_GCLK29_2
FX2.PA3, fpga.U8, IO_L41P_2
FX2.PE0, fpga.R8, IO_L31P_GCLK31_D14_2
FX2.PE1, fpga.P8, IO_L44N_2
FX2.PE2, fpga.P7, IO_L47N_2
FX2.PE3, fpga.R7, IO_L46P_2
LED_R, FX2.PE5
LED_G, FX2.PE6
; probe row A. ACLK, A0-A15 have level shifting circuits. AST0 goes to FPGA directly
PROBE_ACLK, B2, IO_L2P_0
PROBE_A0, B3, IO_L4P_0
PROBE_A1, B4, IO_L5P_0
PROBE_A2, C5, IO_L6P_0
PROBE_A3, A5, IO_L6N_0
PROBE_A4, C7, IO_L10P_0
PROBE_A5, A7, IO_L10N_0
PROBE_A6, B8, IO_L33P_0
PROBE_A7, B9, IO_L35P_GCLK17_0
PROBE_A8, A9, IO_L35N_GCLK16_0
PROBE_A9, A10, IO_L37N_GCLK12_0
PROBE_A10, B11, IO_L39P_0
PROBE_A11, B12, IO_L41P_0
PROBE_A12, A12, IO_L41N_0
PROBE_A13, B14, IO_L62P_0
PROBE_A14, A15, IO_L64N_SCP4_0
PROBE_A15, A16, IO_L66N_SCP0_0
PROBE_AST0, V16, IO_L2N_CMPMOSI_2 # R280=1K series
; probe row B. ACLK, B0-B15 have level shifting circuits
PROBE_BCLK, A2, IO_L2N_0
PROBE_B0, A3, IO_L4N_0
PROBE_B1, A4, IO_L5N_0
PROBE_B2, C6, IO_L3N_0
PROBE_B3, B6, IO_L8P_0
PROBE_B4, D6, IO_L3P_0
PROBE_B5, D8, IO_L11P_0
PROBE_B6, A8, IO_L33N_0
PROBE_B7, C8, IO_L11N_0
PROBE_B8, C10, IO_L37P_GCLK13_0
PROBE_B9, D11, IO_L36P_GCLK15_0
PROBE_B10, A11, IO_L39N_0
PROBE_B11, C11, IO_L36N_GCLK14_0
PROBE_B12, D14, 0 IO_L65P_SCP3_0
PROBE_B13, C14, IO_L65N_SCP2_0
PROBE_B14, C15, IO_L64P_SCP5_0
PROBE_B15, B16, IO_L66P_SCP1_0
PROBE_AST1, U16, 2 IO_L2P_CMPCLK_2 # R281=1K series
; U13 DAC122S085CIMM - probe Vref VCA0/VCB0 DAC
DAC_DIN, N7, IO_L44P_2 # R284=100%1
DAC_DSYNn, N6, IO_L47P_2 # R283=100%1
DAC_DCLK, N5, IO_L64P_D8_2 # R282=100%1
; USBXI
USBXI_B11, V10, IO_L30N_GCLK0_USERCCLK_2 # R90=22 ExtTrigIN
USBXI_B12, T8, IO_L31N_GCLK30_D15_2 # R88=22 ExtTrigOUT
; U5 SDRAM0
; No RZQ resistor found -> use uncalibrated termination
RAM0_CASn, K5, IO_L43N_GCLK22_IRDY2_M3CASN_3
RAM0_RASn, L5, IO_L43P_GCLK23_M3RASN_3
RAM0_WEn, E3, IO_L50P_M3WE_3
RAM0_A0, J7, IO_L47P_M3A0_3
RAM0_A1, J6, IO_L47N_M3A1_3
RAM0_A2, H5, 3 IO_L49N_M3A2_3
RAM0_A3, L7, IO_L45P_M3A3_3
RAM0_A4, F3, IO_L51N_M3A4_3
RAM0_A5, H4, IO_L44P_GCLK21_M3A5_3
RAM0_A6, H3, IO_L44N_GCLK20_M3A6_3
RAM0_A7, H6, IO_L49P_M3A7_3
RAM0_A8, D2, IO_L52P_M3A8_3
RAM0_A9, D1, IO_L52N_M3A9_3
RAM0_A10, F4, IO_L51P_M3A10_3
RAM0_A11, D3, IO_L54N_M3A11_3
RAM0_A12, G6, IO_L53N_M3A12_3
RAM0_A13, F6, IO_L55P_M3A13_3 # Not used on this RAM type
RAM0_BA0, F2, IO_L48P_M3BA0_3
RAM0_BA1, F1, IO_L48N_M3BA1_3
RAM0_BA2, E1, IO_L50N_M3BA2_3
RAM0_ODT, K6, IO_L45N_M3ODT_3 # R78=4K7 - GND
RAM0_CKE, H7, IO_L53P_M3CKE_3 # R79=4K7 - GND
RAM0_CK, G3, IO_L46P_M3CLK_3 # R85=100%1 to CKn
RAM0_CKn, G1, IO_L46N_M3CLKN_3 # /
RAM0_LDM, K3, IO_L42N_GCLK24_M3LDM_3 # untested
RAM0_CSn # R77=1K-GND
RAM0_VREF # 1V8/2 R57=4K7, R60=4K7
; U6 SDRAM1
; No RZQ resistor found -> use uncalibrated termination
RAM1_CASn, K16
K15 RAS#
K12 WE#
H15 A0
H16 A1
F18 A2
J13 A3
E18 A4
L12 A5
L13 A6
F17 A7
H12 A8
G13 A9
E16 A10
G14 A11
D18 A12
C17 A13 # Not used on this RAM type
H13 BA0
H14 BA1
K13 BA2
K14 - R82=4K7 - GND U6.ODT
D17 - R81=4K7 - GND U6.CKE
RAM1_CK, G16, IO_L38P_A5_M1CLK_1 # R86=100%1 to CKn
RAM1_CKn, G18, IO_L38N_A4_M1CLKN_1 # /
RAM1_CSn - R83=1K - GND U6.CS#
RAM1_VREF 1V8/2 R58=4K7, R59=4K7
; SPI flash/FPGA config
CONF_SELn, FX2.PC0, slfash.SELn, fpga
CONF_CLK, FX2.PC1, sflash.CLK, fpga.CLK
CONF_DOUT, FX2.PC2, sflash.DIN, fpga.DOUT
CONF_DIN, FX2.PC3, sflash.DOUT, fpga.DIN
CONF_WPn, FX2.PC4, sflash.WPn
CONF_PROGRAM, FX2.PC5, fpga.PROGRAM_B_2