From 5930cdec6039df7f9dd4f9898770ba66e6868334 Mon Sep 17 00:00:00 2001 From: Andre Weissflog Date: Tue, 9 Jul 2024 20:58:36 +0200 Subject: [PATCH] z80.h: a couple of simplifications I noticed during the zig port --- chips/z80.h | 14 +++++++------- codegen/z80_desc.yml | 13 ++++--------- 2 files changed, 11 insertions(+), 16 deletions(-) diff --git a/chips/z80.h b/chips/z80.h index e9b76b4a..4b34acd9 100644 --- a/chips/z80.h +++ b/chips/z80.h @@ -3383,9 +3383,9 @@ uint64_t z80_tick(z80_t* cpu, uint64_t pins) { case 707: goto step_next; case 708: goto step_next; case 709: _wait();_ioread(cpu->wz++);goto step_next; - case 710: cpu->dlatch=_gd();goto step_next; + case 710: cpu->a=_gd();goto step_next; // -- overlapped - case 711: cpu->a=cpu->dlatch;goto fetch_next; + case 711: goto fetch_next; // DC: CALL C,nn (M:6 T:17) // -- mread @@ -4100,12 +4100,12 @@ uint64_t z80_tick(z80_t* cpu, uint64_t pins) { case 1112: _wait();_ioread(cpu->bc);goto step_next; case 1113: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; // -- overlapped - case 1114: cpu->hlx[cpu->hlx_idx].h=_z80_in(cpu,cpu->dlatch);goto fetch_next; + case 1114: cpu->h=_z80_in(cpu,cpu->dlatch);goto fetch_next; // ED 61: OUT (C),H (M:2 T:8) // -- iowrite case 1115: goto step_next; - case 1116: _iowrite(cpu->bc,cpu->hlx[cpu->hlx_idx].h);goto step_next; + case 1116: _iowrite(cpu->bc,cpu->h);goto step_next; case 1117: _wait();cpu->wz=cpu->bc+1;goto step_next; case 1118: goto step_next; // -- overlapped @@ -4171,12 +4171,12 @@ uint64_t z80_tick(z80_t* cpu, uint64_t pins) { case 1155: _wait();_ioread(cpu->bc);goto step_next; case 1156: cpu->dlatch=_gd();cpu->wz=cpu->bc+1;goto step_next; // -- overlapped - case 1157: cpu->hlx[cpu->hlx_idx].l=_z80_in(cpu,cpu->dlatch);goto fetch_next; + case 1157: cpu->l=_z80_in(cpu,cpu->dlatch);goto fetch_next; // ED 69: OUT (C),L (M:2 T:8) // -- iowrite case 1158: goto step_next; - case 1159: _iowrite(cpu->bc,cpu->hlx[cpu->hlx_idx].l);goto step_next; + case 1159: _iowrite(cpu->bc,cpu->l);goto step_next; case 1160: _wait();cpu->wz=cpu->bc+1;goto step_next; case 1161: goto step_next; // -- overlapped @@ -4677,7 +4677,7 @@ uint64_t z80_tick(z80_t* cpu, uint64_t pins) { // -- generic case 1471: pins=_z80_refresh(cpu,pins);goto step_next; // -- generic - case 1472: cpu->step=_z80_optable[cpu->opcode];goto step_next; + case 1472: cpu->step=_z80_optable[cpu->opcode]; cpu->addr=cpu->hl;goto step_next; // -- overlapped case 1473: goto fetch_next; diff --git a/codegen/z80_desc.yml b/codegen/z80_desc.yml index 6f9c2ddb..7cd91f69 100644 --- a/codegen/z80_desc.yml +++ b/codegen/z80_desc.yml @@ -285,13 +285,11 @@ OUT (n),A: - { type: mread, ab: $PC++, dst: $WZL, action: $WZH=$A } - { type: iowrite, ab: $WZ, db: $A, action: $WZL++ } -# FIXME: ioread can go directly into A IN A,(n): cond: (x == 3) and (y == 3) and (z == 3) mcycles: - { type: mread, ab: $PC++, dst: $WZL, action: $WZH=$A } - - { type: ioread, ab: $WZ++, dst: $DLATCH } - - { type: overlapped, action: $A=$DLATCH } + - { type: ioread, ab: $WZ++, dst: $A } EX (SP),HL: cond: (x == 3) and (y == 4) and (z == 3) @@ -383,13 +381,12 @@ ED NOP: cond: (x == 0) or (x == 3) or ((x == 1) and (z == 7) and (y >= 6)) or ((x == 2) and ((z > 3) or (y < 4))) mcycles: [] -# FIXME: should be RRY (because H/L can't be IXH/IXL etc...) IN $RY,(C): prefix: ed cond: (x == 1) and (y != 6) and (z == 0) mcycles: - { type: ioread, ab: $BC, dst: $DLATCH, action: $WZ=$BC+1 } - - { type: overlapped, action: "$RY=_z80_in(cpu,$DLATCH)" } + - { type: overlapped, action: "$RRY=_z80_in(cpu,$DLATCH)" } IN (C): prefix: ed @@ -399,12 +396,11 @@ IN (C): # discard result, only set flags - { type: overlapped, action: "_z80_in(cpu,$DLATCH)" } -# FIXME: should be RRY (because H/L can't be IXH/IXL etc...) OUT (C),$RY: prefix: ed cond: (x == 1) and (y != 6) and (z == 1) mcycles: - - { type: iowrite, ab: $BC, db: $RY, action: $WZ=$BC+1 } + - { type: iowrite, ab: $BC, db: $RRY, action: $WZ=$BC+1 } OUT (C),0: prefix: ed @@ -679,7 +675,6 @@ ddfdcb: #== INTERRUPT HANDLING ========================================================= -# FIXME: last tcycle also needs "cpu->addr = cpu->hl" int_im0: flags: { special: true } mcycles: @@ -690,7 +685,7 @@ int_im0: - { type: generic, tcycles: 1, action: "_wait();cpu->opcode=_z80_get_db(pins)" } # combined refresh and branch to loaded instruction cycle - { type: generic, tcycles: 1, action: "pins=_z80_refresh(cpu,pins)" } - - { type: generic, tcycles: 1, action: "cpu->step=_z80_optable[cpu->opcode]" } + - { type: generic, tcycles: 1, action: "cpu->step=_z80_optable[cpu->opcode]; cpu->addr=cpu->hl" } int_im1: flags: { special: true }