diff --git a/docs/rseries_performance_and_sizing.rst b/docs/rseries_performance_and_sizing.rst
index 9607e47..8cf9958 100644
--- a/docs/rseries_performance_and_sizing.rst
+++ b/docs/rseries_performance_and_sizing.rst
@@ -9,11 +9,11 @@ In addition to more modern Intel chipsets, the mid-range (r5000) and high-end (r
 
 Some additional links on the benefits of hardware offload using the ePVA in previous generation BIG-IP solutions:
 
-`K12837: Overview of the ePVA feature <https://my.f5.com/manage/s/article/K12837>_`
+`K12837: Overview of the ePVA feature <https://my.f5.com/manage/s/article/K12837>`_
 
-`K09948701: Overview of the FastL4 profile <https://my.f5.com/manage/s/article/K09948701>_`
+`K09948701: Overview of the FastL4 profile <https://my.f5.com/manage/s/article/K09948701>`_
 
-`F5 Fast L4 Acceleration and the F5 Smart Coprocessor (prioritized Fast L4 Acceleration <https://devcentral.f5.com/s/articles/F5-Fast-L4-Acceleration-and-the-F5-Smart-Coprocessor-prioritized-Fast-L4-Acceleration>_`
+`F5 Fast L4 Acceleration and the F5 Smart Coprocessor (prioritized Fast L4 Acceleration <https://devcentral.f5.com/s/articles/F5-Fast-L4-Acceleration-and-the-F5-Smart-Coprocessor-prioritized-Fast-L4-Acceleration>`_
 
 In rSeries there are now multiple FPGAs, the **Application Traffic Services Engine** (ATSE), and the **Appliance Switch** (ASW), and the **Network Services Socket** (NSO). In addition to supporting previous functions done by the ePVA, there are also additional functions that were performed in software or 3rd party chipsets that are now handled within the FPGAs. Below is an architectural diagram of the r10000 Series appliance.