diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index d985b0823f22..4b9a70432273 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -62,7 +62,11 @@ typedef enum { #define RTC_EXT1_TRIG_EN 0 #endif -#define RTC_GPIO_TRIG_EN PMU_GPIO_WAKEUP_EN //!< GPIO wakeup +#if SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE +#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN | PMU_LP_GPIO_WAKEUP_EN) //!< GPIO & LP_GPIO wakeup +#else +#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN) +#endif #if SOC_LP_TIMER_SUPPORTED #define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index a9634f868400..0ac1107cc652 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -154,6 +154,10 @@ const pmu_sleep_config_t* pmu_sleep_config_default( if (dslp) { config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period); + + pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(pd_flags); + config->digital = digital_default; + pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags); config->analog = analog_default; } else { @@ -200,6 +204,7 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig) { pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel); + pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all); } static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp) @@ -255,9 +260,7 @@ void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp) { assert(PMU_instance()); pmu_sleep_power_init(PMU_instance(), &config->power, dslp); - if(!dslp){ - pmu_sleep_digital_init(PMU_instance(), &config->digital); - } + pmu_sleep_digital_init(PMU_instance(), &config->digital); pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp); pmu_sleep_param_init(PMU_instance(), &config->param, dslp); } diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h index a3c48c042028..0d2bb42bf65a 100644 --- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h @@ -314,9 +314,18 @@ typedef struct { pmu_hp_sys_cntl_reg_t syscntl; } pmu_sleep_digital_config_t; + +#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(pd_flags) { \ + .syscntl = { \ + .dig_pad_slp_sel = 0, \ + .lp_pad_hold_all = (pd_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ + } \ +} + #define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags) { \ .syscntl = { \ - .dig_pad_slp_sel = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \ + .dig_pad_slp_sel = (pd_flags & PMU_SLEEP_PD_TOP) ? 0 : 1, \ + .lp_pad_hold_all = (pd_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ } \ } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index c05ba88355cb..5c34c89607b4 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -217,8 +217,8 @@ typedef struct { uint32_t ext0_rtc_gpio_num : 5; #endif #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP - uint32_t gpio_wakeup_mask : 8; // 8 is the maximum RTCIO number in all chips that support GPIO wakeup - uint32_t gpio_trigger_mode : 8; + uint32_t gpio_wakeup_mask : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT; // Only RTC_GPIO supports wakeup deepsleep + uint32_t gpio_trigger_mode : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT; #endif uint32_t sleep_time_adjustment; uint32_t ccount_ticks_record; diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index c8fd88516dd3..2e711551174e 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -311,6 +311,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT + int + default 6 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x00000000001FFFC0 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 545f4e5cdbcc..9ee2f14fed6f 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -135,6 +135,7 @@ #define SOC_GPIO_OUT_RANGE_MAX 20 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) +#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index d16372d97244..95dff02b4565 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -403,6 +403,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT + int + default 6 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x00000000003FFFC0 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 1b18dda18a85..e51177a0518c 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -173,6 +173,7 @@ #define SOC_GPIO_OUT_RANGE_MAX 21 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) +#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index f3f3df1034bb..ab310ecb290f 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -499,6 +499,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT + int + default 8 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x000000007FFFFF00 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index c16ebceee48c..d0c430129ac7 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -203,6 +203,7 @@ #define SOC_GPIO_OUT_RANGE_MAX 30 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) +#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index b40de47a8b9b..cfd681cf291d 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -587,6 +587,10 @@ config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool default y +config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE + bool + default y + config SOC_GPIO_VALID_GPIO_MASK hex default 0x007FFFFFFFFFFFFF @@ -603,6 +607,10 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK int default 0 +config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT + int + default 16 + config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex default 0x007FFFFFFFFF0000 diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a085b517628c..f25fa6948f70 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -232,6 +232,7 @@ #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~15 on ESP32P4 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) +#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) #define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF) #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK @@ -240,6 +241,7 @@ #define SOC_GPIO_OUT_RANGE_MAX 54 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF) +#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (16) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild index 51dffc1f8cac..7c34046cda61 100644 --- a/examples/system/deep_sleep/main/Kconfig.projbuild +++ b/examples/system/deep_sleep/main/Kconfig.projbuild @@ -44,6 +44,7 @@ menu "Example Configuration" range 7 14 if IDF_TARGET_ESP32H2 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 + range 0 15 if IDF_TARGET_ESP32P4 choice EXAMPLE_EXT1_WAKEUP_PIN_1_SEL prompt "Enable wakeup from PIN_1" @@ -118,6 +119,7 @@ menu "Example Configuration" range 7 14 if IDF_TARGET_ESP32H2 range 0 21 if IDF_TARGET_ESP32S2 range 0 21 if IDF_TARGET_ESP32S3 + range 0 15 if IDF_TARGET_ESP32P4 choice EXAMPLE_EXT1_WAKEUP_PIN_2_SEL prompt "Enable wakeup from PIN_2" @@ -247,7 +249,7 @@ menu "Example Configuration" if we turn off the RTC_PERIPH domain or if certain chips lack the RTC_PERIPH domain, we will use the HOLD feature to maintain the pull-up and pull-down on the pins during sleep. but if we turn on the RTC_PERIPH domain, we don not need to use HOLD feature and this will - increase some power comsumption. + increase some power consumption. EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal pull-up/downs are always available. There's no need to explicitly force it on for EXT0. @@ -259,7 +261,7 @@ menu "Example Configuration" depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP help This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly - recommand you to connect external pull-up resistance. + recommend you to connect external pull-up resistance. menu "GPIO wakeup configuration" visible if EXAMPLE_GPIO_WAKEUP @@ -268,6 +270,7 @@ menu "Example Configuration" int "Enable wakeup from GPIO" default 0 range 0 7 if IDF_TARGET_ESP32C6 + range 0 15 if IDF_TARGET_ESP32P4 range 0 5 if !IDF_TARGET_ESP32C6 config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL