diff --git a/esp32p4/src/ahb_dma/in_int_ch/clr.rs b/esp32p4/src/ahb_dma/in_int_ch/clr.rs index b7830c719..84e75710a 100644 --- a/esp32p4/src/ahb_dma/in_int_ch/clr.rs +++ b/esp32p4/src/ahb_dma/in_int_ch/clr.rs @@ -1,19 +1,19 @@ #[doc = "Register `CLR` writer"] pub type W = crate::W; #[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."] -pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."] -pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."] -pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."] -pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."] -pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `INFIFO_OVF` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."] -pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[doc = "Field `INFIFO_UDF` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."] -pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>; +pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>; #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { @@ -73,7 +73,7 @@ impl crate::RegisterSpec for CLR_SPEC { impl crate::Writable for CLR_SPEC { type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; - const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x7f; } #[doc = "`reset()` method sets CLR to value 0"] impl crate::Resettable for CLR_SPEC { diff --git a/esp32p4/src/axi_dma/out_ch/out_conf0.rs b/esp32p4/src/axi_dma/out_ch/out_conf0.rs index 38ca7448b..09943d6b1 100644 --- a/esp32p4/src/axi_dma/out_ch/out_conf0.rs +++ b/esp32p4/src/axi_dma/out_ch/out_conf0.rs @@ -2,10 +2,10 @@ pub type R = crate::R; #[doc = "Register `OUT_CONF0` writer"] pub type W = crate::W; -#[doc = "Field `OUT_RST_` reader - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST__R = crate::BitReader; -#[doc = "Field `OUT_RST_` writer - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] -pub type OUT_RST__W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_RST` reader - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_R = crate::BitReader; +#[doc = "Field `OUT_RST` writer - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] +pub type OUT_RST_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `OUT_LOOP_TEST` reader - reserved"] pub type OUT_LOOP_TEST_R = crate::BitReader; #[doc = "Field `OUT_LOOP_TEST` writer - reserved"] @@ -41,8 +41,8 @@ pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] #[inline(always)] - pub fn out_rst_(&self) -> OUT_RST__R { - OUT_RST__R::new((self.bits & 1) != 0) + pub fn out_rst(&self) -> OUT_RST_R { + OUT_RST_R::new((self.bits & 1) != 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] @@ -89,7 +89,7 @@ impl R { impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("OUT_CONF0") - .field("out_rst_", &self.out_rst_()) + .field("out_rst", &self.out_rst()) .field("out_loop_test", &self.out_loop_test()) .field("out_auto_wrback", &self.out_auto_wrback()) .field("out_eof_mode", &self.out_eof_mode()) @@ -105,8 +105,8 @@ impl W { #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."] #[inline(always)] #[must_use] - pub fn out_rst_(&mut self) -> OUT_RST__W { - OUT_RST__W::new(self, 0) + pub fn out_rst(&mut self) -> OUT_RST_W { + OUT_RST_W::new(self, 0) } #[doc = "Bit 1 - reserved"] #[inline(always)] diff --git a/esp32p4/src/uart0/clk_conf.rs b/esp32p4/src/uart0/clk_conf.rs index dc164ce73..71e295a2b 100644 --- a/esp32p4/src/uart0/clk_conf.rs +++ b/esp32p4/src/uart0/clk_conf.rs @@ -2,6 +2,10 @@ pub type R = crate::R; #[doc = "Register `CLK_CONF` writer"] pub type W = crate::W; +#[doc = "Field `RST_CORE` reader - Write 1 then write 0 to this bit, reset UART Tx/Rx."] +pub type RST_CORE_R = crate::BitReader; +#[doc = "Field `RST_CORE` writer - Write 1 then write 0 to this bit, reset UART Tx/Rx."] +pub type RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `TX_SCLK_EN` reader - Set this bit to enable UART Tx clock."] pub type TX_SCLK_EN_R = crate::BitReader; #[doc = "Field `TX_SCLK_EN` writer - Set this bit to enable UART Tx clock."] @@ -19,6 +23,11 @@ pub type RX_RST_CORE_R = crate::BitReader; #[doc = "Field `RX_RST_CORE` writer - Write 1 then write 0 to this bit to reset UART Rx."] pub type RX_RST_CORE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { + #[doc = "Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx."] + #[inline(always)] + pub fn rst_core(&self) -> RST_CORE_R { + RST_CORE_R::new(((self.bits >> 23) & 1) != 0) + } #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] #[inline(always)] pub fn tx_sclk_en(&self) -> TX_SCLK_EN_R { @@ -48,10 +57,17 @@ impl core::fmt::Debug for R { .field("rx_sclk_en", &self.rx_sclk_en()) .field("tx_rst_core", &self.tx_rst_core()) .field("rx_rst_core", &self.rx_rst_core()) + .field("rst_core", &self.rst_core()) .finish() } } impl W { + #[doc = "Bit 23 - Write 1 then write 0 to this bit, reset UART Tx/Rx."] + #[inline(always)] + #[must_use] + pub fn rst_core(&mut self) -> RST_CORE_W { + RST_CORE_W::new(self, 23) + } #[doc = "Bit 24 - Set this bit to enable UART Tx clock."] #[inline(always)] #[must_use] diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml index 9bfee8eeb..7bbdc1cdb 100644 --- a/esp32p4/svd/patches/esp32p4.yaml +++ b/esp32p4/svd/patches/esp32p4.yaml @@ -59,6 +59,15 @@ SPI[01]: "EFUSE,I2S0,UART0,SPI[01],LP_WDT,PARL_IO,PAU,USB_DEVICE,MIPI_CSI_BRIDGE,MIPI_DSI_BRIDGE,ECDSA,GPIO,H264,PPA,RMT,LP_TOUCH,LP_TSENS,ISP,LP_HUK,LP_I2S0,LP_UART": _include: ../../../common_patches/int_strip.yaml +UART0: + CLK_CONF: + _add: + RST_CORE: + description: Write 1 then write 0 to this bit, reset UART Tx/Rx. + bitOffset: 23 + bitWidth: 1 + access: read-write + LEDC: _include: ../../../common_patches/ledc_int.yaml _expand_array: @@ -487,6 +496,10 @@ AHB_DMA: IN_INT_CLR_CH?: name: CLR _strip_end: _CH_INT_CLR + _modify: + "*": + modifiedWriteValues: oneToClear + OUT_INT_CH%s: OUT_INT_RAW_CH?: name: RAW @@ -868,7 +881,7 @@ AXI_DMA: modifiedWriteValues: oneToClear OUT_CONF0_CH?: name: OUT_CONF0 - _strip_end: [CH, _CH0] + _strip_end: [_CH, _CH0] OUT_CONF1_CH?: name: OUT_CONF1 _strip_end: _CH