diff --git a/esp32p4/src/clic.rs b/esp32p4/src/clic.rs
new file mode 100644
index 000000000..9a98e0d09
--- /dev/null
+++ b/esp32p4/src/clic.rs
@@ -0,0 +1,54 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    int_config: INT_CONFIG,
+    int_info: INT_INFO,
+    int_thresh: INT_THRESH,
+    _reserved3: [u8; 0x0ff4],
+    int_ctrl: [INT_CTRL; 48],
+}
+impl RegisterBlock {
+    #[doc = "0x00 - Interrupt configuration register"]
+    #[inline(always)]
+    pub const fn int_config(&self) -> &INT_CONFIG {
+        &self.int_config
+    }
+    #[doc = "0x04 - Interrupt information register"]
+    #[inline(always)]
+    pub const fn int_info(&self) -> &INT_INFO {
+        &self.int_info
+    }
+    #[doc = "0x08 - Interrupt threshold register"]
+    #[inline(always)]
+    pub const fn int_thresh(&self) -> &INT_THRESH {
+        &self.int_thresh
+    }
+    #[doc = "0x1000..0x10c0 - Interrupt control register for each interrupt source"]
+    #[inline(always)]
+    pub const fn int_ctrl(&self, n: usize) -> &INT_CTRL {
+        &self.int_ctrl[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x1000..0x10c0 - Interrupt control register for each interrupt source"]
+    #[inline(always)]
+    pub fn int_ctrl_iter(&self) -> impl Iterator<Item = &INT_CTRL> {
+        self.int_ctrl.iter()
+    }
+}
+#[doc = "INT_CONFIG (rw) register accessor: Interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_config`] module"]
+pub type INT_CONFIG = crate::Reg<int_config::INT_CONFIG_SPEC>;
+#[doc = "Interrupt configuration register"]
+pub mod int_config;
+#[doc = "INT_INFO (rw) register accessor: Interrupt information register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_info::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_info::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_info`] module"]
+pub type INT_INFO = crate::Reg<int_info::INT_INFO_SPEC>;
+#[doc = "Interrupt information register"]
+pub mod int_info;
+#[doc = "INT_THRESH (rw) register accessor: Interrupt threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_thresh`] module"]
+pub type INT_THRESH = crate::Reg<int_thresh::INT_THRESH_SPEC>;
+#[doc = "Interrupt threshold register"]
+pub mod int_thresh;
+#[doc = "INT_CTRL (rw) register accessor: Interrupt control register for each interrupt source\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ctrl`] module"]
+pub type INT_CTRL = crate::Reg<int_ctrl::INT_CTRL_SPEC>;
+#[doc = "Interrupt control register for each interrupt source"]
+pub mod int_ctrl;
diff --git a/esp32p4/src/clic/int_config.rs b/esp32p4/src/clic/int_config.rs
new file mode 100644
index 000000000..4a6a80780
--- /dev/null
+++ b/esp32p4/src/clic/int_config.rs
@@ -0,0 +1,80 @@
+#[doc = "Register `INT_CONFIG` reader"]
+pub type R = crate::R<INT_CONFIG_SPEC>;
+#[doc = "Register `INT_CONFIG` writer"]
+pub type W = crate::W<INT_CONFIG_SPEC>;
+#[doc = "Field `INT_CONFIG_NVBITS` reader - Number of vector bits for interrupt"]
+pub type INT_CONFIG_NVBITS_R = crate::BitReader;
+#[doc = "Field `INT_CONFIG_NVBITS` writer - Number of vector bits for interrupt"]
+pub type INT_CONFIG_NVBITS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_CONFIG_NLBITS` reader - Number of level bits for interrupt"]
+pub type INT_CONFIG_NLBITS_R = crate::FieldReader;
+#[doc = "Field `INT_CONFIG_NLBITS` writer - Number of level bits for interrupt"]
+pub type INT_CONFIG_NLBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `INT_CONFIG_NMBITS` reader - Number of mode bits for interrupt"]
+pub type INT_CONFIG_NMBITS_R = crate::FieldReader;
+#[doc = "Field `INT_CONFIG_NMBITS` writer - Number of mode bits for interrupt"]
+pub type INT_CONFIG_NMBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 0 - Number of vector bits for interrupt"]
+    #[inline(always)]
+    pub fn int_config_nvbits(&self) -> INT_CONFIG_NVBITS_R {
+        INT_CONFIG_NVBITS_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:4 - Number of level bits for interrupt"]
+    #[inline(always)]
+    pub fn int_config_nlbits(&self) -> INT_CONFIG_NLBITS_R {
+        INT_CONFIG_NLBITS_R::new(((self.bits >> 1) & 0x0f) as u8)
+    }
+    #[doc = "Bits 5:6 - Number of mode bits for interrupt"]
+    #[inline(always)]
+    pub fn int_config_nmbits(&self) -> INT_CONFIG_NMBITS_R {
+        INT_CONFIG_NMBITS_R::new(((self.bits >> 5) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CONFIG")
+            .field("int_config_nmbits", &self.int_config_nmbits())
+            .field("int_config_nlbits", &self.int_config_nlbits())
+            .field("int_config_nvbits", &self.int_config_nvbits())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Number of vector bits for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_config_nvbits(&mut self) -> INT_CONFIG_NVBITS_W<INT_CONFIG_SPEC> {
+        INT_CONFIG_NVBITS_W::new(self, 0)
+    }
+    #[doc = "Bits 1:4 - Number of level bits for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_config_nlbits(&mut self) -> INT_CONFIG_NLBITS_W<INT_CONFIG_SPEC> {
+        INT_CONFIG_NLBITS_W::new(self, 1)
+    }
+    #[doc = "Bits 5:6 - Number of mode bits for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_config_nmbits(&mut self) -> INT_CONFIG_NMBITS_W<INT_CONFIG_SPEC> {
+        INT_CONFIG_NMBITS_W::new(self, 5)
+    }
+}
+#[doc = "Interrupt configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CONFIG_SPEC;
+impl crate::RegisterSpec for INT_CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_config::R`](R) reader structure"]
+impl crate::Readable for INT_CONFIG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_config::W`](W) writer structure"]
+impl crate::Writable for INT_CONFIG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CONFIG to value 0"]
+impl crate::Resettable for INT_CONFIG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32p4/src/clic/int_ctrl.rs b/esp32p4/src/clic/int_ctrl.rs
new file mode 100644
index 000000000..6fd2cec9c
--- /dev/null
+++ b/esp32p4/src/clic/int_ctrl.rs
@@ -0,0 +1,128 @@
+#[doc = "Register `INT_CTRL%s` reader"]
+pub type R = crate::R<INT_CTRL_SPEC>;
+#[doc = "Register `INT_CTRL%s` writer"]
+pub type W = crate::W<INT_CTRL_SPEC>;
+#[doc = "Field `INT_IP` reader - Pending interrupt bit"]
+pub type INT_IP_R = crate::BitReader;
+#[doc = "Field `INT_IP` writer - Pending interrupt bit"]
+pub type INT_IP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_IE` reader - Interrupt enable bit"]
+pub type INT_IE_R = crate::BitReader;
+#[doc = "Field `INT_IE` writer - Interrupt enable bit"]
+pub type INT_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_ATTR_SHV` reader - Shadow vector attribute"]
+pub type INT_ATTR_SHV_R = crate::BitReader;
+#[doc = "Field `INT_ATTR_SHV` writer - Shadow vector attribute"]
+pub type INT_ATTR_SHV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_ATTR_TRIG` reader - Trigger attribute for interrupt"]
+pub type INT_ATTR_TRIG_R = crate::FieldReader;
+#[doc = "Field `INT_ATTR_TRIG` writer - Trigger attribute for interrupt"]
+pub type INT_ATTR_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `INT_ATTR_MODE` reader - Interrupt mode attribute"]
+pub type INT_ATTR_MODE_R = crate::FieldReader;
+#[doc = "Field `INT_ATTR_MODE` writer - Interrupt mode attribute"]
+pub type INT_ATTR_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `INT_CTL` reader - Control bits for interrupt"]
+pub type INT_CTL_R = crate::FieldReader;
+#[doc = "Field `INT_CTL` writer - Control bits for interrupt"]
+pub type INT_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bit 0 - Pending interrupt bit"]
+    #[inline(always)]
+    pub fn int_ip(&self) -> INT_IP_R {
+        INT_IP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 8 - Interrupt enable bit"]
+    #[inline(always)]
+    pub fn int_ie(&self) -> INT_IE_R {
+        INT_IE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Shadow vector attribute"]
+    #[inline(always)]
+    pub fn int_attr_shv(&self) -> INT_ATTR_SHV_R {
+        INT_ATTR_SHV_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - Trigger attribute for interrupt"]
+    #[inline(always)]
+    pub fn int_attr_trig(&self) -> INT_ATTR_TRIG_R {
+        INT_ATTR_TRIG_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bits 22:23 - Interrupt mode attribute"]
+    #[inline(always)]
+    pub fn int_attr_mode(&self) -> INT_ATTR_MODE_R {
+        INT_ATTR_MODE_R::new(((self.bits >> 22) & 3) as u8)
+    }
+    #[doc = "Bits 24:31 - Control bits for interrupt"]
+    #[inline(always)]
+    pub fn int_ctl(&self) -> INT_CTL_R {
+        INT_CTL_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_CTRL")
+            .field("int_ctl", &self.int_ctl())
+            .field("int_attr_mode", &self.int_attr_mode())
+            .field("int_attr_trig", &self.int_attr_trig())
+            .field("int_attr_shv", &self.int_attr_shv())
+            .field("int_ie", &self.int_ie())
+            .field("int_ip", &self.int_ip())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Pending interrupt bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_ip(&mut self) -> INT_IP_W<INT_CTRL_SPEC> {
+        INT_IP_W::new(self, 0)
+    }
+    #[doc = "Bit 8 - Interrupt enable bit"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_ie(&mut self) -> INT_IE_W<INT_CTRL_SPEC> {
+        INT_IE_W::new(self, 8)
+    }
+    #[doc = "Bit 16 - Shadow vector attribute"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_attr_shv(&mut self) -> INT_ATTR_SHV_W<INT_CTRL_SPEC> {
+        INT_ATTR_SHV_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - Trigger attribute for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_attr_trig(&mut self) -> INT_ATTR_TRIG_W<INT_CTRL_SPEC> {
+        INT_ATTR_TRIG_W::new(self, 17)
+    }
+    #[doc = "Bits 22:23 - Interrupt mode attribute"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_attr_mode(&mut self) -> INT_ATTR_MODE_W<INT_CTRL_SPEC> {
+        INT_ATTR_MODE_W::new(self, 22)
+    }
+    #[doc = "Bits 24:31 - Control bits for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_ctl(&mut self) -> INT_CTL_W<INT_CTRL_SPEC> {
+        INT_CTL_W::new(self, 24)
+    }
+}
+#[doc = "Interrupt control register for each interrupt source\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CTRL_SPEC;
+impl crate::RegisterSpec for INT_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ctrl::R`](R) reader structure"]
+impl crate::Readable for INT_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ctrl::W`](W) writer structure"]
+impl crate::Writable for INT_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CTRL%s to value 0"]
+impl crate::Resettable for INT_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32p4/src/clic/int_info.rs b/esp32p4/src/clic/int_info.rs
new file mode 100644
index 000000000..8f6ce7d5e
--- /dev/null
+++ b/esp32p4/src/clic/int_info.rs
@@ -0,0 +1,80 @@
+#[doc = "Register `INT_INFO` reader"]
+pub type R = crate::R<INT_INFO_SPEC>;
+#[doc = "Register `INT_INFO` writer"]
+pub type W = crate::W<INT_INFO_SPEC>;
+#[doc = "Field `INT_INFO_NUM_INT` reader - Number of interrupts"]
+pub type INT_INFO_NUM_INT_R = crate::FieldReader<u16>;
+#[doc = "Field `INT_INFO_NUM_INT` writer - Number of interrupts"]
+pub type INT_INFO_NUM_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+#[doc = "Field `INT_INFO_VERSION` reader - Version of interrupt module"]
+pub type INT_INFO_VERSION_R = crate::FieldReader;
+#[doc = "Field `INT_INFO_VERSION` writer - Version of interrupt module"]
+pub type INT_INFO_VERSION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `INT_INFO_CTLBITS` reader - Control bits for interrupt"]
+pub type INT_INFO_CTLBITS_R = crate::FieldReader;
+#[doc = "Field `INT_INFO_CTLBITS` writer - Control bits for interrupt"]
+pub type INT_INFO_CTLBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:12 - Number of interrupts"]
+    #[inline(always)]
+    pub fn int_info_num_int(&self) -> INT_INFO_NUM_INT_R {
+        INT_INFO_NUM_INT_R::new((self.bits & 0x1fff) as u16)
+    }
+    #[doc = "Bits 13:20 - Version of interrupt module"]
+    #[inline(always)]
+    pub fn int_info_version(&self) -> INT_INFO_VERSION_R {
+        INT_INFO_VERSION_R::new(((self.bits >> 13) & 0xff) as u8)
+    }
+    #[doc = "Bits 21:24 - Control bits for interrupt"]
+    #[inline(always)]
+    pub fn int_info_ctlbits(&self) -> INT_INFO_CTLBITS_R {
+        INT_INFO_CTLBITS_R::new(((self.bits >> 21) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_INFO")
+            .field("int_info_ctlbits", &self.int_info_ctlbits())
+            .field("int_info_version", &self.int_info_version())
+            .field("int_info_num_int", &self.int_info_num_int())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:12 - Number of interrupts"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_info_num_int(&mut self) -> INT_INFO_NUM_INT_W<INT_INFO_SPEC> {
+        INT_INFO_NUM_INT_W::new(self, 0)
+    }
+    #[doc = "Bits 13:20 - Version of interrupt module"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_info_version(&mut self) -> INT_INFO_VERSION_W<INT_INFO_SPEC> {
+        INT_INFO_VERSION_W::new(self, 13)
+    }
+    #[doc = "Bits 21:24 - Control bits for interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_info_ctlbits(&mut self) -> INT_INFO_CTLBITS_W<INT_INFO_SPEC> {
+        INT_INFO_CTLBITS_W::new(self, 21)
+    }
+}
+#[doc = "Interrupt information register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_info::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_info::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_INFO_SPEC;
+impl crate::RegisterSpec for INT_INFO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_info::R`](R) reader structure"]
+impl crate::Readable for INT_INFO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_info::W`](W) writer structure"]
+impl crate::Writable for INT_INFO_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_INFO to value 0"]
+impl crate::Resettable for INT_INFO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32p4/src/clic/int_thresh.rs b/esp32p4/src/clic/int_thresh.rs
new file mode 100644
index 000000000..a5ce0ac62
--- /dev/null
+++ b/esp32p4/src/clic/int_thresh.rs
@@ -0,0 +1,48 @@
+#[doc = "Register `INT_THRESH` reader"]
+pub type R = crate::R<INT_THRESH_SPEC>;
+#[doc = "Register `INT_THRESH` writer"]
+pub type W = crate::W<INT_THRESH_SPEC>;
+#[doc = "Field `CPU_INT_THRESH` reader - CPU interrupt threshold level"]
+pub type CPU_INT_THRESH_R = crate::FieldReader;
+#[doc = "Field `CPU_INT_THRESH` writer - CPU interrupt threshold level"]
+pub type CPU_INT_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 24:31 - CPU interrupt threshold level"]
+    #[inline(always)]
+    pub fn cpu_int_thresh(&self) -> CPU_INT_THRESH_R {
+        CPU_INT_THRESH_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_THRESH")
+            .field("cpu_int_thresh", &self.cpu_int_thresh())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 24:31 - CPU interrupt threshold level"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cpu_int_thresh(&mut self) -> CPU_INT_THRESH_W<INT_THRESH_SPEC> {
+        CPU_INT_THRESH_W::new(self, 24)
+    }
+}
+#[doc = "Interrupt threshold register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_thresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_thresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_THRESH_SPEC;
+impl crate::RegisterSpec for INT_THRESH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_thresh::R`](R) reader structure"]
+impl crate::Readable for INT_THRESH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_thresh::W`](W) writer structure"]
+impl crate::Writable for INT_THRESH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_THRESH to value 0"]
+impl crate::Resettable for INT_THRESH_SPEC {
+    const RESET_VALUE: u32 = 0;
+}
diff --git a/esp32p4/src/lib.rs b/esp32p4/src/lib.rs
index 2ec0de831..b21d7eba7 100644
--- a/esp32p4/src/lib.rs
+++ b/esp32p4/src/lib.rs
@@ -4446,6 +4446,52 @@ impl core::fmt::Debug for USB_WRAP {
 }
 #[doc = "USB_WRAP Peripheral"]
 pub mod usb_wrap;
+#[doc = "Core Local Interrupt Controller (CLIC)"]
+pub struct CLIC {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for CLIC {}
+impl CLIC {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const clic::RegisterBlock = 0x2080_0000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const clic::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for CLIC {
+    type Target = clic::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for CLIC {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLIC").finish()
+    }
+}
+#[doc = "Core Local Interrupt Controller (CLIC)"]
+pub mod clic;
 #[no_mangle]
 static mut DEVICE_PERIPHERALS: bool = false;
 #[doc = r" All the peripherals."]
@@ -4629,6 +4675,8 @@ pub struct Peripherals {
     pub USB_DEVICE: USB_DEVICE,
     #[doc = "USB_WRAP"]
     pub USB_WRAP: USB_WRAP,
+    #[doc = "CLIC"]
+    pub CLIC: CLIC,
 }
 impl Peripherals {
     #[doc = r" Returns all the peripherals *once*."]
@@ -4740,6 +4788,7 @@ impl Peripherals {
             UHCI0: UHCI0::steal(),
             USB_DEVICE: USB_DEVICE::steal(),
             USB_WRAP: USB_WRAP::steal(),
+            CLIC: CLIC::steal(),
         }
     }
 }
diff --git a/esp32p4/svd/patches/esp32p4.yaml b/esp32p4/svd/patches/esp32p4.yaml
index 7bbdc1cdb..08b51cdd3 100644
--- a/esp32p4/svd/patches/esp32p4.yaml
+++ b/esp32p4/svd/patches/esp32p4.yaml
@@ -1380,3 +1380,109 @@ HP_SYS:
         value: 81
       FROM_CPU_INTR3:
         value: 82
+
+_add:
+  CLIC:
+    description: "Core Local Interrupt Controller (CLIC)"
+    baseAddress: 0x20800000
+    groupName: CLIC
+    addressBlock:
+      offset: 0x0
+      size: 0x1000
+      usage: registers
+
+    registers:
+      INT_CONFIG:
+        description: "Interrupt configuration register"
+        addressOffset: 0x0
+        size: 32
+        access: read-write
+        fields:
+          INT_CONFIG_NMBITS:
+            description: "Number of mode bits for interrupt"
+            bitOffset: 5
+            bitWidth: 2
+            access: read-write
+          INT_CONFIG_NLBITS:
+            description: "Number of level bits for interrupt"
+            bitOffset: 1
+            bitWidth: 4
+            access: read-write
+          INT_CONFIG_NVBITS:
+            description: "Number of vector bits for interrupt"
+            bitOffset: 0
+            bitWidth: 1
+            access: read-write
+
+      INT_INFO:
+        description: "Interrupt information register"
+        addressOffset: 0x4
+        size: 32
+        access: read-write
+        fields:
+          INT_INFO_CTLBITS:
+            description: "Control bits for interrupt"
+            bitOffset: 21
+            bitWidth: 4
+            access: read-write
+          INT_INFO_VERSION:
+            description: "Version of interrupt module"
+            bitOffset: 13
+            bitWidth: 8
+            access: read-write
+          INT_INFO_NUM_INT:
+            description: "Number of interrupts"
+            bitOffset: 0
+            bitWidth: 13
+            access: read-write
+
+      INT_THRESH:
+        description: "Interrupt threshold register"
+        addressOffset: 0x8
+        size: 32
+        access: read-write
+        fields:
+          CPU_INT_THRESH:
+            description: "CPU interrupt threshold level"
+            bitOffset: 24
+            bitWidth: 8
+            access: read-write
+
+      INT_CTRL%s:
+        description: "Interrupt control register for each interrupt source"
+        addressOffset: 0x1000
+        size: 32
+        access: read-write
+        dim: 48
+        dimIncrement: 0x4
+        fields:
+          INT_CTL:
+            description: "Control bits for interrupt"
+            bitOffset: 24
+            bitWidth: 8
+            access: read-write
+          INT_ATTR_MODE:
+            description: "Interrupt mode attribute"
+            bitOffset: 22
+            bitWidth: 2
+            access: read-write
+          INT_ATTR_TRIG:
+            description: "Trigger attribute for interrupt"
+            bitOffset: 17
+            bitWidth: 2
+            access: read-write
+          INT_ATTR_SHV:
+            description: "Shadow vector attribute"
+            bitOffset: 16
+            bitWidth: 1
+            access: read-write
+          INT_IE:
+            description: "Interrupt enable bit"
+            bitOffset: 8
+            bitWidth: 1
+            access: read-write
+          INT_IP:
+            description: "Pending interrupt bit"
+            bitOffset: 0
+            bitWidth: 1
+            access: read-write