diff --git a/esp-hal/src/spi/master.rs b/esp-hal/src/spi/master.rs index 5840107ebb..15c85913d5 100644 --- a/esp-hal/src/spi/master.rs +++ b/esp-hal/src/spi/master.rs @@ -509,12 +509,12 @@ where /// Sends out a stuffing byte for every byte to read. This function doesn't /// perform flushing. If you want to read the response to something you /// have written before, consider using [`Self::transfer`] instead. - pub fn read_byte(&mut self) -> nb::Result { + pub fn read_byte(&mut self) -> u8 { self.driver().read_byte() } /// Write a byte to SPI. - pub fn write_byte(&mut self, word: u8) -> nb::Result<(), Error> { + pub fn write_byte(&mut self, word: u8) { self.driver().write_byte(word) } @@ -2126,7 +2126,6 @@ mod dma { mod ehal1 { use embedded_hal::spi::SpiBus; use embedded_hal_async::spi::SpiBus as SpiBusAsync; - use embedded_hal_nb::spi::FullDuplex; use super::*; @@ -2134,19 +2133,6 @@ mod ehal1 { type Error = Error; } - impl FullDuplex for Spi<'_, Dm> - where - Dm: DriverMode, - { - fn read(&mut self) -> nb::Result { - self.driver().read_byte() - } - - fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { - self.driver().write_byte(word) - } - } - impl SpiBus for Spi<'_, Dm> where Dm: DriverMode, @@ -2912,19 +2898,15 @@ impl Driver { }); } - fn read_byte(&self) -> nb::Result { - if self.busy() { - return Err(nb::Error::WouldBlock); - } + fn read_byte(&self) -> u8 { + while (self).busy() {} let reg_block = self.register_block(); - Ok(u32::try_into(reg_block.w(0).read().bits()).unwrap_or_default()) + u32::try_into(reg_block.w(0).read().bits()).unwrap_or_default() } - fn write_byte(&self, word: u8) -> nb::Result<(), Error> { - if self.busy() { - return Err(nb::Error::WouldBlock); - } + fn write_byte(&self, word: u8) { + while (self).busy() {} self.configure_datalen(0, 1); @@ -2932,8 +2914,6 @@ impl Driver { reg_block.w(0).write(|w| w.buf().set(word.into())); self.start_operation(); - - Ok(()) } #[cfg_attr(place_spi_driver_in_ram, ram)] diff --git a/esp-hal/src/timer/mod.rs b/esp-hal/src/timer/mod.rs index ab35b34b2c..7c5f5fd721 100644 --- a/esp-hal/src/timer/mod.rs +++ b/esp-hal/src/timer/mod.rs @@ -35,7 +35,7 @@ //! //! periodic.start(1.secs()); //! loop { -//! nb::block!(periodic.wait()); +//! periodic.wait(); //! } //! # } //! ``` @@ -310,15 +310,10 @@ where Ok(()) } - /// "Wait" until the count down finishes without blocking. - pub fn wait(&mut self) -> nb::Result<(), void::Void> { - if self.inner.is_interrupt_set() { - self.inner.clear_interrupt(); - - Ok(()) - } else { - Err(nb::Error::WouldBlock) - } + /// "Wait", by blocking, until the count down finishes. + pub fn wait(&mut self) { + while !self.inner.is_interrupt_set() {} + self.inner.clear_interrupt(); } /// Tries to cancel the active count down. diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs index 513fa13515..770e37713f 100644 --- a/esp-hal/src/uart.rs +++ b/esp-hal/src/uart.rs @@ -79,8 +79,8 @@ //! let (mut rx, mut tx) = uart1.split(); //! //! // Each component can be used individually to interact with the UART: -//! tx.write_bytes(&[42u8]).expect("write error!"); -//! let byte = rx.read_byte().expect("read error!"); +//! tx.write_bytes(&[42u8]); +//! let byte = rx.read_byte(); //! # } //! ``` //! @@ -198,9 +198,8 @@ //! let serial = serial.as_mut().unwrap(); //! //! let mut cnt = 0; -//! while let nb::Result::Ok(_c) = serial.read_byte() { -//! cnt += 1; -//! } +//! let mut buff = [0u8; 64]; +//! let cnt = serial.read_bytes(&mut buff); //! writeln!(serial, "Read {} bytes", cnt).ok(); //! //! let pending_interrupts = serial.interrupts(); @@ -645,22 +644,18 @@ where pub fn write_bytes(&mut self, data: &[u8]) -> Result { let count = data.len(); - data.iter() - .try_for_each(|c| nb::block!(self.write_byte(*c)))?; + for &byte in data { + self.write_byte(byte); + } Ok(count) } - fn write_byte(&mut self, word: u8) -> nb::Result<(), Error> { - if self.tx_fifo_count() < UART_FIFO_SIZE { - self.register_block() - .fifo() - .write(|w| unsafe { w.rxfifo_rd_byte().bits(word) }); - - Ok(()) - } else { - Err(nb::Error::WouldBlock) - } + fn write_byte(&mut self, word: u8) { + while self.tx_fifo_count() >= UART_FIFO_SIZE {} + self.register_block() + .fifo() + .write(|w| unsafe { w.rxfifo_rd_byte().bits(word) }); } #[allow(clippy::useless_conversion)] @@ -676,12 +671,8 @@ where } /// Flush the transmit buffer of the UART - pub fn flush(&mut self) -> nb::Result<(), Error> { - if self.is_tx_idle() { - Ok(()) - } else { - Err(nb::Error::WouldBlock) - } + pub fn flush(&mut self) { + while !self.is_tx_idle() {} } /// Checks if the TX line is idle for this UART instance. @@ -827,7 +818,7 @@ where } /// Read a byte from the UART - pub fn read_byte(&mut self) -> nb::Result { + pub fn read_byte(&mut self) -> u8 { cfg_if::cfg_if! { if #[cfg(esp32s2)] { // On the ESP32-S2 we need to use PeriBus2 to read the FIFO: @@ -840,33 +831,24 @@ where } } - if self.rx_fifo_count() > 0 { - // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html - cfg_if::cfg_if! { - if #[cfg(esp32)] { - let byte = crate::interrupt::free(|| fifo.read().rxfifo_rd_byte().bits()); - } else { - let byte = fifo.read().rxfifo_rd_byte().bits(); - } + while self.rx_fifo_count() == 0 {} + // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html + cfg_if::cfg_if! { + if #[cfg(esp32)] { + crate::interrupt::free(|| fifo.read().rxfifo_rd_byte().bits()) + } else { + fifo.read().rxfifo_rd_byte().bits() } - - Ok(byte) - } else { - Err(nb::Error::WouldBlock) } } /// Read all available bytes from the RX FIFO into the provided buffer and - /// returns the number of read bytes without blocking. + /// returns the number of read bytes. pub fn read_bytes(&mut self, buf: &mut [u8]) -> usize { let mut count = 0; - while count < buf.len() { - if let Ok(byte) = self.read_byte() { - buf[count] = byte; - count += 1; - } else { - break; - } + while count < buf.len() && self.rx_fifo_count() > 0 { + buf[count] = self.read_byte(); + count += 1; } count } @@ -1134,17 +1116,17 @@ where } /// Write a byte out over the UART - pub fn write_byte(&mut self, word: u8) -> nb::Result<(), Error> { + pub fn write_byte(&mut self, word: u8) { self.tx.write_byte(word) } /// Flush the transmit buffer of the UART - pub fn flush(&mut self) -> nb::Result<(), Error> { + pub fn flush(&mut self) { self.tx.flush() } /// Read a byte from the UART - pub fn read_byte(&mut self) -> nb::Result { + pub fn read_byte(&mut self) -> u8 { self.rx.read_byte() } @@ -1322,50 +1304,6 @@ impl embedded_hal_nb::serial::ErrorType for UartRx<'_, Dm> { type Error = Error; } -impl embedded_hal_nb::serial::Read for Uart<'_, Dm> -where - Dm: DriverMode, -{ - fn read(&mut self) -> nb::Result { - self.read_byte() - } -} - -impl embedded_hal_nb::serial::Read for UartRx<'_, Dm> -where - Dm: DriverMode, -{ - fn read(&mut self) -> nb::Result { - self.read_byte() - } -} - -impl embedded_hal_nb::serial::Write for Uart<'_, Dm> -where - Dm: DriverMode, -{ - fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { - self.write_byte(word) - } - - fn flush(&mut self) -> nb::Result<(), Self::Error> { - self.flush() - } -} - -impl embedded_hal_nb::serial::Write for UartTx<'_, Dm> -where - Dm: DriverMode, -{ - fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { - self.write_byte(word) - } - - fn flush(&mut self) -> nb::Result<(), Self::Error> { - self.flush() - } -} - #[cfg(any(doc, feature = "unstable"))] #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))] impl embedded_io::ErrorType for Uart<'_, Dm> { @@ -1462,14 +1400,7 @@ where } fn flush(&mut self) -> Result<(), Self::Error> { - loop { - match self.flush() { - Ok(_) => break, - Err(nb::Error::WouldBlock) => { /* Wait */ } - Err(nb::Error::Other(e)) => return Err(e), - } - } - + self.flush(); Ok(()) } } @@ -1693,7 +1624,7 @@ impl UartTx<'_, Async> { } for byte in &words[offset..next_offset] { - self.write_byte(*byte).unwrap(); // should never fail + self.write_byte(*byte); count += 1; } diff --git a/examples/src/bin/ieee802154_sniffer.rs b/examples/src/bin/ieee802154_sniffer.rs index c94bb7fc93..f9005c4301 100644 --- a/examples/src/bin/ieee802154_sniffer.rs +++ b/examples/src/bin/ieee802154_sniffer.rs @@ -39,7 +39,8 @@ fn main() -> ! { let mut cnt = 0; let mut read = [0u8; 2]; loop { - let c = nb::block!(uart0.read_byte()).unwrap(); + let c = uart0.read_byte(); + if c == b'r' { continue; } @@ -74,10 +75,9 @@ fn main() -> ! { println!("@RAW {:02x?}", &frame.data); } - if let nb::Result::Ok(c) = uart0.read_byte() { - if c == b'r' { - software_reset(); - } + let mut buff = [0u8; 1]; + if uart0.read_bytes(&mut buff) > 0 && buff[0] == b'r' { + software_reset(); } } } diff --git a/hil-test/tests/embassy_timers_executors.rs b/hil-test/tests/embassy_timers_executors.rs index 95c98e404d..a049518191 100644 --- a/hil-test/tests/embassy_timers_executors.rs +++ b/hil-test/tests/embassy_timers_executors.rs @@ -69,7 +69,8 @@ mod test_cases { let t1 = esp_hal::time::now(); periodic.start(100.millis()).unwrap(); - nb::block!(periodic.wait()).unwrap(); + periodic.wait(); + let t2 = esp_hal::time::now(); assert!(t2 > t1, "t2: {:?}, t1: {:?}", t2, t1); diff --git a/hil-test/tests/uart.rs b/hil-test/tests/uart.rs index b768bb54b4..e7bdc0a4a8 100644 --- a/hil-test/tests/uart.rs +++ b/hil-test/tests/uart.rs @@ -5,13 +5,11 @@ #![no_std] #![no_main] -use embedded_hal_nb::serial::{Read, Write}; use esp_hal::{ uart::{self, ClockSource, Uart}, Blocking, }; use hil_test as _; -use nb::block; struct Context { uart: Uart<'static, Blocking>, @@ -38,9 +36,9 @@ mod tests { #[test] fn test_send_receive(mut ctx: Context) { - ctx.uart.write(0x42).ok(); - let read = block!(ctx.uart.read()); - assert_eq!(read, Ok(0x42)); + ctx.uart.write_byte(0x42); + let read = ctx.uart.read_byte(); + assert_eq!(read, 0x42); } #[test] @@ -55,16 +53,9 @@ mod tests { let mut i = 0; while i < BUF_SIZE { - match ctx.uart.read() { - Ok(byte) => { - buffer[i] = byte; - i += 1; - } - Err(nb::Error::WouldBlock) => continue, - Err(nb::Error::Other(_)) => panic!(), - } + buffer[i] = ctx.uart.read_byte(); + i += 1; } - assert_eq!(data, buffer); } @@ -93,9 +84,10 @@ mod tests { .with_clock_source(clock_source), ) .unwrap(); - ctx.uart.write(byte_to_write).ok(); - let read = block!(ctx.uart.read()); - assert_eq!(read, Ok(byte_to_write)); + ctx.uart.write_byte(byte_to_write); + let read = ctx.uart.read_byte(); + + assert_eq!(read, byte_to_write); byte_to_write = !byte_to_write; } } diff --git a/hil-test/tests/uart_regression.rs b/hil-test/tests/uart_regression.rs index e1537dfce5..eafb64283b 100644 --- a/hil-test/tests/uart_regression.rs +++ b/hil-test/tests/uart_regression.rs @@ -13,7 +13,6 @@ mod tests { uart::{self, UartRx, UartTx}, }; use hil_test as _; - use nb::block; #[test] fn test_that_creating_tx_does_not_cause_a_pulse() { @@ -25,9 +24,6 @@ mod tests { .unwrap() .with_rx(rx); - // start reception - _ = rx.read_byte(); // this will just return WouldBlock - unsafe { tx.set_output_high(false, esp_hal::Internal::conjure()) }; // set up TX and send a byte @@ -35,10 +31,10 @@ mod tests { .unwrap() .with_tx(tx); - tx.flush().unwrap(); + tx.flush(); tx.write_bytes(&[0x42]).unwrap(); - let read = block!(rx.read_byte()); + let read = rx.read_byte(); - assert_eq!(read, Ok(0x42)); + assert_eq!(read, 0x42); } } diff --git a/hil-test/tests/uart_tx_rx.rs b/hil-test/tests/uart_tx_rx.rs index bc05f042ea..f6aaaea367 100644 --- a/hil-test/tests/uart_tx_rx.rs +++ b/hil-test/tests/uart_tx_rx.rs @@ -10,7 +10,6 @@ use esp_hal::{ Blocking, }; use hil_test as _; -use nb::block; struct Context { rx: UartRx<'static, Blocking>, @@ -42,11 +41,11 @@ mod tests { fn test_send_receive(mut ctx: Context) { let byte = [0x42]; - ctx.tx.flush().unwrap(); + ctx.tx.flush(); ctx.tx.write_bytes(&byte).unwrap(); - let read = block!(ctx.rx.read_byte()); + let read = ctx.rx.read_byte(); - assert_eq!(read, Ok(0x42)); + assert_eq!(read, 0x42); } #[test] @@ -54,7 +53,7 @@ mod tests { let bytes = [0x42, 0x43, 0x44]; let mut buf = [0u8; 3]; - ctx.tx.flush().unwrap(); + ctx.tx.flush(); ctx.tx.write_bytes(&bytes).unwrap(); let mut bytes_read = 0;