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I've been banging my head against this for two days now. Reaching out in the hopes of some guidance/pointers. 🙇
I am using a ULXS3 board and have connected two LAN8720 PHY modules via RMII. So far so good - the idea was to try to do some basic packet mangling by ingesting packets on one port, mangle and output on the other.
can you explain the purpose of cascading the 2 packetizers? The packetizer has some idle cycles, adding a FIFO between the two packetizer could help getting better throughput.
This was just an example with no clear purpose to highlight the issue. I also tried adding a PacketFIFO directly after the ingress MAC but with no change.
Basically what seems to happen here is an overrun as the output bandwidth is > input bandwidth. For bursts a FIFO works fine to compensate. But if I run the input hard the issue is that the whole stream/pipeline locks up and doesn't recover. Is there a default way in LiteEth/LiteX to drop further frames/packets into a stream when the output is overloaded?
I've been banging my head against this for two days now. Reaching out in the hopes of some guidance/pointers. 🙇
I am using a ULXS3 board and have connected two LAN8720 PHY modules via RMII. So far so good - the idea was to try to do some basic packet mangling by ingesting packets on one port, mangle and output on the other.
I set up the PHY + MAC like so:
And then I try to create the stream as follows (in one direction to test).
This one works fine - full 100Mbit line rate.
Here the performance drops to about half. From about 50Mbit onwards packet drops start to occur.
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