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I'm not sure if this question is for liteeth or for litex-boards.
I'm running Linux 64bit (Debian sid) with NaxRiscv and Rocket on two boards (qmtech_wukong and qmtech_artix7_fbg484, XC7A100T and XC7A200T"). I can not make the ethernet work. The kernel can see the device and can assign an IRQ, but it is not really working. In the past (last summer) I could use liteeth with reasonable stability (for a FPGA). The only way I can have liteeth operational is to import LiteEthPHYGMII instead of LiteEthPHYMII. If I read the protocol correct, this should not matter, right?
Also (not sure if related) in build messages I'm getting two critical warnings "create_clock attempting to set clock on an unknown port/pin for constraint", because the XDC has :
I'm not sure if this question is for liteeth or for litex-boards.
I'm running Linux 64bit (Debian sid) with NaxRiscv and Rocket on two boards (qmtech_wukong and qmtech_artix7_fbg484, XC7A100T and XC7A200T"). I can not make the ethernet work. The kernel can see the device and can assign an IRQ, but it is not really working. In the past (last summer) I could use liteeth with reasonable stability (for a FPGA). The only way I can have liteeth operational is to import LiteEthPHYGMII instead of LiteEthPHYMII. If I read the protocol correct, this should not matter, right?
Also (not sure if related) in build messages I'm getting two critical warnings "create_clock attempting to set clock on an unknown port/pin for constraint", because the XDC has :
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
but there are no eth_rx_clk or eth_tx_clk anywere
any hints ?
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