Is it possible to generate generic Liteeth Verilog?

[PedroAntunes178]

Hi,

Is there any way to generate the Liteeth Core Verilog independent of specific vendors?
When generating the Verilog with the examples (liteeth_gen wishbone_mii.yml) the generated Verilog uses Xilinx modules for asynchronous registers. Can I edit the *.yml file so that the Verilog code is generated without using Xilinx properties?

Thank you for your time in advance.

[hydroid7]

This would be an interesting question also me. Verilog is still one of the industry standards and it would be nice to use this module as part of other designs.

Similar ethernet core, also written for Migen is available here: https://github.com/HarryMakes/nmigen-stdio/tree/eth/nmigen_stdio/eth

Best