diff --git a/.gitignore b/.gitignore index 1b88e95..6adab01 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,11 @@ -Debug/ -*.dep -*.bat -*.TMP -*.wspos doxygen/html + +# Waf lock files +.lock-waf_* + +# Waf's dir it unpacks itself to. +/waf3-*/ +/.waf3-*/ + +# All build output +/build/ diff --git a/.vscode/.gitignore b/.vscode/.gitignore new file mode 100644 index 0000000..d41a8d4 --- /dev/null +++ b/.vscode/.gitignore @@ -0,0 +1,3 @@ +# Ignore the settings file, but a default is provided which should seed this using the +# config-defaults extension. +settings.json \ No newline at end of file diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..d44c149 --- /dev/null +++ b/.vscode/c_cpp_properties.json @@ -0,0 +1,14 @@ +{ + "configurations": [ + { + "name": "default", + "includePath": [], + "defines": [], + "cStandard": "c99", + "intelliSenseMode": "gcc-arm", + "compileCommands": "${workspaceFolder}/build/compile_commands.json", + "mergeConfigurations": true + } + ], + "version": 4 +} \ No newline at end of file diff --git a/.vscode/extensions.json b/.vscode/extensions.json new file mode 100644 index 0000000..d1e538d --- /dev/null +++ b/.vscode/extensions.json @@ -0,0 +1,19 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=827846 to learn about workspace recommendations. + // Extension identifier format: ${publisher}.${name}. Example: vscode.csharp + // List of extensions which should be recommended for users of this workspace. + "recommendations": [ + "dan-c-underwood.arm", + "ms-vscode.cpptools-extension-pack", + "marus25.cortex-debug", + "trond-snekvik.gnu-mapfiles", + "keroc.hex-fmt", + "zixuanwang.linkerscriptm", + "spadin.config-defaults", + "mhutchie.git-graph", + "eamodio.gitlens", + "ms-vscode.vscode-serial-monitor" + ], + // List of extensions recommended by VS Code that should not be recommended for users of this workspace. + "unwantedRecommendations": [] +} \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..760ba72 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,63 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "cwd": "${workspaceFolder}", + "executable": "./build/firmware-ascii", + "name": "Debug ASCII Board", + "request": "launch", + "type": "cortex-debug", + "device": "ATSAM3U2C", + "runToEntryPoint": "main", + // "breakAfterReset": true, + "showDevDebugOutput": "none", + "servertype": "jlink", + "svdPath": "${workspaceFolder}/firmware_common/bsp/ATSAM3U2C.svd", + "preLaunchTask": "Build firmware" + }, + { + "cwd": "${workspaceFolder}", + "executable": "./build/firmware-dot-matrix", + "name": "Debug Dot Matrix Board", + "request": "launch", + "type": "cortex-debug", + "device": "ATSAM3U2C", + "runToEntryPoint": "main", + // "breakAfterReset": true, + "showDevDebugOutput": "none", + "servertype": "jlink", + "svdPath": "${workspaceFolder}/firmware_common/bsp/ATSAM3U2C.svd", + "preLaunchTask": "Build firmware" + }, + { + "name": "waf", + "type": "python", + "request": "launch", + "program": "${workspaceFolder}/waf", + "args": [ + "${input:waf-command}", + ], + "cwd": "${workspaceFolder}", + "console": "integratedTerminal", + "justMyCode": false, + }, + ], + "inputs": [ + { + "id": "waf-command", + "type": "pickString", + "description": "Which waf subcommand to run", + "default": "build", + "options": [ + "distclean", + "configure", + "clean", + "build", + "clean build", + ] + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.default.json b/.vscode/settings.default.json new file mode 100644 index 0000000..ae65f64 --- /dev/null +++ b/.vscode/settings.default.json @@ -0,0 +1,14 @@ +{ + "cortex-debug.variableUseNaturalFormat": false, + "C_Cpp.autoAddFileAssociations": false, + "cortex-debug.liveWatchRefreshRate": 600, + // These defaults are based on typical install paths, you may need to update them based on + // what version and where you installed things. (they also belong in your user config). + // TODO: Would it be okay to auto-set these from waf? Or in the launch config? That might be + // too much automatic magic. + "cortex-debug.armToolchainPath.windows": "C:\\Program Files (x86)\\Arm GNU Toolchain arm-none-eabi\\13.3 rel1\\bin", + "cortex-debug.armToolchainPath.osx": "/Application/ArmGNUToolchain/13.3.rel1/arm-none-eabi/bin", + "cortex-debug.JLinkGDBServerPath.windows": "C:\\Program Files\\SEGGER\\JLink\\JLinkGDBServerCL.exe", + "cortex-debug.JLinkGDBServerPath.osx": "/Application/SEGGER/JLink/JLinkGDBServerCLExe", + "cortex-debug.JLinkGDBServerPath.linux": "/opt/SEGGER/JLink/JLinkGDBServerCLExe", +} \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..50189fa --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,28 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "Build firmware", + "type": "process", + "command": "python", + "args": [ + "waf", + "build", + "--keep", // Keep going even if error, ensures all compilation failures are found. + ], + "isBuildCommand": true, + "problemMatcher": { + "base": "$gcc", + "fileLocation": [ + "autoDetect", + "${workspaceFolder}/build/", + ] + }, + "options": { + "cwd": "${workspaceFolder}", + }, + } + ] +} \ No newline at end of file diff --git a/docs/setup.md b/docs/setup.md new file mode 100644 index 0000000..ae86bad --- /dev/null +++ b/docs/setup.md @@ -0,0 +1,52 @@ +# Setup + +[TOC] + +## Installation + + +### Required tools +The following tools are necessary to build the project + +- [Python 3](#python-3) +- [The ARM GNU Toolchain](#arm-gnu-toolchain) +- [JLink](#jlink) +- [Git](#git) + +#### Python 3 + +Python 3 is used to run the waf script that controls the configuration and build process of the project + +Install the latest version of python 3 for your operating system from [Python.org](https://www.python.org/downloads/). If you have an older version of python 3 that will probably work fine. +It is recommended to select the option to add python to the path if available during the install. + +#### ARM GNU Toolchain + +The GNU arm toolchain contains the compiler and other tools necessary to build the project. To install + +1. Go to the page for the [ARM GNU Toolchain Download](https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads). +2. Download the version 13.3.Rel1 of the **ARM-none-eabi** toolchain for your operating system. + 1. For windows this is the .exe file. + 2. For macOS this is the .pkg file (make sure to get the correct one for if you are running an x86 or Apple Silicon Mac). + 3. For debian based linux you can run `sudo apt install gcc-arm-non-eabi` and skip downloading from the website. +3. Run the installer. On windows when prompted at the end deselect all boxes except for `Add to path` + +#### JLink + +Segger's JLink tools are necessary to program and debug the board. + +1. Go to the page for the [J-Link Downloads](https://www.segger.com/downloads/jlink/) +2. Download the latest version of J-Link for your operating system. +3. Run the installer +4. When prompted to choose a destination select `Update existing install` even if don't have J-Link already installed. + +#### Git + +Git is the version control platform used to keep track of the project files. Follow the installation instructions for git from the [git-scm](https://git-scm.com/downloads) for your operating system. + +##### Windows Specific Instructions + +1. Download the latest version of git for windows from the [git-scm's download page](https://git-scm.com/download/win). +2. Run the installer +3. When prompted to select an editor for git to use, unless you are already familiar with Vim, it is **highly recommended** to switch to an editor you are familiar and comfortable with. +4. It is recommended to install the [Windows Terminal App](https://apps.microsoft.com/detail/9n0dx20hk701) from the Microsoft Store diff --git a/docs/vscode.md b/docs/vscode.md new file mode 100644 index 0000000..852f871 --- /dev/null +++ b/docs/vscode.md @@ -0,0 +1,20 @@ + +# Visual Studio Code + +[TOC] + +## Introduction and Download + +Visual Studio Code is a popular, cross platform source-code editor made by Microsoft. It is the recommended editor for EiE, although any other editor may work albeit without the debugger integration. VSCode can be downloaded from [Microsoft](https://visualstudio.microsoft.com/downloads/). + +## Extension Setup + +EIE has a number of recommended extensions for VSCode. These can be found by searching `@recommended` in the extensions tab on the side bar. Install all the extensions under the Workspace Recommendations dropdown. + +If you are unfamiliar with VScode extensions please see [Microsoft's Documentation](https://code.visualstudio.com/docs/editor/extension-marketplace). + +## Debugger + +After installing the recommended extensions the VScode debugger should work to enable step through debugging on hardware. In the Run and Debug tab on the sidebar the debug profile can be set as either `Debug ASCII Board` or `Debug Dot Matrix Board` to debug your hardware. + +If you are unfamiliar with the VScode debugger please see [Microsoft's Documentation](https://code.visualstudio.com/docs/editor/debugging). diff --git a/firmware_ascii/bsp/eief1-pcb-01.c b/firmware_ascii/bsp/eief1-pcb-01.c index 3eed821..7402354 100644 --- a/firmware_ascii/bsp/eief1-pcb-01.c +++ b/firmware_ascii/bsp/eief1-pcb-01.c @@ -124,22 +124,23 @@ void WatchDogSetup(void) */ void ClockSetup(void) { - /* Set flash wait states to allow 48 MHz system clock (2 wait states required) */ - AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS; - - /* Activate the peripheral clocks needed for the system */ - AT91C_BASE_PMC->PMC_PCER = PMC_PCER_INIT; - /* Enable the master clock on the PKC0 clock out pin (PA_27_CLOCK_OUT) */ AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_SYS_CLK | AT91C_PMC_PRES_CLK; AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0; + while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_PCKRDY0) ); /* Turn on the main oscillator and wait for it to start up */ AT91C_BASE_PMC->PMC_MOR = PMC_MOR_INIT; while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) ); - /* Assign main clock as crystal */ + /* Assign main clock as crystal and wait for switch */ AT91C_BASE_PMC->PMC_MOR |= (AT91C_CKGR_MOSCSEL | MOR_KEY); + while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) ); + + /* Set flash wait states to allow 48 MHz system clock (2 wait states required) */ + /* Note: There is an errata where the flash controller can't operate at sub-5 Mhz with + wait states programmed, so this must be done after the clock is bumped to 12 Mhz*/ + AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS; /* Initialize PLLA and wait for lock */ AT91C_BASE_PMC->PMC_PLLAR = PMC_PLAAR_INIT; @@ -154,6 +155,10 @@ void ClockSetup(void) /* Initialize UTMI for USB usage */ AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) ); + + /* Activate the peripheral clocks needed for the system, must be done + last to ensure all clock sources are valid before clocking periphs. */ + AT91C_BASE_PMC->PMC_PCER = PMC_PCER_INIT; } /* end ClockSetup */ diff --git a/firmware_ascii/bsp/eief1-pcb-01.h b/firmware_ascii/bsp/eief1-pcb-01.h index 3772190..f0bbaf8 100644 --- a/firmware_ascii/bsp/eief1-pcb-01.h +++ b/firmware_ascii/bsp/eief1-pcb-01.h @@ -391,7 +391,7 @@ counter must be set at 1280. */ #define MOR_KEY (u32)(0x37 << 16) -#define PMC_MOR_INIT (u32)0x0037F019 +#define PMC_MOR_INIT (u32)0x0037F009 /* 31 [0] Reserved 30 [0] " @@ -424,9 +424,9 @@ counter must be set at 1280. */ 08 [0] " 07 [0] Reserved - 06 [0] MOSCRCF 8MHz + 06 [0] MOSCRCF 4MHz (Keep at 4 to match startup) 05 [0] " - 04 [1] " + 04 [0] " 03 [1] MOSCRCEN main on-chip RC osc is on for now 02 [0] WAITMODE disabled @@ -1616,7 +1616,7 @@ Tdiv_slclk = 2*(DIV+1)*Tslow_clock. */ /* PIO Write Protect Mode Register PIO_WPMR -Enables the Write Protect if WPKEY corresponds to 0x50494F (PIO in ASCII). +Enables the Write Protect if WPKEY corresponds to 0x50494F ("PIO" in ASCII). Though this is defined in the user guide, there is no definition in the processor header file. We don't want to lock access to the GPIO registers anyway, so we won't use this for now. */ diff --git a/firmware_ascii/iar_7_20_1/eie_ascii-01.1.ewp b/firmware_ascii/iar_7_20_1/eie_ascii-01.1.ewp deleted file mode 100644 index 8c527ae..0000000 --- a/firmware_ascii/iar_7_20_1/eie_ascii-01.1.ewp +++ /dev/null @@ -1,1991 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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Breakpoints - Breakpoints - - - - 0 - - - TabID-24281-12506 - Workspace - Workspace - - - eie_ascii-01eie_ascii-01/Applicationeie_ascii-01/Application/Sourceeie_ascii-01/_Driverseie_ascii-01/_Drivers/Source - - - - 0 - - - TabID-16962-12643 - Memory - Memory - - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - TabID-16439-12653 - Symbolic Memory - SymbolicMemory - - - - TabID-2261-12509 - Disassembly - Disassembly - - - - - 2 - - - TabID-5168-12659 - Register - Register - - - - - - 0000 - - - TabID-4122-12679 - Watch 1 - WATCH_1 - - - TabID-3599-12689 - Watch 2 - WATCH_2 - - - TabID-22482-12744 - Call Stack - CallStack - - - TabID-10688-12761 - Stack 1 - STACK_1 - - - - - 0 - - - TabID-4645-12669 - Register - Register - - 0 - 0 - 0 - 0 - - - - TabID-13825-12702 - Watch 3 - WATCH_3 - - - TabID-24051-12715 - Watch 4 - WATCH_4 - - - TabID-23528-12725 - Locals - Locals - - - - 1 - - - - - - - TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.c000002128792897TextEditor$WS_DIR$\..\application\main.c00000252579257910TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.h0000019000541492100000045850710000004 - - - - - - - iaridepm.enu1debuggergui.enu1armjlink.enu1-2-2740308-2-2200200104167198610161458736842-2-2341419-2-22002001041671986102192713406160001828743529-2339200200104167198610219271398213-2-2198961-2-296320050156319861010416719861000997224547775643904959-2963200501563198610104167198610 - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.1.wsdt b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.1.wsdt deleted file mode 100644 index e98a924..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.1.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - eie_ascii-01/Debug - - - - - - - - - 270272727 - - 2613913719256994854379 - - - - - - TabID-15058-8790 - Workspace - Workspace - - - eie_ascii-01eie_ascii-01/Applicationeie_ascii-01/Application/Sourceeie_ascii-01/_BSPeie_ascii-01/_BSP/Sourceeie_ascii-01/_Driverseie_ascii-01/_Drivers/Source - - - - 0TabID-25054-9012BuildBuildTabID-11420-10700Find in FilesFind-in-Files0 - - - - - - TextEditor$WS_DIR$\..\application\main.c000002525792579TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.c000001285585558510TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.h00000190005000005000005000005000004 - - - - - - - iaridepm.enu1-2-2565344-2-2160151104167198946225260747036-2-21491538-2-215401511002604198946104167198946 - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.cspy.ps1 b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.cspy.ps1 deleted file mode 100644 index d797cf0..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.cspy.ps1 +++ /dev/null @@ -1,31 +0,0 @@ -param([String]$debugfile = ""); - -# This powershell file has been generated by the IAR Embedded Workbench -# C - SPY Debugger, as an aid to preparing a command line for running -# the cspybat command line utility using the appropriate settings. -# -# Note that this file is generated every time a new debug session -# is initialized, so you may want to move or rename the file before -# making changes. -# -# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed -# by the name of the debug file (usually an ELF / DWARF or UBROF file). -# -# Read about available command line parameters in the C - SPY Debugging -# Guide. Hints about additional command line parameters that may be -# useful in specific cases : -# --download_only Downloads a code image without starting a debug -# session afterwards. -# --silent Omits the sign - on message. -# --timeout Limits the maximum allowed execution time. -# - - -if ($debugfile -eq "") -{ -& "C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\common\bin\cspybat" -f "D:\EiE\EiE_Git\Razor_Atmel\firmware_ascii\iar_7_20_1\settings\eie_ascii-01.Debug.general.xcl" --backend -f "D:\EiE\EiE_Git\Razor_Atmel\firmware_ascii\iar_7_20_1\settings\eie_ascii-01.Debug.driver.xcl" -} -else -{ -& "C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\common\bin\cspybat" -f "D:\EiE\EiE_Git\Razor_Atmel\firmware_ascii\iar_7_20_1\settings\eie_ascii-01.Debug.general.xcl" --debug_file=$debugfile --backend -f "D:\EiE\EiE_Git\Razor_Atmel\firmware_ascii\iar_7_20_1\settings\eie_ascii-01.Debug.driver.xcl" -} diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.driver.xcl b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.driver.xcl deleted file mode 100644 index c5e179f..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.driver.xcl +++ /dev/null @@ -1,29 +0,0 @@ -"--endian=little" - -"--cpu=Cortex-M3" - -"--fpu=None" - -"-p" - -"C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\CONFIG\debugger\Atmel\ATSAM3U2C.ddf" - -"--semihosting" - -"--device=ATSAM3U2C" - -"--drv_communication=USB0" - -"--drv_interface_speed=auto" - -"--jlink_initial_speed=32" - -"--jlink_reset_strategy=0,0" - -"--drv_catch_exceptions=0x000" - -"--drv_swo_clock_setup=72000000,0,2000000" - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.general.xcl b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.general.xcl deleted file mode 100644 index c51b462..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\bin\armproc.dll" - -"C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\bin\armjlink2.dll" - -"D:\EiE\EiE_Git\Razor_Atmel\firmware_ascii\iar_7_20_1\Debug\Exe\eie_ascii-01.out" - ---plugin "C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\bin\armbat.dll" - ---device_macro "C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\config\debugger\Atmel\SAM3U.dmac" - ---flash_loader "C:\Program Files (x86)\IAR Systems\EWARM_8_10_1\arm\config\flashloader\Atmel\sam3u2c\sam3u2c-flash.board" - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.crun b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.crun deleted file mode 100644 index ef39dce..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.crun +++ /dev/null @@ -1,16 +0,0 @@ - - - - 1 - - - * - * - * - 0 - 1 - - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dbgdt b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dbgdt deleted file mode 100644 index 2934d35..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dbgdt +++ /dev/null @@ -1,343 +0,0 @@ - - - - - - - - - 271854 - - 27 - 1390 - 370 - 92 - - - - - - - - 234272727 - - - - - - Disassembly_I0 - - - - 50020 - - - - 11 - - - - - Breakpoint_I0 - - - - 50035 - - - 1 - 0 - - - - Data - Location - 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- - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dni b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dni deleted file mode 100644 index 66483cc..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.dni +++ /dev/null @@ -1,72 +0,0 @@ -[Stack] -FillEnabled=0 -OverflowWarningsEnabled=1 -WarningThreshold=90 -SpWarningsEnabled=1 -WarnLogOnly=1 -UseTrigger=1 -TriggerName=main -LimitSize=0 -ByteLimit=50 -[DebugChecksum] -Checksum=-1739378130 -[Exceptions] -StopOnUncaught=_ 0 -StopOnThrow=_ 0 -[CodeCoverage] -Enabled=_ 0 -[CallStack] -ShowArgs=0 -[Disassembly] -MixedMode=1 -[JLinkDriver] -CStepIntDis=_ 0 -TraceBufferSize=0x00010000 -TraceStallIfFIFOFull=0x00000000 -TracePortSize=0x00000000 -[InterruptLog] -LogEnabled=0 -SumEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -ShowTimeSum=1 -SumSortOrder=0 -[DataLog] -LogEnabled=0 -SumEnabled=0 -GraphEnabled=0 -ShowTimeLog=1 -ShowTimeSum=1 -[Interrupts] -Enabled=1 -[MemConfig] -Base=1 -Manual=0 -Ddf=1 -TypeViol=0 -Stop=1 -[Simulator] -Freq=10000000 -MultiCoreRunAll=1 -[Log file] -LoggingEnabled=_ 0 -LogFile=_ "" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[CallStackLog] -Enabled=0 -[DriverProfiling] -Enabled=0 -Mode=1 -Graph=0 -Symbiont=0 -Exclusions= -[Disassemble mode] -mode=0 -[Breakpoints2] -Count=0 -[Aliases] -Count=0 -SuppressDialog=0 diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.wsdt b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.wsdt deleted file mode 100644 index 132ba3f..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - eie_ascii-01/Debug - - - - - - - - - 270272727 - - 2613913719256994854379 - - - - - - TabID-15058-8790 - Workspace - Workspace - - - eie_ascii-01eie_ascii-01/Applicationeie_ascii-01/Application/Source - - - - 0TabID-25054-9012BuildBuildTabID-11420-10700Find in FilesFind-in-Files0 - - - - - - TextEditor$WS_DIR$\..\..\firmware_common\application\main.c0000031259725970TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.c000000000TextEditor$WS_DIR$\..\..\firmware_common\application\user_app1.h0000014774770524142100000047585710000004 - - - - - - - iaridepm.enu1-2-2872344-2-216017483333150259180208754750-2-22411922-2-21924243100208320984583333150259 - - - - diff --git a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01_Debug.jlink b/firmware_ascii/iar_7_20_1/settings/eie_ascii-01_Debug.jlink deleted file mode 100644 index 39b6d05..0000000 --- a/firmware_ascii/iar_7_20_1/settings/eie_ascii-01_Debug.jlink +++ /dev/null @@ -1,39 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -MonModeVTableAddr = 0xFFFFFFFF -MonModeDebug = 0 -MaxNumAPs = 0 -LowPowerHandlingMode = 0 -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="ARM7" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/firmware_ascii/iar_7_20_1/settings/mpgl1-efmw-01.crun b/firmware_ascii/iar_7_20_1/settings/mpgl1-efmw-01.crun deleted file mode 100644 index ef39dce..0000000 --- a/firmware_ascii/iar_7_20_1/settings/mpgl1-efmw-01.crun +++ /dev/null @@ -1,16 +0,0 @@ - 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- - $PROJ_DIR$\..\..\firmware_common\application\debug.h - - - $PROJ_DIR$\..\..\firmware_common\application\main.h - - - $PROJ_DIR$\..\..\firmware_common\application\music.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\application\blade\blade_api.c - - - $PROJ_DIR$\..\..\firmware_common\application\debug.c - - - $PROJ_DIR$\..\..\firmware_common\application\main.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.c - - - - diff --git a/firmware_ascii/iar_8_10_1/eie_ascii-01.eww b/firmware_ascii/iar_8_10_1/eie_ascii-01.eww deleted file mode 100644 index 295d4c0..0000000 --- a/firmware_ascii/iar_8_10_1/eie_ascii-01.eww +++ /dev/null @@ -1,7 +0,0 @@ - - - - $WS_DIR$\eie_ascii-01.ewp - - - diff --git a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.cspy.ps1 b/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.cspy.ps1 deleted file mode 100644 index 0882699..0000000 --- a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.cspy.ps1 +++ /dev/null @@ -1,31 +0,0 @@ -param([String]$debugfile = ""); - -# This powershell file has been generated by the IAR Embedded Workbench -# C - SPY Debugger, as an aid to preparing a command line for running -# the cspybat command line utility using the appropriate settings. -# -# Note that this file is generated every time a new debug session -# is initialized, so you may want to move or rename the file before -# making changes. -# -# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed -# by the name of the debug file (usually an ELF / DWARF or UBROF file). -# -# Read about available command line parameters in the C - SPY Debugging -# Guide. Hints about additional command line parameters that may be -# useful in specific cases : -# --download_only Downloads a code image without starting a debug -# session afterwards. -# --silent Omits the sign - on message. -# --timeout Limits the maximum allowed execution time. -# - - -if ($debugfile -eq "") -{ -& "D:\IAR\EWARM_8_10_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_ascii\iar_8_10_1\settings\eie_ascii-01.Debug.general.xcl" --backend -f "E:\Github\razor_sam3u2\firmware_ascii\iar_8_10_1\settings\eie_ascii-01.Debug.driver.xcl" -} -else -{ -& "D:\IAR\EWARM_8_10_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_ascii\iar_8_10_1\settings\eie_ascii-01.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Github\razor_sam3u2\firmware_ascii\iar_8_10_1\settings\eie_ascii-01.Debug.driver.xcl" -} diff --git a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.driver.xcl b/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.driver.xcl deleted file mode 100644 index 48d076a..0000000 --- a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.driver.xcl +++ /dev/null @@ -1,29 +0,0 @@ -"--endian=little" - -"--cpu=Cortex-M3" - -"--fpu=None" - -"-p" - -"D:\IAR\EWARM_8_10_1\arm\CONFIG\debugger\Atmel\ATSAM3U2C.ddf" - -"--semihosting" - -"--device=ATSAM3U2C" - -"--drv_communication=USB0" - -"--drv_interface_speed=auto" - -"--jlink_initial_speed=32" - -"--jlink_reset_strategy=0,0" - -"--drv_catch_exceptions=0x000" - -"--drv_swo_clock_setup=72000000,0,2000000" - - - - diff --git a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.general.xcl b/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.general.xcl deleted file mode 100644 index 66c2d55..0000000 --- a/firmware_ascii/iar_8_10_1/settings/eie_ascii-01.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"D:\IAR\EWARM_8_10_1\arm\bin\armproc.dll" - -"D:\IAR\EWARM_8_10_1\arm\bin\armjlink2.dll" - -"E:\Github\razor_sam3u2\firmware_ascii\iar_8_10_1\Debug\Exe\eie_ascii-01.out" - ---plugin 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$PROJ_DIR$\..\..\firmware_common\application\blade\blade_api.c - - - $PROJ_DIR$\..\..\firmware_common\application\debug.c - - - $PROJ_DIR$\..\..\firmware_common\application\main.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.c - - - - diff --git a/firmware_ascii/iar_9_40_1/eie_ascii-01.ewt b/firmware_ascii/iar_9_40_1/eie_ascii-01.ewt deleted file mode 100644 index db60794..0000000 --- a/firmware_ascii/iar_9_40_1/eie_ascii-01.ewt +++ /dev/null @@ -1,3046 +0,0 @@ - - - 4 - - Debug - - ARM - - 1 - - C-STAT - 517 - - 517 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - Debug/C-STAT - - - 2.5.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - Release - - ARM - - 0 - - C-STAT - 517 - - 517 - - 0 - - 1 - 600 - 0 - 2 - 0 - 1 - 100 - Release/C-STAT - - - 2.5.1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - RuntimeChecking - 0 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - _BSP - - Includes - - $PROJ_DIR$\..\..\firmware_common\bsp\AT91SAM3U4.h - - - $PROJ_DIR$\..\..\firmware_common\bsp\configuration.h - - - $PROJ_DIR$\..\bsp\eief1-pcb-01.h - - - $PROJ_DIR$\..\..\firmware_common\bsp\sam3u2-flash.icf - - - $PROJ_DIR$\..\..\firmware_common\bsp\typedefs.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\bsp\board_cstartup_iar.c - - - $PROJ_DIR$\..\bsp\eief1-pcb-01.c - - - $PROJ_DIR$\..\..\firmware_common\bsp\kill_x_cycles.s - - - - - _CMSIS - - $PROJ_DIR$\..\..\firmware_common\cmsis\core_cm3.h - - - - _Drivers - - Include - - $PROJ_DIR$\..\..\firmware_common\drivers\adc12.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant_api.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\antdefines.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\antmessage.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\buttons.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\exceptions.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\interrupts.h - - - $PROJ_DIR$\..\drivers\lcd_nhd-c0220biz.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\leds.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\messaging.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_i2c.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_spi.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_ssp.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_uart.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\timer.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\utilities.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\drivers\adc12.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant_api.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\buttons.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\exceptions.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\interrupts.c - - - $PROJ_DIR$\..\drivers\lcd_nhd-c0220biz.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\leds.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\messaging.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_i2c.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_spi.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_ssp.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\sam3u_uart.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\timer.c - - - $PROJ_DIR$\..\..\firmware_common\drivers\utilities.c - - - - - Application - - Include - - $PROJ_DIR$\..\..\firmware_common\application\blade\blade_api.h - - - $PROJ_DIR$\..\..\firmware_common\application\debug.h - - - $PROJ_DIR$\..\..\firmware_common\application\main.h - - - $PROJ_DIR$\..\..\firmware_common\application\music.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\application\blade\blade_api.c - - - $PROJ_DIR$\..\..\firmware_common\application\debug.c - - - $PROJ_DIR$\..\..\firmware_common\application\main.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.c - - - - diff --git a/firmware_ascii/iar_9_40_1/eie_ascii-01.eww b/firmware_ascii/iar_9_40_1/eie_ascii-01.eww deleted file mode 100644 index 295d4c0..0000000 --- a/firmware_ascii/iar_9_40_1/eie_ascii-01.eww +++ /dev/null @@ -1,7 +0,0 @@ - - - - $WS_DIR$\eie_ascii-01.ewp - - - diff --git a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.cspy.ps1 b/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.cspy.ps1 deleted file mode 100644 index 39d79a3..0000000 --- a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.cspy.ps1 +++ /dev/null @@ -1,31 +0,0 @@ -param([String]$debugfile = ""); - -# This powershell file has been generated by the IAR Embedded Workbench -# C - SPY Debugger, as an aid to preparing a command line for running -# the cspybat command line utility using the appropriate settings. -# -# Note that this file is generated every time a new debug session -# is initialized, so you may want to move or rename the file before -# making changes. -# -# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed -# by the name of the debug file (usually an ELF / DWARF or UBROF file). -# -# Read about available command line parameters in the C - SPY Debugging -# Guide. Hints about additional command line parameters that may be -# useful in specific cases : -# --download_only Downloads a code image without starting a debug -# session afterwards. -# --silent Omits the sign - on message. -# --timeout Limits the maximum allowed execution time. -# - - -if ($debugfile -eq "") -{ -& "D:\IAR\EWARM_9_40_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_ascii\iar_9_40_1\settings\eie_ascii-01.Debug.general.xcl" --backend -f "E:\Github\razor_sam3u2\firmware_ascii\iar_9_40_1\settings\eie_ascii-01.Debug.driver.xcl" -} -else -{ -& "D:\IAR\EWARM_9_40_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_ascii\iar_9_40_1\settings\eie_ascii-01.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Github\razor_sam3u2\firmware_ascii\iar_9_40_1\settings\eie_ascii-01.Debug.driver.xcl" -} diff --git a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.driver.xcl b/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.driver.xcl deleted file mode 100644 index fd0da0e..0000000 --- a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.driver.xcl +++ /dev/null @@ -1,29 +0,0 @@ -"--endian=little" - -"--cpu=Cortex-M3" - -"--fpu=None" - -"-p" - -"D:\IAR\EWARM_9_40_1\arm\config\debugger\Microchip\ATSAM3U2C.ddf" - -"--semihosting" - -"--device=ATSAM3U2C" - -"--drv_communication=USB0" - -"--drv_interface_speed=auto" - -"--jlink_initial_speed=32" - -"--jlink_reset_strategy=0,0" - -"--drv_catch_exceptions=0x000" - -"--drv_swo_clock_setup=72000000,0,2000000" - - - - diff --git a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.general.xcl b/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.general.xcl deleted file mode 100644 index 903e8c1..0000000 --- a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"D:\IAR\EWARM_9_40_1\arm\bin\armPROC.dll" - -"D:\IAR\EWARM_9_40_1\arm\bin\armJLINK.dll" - -"E:\Github\razor_sam3u2\firmware_ascii\iar_9_40_1\Debug\Exe\eie_ascii-01.out" - ---plugin="D:\IAR\EWARM_9_40_1\arm\bin\armbat.dll" - ---device_macro="D:\IAR\EWARM_9_40_1\arm/config/debugger/Microchip/SAM3U.dmac" - ---flash_loader="D:\IAR\EWARM_9_40_1\arm/config/flashloader/Microchip/sam3u2/sam3u2-flash.board" - - - - diff --git a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.crun b/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.crun deleted file mode 100644 index d71ea55..0000000 --- a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.crun +++ /dev/null @@ -1,13 +0,0 @@ - - - 1 - - - * - * - * - 0 - 1 - - - diff --git a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.dbgdt b/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.dbgdt deleted file mode 100644 index 48ee03b..0000000 --- a/firmware_ascii/iar_9_40_1/settings/eie_ascii-01.dbgdt +++ /dev/null @@ -1,1474 +0,0 @@ - - - - - 34048 - 34049 - 34050 - 34051 - 34052 - 34053 - 34054 - 34055 - 34056 - 34057 - 34058 - 34059 - 34060 - 34061 - 34062 - 34063 - 34064 - 34065 - 34066 - 34067 - 34068 - 34069 - 34070 - 34071 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"" -Category=_ 0 -[TermIOLog] -LoggingEnabled=_ 0 -LogFile=_ "" -[CallStackLog] -Enabled=0 -[DriverProfiling] -Enabled=0 -Mode=1 -Graph=0 -Symbiont=0 -Exclusions= -[Disassemble mode] -mode=0 -[Breakpoints2] -Bp0=_ 0 "EMUL_CODE" "{$PROJ_DIR$\..\..\firmware_mpg_common\application\user_app1.c}.155.1" 0 0 1 "" 0 "" 0 -Bp1=_ 0 "EMUL_CODE" "{$PROJ_DIR$\..\..\firmware_mpg_common\application\user_app1.c}.155.1" 0 0 1 "" 0 "" 0 -Count=2 -[Aliases] -Count=0 -SuppressDialog=0 diff --git a/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01.wsdt b/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01.wsdt deleted file mode 100644 index cce8414..0000000 --- a/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01.wsdt +++ /dev/null @@ -1,49 +0,0 @@ - - - - - - mpgl1-efmw-01/Debug - - - - - - - - - 300272727 - - 5699485437928138937092664941138 - - - - - - TabID-21633-19057 - Workspace - Workspace - - - mpgl1-efmw-01mpgl1-efmw-01/Applicationmpgl1-efmw-01/Application/Includempgl1-efmw-01/Application/Sourcempgl1-efmw-01/_BSPmpgl1-efmw-01/_BSP/Sourcempgl1-efmw-01/_Driversmpgl1-efmw-01/_Drivers/Includempgl1-efmw-01/_Drivers/Source - - - - 0TabID-3863-12208Find in FilesFind-in-FilesTabID-23376-31697BuildBuildTabID-16456-8475Ambiguous DefinitionsSelect-Ambiguous-Definitions1 - - - - - - TextEditor$WS_DIR$\..\application\main.c000002419971997TextEditor$WS_DIR$\..\..\firmware_common\drivers\ant.c00000504222732227310580222100000041977710000004 - - - - - - - iaridepm.enu1-2-2782391-2-2200194104167192651204688778550-2-21801922-2-219241821002083180735104167192651 - - - - diff --git a/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01_Debug.jlink b/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01_Debug.jlink deleted file mode 100644 index f40a58f..0000000 --- a/firmware_ascii/iar_9_40_1/settings/mpgl1-efmw-01_Debug.jlink +++ /dev/null @@ -1,34 +0,0 @@ -[BREAKPOINTS] -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="UNSPECIFIED" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/firmware_common/application/blade/blade_imu_lsm6dsl.c b/firmware_common/application/blade/blade_imu_lsm6dsl.c index c842009..49463fb 100644 --- a/firmware_common/application/blade/blade_imu_lsm6dsl.c +++ b/firmware_common/application/blade/blade_imu_lsm6dsl.c @@ -1,5 +1,5 @@ /*!********************************************************************************************************************* -@file blade_imu_lsm6dsl.c +@file blade_imu_lsm6dsl.c @brief Driver for ST LSM6DSL IMU. Provides configuration service and up to 1kHz of 3-axis acceleration, gyro, and compass data. @@ -31,6 +31,7 @@ PROTECTED FUNCTIONS **********************************************************************************************************************/ #include "configuration.h" +#include "blade_imu_lsm6dsl.h" /*********************************************************************************************************************** @@ -62,12 +63,12 @@ Function Definitions **********************************************************************************************************************/ /*--------------------------------------------------------------------------------------------------------------------*/ -/*! @publicsection */ +/*! @publicsection */ /*--------------------------------------------------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------------------------------------------------*/ -/*! @protectedsection */ +/*! @protectedsection */ /*--------------------------------------------------------------------------------------------------------------------*/ /*!-------------------------------------------------------------------------------------------------------------------- @@ -87,7 +88,7 @@ to update and display the data received. This rate *should* be ok for the LCD r debug output. Requires: -- Blade pins (at least for IC comms) are configured) +- Blade pins (at least for I�C comms) are configured) Promises: - Presence of IMU is determined; if present, default configuration is set up. @@ -114,7 +115,7 @@ void Bladelsm6dslInitialize(void) G_u32Bladelsm6dslData.u8AccelYH = 0; G_u32Bladelsm6dslData.u8AccelZL = 0; G_u32Bladelsm6dslData.u8AccelZH = 0; - + /* Blade resource requests: I2C SCL, SDA, IO2 and IO3 interrupt lines */ eErrorStatus += BladeRequestPin(BLADE_PIN2, DIGITAL_IN); eErrorStatus += BladeRequestPin(BLADE_PIN3, DIGITAL_IN); @@ -122,13 +123,13 @@ void Bladelsm6dslInitialize(void) eErrorStatus += BladeRequestPin(BLADE_PIN9, PERIPHERAL); if(eErrorStatus) { - DebugPrintf("LSM6DSL Blade pin resources not available\n\r"); + DebugPrintf("LSM6DSL Blade pin resources not available\n\r"); } else { - DebugPrintf("LSM6DSL Blade pin resources allocated\n\r"); + DebugPrintf("LSM6DSL Blade pin resources allocated\n\r"); } - + /* Ping the accelerometer to check it's responding by reading its ID byte */ TwiWriteReadData(U8_LSM6DSL_I2C_ADDRESS, U8_WHO_AM_I, &u8RxMessage, 1); if(u8RxMessage != U8_LSM6DSL_ID) @@ -141,11 +142,11 @@ void Bladelsm6dslInitialize(void) DebugPrintf("LSM6DSL returned ID: "); DebugPrintNumber(u8RxMessage); DebugLineFeed(); - + /* Send basic configuration - the two registers are sequential so can be done in a single write */ TwiWriteData(U8_LSM6DSL_I2C_ADDRESS, 3, au8TxMessage, TWI_STOP); } - + /* If good initialization, set state to Idle */ if( eErrorStatus == SUCCESS ) { @@ -160,7 +161,7 @@ void Bladelsm6dslInitialize(void) } /* end Bladelsm6dslInitialize() */ - + /*!---------------------------------------------------------------------------------------------------------------------- @fn void Bladelsm6dslRunActiveState(void) @@ -184,7 +185,7 @@ void Bladelsm6dslRunActiveState(void) /*------------------------------------------------------------------------------------------------------------------*/ -/*! @privatesection */ +/*! @privatesection */ /*--------------------------------------------------------------------------------------------------------------------*/ @@ -206,17 +207,17 @@ static void Bladelsm6dslSM_Idle(void) u8* pu8NumberParser; u8* pu8StringParser; u8 u8Digits; - + /* Read the latest IMU data if it's time */ if( IsTimeUp(&Bladelsm6dsl_u32Timeout, U32_MEASUREMENT_RATE_MS) ) { Bladelsm6dsl_u32Timeout = G_u32SystemTime1ms; TwiWriteReadData(U8_LSM6DSL_I2C_ADDRESS, U8_OUT_TEMP_L, &G_u32Bladelsm6dslData.u8TempL, 14); - + /* Write data to debug this will be 1 write behind newest data since the command will not yet be queued */ pu8NumberIndex = &G_u32Bladelsm6dslData.u8TempL; pu8StringParser = au8Outputmessage; - + for(u8 i = 0; i < 7; i++) { u32Number = 0; @@ -226,7 +227,7 @@ static void Bladelsm6dslSM_Idle(void) pu8NumberIndex++; u8Digits = NumberToAscii(u32Number, au8NumberString); pu8NumberParser = au8NumberString; - + /* Copy ASCII number into result string including leading 0s */ u8Digits = 5 - u8Digits; for(u8 j= 0; j < u8Digits; j++) @@ -241,22 +242,22 @@ static void Bladelsm6dslSM_Idle(void) pu8StringParser++; pu8NumberParser++; } - + /* Skip the space */ pu8StringParser++; } /* end for(u8 i = 0; i < 7; i++) */ - + DebugPrintf(au8Outputmessage); } /* end if( IsTimeUp(&Bladelsm6dsl_u32Timeout, U32_MEASUREMENT_RATE_MS) ) */ - + } /* end Bladelsm6dslSM_Idle() */ - + /*-------------------------------------------------------------------------------------------------------------------*/ /* Handle an error */ -static void Bladelsm6dslSM_Error(void) +static void Bladelsm6dslSM_Error(void) { - + } /* end Bladelsm6dslSM_Error() */ diff --git a/firmware_common/application/main.c b/firmware_common/application/main.c index 4212aae..7088bad 100644 --- a/firmware_common/application/main.c +++ b/firmware_common/application/main.c @@ -40,7 +40,7 @@ Variable names shall start with "Main_" and be declared as static. /*!--------------------------------------------------------------------------------------------------------------------- -@fn void main(void) +@fn int main(void) @brief Main program where all tasks are initialized and executed. Requires: @@ -50,7 +50,7 @@ Variable names shall start with "Main_" and be declared as static. - NONE */ -void main(void) +int main(void) { G_u32SystemFlags |= _SYSTEM_INITIALIZING; @@ -83,7 +83,7 @@ void main(void) #ifdef EIE_ASCII #endif /* EIE_ASCII */ -#ifdef EIE_DOTMATRIX +#if defined(EIE_DOTMATRIX) && !defined(EIE_NO_CAPTOUCH) CapTouchInitialize(); #endif /* EIE_DOTMATRIX */ @@ -123,7 +123,7 @@ void main(void) #ifdef EIE_ASCII #endif /* EIE_ASCII */ -#ifdef EIE_DOTMATRIX +#if defined(EIE_DOTMATRIX) && !defined(EIE_NO_CAPTOUCH) CapTouchRunActiveState(); #endif /* EIE_DOTMATRIX */ diff --git a/firmware_common/bsp/ATSAM3U2C.svd b/firmware_common/bsp/ATSAM3U2C.svd new file mode 100644 index 0000000..c6fe971 --- /dev/null +++ b/firmware_common/bsp/ATSAM3U2C.svd @@ -0,0 +1,61859 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3U2C + SAM3U + 0 + Atmel ATSAM3U2C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449L + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 17 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + MCI_SDIOIRQA + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + BLKOVRE + DMA Block Overrun Error + 24 + 1 + read-only + + + DMADONE + DMA Transfer done + 25 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + MCI_SDIOIRQA + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + BLKOVRE + DMA Block Overrun Error Interrupt Enable + 24 + 1 + write-only + + + DMADONE + DMA Transfer completed Interrupt Enable + 25 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + MCI_SDIOIRQA + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + BLKOVRE + DMA Block Overrun Error Interrupt Disable + 24 + 1 + write-only + + + DMADONE + DMA Transfer completed Interrupt Disable + 25 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + MCI_SDIOIRQA + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + BLKOVRE + DMA Block Overrun Error Interrupt Mask + 24 + 1 + read-only + + + DMADONE + DMA Transfer Completed Interrupt Mask + 25 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + DMA + DMA Configuration Register + 0x00000050 + 32 + read-write + 0x00000000 + + + OFFSET + DMA Write Buffer Offset + 0 + 2 + read-write + + + CHKSIZE + DMA Channel Read and Write Chunk Size + 4 + 3 + read-write + + + DMAEN + DMA Hardware Handshaking Enable + 8 + 1 + read-write + + + ROPT + Read Optimization with padding + 12 + 1 + read-write + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x4D4349 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WPVS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (HSMCI_WPSR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WPVSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + DATA + Data to Read or Data to Write + 0 + 32 + read-write + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + + + TC0 + 6082ZF + Timer Counter 0 + TC + TC0_ + 0x40080000 + + 0 + 0x4000 + registers + + + TC0 + 22 + + + TC1 + 23 + + + TC2 + 24 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVEFORM_MODE + Channel Mode Register (channel = 0) + WAVEFORM_MODE + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status (cleared on read) + 0 + 1 + read-only + + + LOVRS + Load Overrun Status (cleared on read) + 1 + 1 + read-only + + + CPAS + RA Compare Status (cleared on read) + 2 + 1 + read-only + + + CPBS + RB Compare Status (cleared on read) + 3 + 1 + read-only + + + CPCS + RC Compare Status (cleared on read) + 4 + 1 + read-only + + + LDRAS + RA Loading Status (cleared on read) + 5 + 1 + read-only + + + LDRBS + RB Loading Status (cleared on read) + 6 + 1 + read-only + + + ETRGS + External Trigger Status (cleared on read) + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVEFORM_MODE + Channel Mode Register (channel = 1) + WAVEFORM_MODE + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status (cleared on read) + 0 + 1 + read-only + + + LOVRS + Load Overrun Status (cleared on read) + 1 + 1 + read-only + + + CPAS + RA Compare Status (cleared on read) + 2 + 1 + read-only + + + CPBS + RB Compare Status (cleared on read) + 3 + 1 + read-only + + + CPCS + RC Compare Status (cleared on read) + 4 + 1 + read-only + + + LDRAS + RA Loading Status (cleared on read) + 5 + 1 + read-only + + + LDRBS + RB Loading Status (cleared on read) + 6 + 1 + read-only + + + ETRGS + External Trigger Status (cleared on read) + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVEFORM_MODE + Channel Mode Register (channel = 2) + WAVEFORM_MODE + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: internal MCK/2 clock signal (from PMC) + 0x0 + + + TIMER_CLOCK2 + Clock selected: internal MCK/8 clock signal (from PMC) + 0x1 + + + TIMER_CLOCK3 + Clock selected: internal MCK/32 clock signal (from PMC) + 0x2 + + + TIMER_CLOCK4 + Clock selected: internal MCK/128 clock signal (from PMC) + 0x3 + + + TIMER_CLOCK5 + Clock selected: internal SLCK clock signal (from PMC) + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status (cleared on read) + 0 + 1 + read-only + + + LOVRS + Load Overrun Status (cleared on read) + 1 + 1 + read-only + + + CPAS + RA Compare Status (cleared on read) + 2 + 1 + read-only + + + CPBS + RB Compare Status (cleared on read) + 3 + 1 + read-only + + + CPCS + RC Compare Status (cleared on read) + 4 + 1 + read-only + + + LDRAS + RA Loading Status (cleared on read) + 5 + 1 + read-only + + + LDRBS + RB Loading Status (cleared on read) + 6 + 1 + read-only + + + ETRGS + External Trigger Status (cleared on read) + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA0 + Signal connected to XC2: TIOA0 + 0x2 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x3 + + + + + QDEN + Quadrature Decoder Enabled + 8 + 1 + read-write + + + POSEN + Position Enabled + 9 + 1 + read-write + + + SPEEDEN + Speed Enabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding Transparent + 11 + 1 + read-write + + + EDGPHA + Edge on PHA Count Mode + 12 + 1 + read-write + + + INVA + Inverted PHA + 13 + 1 + read-write + + + INVB + Inverted PHB + 14 + 1 + read-write + + + INVIDX + Inverted Index + 15 + 1 + read-write + + + SWAP + Swap PHA and PHB + 16 + 1 + read-write + + + IDXPHB + Index Pin is PHB Pin + 17 + 1 + read-write + + + MAXFILT + Maximum Filter + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + Index + 0 + 1 + write-only + + + DIRCHG + Direction Change + 1 + 1 + write-only + + + QERR + Quadrature Error + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + Index + 0 + 1 + write-only + + + DIRCHG + Direction Change + 1 + 1 + write-only + + + QERR + Quadrature Error + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + Index + 0 + 1 + read-only + + + DIRCHG + Direction Change + 1 + 1 + read-only + + + QERR + Quadrature Error + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + Index + 0 + 1 + read-only + + + DIRCHG + Direction Change + 1 + 1 + read-only + + + QERR + Quadrature Error + 2 + 1 + read-only + + + DIR + Direction + 8 + 1 + read-only + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40084000 + + 0 + 0x4000 + registers + + + TWI0 + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x40088000 + + 0 + 0x4000 + registers + + + TWI1 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x4008C000 + + 0 + 0x4000 + registers + + + PWM + 25 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 3) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 3) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 3) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 3) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 3) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 3) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40090000 + + 0 + 0x4000 + registers + + + USART0 + 13 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40094000 + + 0 + 0x4000 + registers + + + USART1 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART2 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 2 + USART + USART2_ + 0x40098000 + + 0 + 0x4000 + registers + + + USART2 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDPHS + 6227O + USB High Speed Device Port + UDPHS_ + 0x400A4000 + + 0 + 0x4000 + registers + + + UDPHS + 29 + + + + CTRL + UDPHS Control Register + 0x00000000 + 32 + read-write + 0x00000200 + + + DEV_ADDR + UDPHS Address + 0 + 7 + read-write + + + FADDR_EN + Function Address Enable + 7 + 1 + read-write + + + EN_UDPHS + UDPHS Enable + 8 + 1 + read-write + + + DETACH + Detach Command + 9 + 1 + read-write + + + REWAKEUP + Send Remote Wake Up + 10 + 1 + read-write + + + PULLD_DIS + Pull-Down Disable + 11 + 1 + read-write + + + + + FNUM + UDPHS Frame Number Register + 0x00000004 + 32 + read-only + 0x00000000 + + + MICRO_FRAME_NUM + Microframe Number + 0 + 3 + read-only + + + FRAME_NUMBER + Frame Number as defined in the Packet Field Formats + 3 + 11 + read-only + + + FNUM_ERR + Frame Number CRC Error + 31 + 1 + read-only + + + + + IEN + UDPHS Interrupt Enable Register + 0x00000010 + 32 + read-write + 0x00000010 + + + DET_SUSPD + Suspend Interrupt Enable + 1 + 1 + read-write + + + MICRO_SOF + Micro-SOF Interrupt Enable + 2 + 1 + read-write + + + INT_SOF + SOF Interrupt Enable + 3 + 1 + read-write + + + ENDRESET + End Of Reset Interrupt Enable + 4 + 1 + read-write + + + WAKE_UP + Wake Up CPU Interrupt Enable + 5 + 1 + read-write + + + ENDOFRSM + End Of Resume Interrupt Enable + 6 + 1 + read-write + + + UPSTR_RES + Upstream Resume Interrupt Enable + 7 + 1 + read-write + + + EPT_0 + Endpoint 0 Interrupt Enable + 8 + 1 + read-write + + + EPT_1 + Endpoint 1 Interrupt Enable + 9 + 1 + read-write + + + EPT_2 + Endpoint 2 Interrupt Enable + 10 + 1 + read-write + + + EPT_3 + Endpoint 3 Interrupt Enable + 11 + 1 + read-write + + + EPT_4 + Endpoint 4 Interrupt Enable + 12 + 1 + read-write + + + EPT_5 + Endpoint 5 Interrupt Enable + 13 + 1 + read-write + + + EPT_6 + Endpoint 6 Interrupt Enable + 14 + 1 + read-write + + + DMA_1 + DMA Channel 1 Interrupt Enable + 25 + 1 + read-write + + + DMA_2 + DMA Channel 2 Interrupt Enable + 26 + 1 + read-write + + + DMA_3 + DMA Channel 3 Interrupt Enable + 27 + 1 + read-write + + + DMA_4 + DMA Channel 4 Interrupt Enable + 28 + 1 + read-write + + + DMA_5 + DMA Channel 5 Interrupt Enable + 29 + 1 + read-write + + + DMA_6 + DMA Channel 6 Interrupt Enable + 30 + 1 + read-write + + + + + INTSTA + UDPHS Interrupt Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + SPEED + Speed Status + 0 + 1 + read-only + + + DET_SUSPD + Suspend Interrupt + 1 + 1 + read-only + + + MICRO_SOF + Micro Start Of Frame Interrupt + 2 + 1 + read-only + + + INT_SOF + Start Of Frame Interrupt + 3 + 1 + read-only + + + ENDRESET + End Of Reset Interrupt + 4 + 1 + read-only + + + WAKE_UP + Wake Up CPU Interrupt + 5 + 1 + read-only + + + ENDOFRSM + End Of Resume Interrupt + 6 + 1 + read-only + + + UPSTR_RES + Upstream Resume Interrupt + 7 + 1 + read-only + + + EPT_0 + Endpoint 0 Interrupt + 8 + 1 + read-only + + + EPT_1 + Endpoint 1 Interrupt + 9 + 1 + read-only + + + EPT_2 + Endpoint 2 Interrupt + 10 + 1 + read-only + + + EPT_3 + Endpoint 3 Interrupt + 11 + 1 + read-only + + + EPT_4 + Endpoint 4 Interrupt + 12 + 1 + read-only + + + EPT_5 + Endpoint 5 Interrupt + 13 + 1 + read-only + + + EPT_6 + Endpoint 6 Interrupt + 14 + 1 + read-only + + + DMA_1 + DMA Channel 1 Interrupt + 25 + 1 + read-only + + + DMA_2 + DMA Channel 2 Interrupt + 26 + 1 + read-only + + + DMA_3 + DMA Channel 3 Interrupt + 27 + 1 + read-only + + + DMA_4 + DMA Channel 4 Interrupt + 28 + 1 + read-only + + + DMA_5 + DMA Channel 5 Interrupt + 29 + 1 + read-only + + + DMA_6 + DMA Channel 6 Interrupt + 30 + 1 + read-only + + + + + CLRINT + UDPHS Clear Interrupt Register + 0x00000018 + 32 + write-only + + + DET_SUSPD + Suspend Interrupt Clear + 1 + 1 + write-only + + + MICRO_SOF + Micro Start Of Frame Interrupt Clear + 2 + 1 + write-only + + + INT_SOF + Start Of Frame Interrupt Clear + 3 + 1 + write-only + + + ENDRESET + End Of Reset Interrupt Clear + 4 + 1 + write-only + + + WAKE_UP + Wake Up CPU Interrupt Clear + 5 + 1 + write-only + + + ENDOFRSM + End Of Resume Interrupt Clear + 6 + 1 + write-only + + + UPSTR_RES + Upstream Resume Interrupt Clear + 7 + 1 + write-only + + + + + EPTRST + UDPHS Endpoints Reset Register + 0x0000001C + 32 + write-only + + + EPT_0 + Endpoint 0 Reset + 0 + 1 + write-only + + + EPT_1 + Endpoint 1 Reset + 1 + 1 + write-only + + + EPT_2 + Endpoint 2 Reset + 2 + 1 + write-only + + + EPT_3 + Endpoint 3 Reset + 3 + 1 + write-only + + + EPT_4 + Endpoint 4 Reset + 4 + 1 + write-only + + + EPT_5 + Endpoint 5 Reset + 5 + 1 + write-only + + + EPT_6 + Endpoint 6 Reset + 6 + 1 + write-only + + + + + TST + UDPHS Test Register + 0x000000E0 + 32 + read-write + 0x00000000 + + + SPEED_CFG + Speed Configuration + 0 + 2 + read-write + + + NORMAL + Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode + 0x0 + + + HIGH_SPEED + Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. + 0x2 + + + FULL_SPEED + Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. + 0x3 + + + + + TST_J + Test J Mode + 2 + 1 + read-write + + + TST_K + Test K Mode + 3 + 1 + read-write + + + TST_PKT + Test Packet Mode + 4 + 1 + read-write + + + OPMODE2 + OpMode2 + 5 + 1 + read-write + + + + + EPTCFG0 + UDPHS Endpoint Configuration Register (endpoint = 0) + 0x00000100 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB0 + UDPHS Endpoint Control Enable Register (endpoint = 0) + 0x00000104 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB0_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 0) + ISOENDPT + 0x00000104 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS0 + UDPHS Endpoint Control Disable Register (endpoint = 0) + 0x00000108 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS0_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 0) + ISOENDPT + 0x00000108 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL0 + UDPHS Endpoint Control Register (endpoint = 0) + 0x0000010C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL0_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 0) + ISOENDPT + 0x0000010C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA0 + UDPHS Endpoint Set Status Register (endpoint = 0) + 0x00000114 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA0_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 0) + ISOENDPT + 0x00000114 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA0 + UDPHS Endpoint Clear Status Register (endpoint = 0) + 0x00000118 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA0_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 0) + ISOENDPT + 0x00000118 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA0 + UDPHS Endpoint Status Register (endpoint = 0) + 0x0000011C + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA0_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 0) + ISOENDPT + 0x0000011C + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG1 + UDPHS Endpoint Configuration Register (endpoint = 1) + 0x00000120 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB1 + UDPHS Endpoint Control Enable Register (endpoint = 1) + 0x00000124 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB1_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 1) + ISOENDPT + 0x00000124 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS1 + UDPHS Endpoint Control Disable Register (endpoint = 1) + 0x00000128 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS1_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 1) + ISOENDPT + 0x00000128 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL1 + UDPHS Endpoint Control Register (endpoint = 1) + 0x0000012C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL1_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 1) + ISOENDPT + 0x0000012C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA1 + UDPHS Endpoint Set Status Register (endpoint = 1) + 0x00000134 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA1_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 1) + ISOENDPT + 0x00000134 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA1 + UDPHS Endpoint Clear Status Register (endpoint = 1) + 0x00000138 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA1_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 1) + ISOENDPT + 0x00000138 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA1 + UDPHS Endpoint Status Register (endpoint = 1) + 0x0000013C + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA1_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 1) + ISOENDPT + 0x0000013C + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG2 + UDPHS Endpoint Configuration Register (endpoint = 2) + 0x00000140 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB2 + UDPHS Endpoint Control Enable Register (endpoint = 2) + 0x00000144 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB2_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 2) + ISOENDPT + 0x00000144 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS2 + UDPHS Endpoint Control Disable Register (endpoint = 2) + 0x00000148 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS2_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 2) + ISOENDPT + 0x00000148 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL2 + UDPHS Endpoint Control Register (endpoint = 2) + 0x0000014C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL2_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 2) + ISOENDPT + 0x0000014C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA2 + UDPHS Endpoint Set Status Register (endpoint = 2) + 0x00000154 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA2_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 2) + ISOENDPT + 0x00000154 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA2 + UDPHS Endpoint Clear Status Register (endpoint = 2) + 0x00000158 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA2_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 2) + ISOENDPT + 0x00000158 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA2 + UDPHS Endpoint Status Register (endpoint = 2) + 0x0000015C + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA2_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 2) + ISOENDPT + 0x0000015C + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG3 + UDPHS Endpoint Configuration Register (endpoint = 3) + 0x00000160 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB3 + UDPHS Endpoint Control Enable Register (endpoint = 3) + 0x00000164 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB3_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 3) + ISOENDPT + 0x00000164 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS3 + UDPHS Endpoint Control Disable Register (endpoint = 3) + 0x00000168 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS3_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 3) + ISOENDPT + 0x00000168 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL3 + UDPHS Endpoint Control Register (endpoint = 3) + 0x0000016C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL3_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 3) + ISOENDPT + 0x0000016C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA3 + UDPHS Endpoint Set Status Register (endpoint = 3) + 0x00000174 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA3_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 3) + ISOENDPT + 0x00000174 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA3 + UDPHS Endpoint Clear Status Register (endpoint = 3) + 0x00000178 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA3_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 3) + ISOENDPT + 0x00000178 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA3 + UDPHS Endpoint Status Register (endpoint = 3) + 0x0000017C + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA3_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 3) + ISOENDPT + 0x0000017C + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG4 + UDPHS Endpoint Configuration Register (endpoint = 4) + 0x00000180 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB4 + UDPHS Endpoint Control Enable Register (endpoint = 4) + 0x00000184 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB4_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 4) + ISOENDPT + 0x00000184 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS4 + UDPHS Endpoint Control Disable Register (endpoint = 4) + 0x00000188 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS4_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 4) + ISOENDPT + 0x00000188 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL4 + UDPHS Endpoint Control Register (endpoint = 4) + 0x0000018C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL4_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 4) + ISOENDPT + 0x0000018C + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA4 + UDPHS Endpoint Set Status Register (endpoint = 4) + 0x00000194 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA4_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 4) + ISOENDPT + 0x00000194 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA4 + UDPHS Endpoint Clear Status Register (endpoint = 4) + 0x00000198 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA4_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 4) + ISOENDPT + 0x00000198 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA4 + UDPHS Endpoint Status Register (endpoint = 4) + 0x0000019C + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA4_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 4) + ISOENDPT + 0x0000019C + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG5 + UDPHS Endpoint Configuration Register (endpoint = 5) + 0x000001A0 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB5 + UDPHS Endpoint Control Enable Register (endpoint = 5) + 0x000001A4 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB5_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 5) + ISOENDPT + 0x000001A4 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS5 + UDPHS Endpoint Control Disable Register (endpoint = 5) + 0x000001A8 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS5_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 5) + ISOENDPT + 0x000001A8 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL5 + UDPHS Endpoint Control Register (endpoint = 5) + 0x000001AC + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL5_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 5) + ISOENDPT + 0x000001AC + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA5 + UDPHS Endpoint Set Status Register (endpoint = 5) + 0x000001B4 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA5_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 5) + ISOENDPT + 0x000001B4 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA5 + UDPHS Endpoint Clear Status Register (endpoint = 5) + 0x000001B8 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA5_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 5) + ISOENDPT + 0x000001B8 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA5 + UDPHS Endpoint Status Register (endpoint = 5) + 0x000001BC + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA5_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 5) + ISOENDPT + 0x000001BC + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTCFG6 + UDPHS Endpoint Configuration Register (endpoint = 6) + 0x000001C0 + 32 + read-write + 0x00000000 + + + EPT_SIZE + Endpoint Size + 0 + 3 + read-write + + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + EPT_DIR + Endpoint Direction + 3 + 1 + read-write + + + EPT_TYPE + Endpoint Type + 4 + 2 + read-write + + + CTRL8 + Control endpoint + 0x0 + + + ISO + Isochronous endpoint + 0x1 + + + BULK + Bulk endpoint + 0x2 + + + INT + Interrupt endpoint + 0x3 + + + + + BK_NUMBER + Number of Banks + 6 + 2 + read-write + + + 0 + Zero bank, the endpoint is not mapped in memory + 0x0 + + + 1 + One bank (bank 0) + 0x1 + + + 2 + Double bank (Ping-Pong: bank0/bank1) + 0x2 + + + 3 + Triple bank (bank0/bank1/bank2) + 0x3 + + + + + NB_TRANS + Number Of Transaction per Microframe + 8 + 2 + read-write + + + EPT_MAPD + Endpoint Mapped + 31 + 1 + read-write + + + + + EPTCTLENB6 + UDPHS Endpoint Control Enable Register (endpoint = 6) + 0x000001C4 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Enable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Enable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Enable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Enable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLENB6_ISOENDPT + UDPHS Endpoint Control Enable Register (endpoint = 6) + ISOENDPT + 0x000001C4 + 32 + write-only + + + EPT_ENABL + Endpoint Enable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Enable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Enable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Enable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enable + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Enable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Send/Short Packet Interrupt Enable + 31 + 1 + write-only + + + + + EPTCTLDIS6 + UDPHS Endpoint Control Disable Register (endpoint = 6) + 0x000001C8 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + NYET_DIS + NYET Enable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY + TX Packet Ready Interrupt Disable + 11 + 1 + write-only + + + RX_SETUP + Received SETUP Interrupt Disable + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Interrupt Disable + 13 + 1 + write-only + + + NAK_IN + NAKIN Interrupt Disable + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Interrupt Disable + 15 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTLDIS6_ISOENDPT + UDPHS Endpoint Control Disable Register (endpoint = 6) + ISOENDPT + 0x000001C8 + 32 + write-only + + + EPT_DISABL + Endpoint Disable + 0 + 1 + write-only + + + AUTO_VALID + Packet Auto-Valid Disable + 1 + 1 + write-only + + + INTDIS_DMA + Interrupts Disable DMA + 3 + 1 + write-only + + + DATAX_RX + DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + write-only + + + MDATA_RX + MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + write-only + + + ERR_OVFLW + Overflow Error Interrupt Disable + 8 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Interrupt Disable + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Disable + 10 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Disable + 11 + 1 + write-only + + + ERR_FL_ISO + Error Flow Interrupt Disable + 12 + 1 + write-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Disable + 13 + 1 + write-only + + + ERR_FLUSH + bank flush error Interrupt Disable + 14 + 1 + write-only + + + BUSY_BANK + Busy Bank Interrupt Disable + 18 + 1 + write-only + + + SHRT_PCKT + Short Packet Interrupt Disable + 31 + 1 + write-only + + + + + EPTCTL6 + UDPHS Endpoint Control Register (endpoint = 6) + 0x000001CC + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled (Not for CONTROL Endpoints) + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + NYET_DIS + NYET Disable (Only for High Speed Bulk OUT endpoints) + 4 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY + TX Packet Ready Interrupt Enabled + 11 + 1 + read-only + + + RX_SETUP + Received SETUP Interrupt Enabled + 12 + 1 + read-only + + + STALL_SNT + Stall Sent Interrupt Enabled + 13 + 1 + read-only + + + NAK_IN + NAKIN Interrupt Enabled + 14 + 1 + read-only + + + NAK_OUT + NAKOUT Interrupt Enabled + 15 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTCTL6_ISOENDPT + UDPHS Endpoint Control Register (endpoint = 6) + ISOENDPT + 0x000001CC + 32 + read-only + 0x00000000 + + + EPT_ENABL + Endpoint Enable + 0 + 1 + read-only + + + AUTO_VALID + Packet Auto-Valid Enabled + 1 + 1 + read-only + + + INTDIS_DMA + Interrupt Disables DMA + 3 + 1 + read-only + + + DATAX_RX + DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 6 + 1 + read-only + + + MDATA_RX + MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) + 7 + 1 + read-only + + + ERR_OVFLW + Overflow Error Interrupt Enabled + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data Interrupt Enabled + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete Interrupt Enabled + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error Interrupt Enabled + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow Interrupt Enabled + 12 + 1 + read-only + + + ERR_CRC_NTR + ISO CRC Error/Number of Transaction Error Interrupt Enabled + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error Interrupt Enabled + 14 + 1 + read-only + + + BUSY_BANK + Busy Bank Interrupt Enabled + 18 + 1 + read-only + + + SHRT_PCKT + Short Packet Interrupt Enabled + 31 + 1 + read-only + + + + + EPTSETSTA6 + UDPHS Endpoint Set Status Register (endpoint = 6) + 0x000001D4 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Set + 5 + 1 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTSETSTA6_ISOENDPT + UDPHS Endpoint Set Status Register (endpoint = 6) + ISOENDPT + 0x000001D4 + 32 + write-only + + + RXRDY_TXKL + KILL Bank Set (for IN Endpoint) + 9 + 1 + write-only + + + TXRDY_TRER + TX Packet Ready Set + 11 + 1 + write-only + + + + + EPTCLRSTA6 + UDPHS Endpoint Clear Status Register (endpoint = 6) + 0x000001D8 + 32 + write-only + + + FRCESTALL + Stall Handshake Request Clear + 5 + 1 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + RX_SETUP + Received SETUP Clear + 12 + 1 + write-only + + + STALL_SNT + Stall Sent Clear + 13 + 1 + write-only + + + NAK_IN + NAKIN Clear + 14 + 1 + write-only + + + NAK_OUT + NAKOUT Clear + 15 + 1 + write-only + + + + + EPTCLRSTA6_ISOENDPT + UDPHS Endpoint Clear Status Register (endpoint = 6) + ISOENDPT + 0x000001D8 + 32 + write-only + + + TOGGLESQ + Data Toggle Clear + 6 + 1 + write-only + + + RXRDY_TXKL + Received OUT Data Clear + 9 + 1 + write-only + + + TX_COMPLT + Transmitted IN Data Complete Clear + 10 + 1 + write-only + + + ERR_FL_ISO + Error Flow Clear + 12 + 1 + write-only + + + ERR_CRC_NTR + Number of Transaction Error Clear + 13 + 1 + write-only + + + ERR_FLUSH + Bank Flush Error Clear + 14 + 1 + write-only + + + + + EPTSTA6 + UDPHS Endpoint Status Register (endpoint = 6) + 0x000001DC + 32 + read-only + 0x00000040 + + + FRCESTALL + Stall Handshake Request + 5 + 1 + read-only + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Reserved for High Bandwidth Isochronous Endpoint + 0x2 + + + MDATA + Reserved for High Bandwidth Isochronous Endpoint + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY + TX Packet Ready + 11 + 1 + read-only + + + RX_SETUP + Received SETUP + 12 + 1 + read-only + + + STALL_SNT + Stall Sent + 13 + 1 + read-only + + + NAK_IN + NAK IN + 14 + 1 + read-only + + + NAK_OUT + NAK OUT + 15 + 1 + read-only + + + CURBK_CTLDIR + Current Bank/Control Direction + 16 + 2 + read-only + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + EPTSTA6_ISOENDPT + UDPHS Endpoint Status Register (endpoint = 6) + ISOENDPT + 0x000001DC + 32 + read-only + 0x00000040 + + + TOGGLESQ_STA + Toggle Sequencing + 6 + 2 + read-only + + + DATA0 + DATA0 + 0x0 + + + DATA1 + DATA1 + 0x1 + + + DATA2 + Data2 (only for High Bandwidth Isochronous Endpoint) + 0x2 + + + MDATA + MData (only for High Bandwidth Isochronous Endpoint) + 0x3 + + + + + ERR_OVFLW + Overflow Error + 8 + 1 + read-only + + + RXRDY_TXKL + Received OUT Data/KILL Bank + 9 + 1 + read-only + + + TX_COMPLT + Transmitted IN Data Complete + 10 + 1 + read-only + + + TXRDY_TRER + TX Packet Ready/Transaction Error + 11 + 1 + read-only + + + ERR_FL_ISO + Error Flow + 12 + 1 + read-only + + + ERR_CRC_NTR + CRC ISO Error/Number of Transaction Error + 13 + 1 + read-only + + + ERR_FLUSH + Bank Flush Error + 14 + 1 + read-only + + + CURBK + Current Bank + 16 + 2 + read-only + + + BANK0 + Bank 0 (or single bank) + 0x0 + + + BANK1 + Bank 1 + 0x1 + + + BANK2 + Bank 2 + 0x2 + + + + + BUSY_BANK_STA + Busy Bank Number + 18 + 2 + read-only + + + 1BUSYBANK + 1 busy bank + 0x0 + + + 2BUSYBANKS + 2 busy banks + 0x1 + + + 3BUSYBANKS + 3 busy banks + 0x2 + + + + + BYTE_COUNT + UDPHS Byte Count + 20 + 11 + read-only + + + SHRT_PCKT + Short Packet + 31 + 1 + read-only + + + + + DMANXTDSC0 + UDPHS DMA Next Descriptor Address Register (channel = 0) + 0x00000300 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS0 + UDPHS DMA Channel Address Register (channel = 0) + 0x00000304 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL0 + UDPHS DMA Channel Control Register (channel = 0) + 0x00000308 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS0 + UDPHS DMA Channel Status Register (channel = 0) + 0x0000030C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + DMANXTDSC1 + UDPHS DMA Next Descriptor Address Register (channel = 1) + 0x00000310 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS1 + UDPHS DMA Channel Address Register (channel = 1) + 0x00000314 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL1 + UDPHS DMA Channel Control Register (channel = 1) + 0x00000318 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS1 + UDPHS DMA Channel Status Register (channel = 1) + 0x0000031C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + DMANXTDSC2 + UDPHS DMA Next Descriptor Address Register (channel = 2) + 0x00000320 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS2 + UDPHS DMA Channel Address Register (channel = 2) + 0x00000324 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL2 + UDPHS DMA Channel Control Register (channel = 2) + 0x00000328 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS2 + UDPHS DMA Channel Status Register (channel = 2) + 0x0000032C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + DMANXTDSC3 + UDPHS DMA Next Descriptor Address Register (channel = 3) + 0x00000330 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS3 + UDPHS DMA Channel Address Register (channel = 3) + 0x00000334 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL3 + UDPHS DMA Channel Control Register (channel = 3) + 0x00000338 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS3 + UDPHS DMA Channel Status Register (channel = 3) + 0x0000033C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + DMANXTDSC4 + UDPHS DMA Next Descriptor Address Register (channel = 4) + 0x00000340 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS4 + UDPHS DMA Channel Address Register (channel = 4) + 0x00000344 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL4 + UDPHS DMA Channel Control Register (channel = 4) + 0x00000348 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS4 + UDPHS DMA Channel Status Register (channel = 4) + 0x0000034C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + DMANXTDSC5 + UDPHS DMA Next Descriptor Address Register (channel = 5) + 0x00000350 + 32 + read-write + 0x00000000 + + + NXT_DSC_ADD + Next Descriptor Address + 0 + 32 + read-write + + + + + DMAADDRESS5 + UDPHS DMA Channel Address Register (channel = 5) + 0x00000354 + 32 + read-write + 0x00000000 + + + BUFF_ADD + Buffer Address + 0 + 32 + read-write + + + + + DMACONTROL5 + UDPHS DMA Channel Control Register (channel = 5) + 0x00000358 + 32 + read-write + 0x00000000 + + + CHANN_ENB + (Channel Enable Command) + 0 + 1 + read-write + + + LDNXT_DSC + Load Next Channel Transfer Descriptor Enable (Command) + 1 + 1 + read-write + + + END_TR_EN + End of Transfer Enable (Control) + 2 + 1 + read-write + + + END_B_EN + End of Buffer Enable (Control) + 3 + 1 + read-write + + + END_TR_IT + End of Transfer Interrupt Enable + 4 + 1 + read-write + + + END_BUFFIT + End of Buffer Interrupt Enable + 5 + 1 + read-write + + + DESC_LD_IT + Descriptor Loaded Interrupt Enable + 6 + 1 + read-write + + + BURST_LCK + Burst Lock Enable + 7 + 1 + read-write + + + BUFF_LENGTH + Buffer Byte Length (Write-only) + 16 + 16 + read-write + + + + + DMASTATUS5 + UDPHS DMA Channel Status Register (channel = 5) + 0x0000035C + 32 + read-write + 0x00000000 + + + CHANN_ENB + Channel Enable Status + 0 + 1 + read-write + + + CHANN_ACT + Channel Active Status + 1 + 1 + read-write + + + END_TR_ST + End of Channel Transfer Status + 4 + 1 + read-write + + + END_BF_ST + End of Channel Buffer Status + 5 + 1 + read-write + + + DESC_LDST + Descriptor Loaded Status + 6 + 1 + read-write + + + BUFF_COUNT + Buffer Byte Count + 16 + 16 + read-write + + + + + + + ADC12B + 6448C + Analog-to-Digital Converter 12bits + ADC12B_ + 0x400A8000 + + 0 + 0x4000 + registers + + + ADC12B + 26 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + LOWRES + Resolution + 4 + 1 + read-write + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 8 + read-write + + + SHTIM + Sample & Hold Time + 24 + 4 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + 0 + 1 + write-only + + + CH1 + 1 + 1 + write-only + + + CH2 + 2 + 1 + write-only + + + CH3 + 3 + 1 + write-only + + + CH4 + 4 + 1 + write-only + + + CH5 + 5 + 1 + write-only + + + CH6 + 6 + 1 + write-only + + + CH7 + 7 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + + + SR + Status Register + 0x0000001C + 32 + read-only + 0x000C0000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + OVRE0 + Overrun Error 0 + 8 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 9 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 10 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 11 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 12 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 13 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 14 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 15 + 1 + read-only + + + DRDY + Data Ready + 16 + 1 + read-only + + + GOVRE + General Overrun Error + 17 + 1 + read-only + + + ENDRX + End of RX Buffer + 18 + 1 + read-only + + + RXBUFF + RX Buffer Full + 19 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + OVRE0 + Overrun Error Interrupt Enable 0 + 8 + 1 + write-only + + + OVRE1 + Overrun Error Interrupt Enable 1 + 9 + 1 + write-only + + + OVRE2 + Overrun Error Interrupt Enable 2 + 10 + 1 + write-only + + + OVRE3 + Overrun Error Interrupt Enable 3 + 11 + 1 + write-only + + + OVRE4 + Overrun Error Interrupt Enable 4 + 12 + 1 + write-only + + + OVRE5 + Overrun Error Interrupt Enable 5 + 13 + 1 + write-only + + + OVRE6 + Overrun Error Interrupt Enable 6 + 14 + 1 + write-only + + + OVRE7 + Overrun Error Interrupt Enable 7 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 16 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 17 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 18 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 19 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + OVRE0 + Overrun Error Interrupt Disable 0 + 8 + 1 + write-only + + + OVRE1 + Overrun Error Interrupt Disable 1 + 9 + 1 + write-only + + + OVRE2 + Overrun Error Interrupt Disable 2 + 10 + 1 + write-only + + + OVRE3 + Overrun Error Interrupt Disable 3 + 11 + 1 + write-only + + + OVRE4 + Overrun Error Interrupt Disable 4 + 12 + 1 + write-only + + + OVRE5 + Overrun Error Interrupt Disable 5 + 13 + 1 + write-only + + + OVRE6 + Overrun Error Interrupt Disable 6 + 14 + 1 + write-only + + + OVRE7 + Overrun Error Interrupt Disable 7 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 16 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 17 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 18 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 19 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + OVRE0 + Overrun Error Interrupt Mask 0 + 8 + 1 + read-only + + + OVRE1 + Overrun Error Interrupt Mask 1 + 9 + 1 + read-only + + + OVRE2 + Overrun Error Interrupt Mask 2 + 10 + 1 + read-only + + + OVRE3 + Overrun Error Interrupt Mask 3 + 11 + 1 + read-only + + + OVRE4 + Overrun Error Interrupt Mask 4 + 12 + 1 + read-only + + + OVRE5 + Overrun Error Interrupt Mask 5 + 13 + 1 + read-only + + + OVRE6 + Overrun Error Interrupt Mask 6 + 14 + 1 + read-only + + + OVRE7 + Overrun Error Interrupt Mask 7 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 16 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 17 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 18 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 19 + 1 + read-only + + + + + 8 + 4 + 0-7 + CDR[%s] + Channel Data Register + 0x00000030 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000064 + 32 + read-write + 0x00000000 + + + GAIN + Input Gain + 0 + 2 + read-write + + + IBCTL + Bias Current Control + 8 + 2 + read-write + + + DIFF + Differential Mode + 16 + 1 + read-write + + + OFFSET + Input OFFSET + 17 + 1 + read-write + + + + + EMR + Extended Mode Register + 0x00000068 + 32 + read-write + 0x00000000 + + + OFFMODES + Off Mode if Sleep Bit (ADC12B_MR) = 1 + 0 + 1 + read-write + + + OFF_MODE_STARTUP_TIME + Startup Time + 16 + 8 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ADC + 6051K + Analog-to-Digital Converter + ADC_ + 0x400AC000 + + 0 + 0x4000 + registers + + + ADC + 27 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + LOWRES + Resolution + 4 + 1 + read-write + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 7 + read-write + + + SHTIM + Sample & Hold Time + 24 + 4 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + + + SR + Status Register + 0x0000001C + 32 + read-only + 0x000C0000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + OVRE0 + Overrun Error 0 + 8 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 9 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 10 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 11 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 12 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 13 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 14 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 15 + 1 + read-only + + + DRDY + Data Ready + 16 + 1 + read-only + + + GOVRE + General Overrun Error + 17 + 1 + read-only + + + ENDRX + End of RX Buffer + 18 + 1 + read-only + + + RXBUFF + RX Buffer Full + 19 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 10 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + OVRE0 + Overrun Error Interrupt Enable 0 + 8 + 1 + write-only + + + OVRE1 + Overrun Error Interrupt Enable 1 + 9 + 1 + write-only + + + OVRE2 + Overrun Error Interrupt Enable 2 + 10 + 1 + write-only + + + OVRE3 + Overrun Error Interrupt Enable 3 + 11 + 1 + write-only + + + OVRE4 + Overrun Error Interrupt Enable 4 + 12 + 1 + write-only + + + OVRE5 + Overrun Error Interrupt Enable 5 + 13 + 1 + write-only + + + OVRE6 + Overrun Error Interrupt Enable 6 + 14 + 1 + write-only + + + OVRE7 + Overrun Error Interrupt Enable 7 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 16 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 17 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 18 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 19 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + OVRE0 + Overrun Error Interrupt Disable 0 + 8 + 1 + write-only + + + OVRE1 + Overrun Error Interrupt Disable 1 + 9 + 1 + write-only + + + OVRE2 + Overrun Error Interrupt Disable 2 + 10 + 1 + write-only + + + OVRE3 + Overrun Error Interrupt Disable 3 + 11 + 1 + write-only + + + OVRE4 + Overrun Error Interrupt Disable 4 + 12 + 1 + write-only + + + OVRE5 + Overrun Error Interrupt Disable 5 + 13 + 1 + write-only + + + OVRE6 + Overrun Error Interrupt Disable 6 + 14 + 1 + write-only + + + OVRE7 + Overrun Error Interrupt Disable 7 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 16 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 17 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 18 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 19 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + OVRE0 + Overrun Error Interrupt Mask 0 + 8 + 1 + read-only + + + OVRE1 + Overrun Error Interrupt Mask 1 + 9 + 1 + read-only + + + OVRE2 + Overrun Error Interrupt Mask 2 + 10 + 1 + read-only + + + OVRE3 + Overrun Error Interrupt Mask 3 + 11 + 1 + read-only + + + OVRE4 + Overrun Error Interrupt Mask 4 + 12 + 1 + read-only + + + OVRE5 + Overrun Error Interrupt Mask 5 + 13 + 1 + read-only + + + OVRE6 + Overrun Error Interrupt Mask 6 + 14 + 1 + read-only + + + OVRE7 + Overrun Error Interrupt Mask 7 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 16 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 17 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 18 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 19 + 1 + read-only + + + + + 8 + 4 + 0-7 + CDR[%s] + Channel Data Register + 0x00000030 + 32 + read-only + + + DATA + Converted Data + 0 + 10 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DMAC + 6233P + DMA Controller + DMAC_ + 0x400B0000 + + 0 + 0x4000 + registers + + + DMAC + 28 + + + + GCFG + DMAC Global Configuration Register + 0x00000000 + 32 + read-write + 0x00000010 + + + ARB_CFG + Arbiter Configuration + 4 + 1 + read-write + + + FIXED + Fixed priority arbiter (see "Basic Definitions" ) + 0 + + + ROUND_ROBIN + Modified round robin arbiter. + 1 + + + + + + + EN + DMAC Enable Register + 0x00000004 + 32 + read-write + 0x00000000 + + + ENABLE + General Enable of DMA + 0 + 1 + read-write + + + + + SREQ + DMAC Software Single Request Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SSREQ0 + Source Request + 0 + 1 + read-write + + + DSREQ0 + Destination Request + 1 + 1 + read-write + + + SSREQ1 + Source Request + 2 + 1 + read-write + + + DSREQ1 + Destination Request + 3 + 1 + read-write + + + SSREQ2 + Source Request + 4 + 1 + read-write + + + DSREQ2 + Destination Request + 5 + 1 + read-write + + + SSREQ3 + Source Request + 6 + 1 + read-write + + + DSREQ3 + Destination Request + 7 + 1 + read-write + + + + + CREQ + DMAC Software Chunk Transfer Request Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SCREQ0 + Source Chunk Request + 0 + 1 + read-write + + + DCREQ0 + Destination Chunk Request + 1 + 1 + read-write + + + SCREQ1 + Source Chunk Request + 2 + 1 + read-write + + + DCREQ1 + Destination Chunk Request + 3 + 1 + read-write + + + SCREQ2 + Source Chunk Request + 4 + 1 + read-write + + + DCREQ2 + Destination Chunk Request + 5 + 1 + read-write + + + SCREQ3 + Source Chunk Request + 6 + 1 + read-write + + + DCREQ3 + Destination Chunk Request + 7 + 1 + read-write + + + + + LAST + DMAC Software Last Transfer Flag Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SLAST0 + Source Last + 0 + 1 + read-write + + + DLAST0 + Destination Last + 1 + 1 + read-write + + + SLAST1 + Source Last + 2 + 1 + read-write + + + DLAST1 + Destination Last + 3 + 1 + read-write + + + SLAST2 + Source Last + 4 + 1 + read-write + + + DLAST2 + Destination Last + 5 + 1 + read-write + + + SLAST3 + Source Last + 6 + 1 + read-write + + + DLAST3 + Destination Last + 7 + 1 + read-write + + + + + EBCIER + DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. + 0x00000018 + 32 + write-only + + + BTC0 + Buffer Transfer Completed [3:0] + 0 + 1 + write-only + + + BTC1 + Buffer Transfer Completed [3:0] + 1 + 1 + write-only + + + BTC2 + Buffer Transfer Completed [3:0] + 2 + 1 + write-only + + + BTC3 + Buffer Transfer Completed [3:0] + 3 + 1 + write-only + + + CBTC0 + Chained Buffer Transfer Completed [3:0] + 8 + 1 + write-only + + + CBTC1 + Chained Buffer Transfer Completed [3:0] + 9 + 1 + write-only + + + CBTC2 + Chained Buffer Transfer Completed [3:0] + 10 + 1 + write-only + + + CBTC3 + Chained Buffer Transfer Completed [3:0] + 11 + 1 + write-only + + + ERR0 + Access Error [3:0] + 16 + 1 + write-only + + + ERR1 + Access Error [3:0] + 17 + 1 + write-only + + + ERR2 + Access Error [3:0] + 18 + 1 + write-only + + + ERR3 + Access Error [3:0] + 19 + 1 + write-only + + + + + EBCIDR + DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. + 0x0000001C + 32 + write-only + + + BTC0 + Buffer Transfer Completed [3:0] + 0 + 1 + write-only + + + BTC1 + Buffer Transfer Completed [3:0] + 1 + 1 + write-only + + + BTC2 + Buffer Transfer Completed [3:0] + 2 + 1 + write-only + + + BTC3 + Buffer Transfer Completed [3:0] + 3 + 1 + write-only + + + CBTC0 + Chained Buffer Transfer Completed [3:0] + 8 + 1 + write-only + + + CBTC1 + Chained Buffer Transfer Completed [3:0] + 9 + 1 + write-only + + + CBTC2 + Chained Buffer Transfer Completed [3:0] + 10 + 1 + write-only + + + CBTC3 + Chained Buffer Transfer Completed [3:0] + 11 + 1 + write-only + + + ERR0 + Access Error [3:0] + 16 + 1 + write-only + + + ERR1 + Access Error [3:0] + 17 + 1 + write-only + + + ERR2 + Access Error [3:0] + 18 + 1 + write-only + + + ERR3 + Access Error [3:0] + 19 + 1 + write-only + + + + + EBCIMR + DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. + 0x00000020 + 32 + read-only + 0x00000000 + + + BTC0 + Buffer Transfer Completed [3:0] + 0 + 1 + read-only + + + BTC1 + Buffer Transfer Completed [3:0] + 1 + 1 + read-only + + + BTC2 + Buffer Transfer Completed [3:0] + 2 + 1 + read-only + + + BTC3 + Buffer Transfer Completed [3:0] + 3 + 1 + read-only + + + CBTC0 + Chained Buffer Transfer Completed [3:0] + 8 + 1 + read-only + + + CBTC1 + Chained Buffer Transfer Completed [3:0] + 9 + 1 + read-only + + + CBTC2 + Chained Buffer Transfer Completed [3:0] + 10 + 1 + read-only + + + CBTC3 + Chained Buffer Transfer Completed [3:0] + 11 + 1 + read-only + + + ERR0 + Access Error [3:0] + 16 + 1 + read-only + + + ERR1 + Access Error [3:0] + 17 + 1 + read-only + + + ERR2 + Access Error [3:0] + 18 + 1 + read-only + + + ERR3 + Access Error [3:0] + 19 + 1 + read-only + + + + + EBCISR + DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. + 0x00000024 + 32 + read-only + 0x00000000 + + + BTC0 + Buffer Transfer Completed [3:0] + 0 + 1 + read-only + + + BTC1 + Buffer Transfer Completed [3:0] + 1 + 1 + read-only + + + BTC2 + Buffer Transfer Completed [3:0] + 2 + 1 + read-only + + + BTC3 + Buffer Transfer Completed [3:0] + 3 + 1 + read-only + + + CBTC0 + Chained Buffer Transfer Completed [3:0] + 8 + 1 + read-only + + + CBTC1 + Chained Buffer Transfer Completed [3:0] + 9 + 1 + read-only + + + CBTC2 + Chained Buffer Transfer Completed [3:0] + 10 + 1 + read-only + + + CBTC3 + Chained Buffer Transfer Completed [3:0] + 11 + 1 + read-only + + + ERR0 + Access Error [3:0] + 16 + 1 + read-only + + + ERR1 + Access Error [3:0] + 17 + 1 + read-only + + + ERR2 + Access Error [3:0] + 18 + 1 + read-only + + + ERR3 + Access Error [3:0] + 19 + 1 + read-only + + + + + CHER + DMAC Channel Handler Enable Register + 0x00000028 + 32 + write-only + + + ENA0 + Enable [3:0] + 0 + 1 + write-only + + + ENA1 + Enable [3:0] + 1 + 1 + write-only + + + ENA2 + Enable [3:0] + 2 + 1 + write-only + + + ENA3 + Enable [3:0] + 3 + 1 + write-only + + + SUSP0 + Suspend [3:0] + 8 + 1 + write-only + + + SUSP1 + Suspend [3:0] + 9 + 1 + write-only + + + SUSP2 + Suspend [3:0] + 10 + 1 + write-only + + + SUSP3 + Suspend [3:0] + 11 + 1 + write-only + + + KEEP0 + Keep on [3:0] + 24 + 1 + write-only + + + KEEP1 + Keep on [3:0] + 25 + 1 + write-only + + + KEEP2 + Keep on [3:0] + 26 + 1 + write-only + + + KEEP3 + Keep on [3:0] + 27 + 1 + write-only + + + + + CHDR + DMAC Channel Handler Disable Register + 0x0000002C + 32 + write-only + + + DIS0 + Disable [3:0] + 0 + 1 + write-only + + + DIS1 + Disable [3:0] + 1 + 1 + write-only + + + DIS2 + Disable [3:0] + 2 + 1 + write-only + + + DIS3 + Disable [3:0] + 3 + 1 + write-only + + + RES0 + Resume [3:0] + 8 + 1 + write-only + + + RES1 + Resume [3:0] + 9 + 1 + write-only + + + RES2 + Resume [3:0] + 10 + 1 + write-only + + + RES3 + Resume [3:0] + 11 + 1 + write-only + + + + + CHSR + DMAC Channel Handler Status Register + 0x00000030 + 32 + read-only + 0x00FF0000 + + + ENA0 + Enable [3:0] + 0 + 1 + read-only + + + ENA1 + Enable [3:0] + 1 + 1 + read-only + + + ENA2 + Enable [3:0] + 2 + 1 + read-only + + + ENA3 + Enable [3:0] + 3 + 1 + read-only + + + SUSP0 + Suspend [3:0] + 8 + 1 + read-only + + + SUSP1 + Suspend [3:0] + 9 + 1 + read-only + + + SUSP2 + Suspend [3:0] + 10 + 1 + read-only + + + SUSP3 + Suspend [3:0] + 11 + 1 + read-only + + + EMPT0 + Empty [3:0] + 16 + 1 + read-only + + + EMPT1 + Empty [3:0] + 17 + 1 + read-only + + + EMPT2 + Empty [3:0] + 18 + 1 + read-only + + + EMPT3 + Empty [3:0] + 19 + 1 + read-only + + + STAL0 + Stalled [3:0] + 24 + 1 + read-only + + + STAL1 + Stalled [3:0] + 25 + 1 + read-only + + + STAL2 + Stalled [3:0] + 26 + 1 + read-only + + + STAL3 + Stalled [3:0] + 27 + 1 + read-only + + + + + SADDR0 + DMAC Channel Source Address Register (ch_num = 0) + 0x0000003C + 32 + read-write + 0x00000000 + + + SADDR + Channel x Source Address + 0 + 32 + read-write + + + + + DADDR0 + DMAC Channel Destination Address Register (ch_num = 0) + 0x00000040 + 32 + read-write + 0x00000000 + + + DADDR + Channel x Destination Address + 0 + 32 + read-write + + + + + DSCR0 + DMAC Channel Descriptor Address Register (ch_num = 0) + 0x00000044 + 32 + read-write + 0x00000000 + + + DSCR + Buffer Transfer Descriptor Address + 2 + 30 + read-write + + + + + CTRLA0 + DMAC Channel Control A Register (ch_num = 0) + 0x00000048 + 32 + read-write + 0x00000000 + + + BTSIZE + Buffer Transfer Size + 0 + 16 + read-write + + + SRC_WIDTH + Transfer Width for the Source + 24 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DST_WIDTH + Transfer Width for the Destination + 28 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DONE + Current Descriptor Stop Command and Transfer Completed Memory Indicator + 31 + 1 + read-write + + + + + CTRLB0 + DMAC Channel Control B Register (ch_num = 0) + 0x0000004C + 32 + read-write + 0x00000000 + + + SRC_DSCR + Source Address Descriptor + 16 + 1 + read-write + + + FETCH_FROM_MEM + Source address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the source. + 1 + + + + + DST_DSCR + Destination Address Descriptor + 20 + 1 + read-write + + + FETCH_FROM_MEM + Destination address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the destination. + 1 + + + + + FC + Flow Control + 21 + 2 + read-write + + + MEM2MEM_DMA_FC + Memory-to-Memory Transfer DMAC is flow controller + 0x0 + + + MEM2PER_DMA_FC + Memory-to-Peripheral Transfer DMAC is flow controller + 0x1 + + + PER2MEM_DMA_FC + Peripheral-to-Memory Transfer DMAC is flow controller + 0x2 + + + PER2PER_DMA_FC + Peripheral-to-Peripheral Transfer DMAC is flow controller + 0x3 + + + + + SRC_INCR + Incrementing, Decrementing or Fixed Address for the Source + 24 + 2 + read-write + + + INCREMENTING + The source address is incremented + 0x0 + + + DECREMENTING + The source address is decremented + 0x1 + + + FIXED + The source address remains unchanged + 0x2 + + + + + DST_INCR + Incrementing, Decrementing or Fixed Address for the Destination + 28 + 2 + read-write + + + INCREMENTING + The destination address is incremented + 0x0 + + + DECREMENTING + The destination address is decremented + 0x1 + + + FIXED + The destination address remains unchanged + 0x2 + + + + + IEN + Interrupt Enable Not + 30 + 1 + read-write + + + + + CFG0 + DMAC Channel Configuration Register (ch_num = 0) + 0x00000050 + 32 + read-write + 0x01000000 + + + SRC_PER + Source with Peripheral identifier + 0 + 4 + read-write + + + DST_PER + Destination with Peripheral identifier + 4 + 4 + read-write + + + SRC_H2SEL + Software or Hardware Selection for the Source + 9 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + DST_H2SEL + Software or Hardware Selection for the Destination + 13 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + SOD + Stop On Done + 16 + 1 + read-write + + + DISABLE + STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. + 0 + + + ENABLE + STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. + 1 + + + + + LOCK_IF + Interface Lock + 20 + 1 + read-write + + + DISABLE + Interface Lock capability is disabled + 0 + + + ENABLE + Interface Lock capability is enabled + 1 + + + + + LOCK_B + Bus Lock + 21 + 1 + read-write + + + DISABLE + AHB Bus Locking capability is disabled. + 0 + + + + + LOCK_IF_L + Master Interface Arbiter Lock + 22 + 1 + read-write + + + CHUNK + The Master Interface Arbiter is locked by the channel x for a chunk transfer. + 0 + + + BUFFER + The Master Interface Arbiter is locked by the channel x for a buffer transfer. + 1 + + + + + AHB_PROT + AHB Protection + 24 + 3 + read-write + + + FIFOCFG + FIFO Configuration + 28 + 2 + read-write + + + ALAP_CFG + The largest defined length AHB burst is performed on the destination AHB interface. + 0x0 + + + HALF_CFG + When half FIFO size is available/filled, a source/destination request is serviced. + 0x1 + + + ASAP_CFG + When there is enough space/data available to perform a single AHB access, then the request is serviced. + 0x2 + + + + + + + SADDR1 + DMAC Channel Source Address Register (ch_num = 1) + 0x00000064 + 32 + read-write + 0x00000000 + + + SADDR + Channel x Source Address + 0 + 32 + read-write + + + + + DADDR1 + DMAC Channel Destination Address Register (ch_num = 1) + 0x00000068 + 32 + read-write + 0x00000000 + + + DADDR + Channel x Destination Address + 0 + 32 + read-write + + + + + DSCR1 + DMAC Channel Descriptor Address Register (ch_num = 1) + 0x0000006C + 32 + read-write + 0x00000000 + + + DSCR + Buffer Transfer Descriptor Address + 2 + 30 + read-write + + + + + CTRLA1 + DMAC Channel Control A Register (ch_num = 1) + 0x00000070 + 32 + read-write + 0x00000000 + + + BTSIZE + Buffer Transfer Size + 0 + 16 + read-write + + + SRC_WIDTH + Transfer Width for the Source + 24 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DST_WIDTH + Transfer Width for the Destination + 28 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DONE + Current Descriptor Stop Command and Transfer Completed Memory Indicator + 31 + 1 + read-write + + + + + CTRLB1 + DMAC Channel Control B Register (ch_num = 1) + 0x00000074 + 32 + read-write + 0x00000000 + + + SRC_DSCR + Source Address Descriptor + 16 + 1 + read-write + + + FETCH_FROM_MEM + Source address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the source. + 1 + + + + + DST_DSCR + Destination Address Descriptor + 20 + 1 + read-write + + + FETCH_FROM_MEM + Destination address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the destination. + 1 + + + + + FC + Flow Control + 21 + 2 + read-write + + + MEM2MEM_DMA_FC + Memory-to-Memory Transfer DMAC is flow controller + 0x0 + + + MEM2PER_DMA_FC + Memory-to-Peripheral Transfer DMAC is flow controller + 0x1 + + + PER2MEM_DMA_FC + Peripheral-to-Memory Transfer DMAC is flow controller + 0x2 + + + PER2PER_DMA_FC + Peripheral-to-Peripheral Transfer DMAC is flow controller + 0x3 + + + + + SRC_INCR + Incrementing, Decrementing or Fixed Address for the Source + 24 + 2 + read-write + + + INCREMENTING + The source address is incremented + 0x0 + + + DECREMENTING + The source address is decremented + 0x1 + + + FIXED + The source address remains unchanged + 0x2 + + + + + DST_INCR + Incrementing, Decrementing or Fixed Address for the Destination + 28 + 2 + read-write + + + INCREMENTING + The destination address is incremented + 0x0 + + + DECREMENTING + The destination address is decremented + 0x1 + + + FIXED + The destination address remains unchanged + 0x2 + + + + + IEN + Interrupt Enable Not + 30 + 1 + read-write + + + + + CFG1 + DMAC Channel Configuration Register (ch_num = 1) + 0x00000078 + 32 + read-write + 0x01000000 + + + SRC_PER + Source with Peripheral identifier + 0 + 4 + read-write + + + DST_PER + Destination with Peripheral identifier + 4 + 4 + read-write + + + SRC_H2SEL + Software or Hardware Selection for the Source + 9 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + DST_H2SEL + Software or Hardware Selection for the Destination + 13 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + SOD + Stop On Done + 16 + 1 + read-write + + + DISABLE + STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. + 0 + + + ENABLE + STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. + 1 + + + + + LOCK_IF + Interface Lock + 20 + 1 + read-write + + + DISABLE + Interface Lock capability is disabled + 0 + + + ENABLE + Interface Lock capability is enabled + 1 + + + + + LOCK_B + Bus Lock + 21 + 1 + read-write + + + DISABLE + AHB Bus Locking capability is disabled. + 0 + + + + + LOCK_IF_L + Master Interface Arbiter Lock + 22 + 1 + read-write + + + CHUNK + The Master Interface Arbiter is locked by the channel x for a chunk transfer. + 0 + + + BUFFER + The Master Interface Arbiter is locked by the channel x for a buffer transfer. + 1 + + + + + AHB_PROT + AHB Protection + 24 + 3 + read-write + + + FIFOCFG + FIFO Configuration + 28 + 2 + read-write + + + ALAP_CFG + The largest defined length AHB burst is performed on the destination AHB interface. + 0x0 + + + HALF_CFG + When half FIFO size is available/filled, a source/destination request is serviced. + 0x1 + + + ASAP_CFG + When there is enough space/data available to perform a single AHB access, then the request is serviced. + 0x2 + + + + + + + SADDR2 + DMAC Channel Source Address Register (ch_num = 2) + 0x0000008C + 32 + read-write + 0x00000000 + + + SADDR + Channel x Source Address + 0 + 32 + read-write + + + + + DADDR2 + DMAC Channel Destination Address Register (ch_num = 2) + 0x00000090 + 32 + read-write + 0x00000000 + + + DADDR + Channel x Destination Address + 0 + 32 + read-write + + + + + DSCR2 + DMAC Channel Descriptor Address Register (ch_num = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + DSCR + Buffer Transfer Descriptor Address + 2 + 30 + read-write + + + + + CTRLA2 + DMAC Channel Control A Register (ch_num = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + BTSIZE + Buffer Transfer Size + 0 + 16 + read-write + + + SRC_WIDTH + Transfer Width for the Source + 24 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DST_WIDTH + Transfer Width for the Destination + 28 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DONE + Current Descriptor Stop Command and Transfer Completed Memory Indicator + 31 + 1 + read-write + + + + + CTRLB2 + DMAC Channel Control B Register (ch_num = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + SRC_DSCR + Source Address Descriptor + 16 + 1 + read-write + + + FETCH_FROM_MEM + Source address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the source. + 1 + + + + + DST_DSCR + Destination Address Descriptor + 20 + 1 + read-write + + + FETCH_FROM_MEM + Destination address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the destination. + 1 + + + + + FC + Flow Control + 21 + 2 + read-write + + + MEM2MEM_DMA_FC + Memory-to-Memory Transfer DMAC is flow controller + 0x0 + + + MEM2PER_DMA_FC + Memory-to-Peripheral Transfer DMAC is flow controller + 0x1 + + + PER2MEM_DMA_FC + Peripheral-to-Memory Transfer DMAC is flow controller + 0x2 + + + PER2PER_DMA_FC + Peripheral-to-Peripheral Transfer DMAC is flow controller + 0x3 + + + + + SRC_INCR + Incrementing, Decrementing or Fixed Address for the Source + 24 + 2 + read-write + + + INCREMENTING + The source address is incremented + 0x0 + + + DECREMENTING + The source address is decremented + 0x1 + + + FIXED + The source address remains unchanged + 0x2 + + + + + DST_INCR + Incrementing, Decrementing or Fixed Address for the Destination + 28 + 2 + read-write + + + INCREMENTING + The destination address is incremented + 0x0 + + + DECREMENTING + The destination address is decremented + 0x1 + + + FIXED + The destination address remains unchanged + 0x2 + + + + + IEN + Interrupt Enable Not + 30 + 1 + read-write + + + + + CFG2 + DMAC Channel Configuration Register (ch_num = 2) + 0x000000A0 + 32 + read-write + 0x01000000 + + + SRC_PER + Source with Peripheral identifier + 0 + 4 + read-write + + + DST_PER + Destination with Peripheral identifier + 4 + 4 + read-write + + + SRC_H2SEL + Software or Hardware Selection for the Source + 9 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + DST_H2SEL + Software or Hardware Selection for the Destination + 13 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + SOD + Stop On Done + 16 + 1 + read-write + + + DISABLE + STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. + 0 + + + ENABLE + STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. + 1 + + + + + LOCK_IF + Interface Lock + 20 + 1 + read-write + + + DISABLE + Interface Lock capability is disabled + 0 + + + ENABLE + Interface Lock capability is enabled + 1 + + + + + LOCK_B + Bus Lock + 21 + 1 + read-write + + + DISABLE + AHB Bus Locking capability is disabled. + 0 + + + + + LOCK_IF_L + Master Interface Arbiter Lock + 22 + 1 + read-write + + + CHUNK + The Master Interface Arbiter is locked by the channel x for a chunk transfer. + 0 + + + BUFFER + The Master Interface Arbiter is locked by the channel x for a buffer transfer. + 1 + + + + + AHB_PROT + AHB Protection + 24 + 3 + read-write + + + FIFOCFG + FIFO Configuration + 28 + 2 + read-write + + + ALAP_CFG + The largest defined length AHB burst is performed on the destination AHB interface. + 0x0 + + + HALF_CFG + When half FIFO size is available/filled, a source/destination request is serviced. + 0x1 + + + ASAP_CFG + When there is enough space/data available to perform a single AHB access, then the request is serviced. + 0x2 + + + + + + + SADDR3 + DMAC Channel Source Address Register (ch_num = 3) + 0x000000B4 + 32 + read-write + 0x00000000 + + + SADDR + Channel x Source Address + 0 + 32 + read-write + + + + + DADDR3 + DMAC Channel Destination Address Register (ch_num = 3) + 0x000000B8 + 32 + read-write + 0x00000000 + + + DADDR + Channel x Destination Address + 0 + 32 + read-write + + + + + DSCR3 + DMAC Channel Descriptor Address Register (ch_num = 3) + 0x000000BC + 32 + read-write + 0x00000000 + + + DSCR + Buffer Transfer Descriptor Address + 2 + 30 + read-write + + + + + CTRLA3 + DMAC Channel Control A Register (ch_num = 3) + 0x000000C0 + 32 + read-write + 0x00000000 + + + BTSIZE + Buffer Transfer Size + 0 + 16 + read-write + + + SRC_WIDTH + Transfer Width for the Source + 24 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DST_WIDTH + Transfer Width for the Destination + 28 + 2 + read-write + + + BYTE + the transfer size is set to 8-bit width + 0x0 + + + HALF_WORD + the transfer size is set to 16-bit width + 0x1 + + + WORD + the transfer size is set to 32-bit width + 0x2 + + + + + DONE + Current Descriptor Stop Command and Transfer Completed Memory Indicator + 31 + 1 + read-write + + + + + CTRLB3 + DMAC Channel Control B Register (ch_num = 3) + 0x000000C4 + 32 + read-write + 0x00000000 + + + SRC_DSCR + Source Address Descriptor + 16 + 1 + read-write + + + FETCH_FROM_MEM + Source address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the source. + 1 + + + + + DST_DSCR + Destination Address Descriptor + 20 + 1 + read-write + + + FETCH_FROM_MEM + Destination address is updated when the descriptor is fetched from the memory. + 0 + + + FETCH_DISABLE + Buffer Descriptor Fetch operation is disabled for the destination. + 1 + + + + + FC + Flow Control + 21 + 2 + read-write + + + MEM2MEM_DMA_FC + Memory-to-Memory Transfer DMAC is flow controller + 0x0 + + + MEM2PER_DMA_FC + Memory-to-Peripheral Transfer DMAC is flow controller + 0x1 + + + PER2MEM_DMA_FC + Peripheral-to-Memory Transfer DMAC is flow controller + 0x2 + + + PER2PER_DMA_FC + Peripheral-to-Peripheral Transfer DMAC is flow controller + 0x3 + + + + + SRC_INCR + Incrementing, Decrementing or Fixed Address for the Source + 24 + 2 + read-write + + + INCREMENTING + The source address is incremented + 0x0 + + + DECREMENTING + The source address is decremented + 0x1 + + + FIXED + The source address remains unchanged + 0x2 + + + + + DST_INCR + Incrementing, Decrementing or Fixed Address for the Destination + 28 + 2 + read-write + + + INCREMENTING + The destination address is incremented + 0x0 + + + DECREMENTING + The destination address is decremented + 0x1 + + + FIXED + The destination address remains unchanged + 0x2 + + + + + IEN + Interrupt Enable Not + 30 + 1 + read-write + + + + + CFG3 + DMAC Channel Configuration Register (ch_num = 3) + 0x000000C8 + 32 + read-write + 0x01000000 + + + SRC_PER + Source with Peripheral identifier + 0 + 4 + read-write + + + DST_PER + Destination with Peripheral identifier + 4 + 4 + read-write + + + SRC_H2SEL + Software or Hardware Selection for the Source + 9 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + DST_H2SEL + Software or Hardware Selection for the Destination + 13 + 1 + read-write + + + SW + Software handshaking interface is used to trigger a transfer request. + 0 + + + HW + Hardware handshaking interface is used to trigger a transfer request. + 1 + + + + + SOD + Stop On Done + 16 + 1 + read-write + + + DISABLE + STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. + 0 + + + ENABLE + STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. + 1 + + + + + LOCK_IF + Interface Lock + 20 + 1 + read-write + + + DISABLE + Interface Lock capability is disabled + 0 + + + ENABLE + Interface Lock capability is enabled + 1 + + + + + LOCK_B + Bus Lock + 21 + 1 + read-write + + + DISABLE + AHB Bus Locking capability is disabled. + 0 + + + + + LOCK_IF_L + Master Interface Arbiter Lock + 22 + 1 + read-write + + + CHUNK + The Master Interface Arbiter is locked by the channel x for a chunk transfer. + 0 + + + BUFFER + The Master Interface Arbiter is locked by the channel x for a buffer transfer. + 1 + + + + + AHB_PROT + AHB Protection + 24 + 3 + read-write + + + FIFOCFG + FIFO Configuration + 28 + 2 + read-write + + + ALAP_CFG + The largest defined length AHB burst is performed on the destination AHB interface. + 0x0 + + + HALF_CFG + When half FIFO size is available/filled, a source/destination request is serviced. + 0x1 + + + ASAP_CFG + When there is enough space/data available to perform a single AHB access, then the request is serviced. + 0x2 + + + + + + + WPMR + DMAC Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444D41 + + + + + + + WPSR + DMAC Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + SMC + 6411D + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + CFG + SMC NFC Configuration Register + 0x00000000 + 32 + read-write + 0x00000000 + + + PAGESIZE + 0 + 2 + read-write + + + PS512_16 + Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes + 0x0 + + + PS1024_32 + Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes + 0x1 + + + PS2048_64 + Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes + 0x2 + + + PS4096_128 + Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes + 0x3 + + + + + WSPARE + Write Spare Area + 8 + 1 + read-write + + + RSPARE + Read Spare Area + 9 + 1 + read-write + + + EDGECTRL + Rising/Falling Edge Detection Control + 12 + 1 + read-write + + + RBEDGE + Ready/Busy Signal Edge Detection + 13 + 1 + read-write + + + DTOCYC + Data Timeout Cycle Number + 16 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 20 + 3 + read-write + + + X1 + DTOCYC + 0x0 + + + X16 + DTOCYC x 16 + 0x1 + + + X128 + DTOCYC x 128 + 0x2 + + + X256 + DTOCYC x 256 + 0x3 + + + X1024 + DTOCYC x 1024 + 0x4 + + + X4096 + DTOCYC x 4096 + 0x5 + + + X65536 + DTOCYC x 65536 + 0x6 + + + X1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + CTRL + SMC NFC Control Register + 0x00000004 + 32 + write-only + 0x00000000 + + + NFCEN + NAND Flash Controller Enable + 0 + 1 + write-only + + + NFCDIS + NAND Flash Controller Disable + 1 + 1 + write-only + + + + + SR + SMC NFC Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + SMCSTS + NAND Flash Controller status (this field cannot be reset) + 0 + 1 + read-only + + + RB_RISE + Selected Ready Busy Rising Edge Detected + 4 + 1 + read-only + + + RB_FALL + Selected Ready Busy Falling Edge Detected + 5 + 1 + read-only + + + NFCBUSY + NFC Busy (this field cannot be reset) + 8 + 1 + read-only + + + NFCWR + NFC Write/Read Operation (this field cannot be reset) + 11 + 1 + read-only + + + NFCSID + NFC Chip Select ID (this field cannot be reset) + 12 + 3 + read-only + + + XFRDONE + NFC Data Transfer Terminated + 16 + 1 + read-only + + + CMDDONE + Command Done + 17 + 1 + read-only + + + DTOE + Data Timeout Error + 20 + 1 + read-only + + + UNDEF + Undefined Area Error + 21 + 1 + read-only + + + AWB + Accessing While Busy + 22 + 1 + read-only + + + NFCASE + NFC Access Size Error + 23 + 1 + read-only + + + RB_EDGE0 + Ready/Busy Line 0 Edge Detected + 24 + 1 + read-only + + + + + IER + SMC NFC Interrupt Enable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + RB_RISE + Ready Busy Rising Edge Detection Interrupt Enable + 4 + 1 + write-only + + + RB_FALL + Ready Busy Falling Edge Detection Interrupt Enable + 5 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Enable + 16 + 1 + write-only + + + CMDDONE + Command Done Interrupt Enable + 17 + 1 + write-only + + + DTOE + Data Timeout Error Interrupt Enable + 20 + 1 + write-only + + + UNDEF + Undefined Area Access Interrupt Enable + 21 + 1 + write-only + + + AWB + Accessing While Busy Interrupt Enable + 22 + 1 + write-only + + + NFCASE + NFC Access Size Error Interrupt Enable + 23 + 1 + write-only + + + RB_EDGE0 + Ready/Busy Line 0 Interrupt Enable + 24 + 1 + write-only + + + + + IDR + SMC NFC Interrupt Disable Register + 0x00000010 + 32 + write-only + 0x00000000 + + + RB_RISE + Ready Busy Rising Edge Detection Interrupt Disable + 4 + 1 + write-only + + + RB_FALL + Ready Busy Falling Edge Detection Interrupt Disable + 5 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 16 + 1 + write-only + + + CMDDONE + Command Done Interrupt Disable + 17 + 1 + write-only + + + DTOE + Data Timeout Error Interrupt Disable + 20 + 1 + write-only + + + UNDEF + Undefined Area Access Interrupt Disable + 21 + 1 + write-only + + + AWB + Accessing While Busy Interrupt Disable + 22 + 1 + write-only + + + NFCASE + NFC Access Size Error Interrupt Disable + 23 + 1 + write-only + + + RB_EDGE0 + Ready/Busy Line 0 Interrupt Disable + 24 + 1 + write-only + + + + + IMR + SMC NFC Interrupt Mask Register + 0x00000014 + 32 + read-only + 0x00000000 + + + RB_RISE + Ready Busy Rising Edge Detection Interrupt Mask + 4 + 1 + read-only + + + RB_FALL + Ready Busy Falling Edge Detection Interrupt Mask + 5 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 16 + 1 + read-only + + + CMDDONE + Command Done Interrupt Mask + 17 + 1 + read-only + + + DTOE + Data Timeout Error Interrupt Mask + 20 + 1 + read-only + + + UNDEF + Undefined Area Access Interrupt Mask5 + 21 + 1 + read-only + + + AWB + Accessing While Busy Interrupt Mask + 22 + 1 + read-only + + + NFCASE + NFC Access Size Error Interrupt Mask + 23 + 1 + read-only + + + RB_EDGE0 + Ready/Busy Line 0 Interrupt Mask + 24 + 1 + read-only + + + + + ADDR + SMC NFC Address Cycle Zero Register + 0x00000018 + 32 + read-write + 0x00000000 + + + ADDR_CYCLE0 + NAND Flash Array Address cycle 0 + 0 + 8 + read-write + + + + + BANK + SMC Bank Address Register + 0x0000001C + 32 + read-write + 0x00000000 + + + BANK + Bank Identifier + 0 + 3 + read-write + + + + + ECC_CTRL + SMC ECC Control Register + 0x00000020 + 32 + write-only + 0x00000000 + + + RST + Reset ECC + 0 + 1 + write-only + + + SWRST + Software Reset + 1 + 1 + write-only + + + + + ECC_MD + SMC ECC Mode Register + 0x00000024 + 32 + read-write + 0x00000000 + + + ECC_PAGESIZE + ECC Page Size + 0 + 2 + read-write + + + PS512_16 + Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes + 0x0 + + + PS1024_32 + Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes + 0x1 + + + PS2048_64 + Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes + 0x2 + + + PS4096_128 + Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes + 0x3 + + + + + TYPCORREC + Type of Correction + 4 + 2 + read-write + + + CPAGE + 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) + 0x0 + + + C256B + 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) + 0x1 + + + C512B + 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) + 0x2 + + + + + + + ECC_SR1 + SMC ECC Status 1 Register + 0x00000028 + 32 + read-only + 0x00000000 + + + RECERR0 + Recoverable Error + 0 + 1 + read-only + + + ECCERR0 + ECC Error + 1 + 2 + read-only + + + RECERR1 + Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes + 4 + 1 + read-only + + + ECCERR1 + ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes + 5 + 1 + read-only + + + MULERR1 + Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes + 6 + 1 + read-only + + + RECERR2 + Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes + 8 + 1 + read-only + + + ECCERR2 + ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes + 9 + 1 + read-only + + + MULERR2 + Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes + 10 + 1 + read-only + + + RECERR3 + Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes + 12 + 1 + read-only + + + ECCERR3 + ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes + 13 + 1 + read-only + + + MULERR3 + Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes + 14 + 1 + read-only + + + RECERR4 + Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes + 16 + 1 + read-only + + + ECCERR4 + ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes + 17 + 2 + read-only + + + RECERR5 + Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes + 20 + 1 + read-only + + + ECCERR5 + ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes + 21 + 2 + read-only + + + RECERR6 + Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes + 24 + 1 + read-only + + + ECCERR6 + ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes + 25 + 2 + read-only + + + RECERR7 + Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes + 28 + 1 + read-only + + + ECCERR7 + ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes + 29 + 2 + read-only + + + + + ECC_PR0 + SMC ECC Parity 0 Register + 0x0000002C + 32 + read-only + 0x00000000 + + + BITADDR + Bit Address + 0 + 4 + read-only + + + WORDADDR + Word Address + 4 + 12 + read-only + + + + + ECC_PR0_W9BIT + SMC ECC Parity 0 Register + W9BIT + 0x0000002C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR0_W8BIT + SMC ECC Parity 0 Register + W8BIT + 0x0000002C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR1 + SMC ECC parity 1 Register + 0x00000030 + 32 + read-only + 0x00000000 + + + NPARITY + Parity N + 0 + 16 + read-only + + + + + ECC_PR1_W9BIT + SMC ECC parity 1 Register + W9BIT + 0x00000030 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR1_W8BIT + SMC ECC parity 1 Register + W8BIT + 0x00000030 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_SR2 + SMC ECC status 2 Register + 0x00000034 + 32 + read-only + 0x00000000 + + + RECERR8 + Recoverable Error in the page between the 2048th and the 2303rd bytes + 0 + 1 + read-only + + + ECCERR8 + ECC Error in the page between the 2048th and the 2303rd bytes + 1 + 2 + read-only + + + RECERR9 + Recoverable Error in the page between the 2304th and the 2559th bytes + 4 + 1 + read-only + + + ECCERR9 + ECC Error in the page between the 2304th and the 2559th bytes + 5 + 1 + read-only + + + MULERR9 + Multiple Error in the page between the 2304th and the 2559th bytes + 6 + 1 + read-only + + + RECERR10 + Recoverable Error in the page between the 2560th and the 2815th bytes + 8 + 1 + read-only + + + ECCERR10 + ECC Error in the page between the 2560th and the 2815th bytes + 9 + 1 + read-only + + + MULERR10 + Multiple Error in the page between the 2560th and the 2815th bytes + 10 + 1 + read-only + + + RECERR11 + Recoverable Error in the page between the 2816th and the 3071st bytes + 12 + 1 + read-only + + + ECCERR11 + ECC Error in the page between the 2816th and the 3071st bytes + 13 + 1 + read-only + + + MULERR11 + Multiple Error in the page between the 2816th and the 3071st bytes + 14 + 1 + read-only + + + RECERR12 + Recoverable Error in the page between the 3072nd and the 3327th bytes + 16 + 1 + read-only + + + ECCERR12 + ECC Error in the page between the 3072nd and the 3327th bytes + 17 + 2 + read-only + + + RECERR13 + Recoverable Error in the page between the 3328th and the 3583rd bytes + 20 + 1 + read-only + + + ECCERR13 + ECC Error in the page between the 3328th and the 3583rd bytes + 21 + 2 + read-only + + + RECERR14 + Recoverable Error in the page between the 3584th and the 3839th bytes + 24 + 1 + read-only + + + ECCERR14 + ECC Error in the page between the 3584th and the 3839th bytes + 25 + 2 + read-only + + + RECERR15 + Recoverable Error in the page between the 3840th and the 4095th bytes + 28 + 1 + read-only + + + ECCERR15 + ECC Error in the page between the 3840th and the 4095th bytes + 29 + 2 + read-only + + + + + ECC_PR2 + SMC ECC parity 2 Register + 0x00000038 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR2_W8BIT + SMC ECC parity 2 Register + W8BIT + 0x00000038 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR3 + SMC ECC parity 3 Register + 0x0000003C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR3_W8BIT + SMC ECC parity 3 Register + W8BIT + 0x0000003C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR4 + SMC ECC parity 4 Register + 0x00000040 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR4_W8BIT + SMC ECC parity 4 Register + W8BIT + 0x00000040 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR5 + SMC ECC parity 5 Register + 0x00000044 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR5_W8BIT + SMC ECC parity 5 Register + W8BIT + 0x00000044 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR6 + SMC ECC parity 6 Register + 0x00000048 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR6_W8BIT + SMC ECC parity 6 Register + W8BIT + 0x00000048 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR7 + SMC ECC parity 7 Register + 0x0000004C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes + 3 + 9 + read-only + + + NPARITY + Parity N + 12 + 12 + read-only + + + + + ECC_PR7_W8BIT + SMC ECC parity 7 Register + W8BIT + 0x0000004C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR8 + SMC ECC parity 8 Register + 0x00000050 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR9 + SMC ECC parity 9 Register + 0x00000054 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR10 + SMC ECC parity 10 Register + 0x00000058 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR11 + SMC ECC parity 11 Register + 0x0000005C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR12 + SMC ECC parity 12 Register + 0x00000060 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR13 + SMC ECC parity 13 Register + 0x00000064 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR14 + SMC ECC parity 14 Register + 0x00000068 + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + ECC_PR15 + SMC ECC parity 15 Register + 0x0000006C + 32 + read-only + 0x00000000 + + + BITADDR + Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 0 + 3 + read-only + + + WORDADDR + Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes + 3 + 8 + read-only + + + NPARITY + Parity N + 12 + 11 + read-only + + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000070 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in Write Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in Read Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000074 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 6 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 6 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 6 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 6 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000078 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + TIMINGS0 + SMC Timings Register (CS_number = 0) + 0x0000007C + 32 + read-write + 0x00000000 + + + TCLR + CLE to REN Low Delay + 0 + 4 + read-write + + + TADL + ALE to Data Start + 4 + 4 + read-write + + + TAR + ALE to REN Low Delay + 8 + 4 + read-write + + + OCMS + Off Chip Memory Scrambling Enable + 12 + 1 + read-write + + + TRR + Ready to REN Low Delay + 16 + 4 + read-write + + + TWB + WEN High to REN to Busy + 24 + 4 + read-write + + + RBNSEL + Ready/Busy Line Selection + 28 + 3 + read-write + + + NFSEL + NAND Flash Selection + 31 + 1 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x00000080 + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + NCS_CTRL + The Read operation is controlled by the NCS signal. + 0 + + + NRD_CTRL + The Read operation is controlled by the NRD signal. + 1 + + + + + WRITE_MODE + 1 + 1 + read-write + + + NCS_CTRL + The Write operation is controller by the NCS signal. + 0 + + + NWE_CTRL + The Write operation is controlled by the NWE signal. + 1 + + + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + BAT + Byte Access Type + 8 + 1 + read-write + + + DBW + Data Bus Width + 12 + 1 + read-write + + + BIT_8 + 8-bit bus + 0 + + + BIT_16 + 16-bit bus + 1 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000084 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in Write Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in Read Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000088 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 6 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 6 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 6 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 6 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x0000008C + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + TIMINGS1 + SMC Timings Register (CS_number = 1) + 0x00000090 + 32 + read-write + 0x00000000 + + + TCLR + CLE to REN Low Delay + 0 + 4 + read-write + + + TADL + ALE to Data Start + 4 + 4 + read-write + + + TAR + ALE to REN Low Delay + 8 + 4 + read-write + + + OCMS + Off Chip Memory Scrambling Enable + 12 + 1 + read-write + + + TRR + Ready to REN Low Delay + 16 + 4 + read-write + + + TWB + WEN High to REN to Busy + 24 + 4 + read-write + + + RBNSEL + Ready/Busy Line Selection + 28 + 3 + read-write + + + NFSEL + NAND Flash Selection + 31 + 1 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x00000094 + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + NCS_CTRL + The Read operation is controlled by the NCS signal. + 0 + + + NRD_CTRL + The Read operation is controlled by the NRD signal. + 1 + + + + + WRITE_MODE + 1 + 1 + read-write + + + NCS_CTRL + The Write operation is controller by the NCS signal. + 0 + + + NWE_CTRL + The Write operation is controlled by the NWE signal. + 1 + + + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + BAT + Byte Access Type + 8 + 1 + read-write + + + DBW + Data Bus Width + 12 + 1 + read-write + + + BIT_8 + 8-bit bus + 0 + + + BIT_16 + 16-bit bus + 1 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000098 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in Write Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in Read Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x0000009C + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 6 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 6 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 6 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 6 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x000000A0 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + TIMINGS2 + SMC Timings Register (CS_number = 2) + 0x000000A4 + 32 + read-write + 0x00000000 + + + TCLR + CLE to REN Low Delay + 0 + 4 + read-write + + + TADL + ALE to Data Start + 4 + 4 + read-write + + + TAR + ALE to REN Low Delay + 8 + 4 + read-write + + + OCMS + Off Chip Memory Scrambling Enable + 12 + 1 + read-write + + + TRR + Ready to REN Low Delay + 16 + 4 + read-write + + + TWB + WEN High to REN to Busy + 24 + 4 + read-write + + + RBNSEL + Ready/Busy Line Selection + 28 + 3 + read-write + + + NFSEL + NAND Flash Selection + 31 + 1 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x000000A8 + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + NCS_CTRL + The Read operation is controlled by the NCS signal. + 0 + + + NRD_CTRL + The Read operation is controlled by the NRD signal. + 1 + + + + + WRITE_MODE + 1 + 1 + read-write + + + NCS_CTRL + The Write operation is controller by the NCS signal. + 0 + + + NWE_CTRL + The Write operation is controlled by the NWE signal. + 1 + + + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + BAT + Byte Access Type + 8 + 1 + read-write + + + DBW + Data Bus Width + 12 + 1 + read-write + + + BIT_8 + 8-bit bus + 0 + + + BIT_16 + 16-bit bus + 1 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x000000AC + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in Write Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in Read Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x000000B0 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 6 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 6 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 6 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 6 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x000000B4 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + TIMINGS3 + SMC Timings Register (CS_number = 3) + 0x000000B8 + 32 + read-write + 0x00000000 + + + TCLR + CLE to REN Low Delay + 0 + 4 + read-write + + + TADL + ALE to Data Start + 4 + 4 + read-write + + + TAR + ALE to REN Low Delay + 8 + 4 + read-write + + + OCMS + Off Chip Memory Scrambling Enable + 12 + 1 + read-write + + + TRR + Ready to REN Low Delay + 16 + 4 + read-write + + + TWB + WEN High to REN to Busy + 24 + 4 + read-write + + + RBNSEL + Ready/Busy Line Selection + 28 + 3 + read-write + + + NFSEL + NAND Flash Selection + 31 + 1 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x000000BC + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + NCS_CTRL + The Read operation is controlled by the NCS signal. + 0 + + + NRD_CTRL + The Read operation is controlled by the NRD signal. + 1 + + + + + WRITE_MODE + 1 + 1 + read-write + + + NCS_CTRL + The Write operation is controller by the NCS signal. + 0 + + + NWE_CTRL + The Write operation is controlled by the NWE signal. + 1 + + + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + BAT + Byte Access Type + 8 + 1 + read-write + + + DBW + Data Bus Width + 12 + 1 + read-write + + + BIT_8 + 8-bit bus + 0 + + + BIT_16 + 16-bit bus + 1 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + + + OCMS + SMC OCMS Register + 0x00000110 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + SRSE + SRAM Scrambling Enable + 1 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000114 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000118 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPCR + Write Protection Control Register + 0x000001E4 + 32 + write-only + 0x00000000 + + + WP_EN + Write Protection Enable + 0 + 1 + write-only + + + WP_KEY + Write Protection KEY password + 8 + 24 + write-only + + + + + WPSR + Write Protection Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + WP_VSRC + Write Protection Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6469A + AHB Bus Matrix + MATRIX_ + 0x400E0200 + + 0 + 0x200 + registers + + + + 5 + 4 + 0-4 + MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 10 + 4 + 0-9 + SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS5 + Priority Register A for Slave 5 + 0x000000A8 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS6 + Priority Register A for Slave 6 + 0x000000B0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS7 + Priority Register A for Slave 7 + 0x000000B8 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS8 + Priority Register A for Slave 8 + 0x000000C0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + PRAS9 + Priority Register A for Slave 9 + 0x000000C8 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MRCR + Master Remap Control Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RCB0 + Remap Command Bit for AHB Master 0 + 0 + 1 + read-write + + + RCB1 + Remap Command Bit for AHB Master 1 + 1 + 1 + read-write + + + RCB2 + Remap Command Bit for AHB Master 2 + 2 + 1 + read-write + + + RCB3 + Remap Command Bit for AHB Master 3 + 3 + 1 + read-write + + + RCB4 + Remap Command Bit for AHB Master 4 + 4 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x200 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Enable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Disable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID16 + Peripheral Clock 16 Status + 16 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + + + CKGR_UCKR + UTMI Clock Register + 0x0000001C + 32 + read-write + 0x10200800 + + + UPLLEN + UTMI PLL Enable + 16 + 1 + read-write + + + UPLLCOUNT + UTMI PLL Start-up Time + 20 + 4 + read-write + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + UPLL_CLK + UPLLClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + UPLLDIV2 + UPLL Divisor by 2 + 13 + 1 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + UPLL_CLK + UPLL Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + LOCKU + UTMI PLL Lock Interrupt Enable + 6 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + LOCKU + UTMI PLL Lock Interrupt Disable + 6 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + LOCKU + UTMI PLL Lock Status + 6 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + LOCKU + UTMI PLL Lock Interrupt Mask + 6 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + UART + 6418H + Universal Asynchronous Receiver Transmitter + UART_ + 0x400E0600 + + 0 + 0x200 + registers + + + UART + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + EFC0 + 6450J + Embedded Flash Controller 0 + EFC + EFC0_ + 0x400E0800 + + 0 + 0x200 + registers + + + EFC0 + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 6315C + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0C00 + + 0 + 0x200 + registers + + + PIOA + 10 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + 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write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + 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read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write 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read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write 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Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 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read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output 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Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. 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Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt 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+ LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 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P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + 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+ Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + RSTC + 6373A + Reset Controller + SYSC + RSTC_ + 0x400E1200 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + Password + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1210 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + VDDIORDY + VDDIO Ready + 14 + 1 + read-write + + + VDDIO_REMOVED + VDDIO is removed (used before going to backup mode when backup batteries are used) + 0 + + + VDDIO_PRESENT + VDDIO is present (used before going to backup mode when backup batteries are used) + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + FWUPEN + Force Wake-up Enable + 0 + 1 + read-write + + + NOT_ENABLE + the Force Wake-up pin has no wake-up effect. + 0 + + + ENABLE + the Force Wake-up pin low forces the wake-up of the core power supply. + 1 + + + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + FWUPDBC + Force Wake-up Debouncer Period + 8 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + FWUP shall be low for at least 3 SLCK periods + 0x1 + + + 32_SCLK + FWUP shall be low for at least 32 SLCK periods + 0x2 + + + 512_SCLK + FWUP shall be low for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + FWUP shall be low for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + FWUP shall be low for at least 32,768 SLCK periods + 0x5 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + FWUPS + FWUP Wake-up Status + 0 + 1 + read-only + + + NO + no wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. + 1 + + + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDUTMI higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDUTMI lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + FWUPIS + FWUP Input Status + 12 + 1 + read-only + + + LOW + FWUP input is tied low. + 0 + + + HIGH + FWUP input is tied high. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081I + Real-time Timer + SYSC + RTT_ + 0x400E1230 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1250 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056O + Real-time Clock + SYSC + RTC_ + 0x400E1260 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01210720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x525443 + + + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1290 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/firmware_common/bsp/board_cstartup_gcc.c b/firmware_common/bsp/board_cstartup_gcc.c new file mode 100644 index 0000000..620058a --- /dev/null +++ b/firmware_common/bsp/board_cstartup_gcc.c @@ -0,0 +1,80 @@ +#include + +#include "configuration.h" + +extern char _bss_start[]; +extern char _bss_end[]; +extern char _data_start[]; +extern char _data_end[]; +extern char _data_load[]; +extern char _stack_init[]; + +int main(void); +__attribute__((noreturn)) void _start(void); + +__attribute__((section(".intvec"))) const void *const vector_table[64] = { + _stack_init, _start, + // Keeping the names the same as the IAR startup file to reduce porting + // effort. + NMI_Handler, + HardFault_Handler, + MemManage_Handler, + BusFault_Handler, + UsageFault_Handler, + 0, 0, 0, 0, // Reserved + SVC_Handler, + DebugMon_Handler, + 0, // Reserved + PendSV_Handler, + SysTick_Handler, + + // Configurable interrupts + SUPC_IrqHandler, // 0 SUPPLY CONTROLLER + RSTC_IrqHandler, // 1 RESET CONTROLLER + RTC_IrqHandler, // 2 REAL TIME CLOCK + RTT_IrqHandler, // 3 REAL TIME TIMER + WDT_IrqHandler, // 4 WATCHDOG TIMER + PMC_IrqHandler, // 5 PMC + EFC0_IrqHandler, // 6 EFC0 + EFC1_IrqHandler, // 7 EFC1 + DBGU_IrqHandler, // 8 DBGU + HSMC4_IrqHandler, // 9 HSMC4 + PIOA_IrqHandler, // 10 Parallel IO Controller A + PIOB_IrqHandler, // 11 Parallel IO Controller B + PIOC_IrqHandler, // 12 Parallel IO Controller C + USART0_IrqHandler, // 13 USART 0 + USART1_IrqHandler, // 14 USART 1 + USART2_IrqHandler, // 15 USART 2 + USART3_IrqHandler, // 16 USART 3 + MCI0_IrqHandler, // 17 Multimedia Card Interface + TWI0_IrqHandler, // 18 TWI 0 + TWI1_IrqHandler, // 19 TWI 1 + SPI0_IrqHandler, // 20 Serial Peripheral Interface + SSC0_IrqHandler, // 21 Serial Synchronous Controller 0 + TC0_IrqHandler, // 22 Timer Counter 0 + TC1_IrqHandler, // 23 Timer Counter 1 + TC2_IrqHandler, // 24 Timer Counter 2 + PWM_IrqHandler, // 25 Pulse Width Modulation Controller + ADCC0_IrqHandler, // 26 ADC controller0 + ADCC1_IrqHandler, // 27 ADC controller1 + HDMA_IrqHandler, // 28 HDMA + UDPD_IrqHandler, // 29 USB Device High Speed UDP_HS +}; + +void c_startup(void) { + // Make sure our vector table is the one actually used. + AT91C_BASE_NVIC->NVIC_VTOFFR = ((uintptr_t)(&vector_table)); + + // Init .data + memcpy(_data_start, _data_load, (size_t)(_data_end - _data_start)); + // Init .bss + memset(_bss_start, 0, (size_t)(_bss_end - _bss_start)); + + main(); + + // NOTE: Normally exit() would be called here to do cleanup. However with + // newlib-nano that pulls in a bunch of stdio code we don't really want. + + // Main shouldn't return. But if it does, lets just reset. + NVIC_SystemReset(); +} diff --git a/firmware_common/bsp/board_cstartup_iar.c b/firmware_common/bsp/board_cstartup_iar.c deleted file mode 100644 index b11e2dd..0000000 --- a/firmware_common/bsp/board_cstartup_iar.c +++ /dev/null @@ -1,140 +0,0 @@ -/*! -@file board_cstartup_iar.c -@brief Atmel-supplied source file for IAR board startup. - -This file captures the vector table in FLASH and has the required -entry symbols to make the IAR compiler happy and generate the proper -startup code to do low level initializations and then call main. -*/ - -/* ---------------------------------------------------------------------------- -* ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#include "configuration.h" - - - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef union { IntFunc __fun; void * __ptr; } IntVector; - -//------------------------------------------------------------------------------ -// ProtoTypes -//------------------------------------------------------------------------------ - -extern void __iar_program_start( void ); - -int __low_level_init( void ); - -//------------------------------------------------------------------------------ -// Variables -//------------------------------------------------------------------------------ -extern unsigned int __ICFEDIT_vector_start__; - -//------------------------------------------------------------------------------ -// Exception Table -//------------------------------------------------------------------------------ - -#pragma language=extended -#pragma segment="CSTACK" - -// The name "__vector_table" has special meaning for C-SPY: -// it is where the SP start value is found, and the NVIC vector -// table register (VTOR) is initialized to this address if != 0. - -#pragma section = ".intvec" -#pragma location = ".intvec" -const IntVector __vector_table[] = -{ - { .__ptr = __sfe( "CSTACK" ) }, - __iar_program_start, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, // Reserved - SVC_Handler, - DebugMon_Handler, - 0, // Reserved - PendSV_Handler, - SysTick_Handler, - - // Configurable interrupts - SUPC_IrqHandler, // 0 SUPPLY CONTROLLER - RSTC_IrqHandler, // 1 RESET CONTROLLER - RTC_IrqHandler, // 2 REAL TIME CLOCK - RTT_IrqHandler, // 3 REAL TIME TIMER - WDT_IrqHandler, // 4 WATCHDOG TIMER - PMC_IrqHandler, // 5 PMC - EFC0_IrqHandler, // 6 EFC0 - EFC1_IrqHandler, // 7 EFC1 - DBGU_IrqHandler, // 8 DBGU - HSMC4_IrqHandler, // 9 HSMC4 - PIOA_IrqHandler, // 10 Parallel IO Controller A - PIOB_IrqHandler, // 11 Parallel IO Controller B - PIOC_IrqHandler, // 12 Parallel IO Controller C - USART0_IrqHandler, // 13 USART 0 - USART1_IrqHandler, // 14 USART 1 - USART2_IrqHandler, // 15 USART 2 - USART3_IrqHandler, // 16 USART 3 - MCI0_IrqHandler, // 17 Multimedia Card Interface - TWI0_IrqHandler, // 18 TWI 0 - TWI1_IrqHandler, // 19 TWI 1 - SPI0_IrqHandler, // 20 Serial Peripheral Interface - SSC0_IrqHandler, // 21 Serial Synchronous Controller 0 - TC0_IrqHandler, // 22 Timer Counter 0 - TC1_IrqHandler, // 23 Timer Counter 1 - TC2_IrqHandler, // 24 Timer Counter 2 - PWM_IrqHandler, // 25 Pulse Width Modulation Controller - ADCC0_IrqHandler, // 26 ADC controller0 - ADCC1_IrqHandler, // 27 ADC controller1 - HDMA_IrqHandler, // 28 HDMA - UDPD_IrqHandler, // 29 USB Device High Speed UDP_HS - IrqHandlerNotUsed // 30 not used -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// This is the code that gets called on processor reset. To initialize the -/// device. -//------------------------------------------------------------------------------ -int __low_level_init( void ) -{ - unsigned int * src = __section_begin(".intvec"); - - AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(src)) | (0x0 << 7); - - return 1; // if return 0, the data sections will not be initialized. -} diff --git a/firmware_common/bsp/board_startup_gcc.s b/firmware_common/bsp/board_startup_gcc.s new file mode 100644 index 0000000..c27abf0 --- /dev/null +++ b/firmware_common/bsp/board_startup_gcc.s @@ -0,0 +1,18 @@ +.thumb +.syntax unified + + +/* +* The goal is to get to C code as fast as possible and do the more involved stuff there. +* All that's really needed is to ensure the stack pointer is set. +*/ +.text + +.align +.global _start +.thumb_func +_start: + LDR R0, =vector_table; + LDR SP, [R0]; + LDR R0, =c_startup; + BX R0; diff --git a/firmware_common/bsp/configuration.h b/firmware_common/bsp/configuration.h index 69b251a..4335ed1 100644 --- a/firmware_common/bsp/configuration.h +++ b/firmware_common/bsp/configuration.h @@ -11,7 +11,7 @@ to match the target hardware. ##### UART peripheral board-specific parameters $$$$$ SPI peripheral board-specific parameters %%%%% SSP peripheral board-specific parameters -^^^^^ IC peripheral board-specific parameters +^^^^^ I�C peripheral board-specific parameters ***********************************************************************************************************************/ @@ -50,7 +50,13 @@ Includes #include "AT91SAM3U4.h" #include "exceptions.h" #include "interrupts.h" + +/* ignore some warnings specific to the CMSIS headers */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wimplicit-int" #include "core_cm3.h" +#pragma GCC diagnostic pop + #include "main.h" #include "typedefs.h" #include "utilities.h" @@ -1202,12 +1208,12 @@ or 2MHz, so no issues. /*! @endcond */ /*********************************************************************************************************************** -^^^^^ IC (TWI) peripheral board-specific parameters +^^^^^ I�C (TWI) peripheral board-specific parameters ***********************************************************************************************************************/ /*! @cond DOXYGEN_EXCLUDE */ /*---------------------------------------------------------------------------------------------------------------------- -IC Master mode for EiE development board (TWI0) +I�C Master mode for EiE development board (TWI0) ASCII: LCD and Blade Dot Matrix: Blade and R01 EIE_DOTMATRIX accelerometer */ diff --git a/firmware_common/bsp/kill_x_cycles.s b/firmware_common/bsp/kill_x_cycles.s index b3b1d5f..f09f1ce 100644 --- a/firmware_common/bsp/kill_x_cycles.s +++ b/firmware_common/bsp/kill_x_cycles.s @@ -1,46 +1,45 @@ /****************************************************************************** * File: kill_x_cycles.s * ******************************************************************************/ +.thumb +.syntax unified - MODULE KillXCyclesAsm - SECTION .text : CODE : NOROOT(2) - THUMB +.text +.align - PUBLIC kill_x_cycles +@ ----------------------------------------------------------------------------- +@ kill_x_cycles(unsigned long int x) +@ This function passes roughly x cycles, where x is any 32-bit integer. +@ Because of the entry and exit times, it will never quite be exact, but the +@ larger x is, the less impact the overhead will be. +@ The processor is fully awake during this time and simply kills instructions +@ by running through a loop. +@ To be compatible with C code, the function parameter must use r0 as, by +@ convention, that's where the compiler would put it. +@ All timing is shown in [ ]. The function overhead is subtracted off the value passed +@ in, then the value is reduced by the number of cycles it takes for each run of the kill_x_loop +@ There will be a remainder error here, but it's at most 2 cycles. +@ +@ Requires: +@ - R0 is an unsigned value holding the number of cycles to be passed +@ +@ Promises: +@ - Roughly x cycles will be passed. At 12 MHz clock, each cycle is 83.3ns. +@ Therefore, the maximum time that can be passed is about 357 seconds. +@ - r0 is destroyed during this code, thus the function is not re-entrant. -;----------------------------------------------------------------------------- -; kill_x_cycles(unsigned long int x) -; This function passes roughly x cycles, where x is any 32-bit integer. -; Because of the entry and exit times, it will never quite be exact, but the -; larger x is, the less impact the overhead will be. -; The processor is fully awake during this time and simply kills instructions -; by running through a loop. -; To be compatible with C code, the function parameter must use r0 as, by -; convention, that's where the compiler would put it. -; All timing is shown in [ ]. The function overhead is subtracted off the value passed -; in, then the value is reduced by the number of cycles it takes for each run of the kill_x_loop -; There will be a remainder error here, but it's at most 2 cycles. -; -; Requires: -; - R0 is an unsigned value holding the number of cycles to be passed -; -; Promises: -; - Roughly x cycles will be passed. At 12 MHz clock, each cycle is 83.3ns. -; Therefore, the maximum time that can be passed is about 357 seconds. -; - r0 is destroyed during this code, thus the function is not re-entrant. +#define OVERHEAD 7 -#define OVERHEAD 7 +.global kill_x_cycles +.thumb_func +kill_x_cycles: @ [1] Function entry + CMP r0, OVERHEAD @ [1] Check if x is at least OVERHEAD. + BLT kill_x_cycles_end @ [1] If x is less than the overhead, just exit + SUB r0, r0, OVERHEAD @ [1] Reduce the count by OVERHEAD -kill_x_cycles ; [1] Function entry - CMP r0, #OVERHEAD ; [1] Check if x is at least OVERHEAD. - BLT kill_x_cycles_end ; [1] If x is less than the overhead, just exit - SUB r0, r0, #OVERHEAD ; [1] Reduce the count by OVERHEAD - -kill_x_loop ; [3 cycle loop] - SUBS r0, r0, #3 ; [1] Subtract the loop cycle cost from the counter - BPL kill_x_loop ; [2] Check if positive or zero and repeat if so +kill_x_loop: @ [3 cycle loop] + SUBS r0, r0, 3 @ [1] Subtract the loop cycle cost from the counter + BPL kill_x_loop @ [2] Check if positive or zero and repeat if so -kill_x_cycles_end ; - MOV PC, r14 ; [1] Move the return address back to the PC - - END +kill_x_cycles_end: @ + BX LR @ [1] Move the return address back to the PC diff --git a/firmware_common/bsp/sam3u2.ld b/firmware_common/bsp/sam3u2.ld new file mode 100644 index 0000000..6366b65 --- /dev/null +++ b/firmware_common/bsp/sam3u2.ld @@ -0,0 +1,54 @@ +LD_FEATURE("SANE_EXPR"); + +MEMORY +{ + ROM0 (rx!w) : ORIGIN = 0x00080000, LENGTH = 128K + RAM0 (rwxa) : ORIGIN = 0x20000000, LENGTH = 16K + RAM1 (rwxa) : ORIGIN = 0x20080000, LENGTH = 16K + NAND_RAM (rwa) : ORIGIN = 0x20100000, LENGTH = 4224 +} + +ENTRY(_start); + +SECTIONS +{ + _stack_size = 0x1000; + _heap_size = 0x4000; /* All of RAM1 */ + + .intvec (READONLY) : { + *(.intvec) + } >ROM0 + + .text (READONLY) : + { + *(.text* .rodata*) + } >ROM0 + + .data : { + _data_start = ABSOLUTE(.); + *(.data*) + _data_end = ABSOLUTE(.); + } > RAM0 AT>ROM0 + _data_load = LOADADDR(.data); + + .bss (NOLOAD) : { + _bss_start = ABSOLUTE(.); + *(.bss*) + *( COMMON*) + _bss_end = ABSOLUTE(.); + } >RAM0 + + .stack (NOLOAD) : { + . = ALIGN(8); + _stack_limit = ABSOLUTE(.); + . += _stack_size; + _stack_init = ABSOLUTE(.); + } > RAM0 + + .heap (NOLOAD) : { + . = ALIGN(8); + _heap_start = ABSOLUTE(.); + . += _heap_size; + _heap_end = ABSOLUTE(.); + } > RAM1 +} \ No newline at end of file diff --git a/firmware_common/bsp/sbrk.c b/firmware_common/bsp/sbrk.c new file mode 100644 index 0000000..372824a --- /dev/null +++ b/firmware_common/bsp/sbrk.c @@ -0,0 +1,26 @@ +// Newlib-nano requires us to provide _sbrk, since it doesn't know if it's +// running on an OS or not. This makes use of the heap defined in the linker +// script. + +#include +#include + +#undef errno +extern int errno; + +extern char _heap_start; +extern char _heap_end; + +static char *pcBreak = &_heap_start; + +void *_sbrk(intptr_t increment) { + if ((increment > (&_heap_end - pcBreak)) || + (increment < -(pcBreak - &_heap_start))) { + errno = ENOMEM; + return ((void *)-1); + } + + void *pcOld = pcBreak; + pcBreak += increment; + return pcOld; +} diff --git a/firmware_common/cmsis/gcc_support.s b/firmware_common/cmsis/gcc_support.s new file mode 100644 index 0000000..0983b25 --- /dev/null +++ b/firmware_common/cmsis/gcc_support.s @@ -0,0 +1,13 @@ +/* Implement some intrinsics temporarily, won't be needed when upgrading to new CMSIS */ +/* Not efficient, but easy */ + +.thumb +.syntax unified + +.text + +.global __RBIT +.thumb_func +__RBIT: + RBIT R0, R0 + BX LR diff --git a/firmware_common/drivers/exceptions.h b/firmware_common/drivers/exceptions.h index 44b996c..59053ad 100644 --- a/firmware_common/drivers/exceptions.h +++ b/firmware_common/drivers/exceptions.h @@ -48,7 +48,7 @@ typedef void( *IntFunc )( void ); /// Weak attribute - #define WEAK __weak + #define WEAK __attribute__((weak)) //------------------------------------------------------------------------------ // Global functions @@ -58,78 +58,78 @@ typedef void( *IntFunc )( void ); // Exception Handlers //------------------------------------------------------------------------------ -extern WEAK void NMI_Handler( void ); -extern WEAK void HardFault_Handler( void ); -extern WEAK void MemManage_Handler( void ); -extern WEAK void BusFault_Handler( void ); -extern WEAK void UsageFault_Handler( void ); -extern WEAK void SVC_Handler( void ); -extern WEAK void DebugMon_Handler( void ); -extern WEAK void PendSV_Handler( void ); -extern WEAK void SysTick_Handler( void ); +extern void NMI_Handler( void ); +extern void HardFault_Handler( void ); +extern void MemManage_Handler( void ); +extern void BusFault_Handler( void ); +extern void UsageFault_Handler( void ); +extern void SVC_Handler( void ); +extern void DebugMon_Handler( void ); +extern void PendSV_Handler( void ); +extern void SysTick_Handler( void ); void IrqHandlerNotUsed(void); // System Controller extern void SYS_IrqHandler(void); // SUPPLY CONTROLLER -extern WEAK void SUPC_IrqHandler(void); +extern void SUPC_IrqHandler(void); // RESET CONTROLLER -extern WEAK void RSTC_IrqHandler(void); +extern void RSTC_IrqHandler(void); // REAL TIME CLOCK -extern WEAK void RTC_IrqHandler(void); +extern void RTC_IrqHandler(void); // REAL TIME TIMER -extern WEAK void RTT_IrqHandler(void); +extern void RTT_IrqHandler(void); // WATCHDOG TIMER -extern WEAK void WDT_IrqHandler(void); +extern void WDT_IrqHandler(void); // PMC -extern WEAK void PMC_IrqHandler(void); +extern void PMC_IrqHandler(void); // EFC0 -extern WEAK void EFC0_IrqHandler(void); +extern void EFC0_IrqHandler(void); // EFC1 -extern WEAK void EFC1_IrqHandler(void); +extern void EFC1_IrqHandler(void); // DBGU -extern WEAK void DBGU_IrqHandler(void); +extern void DBGU_IrqHandler(void); // HSMC4 -extern WEAK void HSMC4_IrqHandler(void); +extern void HSMC4_IrqHandler(void); // Parallel IO Controller A -extern WEAK void PIOA_IrqHandler(void); +extern void PIOA_IrqHandler(void); // Parallel IO Controller B -extern WEAK void PIOB_IrqHandler(void); +extern void PIOB_IrqHandler(void); // Parallel IO Controller C -extern WEAK void PIOC_IrqHandler(void); +extern void PIOC_IrqHandler(void); // USART 0 -extern WEAK void USART0_IrqHandler(void); +extern void USART0_IrqHandler(void); // USART 1 -extern WEAK void USART1_IrqHandler(void); +extern void USART1_IrqHandler(void); // USART 2 -extern WEAK void USART2_IrqHandler(void); +extern void USART2_IrqHandler(void); // USART 3 -extern WEAK void USART3_IrqHandler(void); +extern void USART3_IrqHandler(void); // Multimedia Card Interface -extern WEAK void MCI0_IrqHandler(void); +extern void MCI0_IrqHandler(void); // TWI 0 -extern WEAK void TWI0_IrqHandler(void); +extern void TWI0_IrqHandler(void); // TWI 1 -extern WEAK void TWI1_IrqHandler(void); +extern void TWI1_IrqHandler(void); // Serial Peripheral Interface 0 -extern WEAK void SPI0_IrqHandler(void); +extern void SPI0_IrqHandler(void); // Serial Synchronous Controller 0 -extern WEAK void SSC0_IrqHandler(void); +extern void SSC0_IrqHandler(void); // Timer Counter 0 -extern WEAK void TC0_IrqHandler(void); +extern void TC0_IrqHandler(void); // Timer Counter 1 -extern WEAK void TC1_IrqHandler(void); +extern void TC1_IrqHandler(void); // Timer Counter 2 -extern WEAK void TC2_IrqHandler(void); +extern void TC2_IrqHandler(void); // PWM Controller -extern WEAK void PWM_IrqHandler(void); +extern void PWM_IrqHandler(void); // ADC controller0 -extern WEAK void ADCC0_IrqHandler(void); +extern void ADCC0_IrqHandler(void); // ADC controller1 -extern WEAK void ADCC1_IrqHandler(void); +extern void ADCC1_IrqHandler(void); // HDMA -extern WEAK void HDMA_IrqHandler(void); +extern void HDMA_IrqHandler(void); // USB Device High Speed UDP_HS -extern WEAK void UDPD_IrqHandler(void); +extern void UDPD_IrqHandler(void); diff --git a/firmware_common/drivers/messaging.c b/firmware_common/drivers/messaging.c index e615665..36778a6 100644 --- a/firmware_common/drivers/messaging.c +++ b/firmware_common/drivers/messaging.c @@ -239,9 +239,9 @@ void MessagingRunActiveState(void) */ u32 QueueMessage(MessageType** ppsTargetTxBuffer_, u32 u32MessageSize_, u8* pu8MessageData_) { - MessageSlotType *psSlotParser; - MessageType *psNewMessage; - MessageType *psListParser; + MessageSlotType *psSlotParser = NULL; + MessageType *psNewMessage = NULL; + MessageType *psListParser = NULL; u8 u8SlotsRequired; u32 u32BytesRemaining = u32MessageSize_; u32 u32CurrentMessageSize = 0; diff --git a/firmware_common/drivers/sam3u_spi.c b/firmware_common/drivers/sam3u_spi.c index d149ef5..63d01cc 100644 --- a/firmware_common/drivers/sam3u_spi.c +++ b/firmware_common/drivers/sam3u_spi.c @@ -179,7 +179,7 @@ and the RxBuffer size. void SpiRelease(SpiPeripheralType* psSpiPeripheral_) { /* Check to see if the peripheral is already released */ - if( !(psSpiPeripheral_->u32PrivateFlags) & _SPI_PERIPHERAL_ASSIGNED ) + if( !(psSpiPeripheral_->u32PrivateFlags & _SPI_PERIPHERAL_ASSIGNED) ) { return; } @@ -266,7 +266,7 @@ u32 SpiWriteData(SpiPeripheralType* psSpiPeripheral_, u32 u32Size_, u8* pu8Data_ /* Check for a valid size */ if(u32Size_ == 0) { - return NULL; + return 0; } /* Attempt to queue message and get a response token */ diff --git a/firmware_common/drivers/sam3u_ssp.c b/firmware_common/drivers/sam3u_ssp.c index 12ea61a..9e62c3a 100644 --- a/firmware_common/drivers/sam3u_ssp.c +++ b/firmware_common/drivers/sam3u_ssp.c @@ -352,7 +352,7 @@ and the RxBuffer. void SspRelease(SspPeripheralType* psSspPeripheral_) { /* Check to see if the peripheral is already released */ - if( !(psSspPeripheral_->u32PrivateFlags) & _SSP_PERIPHERAL_ASSIGNED ) + if( !(psSspPeripheral_->u32PrivateFlags & _SSP_PERIPHERAL_ASSIGNED) ) { return; } diff --git a/firmware_common/drivers/sam3u_uart.c b/firmware_common/drivers/sam3u_uart.c index 51c0ba9..9509ee4 100644 --- a/firmware_common/drivers/sam3u_uart.c +++ b/firmware_common/drivers/sam3u_uart.c @@ -291,7 +291,7 @@ u32 UartWriteByte(UartPeripheralType* psUartPeripheral_, u8 u8Byte_) /* Attempt to queue message and get a response token */ u32Token = QueueMessage(&psUartPeripheral_->psTransmitBuffer, 1, &u8Data); - if( u32Token != NULL ) + if( u32Token != 0 ) { /* If the system is initializing, we want to manually cycle the UART task through one iteration to send the message */ @@ -331,7 +331,7 @@ u32 UartWriteData(UartPeripheralType* psUartPeripheral_, u32 u32Size_, u8* pu8Da /* Check for a valid size */ if(u32Size_ == 0) { - return NULL; + return 0; } /* Attempt to queue message and get a response token */ diff --git a/firmware_dotmatrix/bsp/mpgl2-ehdw-01.c b/firmware_dotmatrix/bsp/mpgl2-ehdw-01.c index 8bd6800..a6388f0 100644 --- a/firmware_dotmatrix/bsp/mpgl2-ehdw-01.c +++ b/firmware_dotmatrix/bsp/mpgl2-ehdw-01.c @@ -6,6 +6,7 @@ This file provides core and GPIO functions for the mpgl2-ehdw-01 board. ***********************************************************************************************************************/ #include "configuration.h" +#ifdef EIE_DOTMATRIX_R01 /*********************************************************************************************************************** Global variable definitions with scope across entire project. @@ -373,7 +374,7 @@ void PWMAudioOff(u32 u32Channel_) } /* end PWMAudioOff() */ - +#endif // EIE_DOTMATRIX_R01 /*--------------------------------------------------------------------------------------------------------------------*/ /* End of File */ diff --git a/firmware_dotmatrix/bsp/mpgl2-ehdw-02.c b/firmware_dotmatrix/bsp/mpgl2-ehdw-02.c index 8de37f6..311db84 100644 --- a/firmware_dotmatrix/bsp/mpgl2-ehdw-02.c +++ b/firmware_dotmatrix/bsp/mpgl2-ehdw-02.c @@ -117,6 +117,9 @@ void WatchDogSetup(void) */ void ClockSetup(void) { +<<<<<<< HEAD +/* Enable the master clock on the PKC0 clock out pin (PA_27_CLOCK_OUT) */ +======= /* Set flash wait states to allow 48 MHz system clock (2 wait states required) */ AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_3WS; @@ -124,20 +127,28 @@ void ClockSetup(void) AT91C_BASE_PMC->PMC_PCER = PMC_PCER_INIT; /* Enable the master clock on the PKC0 clock out pin (PA_27_CLOCK_OUT) */ +>>>>>>> master AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_SYS_CLK | AT91C_PMC_PRES_CLK; AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0; + while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_PCKRDY0) ); /* Turn on the main oscillator and wait for it to start up */ AT91C_BASE_PMC->PMC_MOR = PMC_MOR_INIT; while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCXTS) ); - /* Assign main clock as crystal */ + /* Assign main clock as crystal and wait for switch */ AT91C_BASE_PMC->PMC_MOR |= (AT91C_CKGR_MOSCSEL | MOR_KEY); - + while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCSELS) ); + + /* Set flash wait states to allow 48 MHz system clock (2 wait states required) */ + /* Note: There is an errata where the flash controller can't operate at sub-5 Mhz with + wait states programmed, so this must be done after the clock is bumped to 12 Mhz*/ + AT91C_BASE_EFC0->EFC_FMR = AT91C_EFC_FWS_2WS; + /* Initialize PLLA and wait for lock */ AT91C_BASE_PMC->PMC_PLLAR = PMC_PLAAR_INIT; while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) ); - + /* Assign the PLLA as the main system clock with prescaler active using the sequence suggested in the user guide */ AT91C_BASE_PMC->PMC_MCKR = PMC_MCKR_INIT; while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); @@ -146,7 +157,11 @@ void ClockSetup(void) /* Initialize UTMI for USB usage */ AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_UPLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; - while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) ); + while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) ); + + /* Activate the peripheral clocks needed for the system, must be done + last to ensure all clock sources are valid before clocking periphs. */ + AT91C_BASE_PMC->PMC_PCER = PMC_PCER_INIT; } /* end ClockSetup */ diff --git a/firmware_dotmatrix/bsp/mpgl2-ehdw-02.h b/firmware_dotmatrix/bsp/mpgl2-ehdw-02.h index 8687cc5..41f91d9 100644 --- a/firmware_dotmatrix/bsp/mpgl2-ehdw-02.h +++ b/firmware_dotmatrix/bsp/mpgl2-ehdw-02.h @@ -392,7 +392,7 @@ counter must be set at 1280. */ #define MOR_KEY (u32)(0x37 << 16) -#define PMC_MOR_INIT (u32)0x0037F019 +#define PMC_MOR_INIT (u32)0x0037F009 /* 31 [0] Reserved 30 [0] " @@ -425,9 +425,9 @@ counter must be set at 1280. */ 08 [0] " 07 [0] Reserved - 06 [0] MOSCRCF 8MHz + 06 [0] MOSCRCF 4MHz (Keep at 4 to match startup) 05 [0] " - 04 [1] " + 04 [0] " 03 [1] MOSCRCEN main on-chip RC osc is on for now 02 [0] WAITMODE disabled @@ -2158,7 +2158,7 @@ For now, don't worry about explictly disabling any write capability. */ /* PIO Write Protect Mode Register PIO_WPMR -Enables the Write Protect if WPKEY corresponds to 0x50494F (PIO in ASCII). +Enables the Write Protect if WPKEY corresponds to 0x50494F ("PIO" in ASCII). Though this is defined in the user guide, there is no definition in the processor header file. We don't want to lock access to the GPIO registers anyway, so we won't use this for now. */ diff --git a/firmware_dotmatrix/drivers/captouch.c b/firmware_dotmatrix/drivers/captouch.c index dcd9dc8..ba06a20 100644 --- a/firmware_dotmatrix/drivers/captouch.c +++ b/firmware_dotmatrix/drivers/captouch.c @@ -36,7 +36,7 @@ PROTECTED FUNCTIONS #include "configuration.h" #include "libqtouch.h" - +#ifndef EIE_NO_CAPTOUCH #define GET_SENSOR_STATE(SENSOR_NUMBER) (qt_measure_data.qt_touch_status.sensor_states[(SENSOR_NUMBER/8)] & (1 << (SENSOR_NUMBER % 8))) #define GET_ROTOR_SLIDER_POSITION(ROTOR_SLIDER_NUMBER) qt_measure_data.qt_touch_status.rotor_slider_values[ROTOR_SLIDER_NUMBER] @@ -497,7 +497,7 @@ void CapTouchSM_Measure(void) } /* end CapTouchSM_Measure() */ - +#endif /* EIE_NO_CAPTOUCH */ /*--------------------------------------------------------------------------------------------------------------------*/ /* End of File */ /*--------------------------------------------------------------------------------------------------------------------*/ \ No newline at end of file diff --git a/firmware_dotmatrix/iar_7_20_1/eie_dotmatrix_01.ewd b/firmware_dotmatrix/iar_7_20_1/eie_dotmatrix_01.ewd deleted file mode 100644 index cd0a173..0000000 --- a/firmware_dotmatrix/iar_7_20_1/eie_dotmatrix_01.ewd +++ /dev/null @@ -1,2697 +0,0 @@ - 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- - - - - - - - - - - - - - - - - _BSP - - Includes - - $PROJ_DIR$\..\..\firmware_common\bsp\AT91SAM3U4.h - - - $PROJ_DIR$\..\..\firmware_common\bsp\configuration.h - - - $PROJ_DIR$\..\bsp\mpgl2-ehdw-02.h - - - $PROJ_DIR$\..\..\firmware_common\bsp\sam3u2-flash.icf - - - $PROJ_DIR$\..\..\firmware_common\bsp\typedefs.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\bsp\board_cstartup_iar.c - - - $PROJ_DIR$\..\..\firmware_common\bsp\kill_x_cycles.s - - - $PROJ_DIR$\..\bsp\mpgl2-ehdw-02.c - - - - - _CMSIS - - $PROJ_DIR$\..\..\firmware_common\cmsis\core_cm3.h - - - - _Drivers - - Include - - $PROJ_DIR$\..\..\firmware_common\drivers\adc12.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\ant_api.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\antdefines.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\antmessage.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\buttons.h - - - $PROJ_DIR$\..\drivers\captouch.h - - - $PROJ_DIR$\..\..\firmware_common\drivers\exceptions.h - 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$PROJ_DIR$\..\..\firmware_common\application\main.h - - - $PROJ_DIR$\..\..\firmware_common\application\music.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.h - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.h - - - - Source - - $PROJ_DIR$\..\..\firmware_common\application\blade\blade_api.c - - - $PROJ_DIR$\..\..\firmware_common\application\debug.c - - - $PROJ_DIR$\..\..\firmware_common\application\main.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app1.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app2.c - - - $PROJ_DIR$\..\..\firmware_common\application\user_app3.c - - - - diff --git a/firmware_dotmatrix/iar_8_20_1/eie_dotmatrix_01.eww b/firmware_dotmatrix/iar_8_20_1/eie_dotmatrix_01.eww deleted file mode 100644 index 38ff2e0..0000000 --- a/firmware_dotmatrix/iar_8_20_1/eie_dotmatrix_01.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\eie_dotmatrix_01.ewp - - - - - diff --git a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.cspy.ps1 b/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.cspy.ps1 deleted file mode 100644 index aab6869..0000000 --- a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.cspy.ps1 +++ /dev/null @@ -1,31 +0,0 @@ -param([String]$debugfile = ""); - -# This powershell file has been generated by the IAR Embedded Workbench -# C - SPY Debugger, as an aid to preparing a command line for running -# the cspybat command line utility using the appropriate settings. -# -# Note that this file is generated every time a new debug session -# is initialized, so you may want to move or rename the file before -# making changes. -# -# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed -# by the name of the debug file (usually an ELF / DWARF or UBROF file). -# -# Read about available command line parameters in the C - SPY Debugging -# Guide. Hints about additional command line parameters that may be -# useful in specific cases : -# --download_only Downloads a code image without starting a debug -# session afterwards. -# --silent Omits the sign - on message. -# --timeout Limits the maximum allowed execution time. -# - - -if ($debugfile -eq "") -{ -& "D:\IAR\EWARM_8_10_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_dotmatrix\iar_8_20_1\settings\eie_dotmatrix_01.Debug.general.xcl" --backend -f "E:\Github\razor_sam3u2\firmware_dotmatrix\iar_8_20_1\settings\eie_dotmatrix_01.Debug.driver.xcl" -} -else -{ -& "D:\IAR\EWARM_8_10_1\common\bin\cspybat" -f "E:\Github\razor_sam3u2\firmware_dotmatrix\iar_8_20_1\settings\eie_dotmatrix_01.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\Github\razor_sam3u2\firmware_dotmatrix\iar_8_20_1\settings\eie_dotmatrix_01.Debug.driver.xcl" -} diff --git a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.driver.xcl b/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.driver.xcl deleted file mode 100644 index 48d076a..0000000 --- a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.driver.xcl +++ /dev/null @@ -1,29 +0,0 @@ -"--endian=little" - -"--cpu=Cortex-M3" - -"--fpu=None" - -"-p" - -"D:\IAR\EWARM_8_10_1\arm\CONFIG\debugger\Atmel\ATSAM3U2C.ddf" - -"--semihosting" - -"--device=ATSAM3U2C" - -"--drv_communication=USB0" - -"--drv_interface_speed=auto" - -"--jlink_initial_speed=32" - -"--jlink_reset_strategy=0,0" - -"--drv_catch_exceptions=0x000" - -"--drv_swo_clock_setup=72000000,0,2000000" - - - - diff --git a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.general.xcl b/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.general.xcl deleted file mode 100644 index a216c70..0000000 --- a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"D:\IAR\EWARM_8_10_1\arm\bin\armproc.dll" - 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- - - - diff --git a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01_Debug.jlink b/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01_Debug.jlink deleted file mode 100644 index 39b6d05..0000000 --- a/firmware_dotmatrix/iar_8_20_1/settings/eie_dotmatrix_01_Debug.jlink +++ /dev/null @@ -1,39 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -MonModeVTableAddr = 0xFFFFFFFF -MonModeDebug = 0 -MaxNumAPs = 0 -LowPowerHandlingMode = 0 -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="ARM7" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..bfca40c --- /dev/null +++ b/readme.md @@ -0,0 +1,16 @@ +# Embedded in Embedded Development + +[TOC] + +## Setup + +To install the necessary tools to compile the project see [setup.md](docs/setup.md) +To set up the VSCode development environment see [vscode.md](docs/vscode.md) + +## Compiling reference + +To compile the project + +1. Open a new terminal +2. Run `./waf configure --board=` replacing `` with either `ASCII` or `DOT_MATRIX` depending on the board you have. This step should only need to be run once if successful. +3. Run `./waf build` to build or `./waf build -F` to build and flash the device. diff --git a/settings/eie_assembler.Debug.cspy.ps1 b/settings/eie_assembler.Debug.cspy.ps1 deleted file mode 100644 index d74be5b..0000000 --- a/settings/eie_assembler.Debug.cspy.ps1 +++ /dev/null @@ -1,31 +0,0 @@ -param([String]$debugfile = ""); - -# This powershell file has been generated by the IAR Embedded Workbench -# C - SPY Debugger, as an aid to preparing a command line for running -# the cspybat command line utility using the appropriate settings. -# -# Note that this file is generated every time a new debug session -# is initialized, so you may want to move or rename the file before -# making changes. -# -# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed -# by the name of the debug file (usually an ELF / DWARF or UBROF file). -# -# Read about available command line parameters in the C - SPY Debugging -# Guide. Hints about additional command line parameters that may be -# useful in specific cases : -# --download_only Downloads a code image without starting a debug -# session afterwards. -# --silent Omits the sign - on message. -# --timeout Limits the maximum allowed execution time. -# - - -if ($debugfile -eq "") -{ -& "C:\Program Files\IAR Systems\EWARM_8_10_1\common\bin\cspybat" -f "D:\EiE\EiE Git\eiebook\settings\eie_assembler.Debug.general.xcl" --backend -f "D:\EiE\EiE Git\eiebook\settings\eie_assembler.Debug.driver.xcl" -} -else -{ -& "C:\Program Files\IAR Systems\EWARM_8_10_1\common\bin\cspybat" -f "D:\EiE\EiE Git\eiebook\settings\eie_assembler.Debug.general.xcl" --debug_file=$debugfile --backend -f "D:\EiE\EiE Git\eiebook\settings\eie_assembler.Debug.driver.xcl" -} diff --git a/settings/eie_assembler.Debug.driver.xcl b/settings/eie_assembler.Debug.driver.xcl deleted file mode 100644 index e1b627b..0000000 --- a/settings/eie_assembler.Debug.driver.xcl +++ /dev/null @@ -1,29 +0,0 @@ -"--endian=little" - -"--cpu=Cortex-M3" - -"--fpu=None" - -"-p" - -"C:\Program Files\IAR Systems\EWARM_8_10_1\arm\CONFIG\debugger\Atmel\ATSAM3U2C.ddf" - -"--semihosting=none" - -"--device=ATSAM3U2C" - -"--drv_communication=USB0" - -"--drv_interface_speed=auto" - -"--jlink_initial_speed=1000" - -"--jlink_reset_strategy=0,0" - -"--drv_catch_exceptions=0x000" - -"--drv_swo_clock_setup=96000000,0,2000000" - - - - diff --git a/settings/eie_assembler.Debug.general.xcl b/settings/eie_assembler.Debug.general.xcl deleted file mode 100644 index 879f0ac..0000000 --- a/settings/eie_assembler.Debug.general.xcl +++ /dev/null @@ -1,15 +0,0 @@ -"C:\Program Files\IAR Systems\EWARM_8_10_1\arm\bin\armproc.dll" - -"C:\Program Files\IAR Systems\EWARM_8_10_1\arm\bin\armjlink2.dll" - -"D:\EiE\EiE Git\eiebook\Debug\Exe\eie_assembler.out" - ---plugin "C:\Program Files\IAR Systems\EWARM_8_10_1\arm\bin\armbat.dll" - ---device_macro "C:\Program Files\IAR Systems\EWARM_8_10_1\arm\config\debugger\Atmel\SAM3U.dmac" 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- - - - diff --git a/settings/eie_assembler_Debug.jlink b/settings/eie_assembler_Debug.jlink deleted file mode 100644 index 39b6d05..0000000 --- a/settings/eie_assembler_Debug.jlink +++ /dev/null @@ -1,39 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -MonModeVTableAddr = 0xFFFFFFFF -MonModeDebug = 0 -MaxNumAPs = 0 -LowPowerHandlingMode = 0 -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="ARM7" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/waf b/waf new file mode 100755 index 0000000..e0eb88c --- /dev/null +++ b/waf @@ -0,0 +1,172 @@ +#!/usr/bin/env python +# encoding: latin-1 +# Thomas Nagy, 2005-2018 +# +""" +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +""" + +import os, sys, inspect + +VERSION="2.0.26" +REVISION="aef3f131453143e04702b9dddb2c6ef2" +GIT="74b1e2396a98464c8cae45dcf75a9b554b5a5c75" +INSTALL='' +C1='#0' +C2='#/' +C3='#+' +cwd = os.getcwd() +join = os.path.join + + +WAF='waf' +def b(x): + return x +if sys.hexversion>0x300000f: + WAF='waf3' + def b(x): + return x.encode() + +def err(m): + print(('\033[91mError: %s\033[0m' % m)) + sys.exit(1) + +def unpack_wafdir(dir, src): + f = open(src,'rb') + c = 'corrupt archive (%d)' + while 1: + line = f.readline() + if not line: err('run waf-light from a folder containing waflib') + if line == b('#==>\n'): + txt = f.readline() + if not txt: err(c % 1) + if f.readline() != b('#<==\n'): err(c % 2) + break + if not txt: err(c % 3) + txt = txt[1:-1].replace(b(C1), b('\n')).replace(b(C2), b('\r')).replace(b(C3), b('\x00')) + + import shutil, tarfile + try: shutil.rmtree(dir) + except OSError: pass + try: + for x in ('Tools', 'extras'): + os.makedirs(join(dir, 'waflib', x)) + except OSError: + err("Cannot unpack waf lib into %s\nMove waf in a writable directory" % dir) + + os.chdir(dir) + tmp = 't.bz2' + t = open(tmp,'wb') + try: t.write(txt) + finally: t.close() + + try: + t = tarfile.open(tmp) + except: + try: + os.system('bunzip2 t.bz2') + t = tarfile.open('t') + tmp = 't' + except: + os.chdir(cwd) + try: shutil.rmtree(dir) + except OSError: pass + err("Waf cannot be unpacked, check that bzip2 support is present") + + try: + for x in t: t.extract(x) + finally: + t.close() + + for x in ('Tools', 'extras'): + os.chmod(join('waflib',x), 493) + + if sys.hexversion<0x300000f: + sys.path = [join(dir, 'waflib')] + sys.path + import fixpy2 + fixpy2.fixdir(dir) + + os.remove(tmp) + os.chdir(cwd) + + try: dir = unicode(dir, 'mbcs') + except: pass + try: + from ctypes import windll + windll.kernel32.SetFileAttributesW(dir, 2) + except: + pass + +def test(dir): + try: + os.stat(join(dir, 'waflib')) + return os.path.abspath(dir) + except OSError: + pass + +def find_lib(): + src = os.path.abspath(inspect.getfile(inspect.getmodule(err))) + base, name = os.path.split(src) + + #devs use $WAFDIR + w=test(os.environ.get('WAFDIR', '')) + if w: return w + + #waf-light + if name.endswith('waf-light'): + w = test(base) + if w: return w + for dir in sys.path: + if test(dir): + return dir + err('waf-light requires waflib -> export WAFDIR=/folder') + + dirname = '%s-%s-%s' % (WAF, VERSION, REVISION) + for i in (INSTALL,'/usr','/usr/local','/opt'): + w = test(i + '/lib/' + dirname) + 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Many details of how waf works are in the waf-book +# https://waf.io/book/ +# It provides a good introduction to most of what's going on here. + +# This script uses a few of the extra tools not built into waf by default. If you are updating the +# checked-in version of waf you will need to tell waf-light to include the following extra tools: +# +# $ ./waf-light configure build --tools=clang_compilation_database,color_gcc,gccdeps +# +# Also consider adding the --nostrip option if working on the wscript, to generate a waf pack +# that includes comments (or set your WAFDIR variable, see the book). The version you checkin +# should be stripped though to keep size down. + +# Onto the actual build script! It's a bit more involved than most waf examples you can find due +# to the nature of cross-compiling for bare-metal targets. + +# First import a few things we will need from python's stdlib and Waf's core library. +import os +import pathlib +import subprocess + +import waflib.Configure as ConfMod +from waflib.Configure import conf +from waflib.Node import Node +from waflib.Task import Task +from waflib.TaskGen import after, feature +import waflib.Utils as Utils + +# This will make waf automatically re-run configuration if the wscript is modified. +# Useful for those not familiar with waf or the config-build-install cycle. +# The biggest boon is that if configure hasn't run at all it will auto-run during a build command. +ConfMod.autoconfig = True + +# TODO: Remaining tasks +# - Move non-command functinos to tool, or make private so that they stop polluting the help text. + +# The following functions implement waf commands. You can define arbitrary commands here (see the +# waf book) but we only use standard ones. If you don't specify one waf uses "build" by default, +# and a few are always run automatically. + + +# The "options" command is also always implicitly run. It's generally used to add command line +# arguments for use in other steps, and many tools will require loading here to add their own +# arguments. See the waf-book for how to define args. Arge defined here will show up when you +# run waf with the "--help" option. +def options(ctx): + # This tool provides some nice coloring to highlight errors and warnings in the terminal. + ctx.load("color_gcc") + + cfg_gr = ctx.get_option_group("Configuration options") + + # Add an option to set the board type being built for. + cfg_gr.add_option( + "--board", + type="string", + help="Set the board type to build for. Valid options are 'ASCII' or 'DOT_MATRIX'.", + default="", + action='store', + dest='board', + ) + + gr = ctx.get_option_group("Build and installation options") + + # Add an option to install the final program to an attached devboard. + gr.add_option( + "-F", + "--flash", + action="store_true", + help="Write compiled firmware to devboard", + ) + + +# The "configure" command is the first command we are overriding which isn't run by default. It's +# usual role is to inspect the host system and find all the programs/libraries that will be needed +# to do builds. In general though it can be used to do any slow checks you don't want to run +# every time. Anything it stores in ctx.env will be available in all future build commands. +def configure(ctx): + # Waf uses DEST_OS for some magic behaviour. If you don't set it manually it assumes you are + # trying to target the host computer that waf is running on, which will do things we don't want. + ctx.env.DEST_OS = "bare-metal" + + gcc_srch = get_gcc_srch_path() + + # The gcc tool assumes that the compiler name is just "gcc". This is not the case when cross + # compiling so we need to manually find the right program. The gcc tool will re-use whatever + # is stored in "CC", which find_program will do for us. + ctx.find_program( + "arm-none-eabi-gcc", + var="CC", + path_list=gcc_srch, + msg="Checking for cross-gcc", + ) + + # GCC can be the assembler as well. + ctx.env.AS = ctx.env.CC + + # Do the same for "AR" (linker for static libs, we don't actually use it but the c tool pulls it + # in automatically). + ctx.find_program( + "arm-none-eabi-ar", var="AR", path_list=gcc_srch, msg="Checking for cross-ar" + ) + + # Need objcopy for converting to a hex file. + ctx.find_program( + "arm-none-eabi-objcopy", + var="OBJCOPY", + path_list=gcc_srch, + msg="Checking for cross-objcopy", + ) + + # Now we can load the gcc compiler tool, this is how waf knows what to do with c files and how + # to link the program. + ctx.load("gcc gas") + + # There's a few additional tools that are nice to have when compiling c code. + # gccdeps uses gcc itself to tell us what a file depends on, so waf can be a lot smarter about + # only recompiling the files that actually need to be recompiled. + ctx.load("gccdeps") + # Ensure the pre-processor runs on assembly files. Without this gccdeps doesn't work right + # (and also some assembly becomes a pain to write). + ctx.env.append_value("ASFLAGS", "-xassembler-with-cpp") + + # This tool doesn't actually use clang, but it generates a .json file with the exact command + # line used for each .c file. This is nice because vscode understands this format and can use + # it to provide accurate intellisense/go-to-definition operations. + ctx.load("clang_compilation_database") + + # Segger doesn't like to be consistent, need to use a different name based on platform. + jlink_name = "JLinkExe" + if Utils.is_win32: + jlink_name = "Jlink" + + # Find the Jlink tools. Not needed for much, just if you want to flash the firmware through waf + # directly. + ctx.find_program(jlink_name, var="JLINK", path_list=get_jlink_srch_path()) + + # Set the board type based on the command line option. + ctx.set_board() + + +@conf +def set_board(ctx): + """ + Set the board type to build for. + """ + + board = ctx.options.board.lower() + + # Save the board type in the environment variables so the --board + # option doesn't need to be specified every time. + if board == "ascii": + ctx.env.BOARD = "ASCII" + elif board == "dot_matrix": + ctx.env.BOARD = "DOT_MATRIX" + else: + ctx.fatal(f"Invalid board type '{board}' specified.") + + +# The "build" command is the default one run by waf if you don't specify anthing. +# +# An important thing to keep in mind about waf's build process is that this function itself doesn't +# actually build-anything. It just creates task-generators, which are fancy collections of variables +# used by tools to generate the actual tasks run later (eg. the c tool uses the "source" variable +# to create a separate compilation task for each .c file you specify). Generally the tools will +# document what variables they expect. +def build(ctx): + # First setup all the special flags we need to pass to the tools. + # TODO: A lot of this isn't specific to our app, and could be factored out into a general tool + # for arm cross-compilation. + + # Compiler + cflags = [ + # Tell GCC to use newlib-nano + "--specs=nano.specs", + # Tell GCC what processor to build for. + "-mcpu=cortex-m3", + # Our processor only supports thumb2, so target it by default. + "-mthumb", + "-mno-thumb-interwork", + "-masm-syntax-unified", + # This processor does not do anything special on arithmatic overflow. + # Make sure GCC knows to avoid optimizations that assume that. + "-fno-strict-overflow", + # We are using C99 as the target C standard. + "-std=c99", + # Tell GCC to generate all debug info + "-ggdb", + # Set optimizations for best debugging. + "-Og", + # Allow "asm" keyword, old CMSIS headers use it. + "-fasm", + # Warning config. Turn on most, but disable a few that are commonly triggered + # by the used code style. + "-Wall", + "-Wno-unused-function", + "-Wno-pointer-sign", + ] + + # Assembler: + asflags = [ + # Most of these are just duplicating cflags + "--specs=nano.specs", + "-mcpu=cortex-m3", + "-mthumb", + "-masm-syntax-unified", + ] + + # Linker + linkflags = [ + # Tell GCC to use newlib-nano + "--specs=nano.specs", + # We are using our own custom startup code. + "-nostartfiles", + # Target specifics, see cflags. + "-mcpu=cortex-m3", + "-mno-thumb-interwork", + ] + + # Now collect all the things we want to build. + + # To avoid manual lists of all the files, use some globbing to pick up everything of interest + # As long as you organize things that should turn on/off as a unit into folders this will + # work. + work_folders = [ + "firmware_common/cmsis", + "firmware_common/bsp", + "firmware_common/drivers", + "firmware_common/application", + ] + + # Files specific to the ascii and dot matrix boards. + ascii_folders = [ + "firmware_ascii/bsp", + "firmware_ascii/drivers", + ] + dot_matrix_folders = [ + "firmware_dotmatrix/bsp/", + "firmware_dotmatrix/drivers", + "firmware_dotmatrix/libraries/captouch", + "firmware_dotmatrix/libraries/captouch/include", + ] + + # Add blade files directly to the source to avoid compiling the template files + source = [ + "firmware_common/application/blade/blade_api.c", + "firmware_common/application/blade/blade_imu_lsm6dsl.c" + ] + includes = ["firmware_common/application/blade"] + defines = [] + target = "" + + if ctx.env.BOARD == "ASCII": + work_folders += ascii_folders + defines.append("EIE_ASCII") + target = "firmware-ascii" + elif ctx.env.BOARD == "DOT_MATRIX": + work_folders += dot_matrix_folders + defines += ["EIE_DOTMATRIX", "EIE_NO_CAPTOUCH"] + target = "firmware-dot-matrix" + else: + ctx.fatal("No board type specified.") + + for folder in work_folders: + source += ctx.srcnode.ant_glob(f"{folder}/*.s") # assembly files + source += ctx.srcnode.ant_glob(f"{folder}/*.c") # C source + includes.append(folder) # Make sure the matching headers can be found. + + # The program() function creates a task gen with all the features needed to compile+link based + # on what source files you specify (stepping through with a python debugger can be nice to + # undstand exactly how it does that :) ) + # + # If you have a need to you can actually call progam() multiple times to build multiple + # executable files. + ctx.program( + target=target, + features="mapfile ihex", + source=source, + includes=includes, + cflags=cflags, + asflags=asflags, + linkflags=linkflags, + defines=defines, + linker_script="firmware_common/bsp/sam3u2.ld", + ) + + if ctx.options.flash: + + def do_flash(ctx): + # Input we would type interactively. + input = "\n".join( + [ + "erase", + f"loadfile build/{target}.hex", + "reset", + "go", + "quit", + ] + ).encode() + + # Actually do the command. + ctx.exec_command( + [ + ctx.env.JLINK[0], + "-exitonerror", + "1", + "-autoconnect", + "1", + "-device", + "ATSAM3U2C", + "-if", + "SWD", + "-speed", + "4000", + ], + input=input, + timeout=10, + ) + + # Use a post-build function here for simplicity. Could also be done as a task, but getting + # the command line right would be a pain. + ctx.add_post_fun(do_flash) + + +# The rest of these functions are supporting items used during the configure/build commands. + + +def get_jlink_srch_path(): + """ + Get search path to use for JLink programs/DLLs + """ + + paths = os.environ.get("PATH").split(os.pathsep) + + if Utils.is_win32: + # For now just hard-code the default install paths. Don't include default search path due to + # conflicts with java's linker. User can still override with an explicit JLINK=... on the + # command line. + return [ + "C:\\Program Files\\SEGGER\\JLink", + "C:\\Program Files (x86)\\SEGGER\\JLink", + ] + paths + + elif Utils.unversioned_sys_platform() == "darwin": + return ["/Application/SEGGER/JLink"] + paths + + elif Utils.unversioned_sys_platform() == "linux": + return ["/opt/SEGGER/JLink"] + paths + + else: + return paths # Trust in the PATH, Luke. + + +def check_gcc_ver(pth: pathlib.Path, ext=""): + """ + Attempt to extract the version from a specific GCC. + If successfull returned as a tuple (maj, min, rel). + Otherwise returns None + """ + + name = "arm-none-eabi-gcc" + if ext: + name += f".{ext}" + + exe_pth = pth / name + if not exe_pth.exists(): + return None + + try: + ver = subprocess.run( + [exe_pth, "-dumpversion"], stdout=subprocess.PIPE + ).stdout.decode() + except: + return None + + return tuple(int(v) for v in ver.split(".")) + + +def get_gcc_srch_path_win32(): + """ + Look for typical GCC installations. Checked on 11.3 rel1 and 12.3 rel1. + If your gcc is older this may need to be modified (or just make sure it's on the path when you + run configure). + """ + + # Extend with anything we find in the registry or at the default install location. + + # Import a few things JIT. Some of these will only work on windows. + from collections import defaultdict + import winreg + + REGISTRY_PATHS = [(winreg.HKEY_LOCAL_MACHINE, "SOFTWARE\\WOW6432Node\\ARM")] + INSTALL_PATHS = ["C:\\Program Files (x86)\\Arm GNU Toolchain arm-none-eabi"] + + gcc_vers = defaultdict(set) # Map from version numbers to discovered paths. + + def check(pth): + pth = pathlib.Path(pth) / "bin" + ver = check_gcc_ver(pth, ext="exe") + if ver: + gcc_vers[ver].add(str(pth)) + + for root, subk in REGISTRY_PATHS: + try: + key = winreg.OpenKey(root, subk) + (num_subks, _, _) = winreg.QueryInfoKey(key) + for i in range(num_subks): + try: + subk = winreg.EnumKey(key, i) + subk = winreg.OpenKey(key, subk) + (pth, _) = winreg.QueryValueEx(subk, "InstallFolder") + check(pth) + subk.Close() + except: + continue + key.Close() + except: + continue + + for install_pth in INSTALL_PATHS: + install_pth = pathlib.Path(install_pth) + for pth in install_pth.iterdir(): + check(pth) + + if not gcc_vers: + # No installs found. + return None + + vers = sorted(gcc_vers.keys()) + vers.reverse() + + # If different paths to the same version where found, using sorting to at least be + # consistent between runs. + pths = os.environ.get("PATH").split(os.pathsep) + for v in vers: + pths += sorted(gcc_vers[v]) + return pths + + +def get_gcc_srch_path_darwin(): + from collections import defaultdict + + gcc_vers = defaultdict(set) # Map from version numbers to discovered paths. + + # Known default install paths on Mac + INSTALL_PATHS = ["/Applications/ArmGNUToolchain/"] + + for install_pth in INSTALL_PATHS: + install_pth = pathlib.Path(install_pth) + for pth in install_pth.iterdir(): + # Not sure why but the mac paths have an extra path segment here + pth = pth / "arm-none-eabi" / "bin" + ver = check_gcc_ver(pth) + if ver: + gcc_vers[ver].add(str(pth)) + + if not gcc_vers: + # No installs found. + return None + + vers = sorted(gcc_vers.keys()) + vers.reverse() + + # If different paths to the same version where found, using sorting to at least be + # consistent between runs. + pths = os.environ.get("PATH").split(os.pathsep) + for v in vers: + pths += sorted(gcc_vers[v]) + return pths + + +def get_gcc_srch_path(): + if Utils.is_win32: + return get_gcc_srch_path_win32() + elif Utils.unversioned_sys_platform() == "darwin": + return get_gcc_srch_path_darwin() + else: + return None # Tools should just be in the right spot. + + +# This is an example of how to hook into waf's task-generation process. +# by using @feature() here the function will be called on any task-generators +# that specified matching values in their "feature" variable. The function can +# do anything it wants, but typically it will either define a task to run during +# the build process, or it will modify the values of variables for other hooks +# to use (eg. you could add things to source to compile additional files.) +@feature("mapfile") # Run on anything with the "mapfile" feature. +@after( + "apply_link" +) # Run after "apply_link". Needed because that's what creates the link_task +# that we modify +def apply_mapfile(tg): + """ + Instruct the GCC linker to produce a .map file detailing the result of the link process. + """ + # Get the file name to use for the mapfile. + outfile = tg.link_task.outputs[0].change_ext(".map") + # Extend the link task's flags with one telling gcc to generate the map file. + tg.env.append_value("LINKFLAGS", [f"-Wl,-Map={outfile}"]) + tg.link_task.set_outputs([outfile]) + + +@feature("c", "cxx", "d", "fc", "asm") +@after("apply_link") +def apply_custom_linker_script(tg): + """ + process the "linker_script" attribute to add a custom linker script. + Handles the command line, but also sets up waf to recognize it as a dependency. + """ + script = getattr(tg, "linker_script", None) + if not script: + return + if type(script) != Node: + script = tg.bld.srcnode.find_resource(script) + + tg.link_task.dep_nodes.append(script) + tg.env.append_value("LINKFLAGS", [f"-T{script}"]) + + +class ihex(Task): + """ + Waf task for converting executables to .hex files. + Used by the ihex feature. + """ + + color = "BLUE" + ext_out = [".hex"] + run_str = "${OBJCOPY} -O ihex ${SRC} ${TGT}" + + def keyword(self): + return "Creating" + + def __str__(self): + def nice_path(node): + return node.path_from(node.ctx.launch_node()) + + return f"{nice_path(self.outputs[0])}" + + +@feature("ihex") +@after("apply_link") +def apply_ihex(tg): + inf = tg.link_task.outputs[0] + outf = inf.change_ext(".hex") + tg.create_task("ihex", inf, outf)