diff --git a/verify/uvm-python/.gitignore b/verify/uvm-python/.gitignore
index fa489b3..51d311f 100644
--- a/verify/uvm-python/.gitignore
+++ b/verify/uvm-python/.gitignore
@@ -9,4 +9,5 @@
 /coverageReports/
 *.xml
 *.gtkw
-/EF_UVM/
\ No newline at end of file
+/EF_UVM/
+IP_Utilities/
\ No newline at end of file
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index a28dd4d..98c37f2 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -1,7 +1,7 @@
 PLUSARGS += "+UVM_VERBOSITY=UVM_HIGH"
 TOPLEVEL := top
 MODULE   ?= top_module
-VERILOG_SOURCES ?=  $(PWD)/top.v $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.v  $(PWD)/../../hdl/rtl/EF_UART.v
+VERILOG_SOURCES ?=  $(PWD)/top.v  $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/bus_wrappers/EF_UART_APB.pp.v  $(PWD)/../../hdl/rtl/EF_UART.v
 RTL_MACROS ?= ""
 # RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
 YAML_FILE = $(PWD)/../../EF_UART.yaml
@@ -9,7 +9,7 @@ MAKEFLAGS += --no-print-directory
 
 # List of tests
 TESTS := TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest
-# TESTS := WriteReadRegsTest 
+TESTS := WriteReadRegsTest 
 
 # Variable for tag - set this as required
 SIM_TAG ?= default_tag
@@ -18,9 +18,13 @@ SIM_TAG ?= default_tag
 SIM_PATH := $(PWD)/sim/$(SIM_TAG)
 
 # Check and clone EF_UVM repository at the beginning of the Makefile execution
-REPO_DIR := EF_UVM
 
-clone_ef_uvm := $(shell if [ ! -d "$(REPO_DIR)" ]; then \
+clone_ip_util := $(shell if [ ! -d "IP_Utilities" ]; then \
+	echo "Cloning the IP_Utilities repository..."; \
+	git clone https://github.com/shalan/IP_Utilities.git; \
+fi;)
+
+clone_ef_uvm := $(shell if [ ! -d "EF_UVM" ]; then \
 	echo "Cloning the EF_UVM repository..."; \
 	git clone https://github.com/M0stafaRady/EF_UVM.git; \
 fi;)
diff --git a/verify/uvm-python/apb_wrapper.vh b/verify/uvm-python/apb_wrapper.vh
deleted file mode 100644
index c29e4ae..0000000
--- a/verify/uvm-python/apb_wrapper.vh
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
-	Copyright 2020 AUCOHL
-
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-
-`define		APB_BLOCK(name, init)		always @(posedge PCLK or negedge PRESETn) if(~PRESETn) name <= init;
-
-`define     APB_CTRL_SIGNALS            wire		apb_valid   = PSEL & PENABLE;\
-                                        wire		apb_we	    = PWRITE & apb_valid;\
-                                        wire		apb_re	    = ~PWRITE & apb_valid;
-                                        
-`define		APB_REG(name, init, size)	`APB_BLOCK(name, init)\ 
-                                        else if(apb_we & (PADDR[`APB_AW-1:0]==``name``_OFFSET))\ 
-                                            name <= PWDATA[``size``-1:0];
-
-`define		APB_IC_REG(size)			`APB_BLOCK(IC_REG, ``size``'b0)\
-                                        else if(apb_we & (PADDR[`APB_AW-1:0]==IC_REG_OFFSET))\ 
-                                            IC_REG <= PWDATA[``size``-1:0];\ 
-                                        else \
-                                            IC_REG <= ``size``'d0;    
-
-`define     APB_SLAVE_PORTS             input wire          PCLK,\
-                                        input wire          PRESETn,\
-                                        input wire          PWRITE,\
-                                        input wire [31:0]   PWDATA,\
-                                        input wire [31:0]   PADDR,\
-                                        input wire          PENABLE,\
-                                        input wire          PSEL,\
-                                        output wire         PREADY,\
-                                        output wire [31:0]  PRDATA,\
-                                        output wire         IRQ\
-                                        
-`define     APB_MIS_REG(size)           wire[size-1:0]      MIS_REG	= RIS_REG & IM_REG;
\ No newline at end of file
diff --git a/verify/uvm-python/aucohl_lib.v b/verify/uvm-python/aucohl_lib.v
deleted file mode 100644
index 0e36fc4..0000000
--- a/verify/uvm-python/aucohl_lib.v
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
-	Copyright 2020 AUCOHL
-
-    Author: Mohamed Shalan (mshalan@aucegypt.edu)
-	
-	Licensed under the Apache License, Version 2.0 (the "License"); 
-	you may not use this file except in compliance with the License. 
-	You may obtain a copy of the License at:
-
-	http://www.apache.org/licenses/LICENSE-2.0
-
-	Unless required by applicable law or agreed to in writing, software 
-	distributed under the License is distributed on an "AS IS" BASIS, 
-	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
-	See the License for the specific language governing permissions and 
-	limitations under the License.
-*/
-
-`timescale			    1ns/1ps
-`default_nettype		none
-
-`define     PED(clk, sig, pulse)    reg last_``sig``; always @(posedge clk) last_``sig`` <= sig; assign pulse = sig & ~last_``sig``;
-`define     NED(clk, sig, pulse)    reg last_``sig``; always @(posedge clk) last_``sig`` <= sig; assign pulse = ~sig & last_``sig``;
-
-/*
-    Brute-force Synchronizer
-*/
-module aucohl_sync #(parameter NUM_STAGES = 2) (
-    input clk,
-    input in,
-    output out
-);
-
-    reg [NUM_STAGES-1:0] sync;
-
-    always @(posedge clk)
-        sync <= {sync[NUM_STAGES-2:0], in};
-
-    assign out = sync[NUM_STAGES-1];
-
-endmodule
-
-/*
-    A positive edge detector
-*/
-module aucohl_ped (
-    input clk,
-    input in,
-    output out
-);
-    `PED(clk, in, out)
-endmodule
-
-/*
-    A negative edge detector
-*/
-module aucohl_ned (
-    input clk,
-    input in,
-    output out
-);
-    `NED(clk, in, out)
-endmodule
-
-/*
-    A tick generator
-*/
-module aucohl_ticker #(parameter W=8) (
-    input   wire            clk, 
-    input   wire            rst_n,
-    input   wire            en,
-    input   wire [W-1:0]    clk_div,
-    output  wire            tick
-);
-
-    reg [W-1:0] counter;
-    wire        counter_is_zero = (counter == 'b0);
-    wire        tick_w;
-    reg         tick_reg;
-
-    always @(posedge clk, negedge rst_n)
-        if(~rst_n)
-            counter <=  'b0;
-        else if(en) 
-            if(counter_is_zero)
-                counter <=  clk_div;
-            else
-                counter <=  counter - 'b1; 
-
-    assign tick_w = (clk_div == 'b1)  ?   1'b1 : counter_is_zero;
-
-    always @(posedge clk or negedge rst_n)
-        if(!rst_n)
-            tick_reg <= 1'b0;
-        else if(en)
-            tick_reg <= tick_w;
-        else
-            tick_reg <= 0;
-
-    assign tick = tick_reg;
-
-endmodule
-
-/*
-    A glitch filter
-*/
-module aucohl_glitch_filter #(parameter N = 8, CLKDIV = 1) (
-    input   wire    clk,
-    input   wire    rst_n,
-    input   wire    in,
-    output  reg     out
-);
-
-    reg [N-1:0] shifter;
-    wire        tick;
-
-    aucohl_ticker ticker (
-        .clk(clk),
-        .rst_n(rst_n),
-        .en(1'b1),
-        .clk_div(CLKDIV),
-        .tick(tick)
-    );
-
-    always @(posedge clk, negedge rst_n)
-        if(!rst_n)
-            shifter = 'b0;
-        else if(tick)
-            shifter <= {shifter[N-2:0], in};
-
-    wire all_ones   = & shifter;
-    wire all_zeros  = ~| shifter;
-
-    always @(posedge clk, negedge rst_n)
-        if(!rst_n)
-            out <= 1'b0;
-        else
-            if(all_ones) 
-                out <= 1'b1;
-            else if(all_zeros) 
-                out <= 1'b0;
-endmodule
-
-/*
-    A FIFO
-*/
-module aucohl_fifo #(parameter DW=8, AW=4)(
-    input     wire            clk,
-    input     wire            rst_n,
-    input     wire            rd,
-    input     wire            wr,
-    input     wire [DW-1:0]   wdata,
-    output    wire            empty,
-    output    wire            full,
-    output    wire [DW-1:0]   rdata,
-    output    wire [AW-1:0]   level    
-);
-
-    localparam  DEPTH = 2**AW;
-
-    //Internal Signal declarations
-    reg [DW-1:0]  array_reg [DEPTH-1:0];
-    reg [AW-1:0]  w_ptr_reg;
-    reg [AW-1:0]  w_ptr_next;
-    reg [AW-1:0]  w_ptr_succ;
-    reg [AW-1:0]  r_ptr_reg;
-    reg [AW-1:0]  r_ptr_next;
-    reg [AW-1:0]  r_ptr_succ;
-    // array reg 
-    wire[DW-1:0] array_reg_0 = array_reg[0];
-    wire[DW-1:0] array_reg_1 = array_reg[1];
-    wire[DW-1:0] array_reg_2 = array_reg[2];
-    wire[DW-1:0] array_reg_3 = array_reg[3];
-    wire[DW-1:0] array_reg_4 = array_reg[4];
-    wire[DW-1:0] array_reg_5 = array_reg[5];
-    wire[DW-1:0] array_reg_6 = array_reg[6];
-    wire[DW-1:0] array_reg_7 = array_reg[7];
-    wire[DW-1:0] array_reg_8 = array_reg[8];
-    wire[DW-1:0] array_reg_9 = array_reg[9];
-    wire[DW-1:0] array_reg_10 = array_reg[10];
-    wire[DW-1:0] array_reg_11 = array_reg[11];
-    wire[DW-1:0] array_reg_12 = array_reg[12];
-    wire[DW-1:0] array_reg_13 = array_reg[13];
-    wire[DW-1:0] array_reg_14 = array_reg[14];
-    wire[DW-1:0] array_reg_15 = array_reg[15];
-    
-    // Level
-    reg [AW-1:0] level_reg;
-    reg [AW-1:0] level_next;      
-    reg full_reg;
-    reg empty_reg;
-    reg full_next;
-    reg empty_next;
-
-    wire w_en;
-
-    always @ (posedge clk)
-        if(w_en) begin
-            array_reg[w_ptr_reg] <= wdata;
-        end
-
-    assign rdata = array_reg[r_ptr_reg];   
-    assign w_en = wr & ~full_reg;           
-
-    //State Machine
-    always @ (posedge clk, negedge rst_n) begin 
-    if(!rst_n)
-        begin
-            w_ptr_reg <= 'b0;
-            r_ptr_reg <= 'b0;
-            full_reg  <= 1'b0;
-            empty_reg <= 1'b1;
-            level_reg <= 4'd0;
-        end
-    else
-        begin
-            w_ptr_reg <= w_ptr_next;
-            r_ptr_reg <= r_ptr_next;
-            full_reg  <= full_next;
-            empty_reg <= empty_next;
-            level_reg <= level_next;
-        end
-    end
-
-    //Next State Logic
-    always @* begin
-        w_ptr_succ = w_ptr_reg + 1;
-        r_ptr_succ = r_ptr_reg + 1;
-
-        w_ptr_next = w_ptr_reg;
-        r_ptr_next = r_ptr_reg;
-        full_next = full_reg;
-        empty_next = empty_reg;
-        level_next = level_reg;
-
-        case({w_en,rd})
-            //2'b00: nop
-            2'b01: 
-                if(~empty_reg) begin
-                    r_ptr_next = r_ptr_succ;
-                    full_next = 1'b0;
-                    level_next = level_reg - 1;
-                    if (r_ptr_succ == w_ptr_reg)
-                        empty_next = 1'b1;
-                end
-            
-            2'b10: 
-                if(~full_reg) begin
-                    w_ptr_next = w_ptr_succ;
-                    empty_next = 1'b0;
-                    level_next = level_reg + 1;
-                    if (w_ptr_succ == r_ptr_reg)
-                        full_next = 1'b1;
-                end
-            
-            2'b11: begin
-                w_ptr_next = w_ptr_succ;
-                r_ptr_next = r_ptr_succ;
-            end
-        endcase
-    end
-
-    //Set Full and Empty
-    assign full = full_reg;
-    assign empty = empty_reg;
-    assign level = level_reg;
-  
-endmodule