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EF_SPI

SPI master controller with receive and transmit FIFOs.

The wrapped IP

APB, AHBL, and Wishbone wrappers, generated by the BusWrap bus_wrap.py utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.

Wrapped IP System Integration

Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:

EF_SPI_APB INST (
	`TB_APB_SLAVE_CONN,
	.miso(miso),
	.mosi(mosi),
	.csb(csb),
	.sclk(sclk)
);

NOTE: `TB_APB_SLAVE_CONN is a convenient macro provided by BusWrap.

Implementation example

The following table is the result for implementing the EF_SPI IP with different wrappers using Sky130 PDK and OpenLane2 flow.

Module Number of cells Max. freq
EF_SPI TBD TBD
EF_SPI_APB TBD TBD
EF_SPI_AHBL TBD TBD
EF_SPI_WB TBD TBD

The Programmer's Interface

Registers

Name Offset Reset Value Access Mode Description
RXDATA 0000 0x00000000 r RX Data register; the interface to the Receive FIFO.
TXDATA 0004 0x00000000 w TX Data register; ; the interface to the Receive FIFO.
CFG 0008 0x00000000 w Configuration Register.
CTRL 000c 0x00000000 w Control Register.
PR 0010 0x00000002 w SPI clock Prescaler; should have a value >= 2. SPI Clock Frequency = System Clock / PR.
STATUS 0014 0x00000000 r Status resgister
RX_FIFO_LEVEL fe00 0x00000000 r RX_FIFO Level Register
RX_FIFO_THRESHOLD fe04 0x00000000 w RX_FIFO Level Threshold Register
RX_FIFO_FLUSH fe08 0x00000000 w RX_FIFO Flush Register
TX_FIFO_LEVEL fe10 0x00000000 r TX_FIFO Level Register
TX_FIFO_THRESHOLD fe14 0x00000000 w TX_FIFO Level Threshold Register
TX_FIFO_FLUSH fe18 0x00000000 w TX_FIFO Flush Register
IM ff00 0x00000000 w Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details
RIS ff08 0x00000000 w Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details
MIS ff04 0x00000000 w Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details
IC ff0c 0x00000000 w Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details

RXDATA Register [Offset: 0x0, mode: r]

RX Data register; the interface to the Receive FIFO.

TXDATA Register [Offset: 0x4, mode: w]

TX Data register; ; the interface to the Receive FIFO.

CFG Register [Offset: 0x8, mode: w]

Configuration Register.

bit field name width description
0 cpol 1 SPI Clock Polarity.
1 cpha 1 SPI Clock Phase.

CTRL Register [Offset: 0xc, mode: w]

Control Register.

bit field name width description
0 SS 1 Slave Select (Active High).
1 enable 1 enable spi master pulse generation
2 rx_en 1 enable storing bytes recieved from slave

PR Register [Offset: 0x10, mode: w]

SPI clock Prescaler; should have a value >= 2. SPI Clock Frequency = System Clock / PR.

STATUS Register [Offset: 0x14, mode: r]

Status resgister

bit field name width description
0 TX_E 1 Transmit FIFO is Empty.
1 TX_F 1 Transmit FIFO is Full.
2 RX_F 1 Receive FIFO is Empty.
3 RX_E 1 Receive FIFO is Full.
4 TX_B 1 Transmit FIFO level is Below Threshold.
5 RX_A 1 Receive FIFO level is Above Threshold.

RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]

RX_FIFO Level Register

bit field name width description
0 level 4 FIFO data level

RX_FIFO_THRESHOLD Register [Offset: 0xfe04, mode: w]

RX_FIFO Level Threshold Register

bit field name width description
0 threshold 4 FIFO level threshold value

RX_FIFO_FLUSH Register [Offset: 0xfe08, mode: w]

RX_FIFO Flush Register

bit field name width description
0 flush 1 FIFO flush

TX_FIFO_LEVEL Register [Offset: 0xfe10, mode: r]

TX_FIFO Level Register

bit field name width description
0 level 4 FIFO data level

TX_FIFO_THRESHOLD Register [Offset: 0xfe14, mode: w]

TX_FIFO Level Threshold Register

bit field name width description
0 threshold 4 FIFO level threshold value

TX_FIFO_FLUSH Register [Offset: 0xfe18, mode: w]

TX_FIFO Flush Register

bit field name width description
0 flush 1 FIFO flush

Interrupt Flags

The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the BusWrap bus_wrap.py utility.

Each register has a group of bits for the interrupt sources/flags.

  • IM: is used to enable/disable interrupt sources.

  • RIS: has the current interrupt status (interrupt flags) whether they are enabled or disabled.

  • MIS: is the result of masking (ANDing) RIS by IM.

  • IC: is used to clear an interrupt flag.

The following are the bit definitions for the interrupt registers:

Bit Flag Width Description
0 TXE 1 Transmit FIFO is Empty.
1 TXF 1 Transmit FIFO is Full.
2 RXE 1 Receive FIFO is Empty.
3 RXF 1 Receive FIFO is Full.
4 TXB 1 Transmit FIFO level is Below Threshold.
5 RXA 1 Receive FIFO level is Above Threshold.

The Interface

Module Parameters

Parameter Description Default Value
CDW The width of the clock divider used to generate the SPI clock. 8
FAW Log2 of the FIFO depth. 4

Ports

Port Direction Width Description
miso input 1 SPI Master In Slave Out.
mosi output 1 SPI Master Out Slave In.
csb output 1 Chip/Slave Select (Active Low)
sclk output 1 None
CPOL input 1 SPI Clock Polarity.
CPHA input 1 SPI CLock Phase.
clk_divider input CDW The SPI clock divider; SPI clock frequency = System Clock Frequency / clk_divider.
wr input 1 Write to the TX FIFO.
rd input 1 Read from the RX FIFO.
datai input 8 Data to place into the TX FIFO.
datao output 8 Data from the RX FIFO.
rx_en input 1 Enable the RX FIFO.
rx_flush input 1 Flush the RX FIFO.
rx_threshold input FAW RX FIFO level threshold.
rx_empty output 1 RX FIFO is empty.
rx_full output 1 RX FIFO is full.
rx_level_above output 1 RX FIFO level is above the threshold.
rx_level output FAW RX FIFO data level.
tx_flush input 1 Flush the TX FIFO.
tx_threshold input FAW TX FIFO level threshold.
tx_empty output 1 TX FIFO is empty.
tx_full output 1 TX FIFO is full.
tx_level_below output 1 TX FIFO level is below trhe threshold.
tx_level output FAW TX FIFO data level.
ss input 1 None
enable input 1 enable for spi master pulse generation

F/W Usage Guidelines:

  1. Set the prescaler by writing to the PR register where SPI Clock Frequency = System Clock / PR. Note: should have a value >= 2.
  2. Configure clock polarity and clock phase bu setting cpol and cpha fields in the CFG register.
  3. Set the SSn field in the CTRL register

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

  • To clone repo: git clone https://github.com/efabless/EF_SPI
  • To download via IPM , follow installation guides here then run ipm install EF_SPI

Run cocotb UVM Testbench:

In IP directory run:

cd verify/uvm-python/
To run testbench for design with APB

To run all tests:

make run_all_tests BUS_TYPE=APB

To run a certain test:

make run_<test_name> BUS_TYPE=APB

To run all tests with a tag:

make run_all_tests TAG=<new_tag> BUS_TYPE=APB
To run testbench for design with APB

To run all tests:

make run_all_tests BUS_TYPE=AHB

To run a certain test:

make run_<test_name> BUS_TYPE=AHB

To run all tests with a tag:

make run_all_tests TAG=<new_tag> BUS_TYPE=AHB