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It's a bit of a pain, but I would use aliasing if it's all just a 1:1. I am kind of surprised it's taking that long though honestly. |
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Thanks for the reply. So if we have a UDT tag called pylogix comprised of [300]real and [300]bool with a structure, pylogix.real[0]...[299] and we are copying tags into this UDT using a ST routine, pylogix.real[0] := pressureTag_Real That you are advocating the following...? pressureTag_Real != base tag with controller scope Such that the ST routine would then become redundant as the data already resides in the UDT ready for pylogix to read. Is this a recognised and widely practiced approach? It is quite new to me. Could it lead to any confusion or misinterpretation for other programmers? On closer inspection there are also a number of INT and DINT tags that are being converted into the REAL array; likely increasing the scan time further. Another possible performance improvement would be to expand the UDT structure to include a DINT array. |
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Using pylogix to read a UDT from a compactlogix 5370 controller there is a concern that the Logix code is not optimal.
The pylogix part has been optimised by creating the UDT of several hundred tags and thus making only one tag read request every 100ms. This is all good.
However to populate the UDT we are using a ST routine to copy the individual tags (300 reals and 300bools). The routine has a scan time of almost 1ms and we are looking for a better way.
Any thoughts on a more performant method than 600 line by line copy and pastes?
We have access to Ladder, ST, etc..
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