From 210b43f15251f7100dc5130aa3bf828e322e8e0b Mon Sep 17 00:00:00 2001 From: sdcioc Date: Sun, 10 Nov 2024 18:50:47 +0200 Subject: [PATCH] [Course] Add slides for all courses with exam questions (#35) * Fixed the typos. * feat: course no.2 information representation * feat: course no.3 memory * feat: exam questions ofr course no.3 * Modified course 2 - first modification * Modified course 2 - reset text from number.tex * wip: course no. 4 * feat: course no.4 add riple carry and carry lookahead * feat: course no.4 * fix: some grammar for course no. 4 * fix: grammar for course no. 3 * fix: improve course no. 3 * fix: improve course no. 4 * fix: cousre no.4 small changes. * fix: delete education hub linter * feat: course no. 5 * fix: exam questions for course no.5 * feat: course no. 6 * feat: course no. 7 * wip: course no. 8 * feat: course no. 8 * feat: course no. 9 --- .devcontainer/devcontainer.json | 39 +- .../latex.Dockerfile | 8 +- .vscode/settings.json | 44 +++ slides/.devcontainer/devcontainer.json | 18 - slides/.vscode/settings.json | 14 - slides/courses/5/architecture.tex | 8 + slides/courses/5/components.tex | 166 +++++++++ slides/courses/5/format.tex | 98 +++++ slides/courses/5/isa.tex | 104 ++++++ slides/courses/5/main.tex | 117 ++++++ slides/courses/5/media/architecture.drawio | 338 ++++++++++++++++++ slides/courses/5/media/architecture.png | Bin 0 -> 101715 bytes slides/courses/5/memory.tex | 174 +++++++++ slides/courses/6/assembly.tex | 151 ++++++++ slides/courses/6/compilation.tex | 203 +++++++++++ slides/courses/6/main.tex | 112 ++++++ slides/courses/7/implementation.tex | 118 ++++++ slides/courses/7/intro.tex | 43 +++ slides/courses/7/main.tex | 118 ++++++ slides/courses/7/media/UART.png | Bin 0 -> 55595 bytes slides/courses/7/media/dma.drawio | 329 +++++++++++++++++ slides/courses/7/media/dma.png | Bin 0 -> 54726 bytes slides/courses/7/media/io.drawio | 190 ++++++++++ slides/courses/7/media/io.png | Bin 0 -> 39413 bytes slides/courses/7/media/uart_timing.png | Bin 0 -> 44048 bytes slides/courses/7/types.tex | 231 ++++++++++++ slides/courses/7/uart.tex | 46 +++ slides/courses/8/implementation.tex | 210 +++++++++++ slides/courses/8/irqs.tex | 131 +++++++ slides/courses/8/main.tex | 113 ++++++ slides/courses/8/media/isarchitecture.drawio | 265 ++++++++++++++ slides/courses/8/media/isarchitecture.png | Bin 0 -> 34374 bytes slides/courses/9/basic.tex | 204 +++++++++++ slides/courses/9/implementation.tex | 115 ++++++ slides/courses/9/main.tex | 116 ++++++ .../courses/9/media/mpcuarchitecture.drawio | 85 +++++ slides/courses/9/media/mpcuarchitecture.png | Bin 0 -> 15010 bytes slides/courses/9/minimal.tex | 332 +++++++++++++++++ 38 files changed, 4196 insertions(+), 44 deletions(-) rename slides/.devcontainer/Dockerfile => .devcontainer/latex.Dockerfile (83%) create mode 100644 .vscode/settings.json delete mode 100644 slides/.devcontainer/devcontainer.json delete mode 100644 slides/.vscode/settings.json create mode 100644 slides/courses/5/architecture.tex create mode 100644 slides/courses/5/components.tex create mode 100644 slides/courses/5/format.tex create mode 100644 slides/courses/5/isa.tex create mode 100644 slides/courses/5/main.tex create mode 100644 slides/courses/5/media/architecture.drawio create mode 100644 slides/courses/5/media/architecture.png create mode 100644 slides/courses/5/memory.tex create mode 100644 slides/courses/6/assembly.tex create mode 100644 slides/courses/6/compilation.tex create mode 100644 slides/courses/6/main.tex create mode 100644 slides/courses/7/implementation.tex create mode 100644 slides/courses/7/intro.tex create mode 100644 slides/courses/7/main.tex create mode 100644 slides/courses/7/media/UART.png create mode 100644 slides/courses/7/media/dma.drawio create mode 100644 slides/courses/7/media/dma.png create mode 100644 slides/courses/7/media/io.drawio create mode 100644 slides/courses/7/media/io.png create mode 100644 slides/courses/7/media/uart_timing.png create mode 100644 slides/courses/7/types.tex create mode 100644 slides/courses/7/uart.tex create mode 100644 slides/courses/8/implementation.tex create mode 100644 slides/courses/8/irqs.tex create mode 100644 slides/courses/8/main.tex create mode 100644 slides/courses/8/media/isarchitecture.drawio create mode 100644 slides/courses/8/media/isarchitecture.png create mode 100644 slides/courses/9/basic.tex create mode 100644 slides/courses/9/implementation.tex create mode 100644 slides/courses/9/main.tex create mode 100644 slides/courses/9/media/mpcuarchitecture.drawio create mode 100644 slides/courses/9/media/mpcuarchitecture.png create mode 100644 slides/courses/9/minimal.tex diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json index b696fef..5c00081 100644 --- a/.devcontainer/devcontainer.json +++ b/.devcontainer/devcontainer.json @@ -1,16 +1,37 @@ { - "name": "Vivado Slim Dev", - "image": "gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0", - "runArgs": [ - "--rm", - "--privileged" - ], - "mounts": ["type=bind,source=/dev,target=/dev"], + // Lab development container configuration Vivado Slim Dev + // "name": "Vivado Slim Dev", + // "image": "gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0", + // Open source toolchain container for VPL + // "name": "Icarus Verilog", + // "build": { + // "dockerfile": "open.Dockerfile", + // }, + // Latex container for course materials + "name": "Latex", + "build": { + "dockerfile": "latex.Dockerfile", + }, "customizations": { "vscode": { "extensions": [ - "mshr-h.veriloghdl" + "GitHub.vscode-pull-request-github", + "james-yu.latex-workshop", + "GitHub.copilot", + "Bito.Bito" ] } - } + }, + "runArgs": [ + "--rm", + "--privileged" + ], + // "mounts": ["type=bind,source=/dev,target=/dev"], + // "customizations": { + // "vscode": { + // "extensions": [ + // "mshr-h.veriloghdl" + // ] + // } + // } } \ No newline at end of file diff --git a/slides/.devcontainer/Dockerfile b/.devcontainer/latex.Dockerfile similarity index 83% rename from slides/.devcontainer/Dockerfile rename to .devcontainer/latex.Dockerfile index ecc49c8..13f3898 100644 --- a/slides/.devcontainer/Dockerfile +++ b/.devcontainer/latex.Dockerfile @@ -2,9 +2,9 @@ FROM ubuntu:22.04 # LABEL about the custom image -LABEL maintainer="dancioc@nus.edu.sg" +LABEL maintainer="stefan_dan.ciocirlan@upb.ro" LABEL version="0.1" -LABEL description="Latex environment for SBIP" +LABEL description="Latex environment for AC course" # Disable Prompt During Packages Installation ARG DEBIAN_FRONTEND=noninteractive @@ -25,4 +25,6 @@ RUN apt-get update && \ #RUN wget http://beta.plantuml.net/batikAndFop.zip -P ./plantuml && wget http://beta.plantuml.net/plantuml-jlatexmath.zip -P ./plantuml # RUN unzip -o ./plantuml/batikAndFop.zip -d ./plantuml && unzip -o ./plantuml/plantuml-jlatexmath.zip -d ./plantuml -# RUN java -Djava.awt.headless=true -jar ./plantuml/plantuml-1.2023.11.jar ./diagrams/architecturev2.uml -o ./plantuml -tpdf \ No newline at end of file +# RUN java -Djava.awt.headless=true -jar ./plantuml/plantuml-1.2023.11.jar ./diagrams/architecturev2.uml -o ./plantuml -tpdf +# for latex coding with minted +RUN pip3 install Pygments \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..a5a9e3e --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,44 @@ +{ + "latex-workshop.latex.outDir": "out", + "latex-workshop.synctex.afterBuild.enabled": true, + "latex-workshop.view.pdf.viewer": "tab", + "latex-workshop.latex.build.forceRecipeUsage": false, + "latex-workshop.latex.search.rootFiles.include": ["**/courses/5/main.tex"], // Change this to the path of your main tex file + "latex-workshop.view.pdf.internal.synctex.keybinding": "double-click", + "latex-workshop.latex.autoClean.run": "onBuilt", + "latex-workshop.latex.autoBuild.run": "onSave", + "latex-workshop.latex.tools": [ + { + "name": "latexmk", + "command": "latexmk", + "args": [ + "-synctex=1", + "-interaction=nonstopmode", + "-file-line-error", + "--shell-escape", + "-pdf", + "-outdir=%OUTDIR%", + "%DOC%" + ] + }, + { + "name": "pdflatex", + "command": "pdflatex", + "args": [ + "--shell-escape", + "-synctex=1", + "-interaction=nonstopmode", + "-file-line-error", + "%DOC%" + ] + }, + { + "name": "bibtex", + "command": "bibtex", + "args": [ + "%DOCFILE%" + ], + "env": {} + } + ], +} \ No newline at end of file diff --git a/slides/.devcontainer/devcontainer.json b/slides/.devcontainer/devcontainer.json deleted file mode 100644 index 2557e28..0000000 --- a/slides/.devcontainer/devcontainer.json +++ /dev/null @@ -1,18 +0,0 @@ -// If you want to run as a non-root user in the container, see .devcontainer/docker-compose.yml. -{ - "name": "Latex env container", - "build": { "dockerfile": "Dockerfile" }, - "runArgs": [ - "--rm" - ], - "customizations": { - "vscode": { - "extensions": [ - "GitHub.vscode-pull-request-github", - "james-yu.latex-workshop", - "GitHub.copilot" - ] - } - }//, - //"postStartCommand": "wget https://github.com/plantuml/plantuml/releases/download/v1.2023.11/plantuml-1.2023.11.jar -P ./plantuml && wget http://beta.plantuml.net/batikAndFop.zip -P ./plantuml && wget http://beta.plantuml.net/plantuml-jlatexmath.zip -P ./plantuml && unzip -o ./plantuml/batikAndFop.zip -d ./plantuml && unzip -o ./plantuml/plantuml-jlatexmath.zip -d ./plantuml" -} \ No newline at end of file diff --git a/slides/.vscode/settings.json b/slides/.vscode/settings.json deleted file mode 100644 index ad76bab..0000000 --- a/slides/.vscode/settings.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "latex-workshop.latex.outDir": "out", - "latex-workshop.synctex.afterBuild.enabled": true, - "latex-workshop.view.pdf.viewer": "tab", - "latex-workshop.latex.build.forceRecipeUsage": false, - "latex-workshop.latex.search.rootFiles.include": ["**/courses/0/main.tex"], // Change this to the path of your main tex file - "latex-workshop.view.pdf.internal.synctex.keybinding": "double-click", - "latex-workshop.latex.autoClean.run": "onBuilt", - "latex-workshop.latex.autoBuild.run": "onSave", - "python.analysis.typeCheckingMode": "off", - "python.linting.enabled": true, - "python.linting.pylintEnabled": false, - "python.linting.flake8Enabled": true -} \ No newline at end of file diff --git a/slides/courses/5/architecture.tex b/slides/courses/5/architecture.tex new file mode 100644 index 0000000..d5065c3 --- /dev/null +++ b/slides/courses/5/architecture.tex @@ -0,0 +1,8 @@ +\begin{frame} + \frametitle{Architecture} + \begin{figure} + \centering + \includegraphics[height=0.7\textheight]{media/architecture.png} + \caption{Architecture} + \end{figure} +\end{frame} \ No newline at end of file diff --git a/slides/courses/5/components.tex b/slides/courses/5/components.tex new file mode 100644 index 0000000..b6c1d1c --- /dev/null +++ b/slides/courses/5/components.tex @@ -0,0 +1,166 @@ +\begin{frame} + \frametitle{Register} + \begin{circuitikz} + \draw + (0,0) node[draw, minimum width=2cm, minimum height=3cm] (chip) {Register} + (chip.west) ++(-0.5,1) node[left] {Data Input (DI)} -- (chip.west |- 0,1) + (chip.west) ++(-0.5,0) node[left] {Write Enable (WE)} -- (chip.west |- 0,0) + (chip.west) ++(-0.5,-1) node[left] {Output Enable (OE)} -- (chip.west |- 0,-1) + (chip.east) ++(0.5,0) node[right] {Data Output (DO)} -- (chip.east |- 0,0); + \end{circuitikz} + + \note{ + } +\end{frame} + +\begin{frame} + \frametitle{General Purpose Registers (GR)} + \begin{table}[] + \begin{tabular}{|l|l|l|} + \hline + \textbf{Register} & \textbf{Acronym} & \textbf{Size} \\ \hline + Register A & RA & 16-bit \\ \hline + Register B & RB & 16-bit \\ \hline + Register C & RC & 16-bit \\ \hline + Stack Pointer Register & SP & 16-bit \\ \hline + Index Register A & XA & 16-bit \\ \hline + Index Register B & XB & 16-bit \\ \hline + Base Address A & BA & 16-bit \\ \hline + Base Address B & BB & 16-bit \\ \hline + \end{tabular} + \end{table} + \note{ + } +\end{frame} + + +\begin{frame} + \frametitle{Registers File (RF)} + + \begin{circuitikz} + % Demux + \draw + (0,0) node[muxdemux, muxdemux def={Lh=4, Rh=8, NL=3, NR=8, NT=0, NB=3, w=2, + square pins=1}] (C) at (0,0) {I}; + % Inputs + \node[left, font=\tiny] at (C.lpin 1) {DI}; + \node[left, font=\tiny] at (C.lpin 2) {WE}; + \node[left, font=\tiny] at (C.lpin 3) {OE}; + + % Outputs + \node[above, font=\tiny] at (C.rpin 1) {RA}; + \node[right, font=\tiny] at (C.rpin 2) {RB}; + \node[right, font=\tiny] at (C.rpin 3) {RC}; + \node[right, font=\tiny] at (C.rpin 4) {SP}; + \node[right, font=\tiny] at (C.rpin 5) {XA}; + \node[right, font=\tiny] at (C.rpin 6) {XB}; + \node[right, font=\tiny] at (C.rpin 7) {BA}; + \node[right, font=\tiny] at (C.rpin 8) {BB}; + \node[below, font=\tiny] at (C.bpin 1) {Register Address (REG)}; + + % Split RA output into 3 connections + \draw (C.rpin 1) -- ++(1.0,0) coordinate (split) + (split) |- ++(1,1.0) node[right, font=\tiny] {DI} + (split) |- ++(1,-1.0) node[right, font=\tiny] {WE} + (split) -- ++(1,0) node[right, font=\tiny] {OE}; + + % Connect to another component + \draw (split) -- ++(1,0) node[draw, minimum width=2cm, minimum height=3cm, anchor=west] (chip) {RA} + (chip.east) node[left, font=\tiny] {DO} + (chip.east) |- ++(1,0.0) node[muxdemux, muxdemux def={Lh=8, Rh=1, NL=8, NR=1, NT=0, NB=3, w=2, + square pins=1}] (D) at (6.5,0) {O}; + % Inputs + \node[above, font=\tiny] at (D.lpin 1) {RA}; + \node[left, font=\tiny] at (D.lpin 2) {RB}; + \node[left, font=\tiny] at (D.lpin 3) {RC}; + \node[left, font=\tiny] at (D.lpin 4) {SP}; + \node[left, font=\tiny] at (D.lpin 5) {XA}; + \node[left, font=\tiny] at (D.lpin 6) {XB}; + \node[left, font=\tiny] at (D.lpin 7) {BA}; + \node[left, font=\tiny] at (D.lpin 8) {BB}; + \node[below, font=\tiny] at (D.bpin 1) {Register Address (REG)}; + + % Outputs + \node[above, font=\tiny] at (D.rpin 1) {DO}; + + \end{circuitikz} +\end{frame} + +\begin{frame} + \frametitle{Special Purpose Registers} + \begin{table}[] + \begin{tabular}{|l|l|l|} + \hline + \textbf{Register} & \textbf{Acronym} & \textbf{Size} \\ \hline + Program Counter & PC & 16-bit \\ \hline + Instruction Register & IR & 16-bit \\ \hline + Memory Address Register & MA & 16-bit \\ \hline + Flags Register & FR & 16-bit \\ \hline + Operand Register 1 & T1 & 16-bit \\ \hline + Operand Register 2 & T2 & 16-bit \\ \hline + Input/Output Addressing Register & IOA & 16-bit \\ \hline + \end{tabular} + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Memory (M)} + \begin{itemize} + \item Address width: 16-bit + \item Data width: 16-bit + \end{itemize} + \begin{circuitikz} + \draw + (0,0) node[draw, minimum width=2cm, minimum height=4cm] (chip) {Memory} + (chip.west) ++(-0.5,1) node[left] {Address (MA)} -- (chip.west |- 0,1) + (chip.west) ++(-0.5,0.5) node[left] {Memory Input (MI)} -- (chip.west |- 0,0.5) + (chip.west) ++(-0.5,-0.5) node[left] {Write Enable (WE)} -- (chip.west |- 0,-0.5) + (chip.west) ++(-0.5,-1) node[left] {Output Enable (OE)} -- (chip.west |- 0,-1) + (chip.east) ++(0.5,0) node[right] {Memory Output (MO)} -- (chip.east |- 0,0); + \end{circuitikz} + +\end{frame} + +\begin{frame} + \frametitle{Arithmetic Logic Unit (ALU)} + \begin{circuitikz} + \draw + (0,0) node[muxdemux, muxdemux def={Lh=7, NL=2, Rh=4, NR=2, NB=1, NT=2, w=4, + inset w=1, inset Lh=2, inset Rh=0, square pins=1}] (chip) {ALU} + % Inputs + (chip.lpin 1) node[left] {Operand 1 (T1)} + (chip.lpin 2) node[left] {Operand 2 (T2)} + (chip.bpin 1) node[below] {Operation (OP)} + (chip.tpin 1) node[left] {Carry In (CI)} + (chip.tpin 2) node[right] {Output Enable (OE)} + + % Outputs + (chip.rpin 1) node[right] {Result (R)} + (chip.rpin 2) node[right] {Flags (FR)}; + + \end{circuitikz} +\end{frame} + +\begin{frame} + \frametitle{Internal Bus} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|} + \hline + \textbf{Source} & \textbf{GR} & \textbf{M} & \textbf{T1} & \textbf{T2} & \textbf{IR} & \textbf{PC} & \textbf{IO} & \textbf{IOA} & \textbf{ALU} & \textbf{MA} & \textbf{FR} \\ \hline + \textbf{GR} & X & X & X & X & - & X & X & - & - & X & - \\ \hline + \textbf{M} & X & X & X & X & X & X & X & - & - & X & X \\ \hline + \textbf{T1} & - & - & - & - & - & - & - & - & X & - & - \\ \hline + \textbf{T2} & - & - & - & - & - & - & - & - & X & - & - \\ \hline + \textbf{IR} & - & - & - & - & - & - & - & X & - & - & - \\ \hline + \textbf{PC} & X & X & - & - & - & X & - & - & - & X & - \\ \hline + \textbf{IO} & X & X & - & - & - & - & - & - & - & - & - \\ \hline + \textbf{IOA} & - & - & - & - & - & - & X & - & - & - & - \\ \hline + \textbf{ALU} & X & X & X & X & - & X & - & - & - & X & X \\ \hline + \textbf{MA} & - & - & - & - & - & - & - & - & - & - & - \\ \hline + \textbf{FR} & - & X & - & - & - & - & - & - & - & - & - \\ \hline + \end{tabular} + } + \end{table} + +\end{frame} \ No newline at end of file diff --git a/slides/courses/5/format.tex b/slides/courses/5/format.tex new file mode 100644 index 0000000..3e5fd73 --- /dev/null +++ b/slides/courses/5/format.tex @@ -0,0 +1,98 @@ +\begin{frame} + \frametitle{Format} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} + \hline + \multicolumn{16}{|c|}{Instruction Register (IR)} \\ \hline + \textbf{0} & \textbf{1} & \textbf{2} & \textbf{3} & \textbf{4} & \textbf{5} & \textbf{6} & \textbf{7} & \textbf{8} & \textbf{9} & \textbf{10} & \textbf{11} & \textbf{12} & \textbf{13} & \textbf{14} & \textbf{15} \\ \hline + \multicolumn{7}{|c|}{OPC} & d & \multicolumn{2}{|c|}{MOD} & \multicolumn{3}{|c|}{REG} & \multicolumn{3}{|c|}{RM} \\ \hline + \multicolumn{16}{|c|}{immediate/data} \\ \hline + \multicolumn{16}{|c|}{data} \\ \hline + \end{tabular} + } + \begin{itemize} + \item \textbf{OPC} - Operation code + \item \textbf{d} - Destination (0 - RM, 1 - REG) + \item \textbf{MOD} - Addressing mode + \item \textbf{REG} - Register or extension for operation code + \item \textbf{RM} - Register/Memory + \end{itemize} + \end{table} +\end{frame} + +\begin{frame} + \frametitle{OPC} + \begin{itemize} + \item $IR_{0}$ - 0 for addressing memory, 1 for addressing register + \item $IR_{1}$ - 0 for one address, 1 for two addresses + \item $IR_{2}$ - 0 for without immediate data, 1 for immediate data + \item $IR_{1}=0, IR_{3}$ - 0 data transfer/flow control, 1 one operand + \item $IR_{1}=1, IR_{3}$ - 0 without saving the result, 1 with saving the result + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{OPC} + \begin{table}[] + \resizebox{0.8\textwidth}{!}{% + \begin{tabular}{|l|l||l|l|l|l|} + \hline + \multirow{2}{*}{\textbf{$IR_{1}$}} & \multirow{2}{*}{\textbf{$IR_{3}$}} & \multicolumn{2}{|l|}{$IR_{0}=0$} & \multicolumn{2}{|l|}{$IR_{0}=1$} \\ \cline{3-6} + & & $IR_{2}=0$ & $IR_{2}=1$ & \multicolumn{2}{|l|}{$IR_{2}=0$} \\ \hline \hline + \multirow{14}{*}{$0$} & \multirow{7}{*}{$0$} & $000=\text{MOV}$ & $000=\text{MOV}$ & $000=\text{IN}$ & \\ \cline{3-6} + & & $001=$ & $001=$ & $001=\text{OUT}$ & \\ \cline{3-6} + & & $010=\text{PUSH}$ & $010=$ & $010=\text{PUSHF}$ &\\ \cline{3-6} + & & $011=\text{POP}$ & $011=$ & $011=\text{POPF}$ & \\ \cline{3-6} + & & $100=\text{CALL}$ & $100=$ & $100=\text{RET}$ & \\ \cline{3-6} + & & $101=\text{JMP}$ & $101=$ & $101=\text{IRET}$ & \\ \cline{3-6} + & & $110=$ & $110=$ & $110=\text{HLT}$ & \\ \cline{3-6} + & & $111=$ & $111=$ & $111=$ & \\ \cline{2-6} + & \multirow{7}{*}{$1$} & $000=\text{INC}$ & $000=$ & $0000=\text{JBE}$ & $1000=\text{JBA}$ \\ \cline{3-6} + & & $001=\text{DEC}$ & $001=$ & $0001=\text{JB/JC}$ & $1001=\text{JAE/JNC}$ \\ \cline{3-6} + & & $010=\text{NEG}$ & $010=$ & $0010=\text{JLE}$ & $1010=\text{JG}$ \\ \cline{3-6} + & & $011=\text{NOT}$ & $011=$ & $0011=\text{JL}$ & $1011=\text{JGE}$ \\ \cline{3-6} + & & $100=\text{SHL/SAL}$ & $100=$ & $0100=\text{JE/JZ}$ & $1100=\text{JNE/JNZ}$ \\ \cline{3-6} + & & $101=\text{SHR}$ & $101=$ & $0101=\text{JO}$ & $1101=\text{JNO}$ \\ \cline{3-6} + & & $110=\text{SAR}$ & $110=$ & $0110=\text{JS}$ & $1110=\text{JNS}$ \\ \cline{3-6} + & & $111=$ & $111=$ & $0111=\text{JPE}$ & $1111=\text{JPO}$ \\ \hline + + \end{tabular} + } + \end{table} + + +\end{frame} + + +\begin{frame} + \frametitle{OPC} + \begin{table}[] + \resizebox{0.6\textwidth}{!}{% + \begin{tabular}{|l|l||l|l|l|l|} + \hline + \multirow{2}{*}{\textbf{$IR_{1}$}} & \multirow{2}{*}{\textbf{$IR_{3}$}} & \multicolumn{2}{|l|}{$IR_{0}=0$} & \multicolumn{2}{|l|}{$IR_{0}=1$} \\ \cline{3-6} + & & $IR_{2}=0$ & $IR_{2}=1$ & \multicolumn{2}{|l|}{$IR_{2}=0$} \\ \hline \hline + \multirow{14}{*}{$1$} & \multirow{7}{*}{$0$} & $000=$ & $000=$ & & \\ \cline{3-6} + & & $001=$ & $001=$ & & \\ \cline{3-6} + & & $010=\text{CMP}$ & $010=\text{CMP}$ & &\\ \cline{3-6} + & & $011=$ & $011=$ & & \\ \cline{3-6} + & & $100=\text{TEST}$ & $100=\text{TEST}$ & & \\ \cline{3-6} + & & $101=$ & $101=$ & & \\ \cline{3-6} + & & $110=$ & $110=$ & & \\ \cline{3-6} + & & $111=$ & $111=$ & & \\ \cline{2-6} + & \multirow{7}{*}{$1$} & $000=\text{ADD}$ & $000=\text{ADD}$ & & \\ \cline{3-6} + & & $001=\text{ADC}$ & $001=\text{ADC}$ & & \\ \cline{3-6} + & & $010=\text{SUB}$ & $010=\text{SUB}$ & & \\ \cline{3-6} + & & $011=\text{SBB}$ & $011=\text{SBB}$ & & \\ \cline{3-6} + & & $100=\text{AND}$ & $100=\text{AND}$ & & \\ \cline{3-6} + & & $101=\text{OR}$ & $101=\text{OR}$ & & \\ \cline{3-6} + & & $110=\text{XOR}$ & $110=\text{XOR}$ & & \\ \cline{3-6} + & & $111=$ & $111=$ & & \\ \hline + + \end{tabular} + } + \end{table} + + +\end{frame} \ No newline at end of file diff --git a/slides/courses/5/isa.tex b/slides/courses/5/isa.tex new file mode 100644 index 0000000..af2c6d4 --- /dev/null +++ b/slides/courses/5/isa.tex @@ -0,0 +1,104 @@ +\begin{frame} + \frametitle{Instruction Set Architecture (ISA)} + \textbf{Types of instructions:} + \begin{itemize} + \item \textbf{Data transfer} + \item \textbf{Arithmetic} + \item \textbf{Logical and bit manipulation} + \item \textbf{Flow Control} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Data transfer} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|l|l|l|} + \hline + \textbf{Goal} & \textbf{Acronym} & \textbf{Description} \\ \hline + \multirow{3}{*}{General} & MOV & Move data from source to destination \\ \cline{2-3} + & PUSH & Push data onto the stack \\ \cline{2-3} + & POP & Pop data from the stack \\ \hline + \multirow{2}{*}{IO} & IN & Input data from an I/O port \\ \cline{2-3} + & OUT & Output data to an I/O port \\ \hline + \multirow{2}{*}{Flags} & PUSHF & Push flags onto the stack \\ \cline{2-3} + & POPF & Pop flags from the stack \\ \hline + \end{tabular} + } + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Arithmetic} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|l|l|l|} + \hline + \textbf{Goal} & \textbf{Acronym} & \textbf{Description} \\ \hline + \multirow{3}{*}{Addition} & ADD & Add two operands \\ \cline{2-3} + & ADC & Add two operands with carry \\ \cline{2-3} + & INC & Increment one operand\\ \hline + \multirow{5}{*}{Subtraction} & SUB & Subtract destination with source \\ \cline{2-3} + & SBB & Subtract with borrow \\ \cline{2-3} + & DEC & Decrement one operand \\ \cline{2-3} + & NEG & Negate one operand (two's complement) \\ \cline{2-3} + & CMP & Compare two operands \\ \hline + \end{tabular} + } + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Logical and bit manipulation} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|l|l|l|} + \hline + \textbf{Goal} & \textbf{Acronym} & \textbf{Description} \\ \hline + \multirow{3}{*}{Logic} & AND & Bitwise AND operation \\ \cline{2-3} + & OR & Bitwise OR operation \\ \cline{2-3} + & XOR & Bitwise XOR operation \\ \cline{2-3} + & NOT & Not one operand (one's complement) \\ \cline{2-3} + & TEST & Bitwise AND without result \\ \hline + \multirow{3}{*}{Shift} & SHL/SAL & Shift left \\ \cline{2-3} + & SHR & Shift right \\ \cline{2-3} + & SAR & Arithmetic shift right \\ \hline + \end{tabular} + } + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Flow Control} + \begin{table}[] + \resizebox{0.6\textwidth}{!}{% + \begin{tabular}{|l|l|l|} + \hline + \textbf{Goal} & \textbf{Acronym} & \textbf{Description} \\ \hline + \multirow{3}{*}{Jump} & JMP & Jump to an address \\ \cline{2-3} + & CALL & Call a subroutine \\ \cline{2-3} + & RET & Return from a subroutine \\ \cline{2-3} + & IRET & Return from a interuption subroutine \\ \cline{2-3} + & HLT & Halt the processor \\ \hline + \multirow{3}{*}{Conditional} & JA & Jump above (C or Z = 0) \\ \cline{2-3} + & JAE & Jump above or equal (C = 0) \\ \cline{2-3} + & JB & Jump below (C) \\ \cline{2-3} + & JBE & Jump below or equal (C or Z) \\ \cline{2-3} + & JC & Jump if carry (C) \\ \cline{2-3} + & JE & Jump if equal (Z) \\ \cline{2-3} + & JG & Jump if greater ($(S \oplus O) | Z = 0$) \\ \cline{2-3} + & JGE & Jump if greater or equal ($(S \oplus O) = 0$) \\ \cline{2-3} + & JL & Jump if less ($(S \oplus O) = 1$) \\ \cline{2-3} + & JLE & Jump if less or equal ($(S \oplus O) | Z = 1$) \\ \cline{2-3} + & JNC & Jump if not carry \\ \cline{2-3} + & JNE & Jump if not equal \\ \cline{2-3} + & JNO & Jump if not overflow \\ \cline{2-3} + & JPO & Jump if parity odd \\ \cline{2-3} + & JNS & Jump if sign \\ \cline{2-3} + & JO & Jump if overflow \\ \cline{2-3} + & JPE & Jump if parity even \\ \cline{2-3} + & JS & Jump if sign \\ \hline + \end{tabular} + } + \end{table} +\end{frame} \ No newline at end of file diff --git a/slides/courses/5/main.tex b/slides/courses/5/main.tex new file mode 100644 index 0000000..db1acbd --- /dev/null +++ b/slides/courses/5/main.tex @@ -0,0 +1,117 @@ +%\documentclass[notes,usenames,dvipsnames]{beamer} +%\documentclass[notes]{beamer} % print frame + notes +%\documentclass[notes=only]{beamer} % only notes +\documentclass[usenames,dvipsnames]{beamer} % only frames +\usepackage{pgfpages} +%\setbeameroption{show notes on second screen} +%\setbeameroption{show notes} +%subfigures +\usepackage{caption} +\usepackage{subcaption} + +%tables packages +\usepackage{multirow} + +% math +\usepackage{amsmath} + +% bash command +\usepackage{graphicx} +\usepackage{listings} +% varbatim for ascii figures +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +%\usepackage{verbatim} +\usepackage{lipsum} % for context +\usepackage{fancyvrb} +\usepackage{varwidth} +\usepackage{circuitikz} +\ctikzset{logic ports=ieee} + + +\newsavebox{\asciigcn} + +% notes prefixed in pympress +\addtobeamertemplate{note page}{}{\thispdfpagelabel{notes:\insertframenumber}} +%theme used +\usetheme{Madrid} +%Information to be included in the title page: +\title[Computer Architecture] %optional +{Computer Architecture} + +\subtitle{Course no. 5 - CPU Architecture} + +\author[Ștefan-Dan Ciocîrlan] % (optional, for multiple authors) +{} + +\institute[NUSTPB] % (optional) +{ + \inst{}% + National University of Science and Technology\\ + POLITEHNICA Bucharest +} + +\date[NUSTPB 2024] % (optional) +{Computer Architecture} + +\logo{ +\includegraphics[height=0.9cm]{../../media/LOGO_UNSTPB_en.png} +\includegraphics[height=0.9cm]{../../media/logoACSQ.jpeg} +} + + +% Roman numerals +\newcommand*{\rom}[1]{\expandafter\@slowromancap\romannumeral #1@} +%split +\usepackage{amsmath} +%colors +%\usepackage[usenames,dvipsnames]{color} %loaded by the dcoument class +%subfigure +\usepackage{subcaption} +% block over block uncover +\setbeamercovered{invisible} +%\setbeamercovered{transparent} + +%extra slide content +\AtBeginSection[] +{ + \begin{frame} + \frametitle{Content} + \tableofcontents[currentsection] + \end{frame} +} +%notes or not +%\setbeamertemplate{note page}[plain] + +\begin{document} + +\frame{\titlepage} + +\section{CPU components} +\input{components.tex} + +\section{Architecture} +\input{architecture.tex} + +\section{Instruction Set Architecture (ISA)} +\input{isa.tex} + +\section{Instruction Coding} +\input{format.tex} + +\section{Memory addressing} +\input{memory.tex} + + + +\section{Q\&A} +\begin{frame} +\end{frame} + +%\begin{frame} +%\frametitle{Table of Contents} +%\tableofcontents +%\end{frame} + + +\end{document} \ No newline at end of file diff --git a/slides/courses/5/media/architecture.drawio b/slides/courses/5/media/architecture.drawio new file mode 100644 index 0000000..31432dd --- /dev/null +++ b/slides/courses/5/media/architecture.drawio @@ -0,0 +1,338 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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0 HcmV?d00001 diff --git a/slides/courses/5/memory.tex b/slides/courses/5/memory.tex new file mode 100644 index 0000000..efa5022 --- /dev/null +++ b/slides/courses/5/memory.tex @@ -0,0 +1,174 @@ +\begin{frame} + \frametitle{Direct Addressing} + \begin{itemize} + \item Address is directly specified in the instruction (immediate) + \item Example: \texttt{MOV RA, M[0x1234]} + \item $MA = 0x1234$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from Memory} + \begin{itemize} + \item Address is stored in memory + \item Example: \texttt{MOV RA, M[M[0x1234]]} + \item Step 1: $MA = 0x1234$ + \item Step 2: $MA = M[0x1234]$ (indirect) + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from Register} + \begin{itemize} + \item Address is stored in a register + \item Example: \texttt{MOV RA, M[BA]} + \item $MA = BA$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from base and index registers} + \begin{itemize} + \item Address is stored in the sum of two registers (base and index) + \item Example: \texttt{MOV RA, M[BA + XA]} + \item $MA = BA + XA$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from base and index registers with increment after for index} + \begin{itemize} + \item Address is stored in the sum of two registers (base and index) + \item Index register is incremented after the operation + \item Example: \texttt{MOV RA, M[BA + XA++]} + \item $MA = BA + XA$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from base and index registers with decrement before for index} + \begin{itemize} + \item Address is stored in the sum of two registers (base and index) + \item Index register is decremented before the operation + \item Only with $XA$ register + \item Example: \texttt{MOV RA, M[BA + XA--]} + \item $MA = BA + XA - 1$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from base and immediate} + \begin{itemize} + \item Address is stored in the sum of a base register and an immediate value + \item Example: \texttt{MOV RA, M[BA + 0x1234]} + \item $MA = BA + 0x1234$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from index and immediate} + \begin{itemize} + \item Address is stored in the sum of a index register and an immediate value + \item Example: \texttt{MOV RA, M[XA + 0x1234]} + \item $MA = XA + 0x1234$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Indirect Addressing from base and index with immediate} + \begin{itemize} + \item Address is stored in the sum of a base register, an index register and an immediate value + \item Example: \texttt{MOV RA, M[BA + XA + 0x1234]} + \item $MA = BA + XA + 0x1234$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Immediate Addressing} + \begin{itemize} + \item Address is directly specified in the instruction (immediate) + \item Example: \texttt{MOV RA, 7} + \item $MA = PC + 1$ or $MA = PC + 2$ + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Direct Register Addressing} + \begin{itemize} + \item Data is in a register specified in the instruction (RM) + \item Example: \texttt{MOV RA, RB} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Address Table for IR} + \begin{table}[] + \resizebox{0.9\textwidth}{!}{% + \begin{tabular}{|l||l|l|l|l|} + \hline + \multirow{2}{*}{$RM=IR_{13:15}$} & \multicolumn{4}{|l|}{$MOD=IR_{8:9}$} \\ \cline{2-5} + & $00$ & $01$ & $10$ & $11$ \\ \hline \hline + $000$ & $[BA+XA]$ & $[BA+XA+]$ & $[BA+XA+\text{Imm}]$ & $RA$ \\ \hline + $001$ & $[BA+XB]$ & $[BA+XB+]$ & $[BA+XB+\text{Imm}]$ & $RB$ \\ \hline + $010$ & $[BB+XA]$ & $[BB+XA+]$ & $[BB+XA+\text{Imm}]$ & $RC$ \\ \hline + $011$ & $[BB+XB]$ & $[BB+XB+]$ & $[BB+XB+\text{Imm}]$ & $SP$ \\ \hline + $100$ & $[XA]$ & $[BA+(--XA)]$ & $[XA+\text{Imm}]$ & $XA$ \\ \hline + $101$ & $[XB]$ & $[BB+(--XA)]$ & $[XB+\text{Imm}]$ & $XB$ \\ \hline + $110$ & $[BA]$ & $[\text{Imm}]$ & $[BA+\text{Imm}]$ & $BA$ \\ \hline + $111$ & $[BB]$ & $[[\text{Imm}]]$ & $[BB+\text{Imm}]$ & $BB$ \\ \hline \hline + + \end{tabular} + } + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Exam Question} + Template: Having the following registers value, main memory address and data, and the immediate value what is the value of the MA register if we use the X addressing mode? + + Example: Having the following registers value, main memory address and data, and the immediate value of $0x1234$ what is the value of the MA register if we use the direct addressing mode? + + \begin{columns} + \column{0.5\textwidth} + \begin{table}[] + \begin{tabular}{|l|l|} + \hline + \textbf{Register} & \textbf{Value} \\ \hline + BA & 0x1234 \\ \hline + BB & 0x5678 \\ \hline + XA & 0x0001 \\ \hline + XB & 0x0002 \\ \hline + RA & 0x0003 \\ \hline + RB & 0x0004 \\ \hline + RC & 0x0005 \\ \hline + SP & 0x0006 \\ \hline + \end{tabular} + \end{table} + + \column{0.5\textwidth} + \begin{table}[] + \begin{tabular}{|l|l|} + \hline + \textbf{Memory Address} & \textbf{Data} \\ \hline + 0x1234 & 0x0007 \\ \hline + 0x5678 & 0x0008 \\ \hline + \end{tabular} + \end{table} + \end{columns} +\end{frame} + + +\begin{frame} + \frametitle{Exam Question} + Template: Having the memory addressing table and instruction format tables, what is the instruction conding for the X operation? + + Example: Having the memory addressing table and instruction format tables, what is the instruction conding for the $MOV\ RA, [BA+XA+]$? +\end{frame} + + +\begin{frame} + \frametitle{Exam Question} + Template: Having the memory addressing table and instruction format tables, what is the instruction for the $IR=x$? + + Example: Having the memory addressing table and instruction format tables, what is the instruction for the $IR=0x47AB$? +\end{frame} \ No newline at end of file diff --git a/slides/courses/6/assembly.tex b/slides/courses/6/assembly.tex new file mode 100644 index 0000000..d24fda1 --- /dev/null +++ b/slides/courses/6/assembly.tex @@ -0,0 +1,151 @@ +\begin{frame} + \frametitle{Assembly Language} + \begin{itemize} + \item Low-level programming language + \item Directly related to machine code + \item Most cases: each instruction corresponds to a machine code instruction + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Advantages} + \begin{itemize} + \item Direct access to hardware + \item High performance + \item Small code size + \item Full control over the system + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Disadvantages} + \begin{itemize} + \item Difficult to write + \item Difficult to read + \item Difficult to maintain + \item Difficult to debug + \item Difficult to port + \item Time consuming + \end{itemize} +\end{frame} + + +\begin{frame} + \frametitle{Position of Code} + \begin{itemize} + \item Independent (absolute/PIC) + \item Relative to the current instruction (PC-relative) + \item External to the code (libaries) + \end{itemize} +\end{frame} + + +\begin{frame} + \frametitle{Mnemonics} + \begin{itemize} + \item Instruction: + + [Label:] \texttt{Operation} [List of Operands] [; Comment] + + \item Variables: + + \texttt{name type size} [value/expresion] [; Comment] + + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Data Types} + \begin{itemize} + \item DB Byte: 8 bits + \item DW Word: 16 bits + \item DD Double Word: 32 bits + \item DQ Quad Word: 64 bits + \item DT Ten Bytes: 80 bits + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Constants} + \begin{itemize} + \item binary 10101B + \item octal 1234Q + \item decimal 1234D + \item hexadecimal 1234H (first digit must be 0-9) + \item character 'A' + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Operator DUP} + \begin{itemize} + \item \texttt{var DB 10 DUP(?)} + \item \texttt{var DB 10 DUP(0)} + \item \texttt{var DB 5 DUP(5 DUP(5 DUP(0)))} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Sections} + \begin{itemize} + \item \texttt{.data} + \item \texttt{.text} + \item \texttt{.rodata} + \item \texttt{.section} + \item \texttt{.global} + \item \texttt{.extern} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Directives} + \begin{itemize} + \item \texttt{.equ} + \item \texttt{=} + \item \texttt{.asci} + \item \texttt{.include} + \end{itemize} +\end{frame} + + +\begin{frame}[fragile] + \frametitle{Code Example} + \begin{minted}{gas} + VEC DW 10 DUP(0); 10 words initialized with 0 + SUM DW 0; 1 word initialized with 0 + SIZE EQU 10; SIZE = 10 + + MAIN: + MOV BA, VEC; BA = VEC + XOR XA, XA; XA = 0 + + INIT_LOOP: + MOV [BA + XA+], XA; VEC[XA++] = XA + CMP XA, 10; Compare XA with 10 + JL INIT_LOOP; If XA < 10, jump to INIT_LOOP + + \end{minted} + +\end{frame} + + +\begin{frame}[fragile] + \frametitle{Code Example} + \begin{minted}{gas} + + MOV BA, VEC; BA = VEC + XOR XA, XA; XA = 0 + MOV RA, XA; RA = XA + + SUM_LOOP: + ADD RA, [BA + XA+]; RA += VEC[XA++] + CMP XA, 10; Compare XA with 10 + JL SUM_LOOP; If XA < 10, jump to SUM_LOOP + + MOV SUM, RA; SUM = RA + HALT: + HLT; Stop the program + + \end{minted} + +\end{frame} \ No newline at end of file diff --git a/slides/courses/6/compilation.tex b/slides/courses/6/compilation.tex new file mode 100644 index 0000000..b98c40b --- /dev/null +++ b/slides/courses/6/compilation.tex @@ -0,0 +1,203 @@ +\begin{frame} + \frametitle{Compilation Steps} + \begin{itemize} + \item Preprocess + \item Compile + \item Assemble + \item Link + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Code example C} + \inputminted{c}{add.c} +\end{frame} + + +\begin{frame} + \frametitle{Preprocess} + + \begin{columns} + \column{0.5\textwidth} +\begin{itemize} + \item Remove comments + \item Include files + \item Macros + \item \mint{bash}|clang -O0 -E add.c -o add.i| + \end{itemize} + \column{0.5\textwidth} + \inputminted[firstline=8]{c}{add.i} + \end{columns} +\end{frame} + +\begin{frame}[fragile] + \frametitle{Compile} + \begin{columns} + \column{0.5\textwidth} +\begin{itemize} + \item Translate to assembly + \item \mint{bash}|clang -O0 -S add.i -o add.s| + \end{itemize} + \column{0.5\textwidth} + \begin{minted}[fontsize=\footnotesize]{gas} +main: + ... + movl $0, -4(%rbp) + movl $0, -8(%rbp) +.LBB0_1: + cmpl $10, -8(%rbp) + jge .LBB0_4 + movl -8(%rbp), %edx + movslq -8(%rbp), %rcx + leaq n(%rip), %rax + movl %edx, (%rax,%rcx,4) + movl -8(%rbp), %eax + addl $1, %eax + movl %eax, -8(%rbp) + jmp .LBB0_1 +.LBB0_4: + \end{minted} + \end{columns} +\end{frame} + + +\begin{frame}[fragile] + \frametitle{Compile} + \begin{columns} + \column{0.5\textwidth} + \begin{minted}[fontsize=\footnotesize]{gas} + movl $0, sum(%rip) + movl $0, -8(%rbp) +.LBB0_5: + cmpl $10, -8(%rbp) + jge .LBB0_8 + movslq -8(%rbp), %rcx + leaq n(%rip), %rax + movl (%rax,%rcx,4), %eax + addl sum(%rip), %eax + movl %eax, sum(%rip) + movl -8(%rbp), %eax + addl $1, %eax + movl %eax, -8(%rbp) + jmp .LBB0_5 +.LBB0_8: + movl sum(%rip), %eax + popq %rbp + retq + \end{minted} + \column{0.5\textwidth} + \begin{minted}[fontsize=\footnotesize]{gas} + .bss + .globl n + .p2align 4 +n: + .zero 40 + .size n, 40 + + .globl sum + .p2align 2 +sum: + .long 0 + .size sum, 4 + \end{minted} + +\end{columns} +\end{frame} + +\begin{frame} + \frametitle{Assemble} + \begin{itemize} + \item Translate to machine code + \item \mint{bash}|clang -O0 -c add.s -o add.o| + \item Disassemble the object file to inspect the assembly code + \item \mint{bash}|objdump -S add.o| + \item Reverse engineering + \item \mint{bash}|xxd add.o| + \end{itemize} +\end{frame} + +\begin{frame}[fragile] + \frametitle{Assemble} + \begin{minted}[fontsize=\footnotesize]{c-objdump} +0000000000000000

: +00: 55 push %rbp +01: 48 89 e5 mov %rsp,%rbp +04: c7 45 fc 00 00 00 00 movl $0x0,-0x4(%rbp) +0b: c7 45 f8 00 00 00 00 movl $0x0,-0x8(%rbp) +12: c7 45 f8 00 00 00 00 movl $0x0,-0x8(%rbp) +19: 83 7d f8 0a cmpl $0xa,-0x8(%rbp) +1d: 7d 1c jge 3b +1f: 8b 55 f8 mov -0x8(%rbp),%edx +22: 48 63 4d f8 movslq -0x8(%rbp),%rcx +26: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # 2d +2d: 89 14 88 mov %edx,(%rax,%rcx,4) +30: 8b 45 f8 mov -0x8(%rbp),%eax +33: 83 c0 01 add $0x1,%eax +36: 89 45 f8 mov %eax,-0x8(%rbp) +39: eb de jmp 19 + \end{minted} + +\end{frame} + + +\begin{frame}[fragile] + \frametitle{Assemble} + \begin{minted}[fontsize=\footnotesize]{c-objdump} +3b: c7 05 00 00 00 00 00 movl $0x0,0x0(%rip) # 45 +42: 00 00 00 +45: c7 45 f8 00 00 00 00 movl $0x0,-0x8(%rbp) +4c: 83 7d f8 0a cmpl $0xa,-0x8(%rbp) +50: 7d 25 jge 77 +52: 48 63 4d f8 movslq -0x8(%rbp),%rcx +56: 48 8d 05 00 00 00 00 lea 0x0(%rip),%rax # 5d +5d: 8b 04 88 mov (%rax,%rcx,4),%eax +60: 03 05 00 00 00 00 add 0x0(%rip),%eax # 66 +66: 89 05 00 00 00 00 mov %eax,0x0(%rip) # 6c +6c: 8b 45 f8 mov -0x8(%rbp),%eax +6f: 83 c0 01 add $0x1,%eax +72: 89 45 f8 mov %eax,-0x8(%rbp) +75: eb d5 jmp 4c +77: 8b 05 00 00 00 00 mov 0x0(%rip),%eax # 7d +7d: 5d pop %rbp +7e: c3 ret + \end{minted} + +\end{frame} + + +\begin{frame}[fragile] + \frametitle{Assemble} + \begin{minted}[fontsize=\footnotesize]{hexdump} +00000040: 5548 89e5 c745 fc00 0000 00c7 45f8 0000 UH...E......E... +00000050: 0000 c745 f800 0000 0083 7df8 0a7d 1c8b ...E......}..}.. +00000060: 55f8 4863 4df8 488d 0500 0000 0089 1488 U.HcM.H......... +00000070: 8b45 f883 c001 8945 f8eb dec7 0500 0000 .E.....E........ +00000080: 0000 0000 00c7 45f8 0000 0000 837d f80a ......E......}.. +00000090: 7d25 4863 4df8 488d 0500 0000 008b 0488 }%HcM.H......... +000000a0: 0305 0000 0000 8905 0000 0000 8b45 f883 .............E.. +000000b0: c001 8945 f8eb d58b 0500 0000 005d c300 ...E.........].. + \end{minted} + +\end{frame} + +\begin{frame} + \frametitle{Link} + \begin{itemize} + \item Combine object files + \item Resolve external references + \item \mint{bash}|ld| + \item \mint{bash}|clang -v -O0 add.o -o add| + \item \mint{bash}|./add| + \item \mint{bash}|objdump -S add| + \item \mint{bash}|xxd add| + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Practice} + \begin{itemize} + \item try with different optimization levels + \item try with "-g" flag + \item try with different compilers + \end{itemize} +\end{frame} \ No newline at end of file diff --git a/slides/courses/6/main.tex b/slides/courses/6/main.tex new file mode 100644 index 0000000..d5bb1ef --- /dev/null +++ b/slides/courses/6/main.tex @@ -0,0 +1,112 @@ +%\documentclass[notes,usenames,dvipsnames]{beamer} +%\documentclass[notes]{beamer} % print frame + notes +%\documentclass[notes=only]{beamer} % only notes +\documentclass[usenames,dvipsnames]{beamer} % only frames +\usepackage[outputdir=out]{minted} +\usepackage{pgfpages} +%\setbeameroption{show notes on second screen} +%\setbeameroption{show notes} +%subfigures +\usepackage{caption} +\usepackage{subcaption} + +%tables packages +\usepackage{multirow} + +% math +\usepackage{amsmath} + +% bash command +\usepackage{graphicx} +\usepackage{listings} +% varbatim for ascii figures +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +%\usepackage{verbatim} +\usepackage{lipsum} % for context +\usepackage{fancyvrb} +\usepackage{varwidth} +\usepackage{circuitikz} +\ctikzset{logic ports=ieee} +\usepackage{listings} +% \lstset{language=[Motorola68k]Assembler,basicstyle=\ttfamily,keywordstyle=\color{blue}} + +\usepackage{shellesc} +\usepackage{adjustbox} + +\newsavebox{\asciigcn} + +% notes prefixed in pympress +\addtobeamertemplate{note page}{}{\thispdfpagelabel{notes:\insertframenumber}} +%theme used +\usetheme{Madrid} +%Information to be included in the title page: +\title[Computer Architecture] %optional +{Computer Architecture} + +\subtitle{Course no. 6 - Programing Lanuages} + +\author[Ștefan-Dan Ciocîrlan] % (optional, for multiple authors) +{} + +\institute[NUSTPB] % (optional) +{ + \inst{}% + National University of Science and Technology\\ + POLITEHNICA Bucharest +} + +\date[NUSTPB 2024] % (optional) +{Computer Architecture} + +\logo{ +\includegraphics[height=0.9cm]{../../media/LOGO_UNSTPB_en.png} +\includegraphics[height=0.9cm]{../../media/logoACSQ.jpeg} +} + + +% Roman numerals +\newcommand*{\rom}[1]{\expandafter\@slowromancap\romannumeral #1@} +%split +\usepackage{amsmath} +%colors +%\usepackage[usenames,dvipsnames]{color} %loaded by the dcoument class +%subfigure +\usepackage{subcaption} +% block over block uncover +\setbeamercovered{invisible} +%\setbeamercovered{transparent} + +%extra slide content +\AtBeginSection[] +{ + \begin{frame} + \frametitle{Content} + \tableofcontents[currentsection] + \end{frame} +} +%notes or not +%\setbeamertemplate{note page}[plain] + +\begin{document} + +\frame{\titlepage} + +\section{Assemby Language} +\input{assembly.tex} + +\section{Compilation} +\input{compilation.tex} + + +\section{Q\&A} +\begin{frame} +\end{frame} + +%\begin{frame} +%\frametitle{Table of Contents} +%\tableofcontents +%\end{frame} + + +\end{document} \ No newline at end of file diff --git a/slides/courses/7/implementation.tex b/slides/courses/7/implementation.tex new file mode 100644 index 0000000..b81c0f2 --- /dev/null +++ b/slides/courses/7/implementation.tex @@ -0,0 +1,118 @@ +\begin{frame} + \frametitle{Lab CPU} + \begin{itemize} + \item Port-Mapped I/O + \item First 256 addresses are reserved for I/O + \item Special instructions for I/O (IN, OUT) + \item I/O devices are connected to the CPU through the bus + \item CPU is pooling the I/O devices + \item Status and Command registers for each device are mapped to the same I/O addresses + \item Data registers are mapped to the next I/O addresses + \item Can be changed to memory-mapped I/O or DMA + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Lab I/O} + \begin{figure} + \centering + \includegraphics[width=0.8\textwidth]{media/io.png} + \end{figure} +\end{frame} + +\begin{frame} + \frametitle{Lab I/O DMA} + \begin{itemize} + \item 8 registers for DMA into the I/O space (let's start from 0x08) + \end{itemize} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|c|c|c|} + \hline + \textbf{Address} & \textbf{Name} & \textbf{Function} \\ \hline + 0x08 & SCIO0 & Status/Command Register for IO device 0 \\ \hline + 0x09 & SCIO1 & Status/Command Register for IO device 1 \\ \hline + 0x0a & SCIO2 & Status/Command Register for IO device 2 \\ \hline + 0x0b & SCIO3 & Status/Command Register for IO device 3 \\ \hline + 0x0c & SCDMA & Status/Command Register for DMA \\ \hline + 0x0d & MADMA & Memory Address Register for DMA \\ \hline + 0x0e & CNTDMA & Count Register for DMA \\ \hline + 0x0f & INITDMA & Initialize DMA Register \\ \hline + \end{tabular} + } + \end{table} +\end{frame} + +\begin{frame} + \frametitle{Architecture with DMA} + \begin{figure} + \centering + \includegraphics[width=0.9\textwidth]{media/dma.png} + \end{figure} +\end{frame} + +\begin{frame} + \frametitle{SCDMA Register} + \begin{table}[] + \resizebox{\textwidth}{!}{% + \begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|} + \hline + \textbf{0} & \textbf{1} & \textbf{2} & \textbf{3} & \textbf{4} & \textbf{5} & \textbf{6} & \textbf{7} & \textbf{8} & \textbf{9} & \textbf{10} & \textbf{11} & \textbf{12} & \textbf{13} & \textbf{14} & \textbf{15} \\ \hline + $SIO_{0}$ & $SIO_{1}$ & $SIO_{2}$ & $SIO_{3}$ & X & X & SDMA & EOBT & EXTIRQ & X & PIRQ & ENIRQ & X & MT & DT & ENT \\ \hline + \end{tabular} + } + \end{table} + \begin{itemize} + \item $SIO_{0-3}$ - Status of the I/O devices 0 - functional 1 - not functional + \item SDMA - DMA is active for 0 - inactive for 1 + \item EOBT - End of block transfer for 0 - not for 1 + \item EXTIRQ - There is an external interrupt from IO device for 0 - not for 1 + \item PIRQ - There is a programable interrupt from CPU for 0 - not for 1 (testing) + \item ENIRQ - Enable interrupt for 0 - disable for 1 + \item MT - Mode of transfer 0 - block for 1 - cycle stealing + \item DT - Direction of transfer 0 - from IO to memory to IO for 1 - from memory to IO + \item ENT - Enable transfer for 0 - disable for 1 + \end{itemize} + \note{ + } +\end{frame} + +\begin{frame} + \frametitle{Exam Question} + Template: Having the following IO registers value, main memory address and data, what can you find on the data bus? + + Example: Having the following IO registers value, main memory address and data, what can you find on the data bus? + \begin{columns} + \column{0.5\textwidth} + \begin{table}[] + \begin{tabular}{|l|l|} + \hline + \textbf{Register} & \textbf{Value} \\ \hline + SCDMA & 0x1234 \\ \hline + MADMA & 0x5678 \\ \hline + CNTDMA & 0x0001 \\ \hline + INITDMA & 0x0002 \\ \hline + SCIO0 & 0x0000 \\ \hline + SCIO1 & 0x0000 \\ \hline + SCIO2 & 0x0000 \\ \hline + SCIO3 & 0x0000 \\ \hline + \end{tabular} + \end{table} + \column{0.5\textwidth} + \begin{table}[] + \begin{tabular}{|l|l|} + \hline + \textbf{Memory Address} & \textbf{Data} \\ \hline + 0x5678 & 0x0000 \\ \hline + 0x5679 & 0x0001 \\ \hline + 0x567a & 0x0002 \\ \hline + 0x567b & 0x0003 \\ \hline + 0x567c & 0x0004 \\ \hline + 0x567d & 0x0005 \\ \hline + 0x567e & 0x0006 \\ \hline + 0x567f & 0x0007 \\ \hline + \end{tabular} + \end{table} + \end{columns} + +\end{frame} diff --git a/slides/courses/7/intro.tex b/slides/courses/7/intro.tex new file mode 100644 index 0000000..fc10a5f --- /dev/null +++ b/slides/courses/7/intro.tex @@ -0,0 +1,43 @@ +\begin{frame} + \frametitle{Components} + \begin{itemize} + \item Input/Output Devices (makes the conversion between the external world and the computer) + \item Input/Output Interfaces (connects the devices to the computer) + \item Input/Output Middleware (manages the data transfer between the devices and the computer) can be CPU + \item Input/Output Device Drivers (software that allows the computer to communicate with the devices) + \item Input/Output Memory + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Types of data in I/O} + \begin{itemize} + \item Fixed Block + \item Variable Block + \item Character + \item Hybrid + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{I/O Registers} + \begin{itemize} + \item Control + \item Status + \item Data + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Communication with I/O} + \begin{itemize} + \item Through status registers (polling) + \item Through hardware interrupts + \begin{itemize} + \item Save the context + \item Jump to the interrupt handler + \item Restore the context + \item Return from the interrupt + \end{itemize} + \end{itemize} +\end{frame} \ No newline at end of file diff --git a/slides/courses/7/main.tex b/slides/courses/7/main.tex new file mode 100644 index 0000000..bbf38a7 --- /dev/null +++ b/slides/courses/7/main.tex @@ -0,0 +1,118 @@ +%\documentclass[notes,usenames,dvipsnames]{beamer} +%\documentclass[notes]{beamer} % print frame + notes +%\documentclass[notes=only]{beamer} % only notes +\documentclass[usenames,dvipsnames]{beamer} % only frames +\usepackage[outputdir=out]{minted} +\usepackage{pgfpages} +%\setbeameroption{show notes on second screen} +%\setbeameroption{show notes} +%subfigures +\usepackage{caption} +\usepackage{subcaption} + +%tables packages +\usepackage{multirow} + +% math +\usepackage{amsmath} + +% bash command +\usepackage{graphicx} +\usepackage{listings} +% varbatim for ascii figures +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +%\usepackage{verbatim} +\usepackage{lipsum} % for context +\usepackage{fancyvrb} +\usepackage{varwidth} +\usepackage{circuitikz} +\ctikzset{logic ports=ieee} +\usepackage{listings} +% \lstset{language=[Motorola68k]Assembler,basicstyle=\ttfamily,keywordstyle=\color{blue}} + +\usepackage{shellesc} +\usepackage{adjustbox} + +\newsavebox{\asciigcn} + +% notes prefixed in pympress +\addtobeamertemplate{note page}{}{\thispdfpagelabel{notes:\insertframenumber}} +%theme used +\usetheme{Madrid} +%Information to be included in the title page: +\title[Computer Architecture] %optional +{Computer Architecture} + +\subtitle{Course no. 7 - Input/Output Systems} + +\author[Ștefan-Dan Ciocîrlan] % (optional, for multiple authors) +{} + +\institute[NUSTPB] % (optional) +{ + \inst{}% + National University of Science and Technology\\ + POLITEHNICA Bucharest +} + +\date[NUSTPB 2024] % (optional) +{Computer Architecture} + +\logo{ +\includegraphics[height=0.9cm]{../../media/LOGO_UNSTPB_en.png} +\includegraphics[height=0.9cm]{../../media/logoACSQ.jpeg} +} + + +% Roman numerals +\newcommand*{\rom}[1]{\expandafter\@slowromancap\romannumeral #1@} +%split +\usepackage{amsmath} +%colors +%\usepackage[usenames,dvipsnames]{color} %loaded by the dcoument class +%subfigure +\usepackage{subcaption} +% block over block uncover +\setbeamercovered{invisible} +%\setbeamercovered{transparent} + +%extra slide content +\AtBeginSection[] +{ + \begin{frame} + \frametitle{Content} + \tableofcontents[currentsection] + \end{frame} +} +%notes or not +%\setbeamertemplate{note page}[plain] + +\begin{document} + +\frame{\titlepage} + +\section{Overview of Input/Output Systems} +\input{intro.tex} + +\section{Type of data transfer} +\input{types.tex} + +\section{Implementation of I/O} +\input{implementation.tex} + +\section{UART} +\input{uart.tex} + + +\section{Q\&A} +\begin{frame} +\end{frame} + +%\begin{frame} +%\frametitle{Table of Contents} +%\tableofcontents +%\end{frame} + + +\end{document} \ No newline at end of file diff --git a/slides/courses/7/media/UART.png b/slides/courses/7/media/UART.png new file mode 100644 index 0000000000000000000000000000000000000000..7d2a1cb7e9838db6850fd19ff375d9eddd8ed458 GIT binary patch literal 55595 zcmbUIXIv9q_%#ZvD5wYsNN<85N|h!Zl#U1pN+%#7AiWbhD$+rui_)t|?r0zxKIQxbTGzR7LCl zryH-J!TBHVhXqpIH6_3I_yu`l{yjygb{==wBT&TsSo&u#DCABMjiNuU%W*nzLQuE^ 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Slide 2: Programmed I/O (Polling) +\begin{frame} + \frametitle{Programmed I/O (Polling)} + \begin{itemize} + \item \textbf{How it Works}: The CPU actively checks the I/O device's status register. + \item \textbf{Characteristics}: + \begin{itemize} + \item CPU performs data transfers directly. + \item CPU waits, consuming time, which may be inefficient. + \end{itemize} + \item \textbf{Best Used For}: Simple or low-throughput devices (e.g., keyboard). + \item \textbf{Drawbacks}: Inefficient for high-speed devices or systems needing high CPU availability. + \end{itemize} + \note{ + Every word transfer is done by the CPU. + The CPU is reading the status register cyclically. + + } +\end{frame} + +% Slide 3: Interrupt-Driven I/O +\begin{frame} + \frametitle{Interrupt-Driven I/O} + \begin{itemize} + \item \textbf{How it Works}: The I/O device sends an interrupt signal to the CPU when it’s ready to transfer data. + \item \textbf{Characteristics}: + \begin{itemize} + \item Reduces CPU waiting time. + \item I/O requests are handled via prioritized interrupts. + \end{itemize} + \item \textbf{Best Used For}: Situations requiring timely data handling, such as network interfaces. + \item \textbf{Drawbacks}: High interrupt rates can overwhelm the CPU. + \end{itemize} +\end{frame} + +% Slide 4.1: Direct Memory Access (DMA) +\begin{frame} + \frametitle{Direct Memory Access (DMA)} + \begin{itemize} + \item \textbf{How it Works}: A DMA controller handles data transfer between the I/O device and memory, bypassing the CPU. + \item \textbf{Characteristics}: + \begin{itemize} + \item Reduces CPU involvement in large data transfers. + \item Allows high-speed data transfers. + \end{itemize} + \item \textbf{Best Used For}: High-throughput devices needing large data block transfers (e.g., disk drives). + \item \textbf{Drawbacks}: Requires additional hardware (DMA controller). + \end{itemize} + \note{ + The CPU initiates the transfer, but the DMA controller handles the data transfer. + The CPU verify if the transfer is done. + } +\end{frame} + +\begin{frame} + \frametitle{CPU Tasks in DMA Transfer} + + \begin{enumerate} + \item \textbf{Configuring the DMA Controller} + \begin{itemize} + \item Set source and destination addresses in DMA registers. + \item Specify transfer length and define transfer mode: + \begin{itemize} + \item \textit{Burst Mode}: Transfers data in large chunks. CPU is blocked during transfer. + \item \textit{Cycle Stealing Mode}: Transfers in small chunks, shares bus with CPU. DMA has higher priority. + \item \textit{Transparent Mode}: Transfers data when CPU is not using the bus. + \end{itemize} + \item Set up DMA interrupt on transfer completion. + \end{itemize} + + \item \textbf{Initiating the DMA Transfer} + \begin{itemize} + \item Issue command to start the transfer, allowing DMA to handle data movement directly. + \end{itemize} + + \item \textbf{Handling DMA Interrupts} + \begin{itemize} + \item Process interrupt after transfer completes, update status, and prepare for further operations. + \end{itemize} + + \item \textbf{Error Handling and Recovery} + \begin{itemize} + \item If it gets an error interrupt, diagnose and initiate corrective actions. + \end{itemize} + \end{enumerate} +\end{frame} + +% Slide 5: Memory-Mapped I/O +\begin{frame} + \frametitle{Memory-Mapped I/O} + \begin{itemize} + \item \textbf{How it Works}: I/O devices are mapped into the same address space as the main memory. + \item \textbf{Characteristics}: + \begin{itemize} + \item Devices are accessed like memory addresses. + \item Simplifies the programming model. + \end{itemize} + \item \textbf{Best Used For}: Systems where unified memory and I/O accesses are beneficial, such as embedded systems. + \item \textbf{Drawbacks}: Potential for memory address conflicts. + \end{itemize} +\end{frame} + +% Slide 6: Channel I/O +\begin{frame} + \frametitle{Channel I/O} + \begin{itemize} + \item \textbf{How it Works}: Dedicated I/O processors, or "channels," handle complex I/O tasks independently. + \item \textbf{Characteristics}: + \begin{itemize} + \item Channels have their own instructions, allowing complex I/O without CPU involvement. + \item Common in mainframes. + \end{itemize} + \item \textbf{Best Used For}: High-performance systems handling many I/O requests, like mainframes. + \item \textbf{Drawbacks}: Additional hardware and complexity. + \end{itemize} +\end{frame} +% Slide 6.1: Channel I/O +\begin{frame} + \frametitle{Channel I/O Operation} + \begin{enumerate} + \item \textbf{Channel Program Setup} + \begin{itemize} + \item CPU prepares a channel program, specifying I/O operations and data transfer details. + \item Channel program is loaded into the channel's control memory. + \end{itemize} + + \item \textbf{Channel Program Execution} + \begin{itemize} + \item CPU initiates the channel program execution. + \item Channel processor executes the program, handling I/O operations independently. + \end{itemize} + + \item \textbf{Channel Program Completion} + \begin{itemize} + \item Channel processor signals the CPU when the program completes. + \item CPU processes the completion status and prepares for further operations. + \end{itemize} + \end{enumerate} +\end{frame} +% Slide 6.2: Channel I/O +\begin{frame} + \frametitle{Channel I/O vs. DMA} + \begin{itemize} + \item Can handle interupts and errors. (except fatal errors) + \item Can handle multiple I/O devices and multiple I/O operations at the same time. + \item Bus sharing is the same as DMA. + \end{itemize} +\end{frame} + +% Slide 7: Isolated I/O +\begin{frame} + \frametitle{Isolated I/O or Port-Mapped I/O} + \begin{itemize} + \item \textbf{How it Works}: Separate address space for I/O operations, accessed via specific I/O instructions. + \item \textbf{Characteristics}: + \begin{itemize} + \item Prevents conflicts between memory and I/O addresses. + \item Uses dedicated I/O instructions (e.g., IN and OUT in x86). + \end{itemize} + \item \textbf{Best Used For}: Systems with separate I/O instruction sets, such as x86 PCs. + \item \textbf{Drawbacks}: Adds complexity in CPU design. + \end{itemize} +\end{frame} + +% Slide 8: Co-Processor I/O +\begin{frame} + \frametitle{Co-Processor I/O} + \begin{enumerate} + \item \textbf{Dedicated I/O Processor} + \begin{itemize} + \item A co-processor (specialized processor) manages I/O operations independently. + \item Reduces the main CPU’s workload by handling data transfers and processing tasks. + \end{itemize} + + \item \textbf{Functionality and Complexity} + \begin{itemize} + \item The co-processor can handle complex I/O tasks, similar to Channel I/O. + \item It can perform operations such as data formatting, error checking, and signal processing. + \end{itemize} + + \item \textbf{CPU Involvement} + \begin{itemize} + \item The CPU is involved only in setup and initialization. + \item Once configured, the co-processor operates autonomously, reporting back on completion or errors. + \end{itemize} + + \item \textbf{Use Cases} + \begin{itemize} + \item Found in systems with high-performance needs, such as graphics processing units (GPUs) and digital signal processors (DSPs). + \item Common in tasks requiring substantial data processing, like multimedia, AI, and scientific computation. + \end{itemize} + \end{enumerate} +\end{frame} + +% Slide 9: Summary Table +\begin{frame}[fragile] + \frametitle{Summary of Data Transfer Methods} + \begin{table}[] + \centering + \resizebox{\textwidth}{!}{% + \begin{tabular}{|l|l|l|l|} + \hline + \textbf{Method} & \textbf{CPU Involvement} & \textbf{Best For} & \textbf{Examples} \\ + \hline + Programmed I/O & High & Simple devices & Keyboards, mice \\ + \hline + Interrupt-Driven & Moderate & Timely data handling & Network cards \\ + \hline + DMA & Low & High-throughput & Disk drives, GPUs \\ + \hline + Memory-Mapped I/O & Moderate & Unified memory-I/O & Embedded systems \\ + \hline + Channel I/O & Low & Complex I/O needs & Mainframes \\ + \hline + Port-Mapped & Moderate & Separate I/O instructions & x86 PCs \\ + \hline + Co-Processor & Very-Low & High-performance tasks & GPUs, DSPs \\ + \hline + \end{tabular}% + } + \end{table} +\end{frame} \ No newline at end of file diff --git a/slides/courses/7/uart.tex b/slides/courses/7/uart.tex new file mode 100644 index 0000000..5d95152 --- /dev/null +++ b/slides/courses/7/uart.tex @@ -0,0 +1,46 @@ + +\begin{frame} + \frametitle{Introduction to UART} + \begin{itemize} + \item Universal Asynchronous Receiver-Transmitter. + \item Hardware communication protocol. + \item Used for asynchronous serial communication. + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Setting Up UART} + \begin{itemize} + \item Two devices connected by TX and RX lines. + \item Voltage levels must match. (3.3 V, 5 V) + \item Baud rate must be agreed upon. (9600, 19200, 38400, 57600, and 115200) + \item Data format must be agreed upon. (8E1, 8 data bits, even parity, 1 stop bit) + \item Flow control: + \begin{itemize} + \item Hardware: RTS/CTS (Request to Send/Clear to Send) + \item Software: XON/XOFF (ASCII characters 0x11 and 0x13, ready to accept data as receiver) + \item No flow control + \end{itemize} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Format of UART Data} + \begin{figure} + \includegraphics[width=0.9\linewidth]{media/UART.png} + \caption{By EidenNor - Own work, CC BY-SA 4.0, https://commons.wikimedia.org/w/index.php?curid=118379174} + \end{figure} +\end{frame} + +\begin{frame} + \frametitle{Transmission of Data Bits} + \includegraphics[width=0.8\linewidth]{media/uart_timing.png} +\end{frame} + + +\begin{frame} + \frametitle{Exam Question} + Template: Having the X UART configuration, what is the maxim data rate that can be achieved? + + Example: Having the 3.3V 9600 baud rate 8E1 with no flow control UART configuration, what is the maxim data rate that can be achieved? +\end{frame} \ No newline at end of file diff --git a/slides/courses/8/implementation.tex b/slides/courses/8/implementation.tex new file mode 100644 index 0000000..330b876 --- /dev/null +++ b/slides/courses/8/implementation.tex @@ -0,0 +1,210 @@ +\begin{frame} + \frametitle{Implementation for Lab CPU} + \textbf{Type of interrupts:} + \begin{itemize} + \item Internal interrupts (non-maskable): + \begin{itemize} + \item ALU overflow + \item Software interrupt through the \texttt{INT} instruction + \end{itemize} + \item External non-maskable interrupts: + \begin{itemize} + \item Lack of Voltage (Power Off) + \item Special hardware line \texttt{cinm} + \end{itemize} + \item External maskable interrupts: + \begin{itemize} + \item 8 IO deivce interrupts + \item Special hardware line \texttt{cintr} for all. + \end{itemize} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Implementation of IVT} + \begin{table}[] + \resizebox{0.9\textwidth}{!}{% + \begin{tabular}{|c|c|c|} + \hline + \textbf{Address} & \textbf{Name} & \textbf{Type} \\ \hline + 0x0 & Reserved & \multirow{3}{*}{Internal Interrupt} \\ \cline{1-2} + 0x1 & Software Interrupt (INT) & \\ \cline{1-2} + 0x2 & ALU Overflow & \\ \hline + 0x3 & Lack of Voltage (Power Off) & External Non-Maskable Interrupt \\ \hline + 0x4 & Level 0 & \multirow{8}{*}{External Maskable Interrupt} \\ \cline{1-2} + 0x5 & Level 1 & \\ \cline{1-2} + 0x6 & Level 2 & \\ \cline{1-2} + 0x7 & Level 3 & \\ \cline{1-2} + 0x8 & Level 4 & \\ \cline{1-2} + 0x9 & Level 5 & \\ \cline{1-2} + 0xA & Level 6 & \\ \cline{1-2} + 0xB & Level 7 & \\ \hline + \end{tabular} + } + \end{table} + \note{ + } + +\end{frame} + +\begin{frame} + \frametitle{Interupt Instructions} + The FR (Flag Register) will have a new bit \texttt{I} which will be used to enable or disable interrupts. + The following instructions will be added: + \begin{itemize} + \item \texttt{EI} - Enable interrupts (sei) + \item \texttt{DI} - Disable interrupts (cli) + \item \texttt{INT} - Genrate software interrupt + \item \texttt{RETI} - Return from interrupt + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Architecture} + \begin{figure} + \centering + \includegraphics[width=0.8\textwidth]{media/isarchitecture.png} + \end{figure} +\end{frame} + +\begin{frame} + \frametitle{Architecture Signals} + \begin{itemize} + \item $ip$ - Software Interrupt + \item $id$ - ALU Overflow Interrupt + \item $inm$ - external non-maskable interrupt (comes from $cinm$) + \item $cintr_{i}$ - external maskable interrupt from device $i$ + \item $ai$ - external maskable interrupt active + \item $intr$ - external maskable interrupt request to CPU + \item $sie$/$cie$ - enable/disable external maskable interrupts + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Architecture Components} + \begin{itemize} + \item \texttt{REQINT} - Request external maskable interrupt register ($REQINT_{i} = 1$ means that the interrupt $i$ is requested) + \item \texttt{MEXTINT} - Maskable external interrupt register ($MEXTINT_{i} = 1$ means that the interrupt $i$ is masked) + \item \texttt{RUNINT} - Current running interrupts register ($RUNINT_{i} = 1$ means that the interrupt on level $i$ is running) + \item \texttt{Priorrity INT} - Compute if the current interrupt has higher priority than the current running interrupt + \item \texttt{INTADDR} - Compute the address of the ISR + \item \texttt{INTPC} - The address for the current ISR + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{External maskable interrupts Handling} + \begin{enumerate} + \item Verify for external maskable interrupt requests in the \texttt{REQINT} register. + \item If there is one, verify if external maskable interrupts are enabled. (flag \texttt{I} in FR) + \item If yes, filter the interrupts that are masked in the \texttt{MEXTINT} register. + \item Find the highest priority interrupt that is not masked. + \item Verify ff it has higher priority than the current running interrupts in the \texttt{RUNINT} register: + \item Send the interrupt to the CPU through the $intr$ signal. + \item Wait for the CPU to acknowledge the interrupt. ($ai$ signal) + \item Set the bit in the \texttt{RUNINT} register. + \item Clear the bit in the \texttt{REQINT} register. + \item Compute the address of the ISR and set the \texttt{INTPC} register. + \end{enumerate} +\end{frame} + +\begin{frame} + \frametitle{External non-maskable interrupts Handling} + \begin{enumerate} + \item Verify for external non-maskable interrupt requests in the \texttt{inm} signal. + \item Verify if there is no higher priority interrupt running. + \item Compute the address of the ISR and set the \texttt{INTPC} register. + \end{enumerate} +\end{frame} + +\begin{frame} + \frametitle{ALU Overflow Handling} + \begin{enumerate} + \item Verify for ALU overflow interrupt requests in the \texttt{id} signal. + \item Verify if there is no higher priority interrupt running. + \item Compute the address of the ISR and set the \texttt{INTPC} register. + \item Inside the ISR, the CPU must clear the overflow flag in the FR. + \end{enumerate} +\end{frame} + +\begin{frame} + \frametitle{Software interrupts Handling} + \begin{enumerate} + \item Verify for software interrupt requests in the \texttt{ip} signal. + \item There is no higher priority interrupt running. + \item Compute the address of the ISR and set the \texttt{INTPC} register. + \end{enumerate} +\end{frame} + +\begin{frame} + \frametitle{CPU acknowledge interrupts} + \begin{enumerate} + \item Save FR on the stack. + \item Disable external maskable interrupts. (\texttt{EI} can be used to enable them back inside ISR) + \item Save the current PC on the stack. + \item Run the jump instruction from the \texttt{INTPC} register address. + \end{enumerate} +\end{frame} + +\begin{frame} + \frametitle{Exam Questions} + Template: Having the following values in the registers at time 0, + interrupts requested with the time of the request and the type of the interrupt, + and how much time the CPU will take to handle every type of interrupt, + which is the order of the interrupts that will be handled by the CPU? +\end{frame} + + +\begin{frame} + \frametitle{Exam Questions} + \begin{table}[] + \begin{tabular}{|c|c|c|c|} + \hline + \texttt{REQINT} & \texttt{MEXTINT} & \texttt{RUNINT} & \texttt{FR} \\ \hline + 0x00 & 0x00 & 0x00 & 0x00 \\ \hline + \end{tabular} + \end{table} + + \begin{table}[] + \begin{tabular}{|c|c|c|c|} + \hline + Cycles from time 0 & Type of Request & Name \\ \hline + 10 & External Maskable Interupt Level 5 & A \\ \hline + 30 & External Maskable Interupt Level 3 & B \\ \hline + 50 & External Maskable Interupt Level 7 & C \\ \hline + 60 & External Maskable Interupt Level 1 & D \\ \hline + 100 & External Non-Maskable Interupt & E \\ \hline + 140 & ALU Overflow & F \\ \hline + 150 & Software Interupt & G \\ \hline + \end{tabular} + \end{table} +\end{frame} + + + +\begin{frame} + \frametitle{Exam Questions} + \begin{table} + \begin{tabular}{|c|c|c|c|} + \hline + Type of Request & Cycle to handle \\ \hline + External Maskable Interupt Level 0 & 30 \\ \hline + External Maskable Interupt Level 1 & 20 \\ \hline + External Maskable Interupt Level 2 & 10 \\ \hline + External Maskable Interupt Level 3 & 40 \\ \hline + External Maskable Interupt Level 4 & 20 \\ \hline + External Maskable Interupt Level 5 & 30 \\ \hline + External Maskable Interupt Level 6 & 10 \\ \hline + External Maskable Interupt Level 7 & 20 \\ \hline + External Non-Maskable Interupt & 5 \\ \hline + ALU Overflow & 10 \\ \hline + Software Interupt & 10 \\ \hline + \end{tabular} + \end{table} +\end{frame} + + + +\begin{frame} + \frametitle{Exam Questions} +\end{frame} \ No newline at end of file diff --git a/slides/courses/8/irqs.tex b/slides/courses/8/irqs.tex new file mode 100644 index 0000000..51ab82e --- /dev/null +++ b/slides/courses/8/irqs.tex @@ -0,0 +1,131 @@ + +\begin{frame} + \frametitle{Pooling Problems} + \begin{itemize} + \item It consumes a lot of CPU time + \item It is not efficient, because it depends on the pooling time + \begin{itemize} + \item If the pooling time is too short, the CPU will consume a lot of time + \item If the pooling time is too long, it delays the response time to the I/O devices + \end{itemize} + \item It is synchronous and it is nto a good solution for real-time systems (It is a need for an asynchronous solution) + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Interrupts Systems} + \begin{itemize} + \item Asyncrhonous system + \item Control and syncronize the asynchronous events in the system + \item \textbf{Definition:} An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention + \item \textbf{How it Works:} When a device needs service, it sends an interrupt signal. The CPU suspends its current task, processes the interrupt via an Interrupt Service Routine (ISR), and then resumes its previous work. + \item \textbf{Advantages:} + \begin{itemize} + \item \textbf{Efficiency:} The CPU only handles the device when it is needed, freeing it up for other tasks. + \item \textbf{Responsive System:} The system can quickly respond to time-sensitive events. + \item \textbf{Better Multitasking:} Interrupts enable systems to handle multiple tasks effectively without wasting CPU cycles. + \end{itemize} + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Types of Interrupts} + \begin{itemize} + \item \textbf{Hardware Interrupts:} Generated by hardware devices or CPU. + \item \textbf{Software Interrupts:} Generated by a program. + \item \textbf{Maskable Interrupts:} Can be disabled or enabled. + \item \textbf{Non-Maskable Interrupts:} Cannot be disabled. + \item \textbf{Internal Interrupts:} Generated by the CPU itself. + \item \textbf{External Interrupts:} Generated by external devices. + \end{itemize} +\end{frame} + +\begin{frame} + \frametitle{Interrupts Systems Concepts} + \begin{itemize} + \item Classes of Interrupts, depending on source of the interupt we have different levels of interrupts + \item Order of Priority, the CPU must know which interrupt to handle first + \item Identification of the Interrupt, the CPU must known the level of the interrupt and if present order of priority in that level. + \item Critical section of code where interupts are disabled. The interupts can be globally or specifically disabled. + \item A save and restore context of the CPU, the CPU must save the context of the current task and restore it after the interrupt is handled. + \item Comunication between the CPU and the I/O devices. + \item Time of the interrupt. It must be as short as possible. + \end{itemize} +\end{frame} + +% Slide 1: Overview of Interrupt Handling Mechanism +\begin{frame} + \frametitle{Interrupt Handling Mechanism: Overview} + \begin{itemize} + \item Interrupt Request (IRQ) Lines + \item Interrupt Vector Table (IVT) + \item Interrupt Service Routines (ISRs) + \item Prioritization and Nesting + \item Context Switching + \end{itemize} +\end{frame} + +% Slide 2: Interrupt Request (IRQ) Lines +\begin{frame} + \frametitle{Interrupt Request (IRQ) Lines} + + \begin{itemize} + \item \textbf{Definition}: IRQ lines are dedicated hardware lines used by I/O devices to signal the CPU. + \item \textbf{Functionality}: When a device needs attention, it sends an IRQ signal, alerting the CPU. + \item \textbf{CPU Response}: The CPU identifies the source of the interrupt and initiates the appropriate Interrupt Service Routine (ISR). + \end{itemize} +\end{frame} + +% Slide 3: Interrupt Vector Table (IVT) +\begin{frame} + \frametitle{Interrupt Vector Table (IVT)} + + \begin{itemize} + \item \textbf{Definition}: The IVT is a table in memory that holds jumps instruction to addresses of Interrupt Service Routines (ISRs). + \item \textbf{Purpose}: Provides a quick way to look up and execute the correct ISR based on the interrupt. + \item \textbf{Mechanism}: When an interrupt occurs, the CPU retrieves the ISR address from the IVT and jumps to that address to execute the instruction which starts the ISR. + \end{itemize} +\end{frame} + +% Slide 4: Interrupt Service Routine (ISR) +\begin{frame} + \frametitle{Interrupt Service Routine (ISR)} + + \begin{itemize} + \item \textbf{Definition}: An ISR is a special function that executes in response to an interrupt. + \item \textbf{Purpose}: Handles the specific task associated with the interrupt (e.g., data transfer, status update). + \item \textbf{Execution Flow}: + \begin{itemize} + \item usually disable interrupts at the beginning of the ISR. (cli) + \item Execute the ISR code. + \item last instruction of the ISR is a return from interrupt instruction. (reti) (enable interrupts) + \end{itemize} + \end{itemize} +\end{frame} + +% Slide 5: Prioritization and Nesting +\begin{frame} + \frametitle{Prioritization and Nesting} + + \begin{itemize} + \item \textbf{Prioritization}: High-priority interrupts can preempt lower-priority ones, allowing critical events to be addressed immediately. + \item \textbf{Nesting}: Allows multiple interrupts to be handled simultaneously, where an interrupt may trigger another. + \item \textbf{Benefits}: Enhances system responsiveness and ensures critical events are handled first. + \end{itemize} +\end{frame} + +% Slide 6: Context Switching +\begin{frame} + \frametitle{Context Switching in Interrupt Handling} + + \begin{itemize} + \item \textbf{Definition}: Saving the CPU's current state (registers, program counter) before handling an interrupt. + \item \textbf{Process}: + \begin{enumerate} + \item Save the context of the interrupted task. + \item Execute the ISR. + \item Restore the context after ISR completion. + \end{enumerate} + \item \textbf{Importance}: Ensures that the CPU resumes its previous task exactly where it left off. + \end{itemize} +\end{frame} \ No newline at end of file diff --git a/slides/courses/8/main.tex b/slides/courses/8/main.tex new file mode 100644 index 0000000..cf6a6d8 --- /dev/null +++ b/slides/courses/8/main.tex @@ -0,0 +1,113 @@ +%\documentclass[notes,usenames,dvipsnames]{beamer} +%\documentclass[notes]{beamer} % print frame + notes +%\documentclass[notes=only]{beamer} % only notes +\documentclass[usenames,dvipsnames]{beamer} % only frames +\usepackage[outputdir=out]{minted} +\usepackage{pgfpages} +%\setbeameroption{show notes on second screen} +%\setbeameroption{show notes} +%subfigures +\usepackage{caption} +\usepackage{subcaption} + +%tables packages +\usepackage{multirow} + +% math +\usepackage{amsmath} + +% bash command +\usepackage{graphicx} +\usepackage{listings} +% varbatim for ascii figures +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +%\usepackage{verbatim} +\usepackage{lipsum} % for context +\usepackage{fancyvrb} +\usepackage{varwidth} +\usepackage{circuitikz} +\ctikzset{logic ports=ieee} +\usepackage{listings} +% \lstset{language=[Motorola68k]Assembler,basicstyle=\ttfamily,keywordstyle=\color{blue}} + +\usepackage{shellesc} +\usepackage{adjustbox} + +\newsavebox{\asciigcn} + +% notes prefixed in pympress +\addtobeamertemplate{note page}{}{\thispdfpagelabel{notes:\insertframenumber}} +%theme used +\usetheme{Madrid} +%Information to be included in the title page: +\title[Computer Architecture] %optional +{Computer Architecture} + +\subtitle{Course no. 8 - Interupts Systems} + +\author[Ștefan-Dan Ciocîrlan] % (optional, for multiple authors) +{} + +\institute[NUSTPB] % (optional) +{ + \inst{}% + National University of Science and Technology\\ + POLITEHNICA Bucharest +} + +\date[NUSTPB 2024] % (optional) +{Computer Architecture} + +\logo{ +\includegraphics[height=0.9cm]{../../media/LOGO_UNSTPB_en.png} +\includegraphics[height=0.9cm]{../../media/logoACSQ.jpeg} +} + + +% Roman numerals +\newcommand*{\rom}[1]{\expandafter\@slowromancap\romannumeral #1@} +%split +\usepackage{amsmath} +%colors +%\usepackage[usenames,dvipsnames]{color} %loaded by the dcoument class +%subfigure +\usepackage{subcaption} +% block over block uncover +\setbeamercovered{invisible} +%\setbeamercovered{transparent} + +%extra slide content +\AtBeginSection[] +{ + \begin{frame} + \frametitle{Content} + \tableofcontents[currentsection] + \end{frame} +} +%notes or not +%\setbeamertemplate{note page}[plain] + +\begin{document} + +\frame{\titlepage} + +\section{Interupts Systems} +\input{irqs.tex} + +\section{Implementation} +\input{implementation.tex} + + + +\section{Q\&A} +\begin{frame} +\end{frame} + +%\begin{frame} +%\frametitle{Table of Contents} +%\tableofcontents +%\end{frame} + + +\end{document} \ No newline at end of file diff --git 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instructions. + \item Types of control units: + \begin{itemize} + \item \textbf{Unpipelined Hardwired Control Unit} (Von Neumann-style): Control signals generated directly by hardware. + \item \textbf{Microprogrammed Control Unit} (Wilkes-style): Control signals generated by stored microinstructions. + \item \textbf{Pipelined Hardwired Control Unit}: Adds pipeline stages for improved performance. + \end{itemize} + \item They aim to generate control signals, + but they differ in implementation and use cases. + \end{itemize} + \note{ + This slide introduces students to the idea that control units + play a critical role in CPU operation by generating the signals + needed for instruction execution. We'll examine the characteristics, + pros, and cons of two major types: unpipelined hardwired and microprogrammed units. + } +\end{frame} + +% Slide 2: Unpipelined Hardwired Control Unit +\begin{frame} + \frametitle{Unpipelined Hardwired Control Unit} + \begin{itemize} + \item \textbf{Control Signal Generation}: Based on combinational logic from instruction and status bits. + \item \textbf{Finite State Machine (FSM)}: Maps control signals to FSM states. + \item \textbf{Direct Control}: Instructions directly trigger specific control signals through hardware. + \end{itemize} + \note{ + Hardwired control units generate control signals through combinational circuits, + with each instruction mapped to specific signals. + This approach is faster but less adaptable, making it suitable for RISC. + Introducing the FSM concept here gives a high-level overview + of states corresponding to control signals. + } +\end{frame} + +% Slide 3: Advantages of Hardwired Control Units +\begin{frame} + \frametitle{Advantages of Hardwired Control Units} + \begin{itemize} + \item \textbf{Speed}: Faster execution due to direct signal generation. + \item \textbf{Simplicity for Simple ISAs}: Suitable for RISC, where a simpler instruction set matches well with hardwired control. + \item \textbf{Lower Latency}: Minimal delay since signals do not need to be fetched from memory. + \end{itemize} + \note{ + The speed of hardwired control units is a key advantage, + as control signals are generated without the memory fetch + delay seen in microprogrammed units. + This makes them ideal for simpler, RISC-based architectures, + which rely on rapid instruction processing. + } +\end{frame} + + +% Slide 4: Disadvantages of Hardwired Control Units +\begin{frame} + \frametitle{Disadvantages of Hardwired Control Units} + \begin{itemize} + \item \textbf{Inflexibility}: Modifications require hardware changes. + \item \textbf{Design Complexity}: Complex to design for extensive instruction sets, + such as CISC. + \end{itemize} + \note{ + Hardwired units lack flexibility; + hardware updates are needed to add new instructions. + This is particularly challenging for complex instruction set architectures, + where the breadth of instructions demands more intricate control circuitry. + } +\end{frame} + + +% Slide 5: Microprogrammed Control Unit +\begin{frame} + \frametitle{Microprogrammed Control Unit} + \begin{itemize} + \item \textbf{Control Signals}: Generated through a stored microprogram. + \item \textbf{Instruction}: Each machine instruction is broken into smaller steps called microinstructions. + \item \textbf{Micro-instructions $\mu I$}: Set of data and resource independent micro-operations that can be executed in one clock cycle. + \item \textbf{Micro-operations $\mu O$}: Control signals for the data flow in the processor. + \end{itemize} + \note{ + The microprogrammed control unit uses a microprogram—a sequence of microinstructions stored in + memory—to generate control signals. Each high-level instruction is implemented as + a series of micro-instructions. This unit is advantageous for handling complex + instructions because it's easier to update and modify through changes to the microprogram, + rather than requiring hardware changes. + } +\end{frame} + +% Slide 6: Microprogrammed Control Unit Components +\begin{frame}[fragile] + \frametitle{Microprogrammed Control Unit Components} + \begin{columns} + \column{0.5\textwidth} + \begin{figure} + \centering + \includegraphics[width=0.8\textwidth]{media/mpcuarchitecture.png} + \end{figure} + \column{0.5\textwidth} + \begin{itemize} + \item \textbf{Control Memory $CM$}: Stores the microprogram (microinstructions). + \item \textbf{Micro-Sequencer $\mu S$}: Fetches microinstructions from the control memory. + \item \textbf{Micro-instruction Register $\mu IR$}: Stores the current microinstruction. + \item \textbf{Micro-instruction Program Counter $\mu PC$}: Keeps track of the current microinstruction. + \end{itemize} + \end{columns} + \note{ + The microprogrammed control unit consists of several key components: + the control memory, micro-sequencer, micro-instruction register, + and micro-instruction program counter. + These components work together to fetch, store, and execute + the microinstructions that generate control signals. + } +\end{frame} + +% Slide 7: Advantages of Microprogrammed Control Units +\begin{frame} + \frametitle{Advantages of Microprogrammed Control Units} + \begin{itemize} + \item \textbf{Flexibility}: Easy to update; modifying control + logic only requires updating the microprogram. + \item \textbf{Simplicity}: Simplifies the design for CPUs + with complex instruction sets. + \item \textbf{Debugging}: Easier to debug because the logic is in the microcode. + \item \textbf{Instruction Set Expansion}: Allows for adding new instructions + \item \textbf{Less Hardware}: Requires less hardware than hardwired control units. + \item \textbf{Emulates diffrent ISAs}: Can emulate any ISA. + \end{itemize} + \note{ + Microprogrammed control units are especially valuable in complex instruction + set computers (CISC) due to their flexibility. + Updating microinstructions is easier than changing hardware, + which makes adding new instructions or optimizing existing ones simpler. + } +\end{frame} + +% Slide 7: Advantages of Microprogrammed Control Units +\begin{frame} + \frametitle{Advantages of Microprogrammed Control Units} + \begin{itemize} + \item \textbf{Flexibility}: Easily updated by changing the microprogram. + \item \textbf{Simplicity in Design}: Streamlines complex instruction set implementations. + \item \textbf{Debugging Ease}: Centralized control logic simplifies error detection. + \item \textbf{ISA Expansion}: Easily add new instructions. + \item \textbf{Hardware Minimization}: Requires less control-specific hardware. + \item \textbf{ISA Emulation}: Capable of emulating various instruction sets. + \end{itemize} + \note{ + Microprogrammed control units are highly flexible and easier to modify + than hardwired units. This is especially beneficial in complex instruction + set computers (CISC), where frequent updates are needed. Debugging is + also simplified as the control logic is within the microprogram. + } +\end{frame} + +% Slide 8: Disadvantages of Microprogrammed Control Units +\begin{frame} + \frametitle{Disadvantages of Microprogrammed Control Units} + \begin{itemize} + \item \textbf{Speed}: Slower than hardwired units due to microinstruction fetches. + \item \textbf{Memory Requirements}: Additional memory required for microprogram storage. + \end{itemize} + \note{ + The primary downside of microprogrammed control units is their slower + execution speed, as control signals must be fetched from memory. + There's also memory overhead, as the microprogram must be stored + separately from other data. + } +\end{frame} + +% Slide 9: Key Differences Between Control Units +\begin{frame}[fragile] + \frametitle{Key Differences Between Control Units} + \begin{table} + \resizebox{0.9\textwidth}{!}{% + \begin{tabular}{|c|c|c|c|} + \hline + \textbf{Feature} & \textbf{Unpipelined Hardwired} & \textbf{Microprogrammed} & \textbf{Pipelined Hardwired} \\ + \hline + Control Signal Generation & Combinational Logic & Microinstructions & Combinational Logic \\ + \hline + Flexibility & Low & High & Low \\ + \hline + Best For & RISC & CISC & RISC/CISC \\ + \hline + Memory Usage & No extra memory & Requires microprogram memory & Requires intermediate storage \\ + \hline + CPI & 1 & >1 & 1 \\ + \hline + Cycle Time & Longer & Shorter (sequential) & Short (parallel)\\ + \hline + \end{tabular} + } + \end{table} + \note{ + This summary table contrasts each type of control unit across factors like flexibility, + memory usage, and cycle time. Pipelined hardwired units, + though similar to unpipelined ones in logic, can achieve lower cycle times + due to parallelism. + } +\end{frame} \ No newline at end of file diff --git a/slides/courses/9/implementation.tex b/slides/courses/9/implementation.tex new file mode 100644 index 0000000..5efbe33 --- /dev/null +++ b/slides/courses/9/implementation.tex @@ -0,0 +1,115 @@ + + +% Slide: Dependency on Main Memory +\begin{frame} + \frametitle{Dependency on Main Memory} + \begin{itemize} + \item \textbf{Independent Control Memory}: Separate memory specifically for microinstructions, allowing fast access. + \item \textbf{Shared Control Memory}: Microinstructions share space with main memory, creating possible contention. + \item \textbf{Cached Control Memory}: Microinstructions are cached from main memory, improving access speed with fewer memory calls. + \end{itemize} + \note{ + This slide discusses the organizational impact of where control memory is stored. + Each structure offers trade-offs between speed and design complexity. + For example, independent memory provides high-speed access, + whereas shared memory may lead to access delays. + } +\end{frame} + +% Slide: Control Memory Organization +\begin{frame} + \frametitle{Control Memory Organization} + \begin{itemize} + \item \textbf{Word-Addressed}: Each address points to a single microinstruction. + \item \textbf{Page-Addressed}: Each address points to a set of microinstructions in different pages (e.g., branching or subroutine instructions). + \item \textbf{Block-Addressed}: Each address points to a block of related microinstructions, reducing fetches for grouped operations. + \item \textbf{Divided Memory}: Unique microinstructions stored separately; control memory holds references. + \item \textbf{Two-Level Memory}: Microinstructions point to nano-instructions, which further specify control signals. + \end{itemize} + \note{ + Different control memory organizations allow trade-offs in memory usage and control complexity. + Page and block organization allow faster execution for sequences of instructions, + while divided and two-level organizations reduce redundancy and can handle complex microoperations. + } +\end{frame} + +\begin{frame} + \frametitle{Micro-instruction Format} + \textbf{Constraints:} + \begin{itemize} + \item Parallelism between micro-operations. + \item Control signals for the data flow. + \item Felixibility for future expansion. + \item Micro-instruction size. + \end{itemize} +\end{frame} + +% Slide: Micro-instruction Format +\begin{frame} + \frametitle{Micro-instruction Format} + \textbf{Key Considerations:} + \begin{itemize} + \item \textbf{Parallelism}: Allow simultaneous execution of multiple micro-operations. + \item \textbf{Control Signal Flexibility}: Supports data flow, branch control, and additional operations for the underlying hardware. + \item \textbf{Future Expansion}: Design accommodates new instructions or signals. + \item \textbf{Micro-instruction Size}: Optimizes between memory usage and instruction capability. + \end{itemize} + \note{ + Micro-instruction format impacts CPU performance and expandability. + Parallelism and control signal flexibility are critical for efficient data flow, + while expandability ensures the design remains adaptable for future updates. + } +\end{frame} + +% Slide: Types of Micro-instruction Coding +\begin{frame} + \frametitle{Types of Micro-instruction Coding} + \begin{itemize} + \item \textbf{Horizontal Coding}: Each bit represents a micro-operation, enabling high parallelism. + \item \textbf{Vertical Coding}: Each micro-instruction represents a single micro-operation. + \item \textbf{Minimal Coding}: Fields group compatible micro-operations (horizontal and vertical coding combined). + \item \textbf{Residual Coding}: Micro-operations are in control registers, modified by microinstructions. + \item \textbf{Address Coding}: Each micro-instruction is an refference for a unique micro-operation in a separate memory. + \item \textbf{Mixed Coding}: Combines field-based micro-operations with address-based sequential steps. + \end{itemize} + \note{ + Each coding type offers different levels of flexibility and memory efficiency. + For example, horizontal coding is suited for CPUs needing high parallelism, + while address and residual coding enable efficient memory use by referencing existing control registers or memory locations. + Mixed coding - First part of the micro-instruction + is form of fields which contains coded micro-operations. The second + part is an address to the next microinstruction. + } +\end{frame} + +% Slide: Execution of Micro-instructions +\begin{frame} + \frametitle{Execution of Micro-instructions} + Each micro-instruction is executed in two stages: fetch and execute. + \begin{itemize} + \item \textbf{Sequential Execution}: Microinstructions execute in a fixed order, ideal for simple instruction flow. + \item \textbf{Parallel Execution}: The next microinstruction is fetched while the current one executes, improving throughput. + \item \textbf{Sequential-Parallel Execution}: Instructions run in parallel except for branches, balancing speed with control complexity. + \end{itemize} + \note{ + This slide introduces students to different execution models for micro-instructions. + Sequential-parallel execution is a common optimization, + allowing multiple instructions to run simultaneously while handling branches independently. + } +\end{frame} + +% Slide: Phases of Micro-instruction Execution +\begin{frame} + \frametitle{Phases of Micro-instruction Execution} + \begin{itemize} + \item \textbf{Mono-phase Execution}: All micro-operations run in a single phase. + \item \textbf{Poly-phase Execution}: Micro-operations execute across different phases, allowing complex singals sequencing. + \end{itemize} + \textbf{Cycle Time}: Execution can have fixed or variable cycle times depending on the micro-instruction complexity. + \note{ + Mono-phase and poly-phase executions highlight flexibility in instruction handling. + Mono-phase is simpler but less versatile than poly-phase, + which can handle more intricate operations at the cost of increased cycle time variability. + } +\end{frame} + diff --git a/slides/courses/9/main.tex b/slides/courses/9/main.tex new file mode 100644 index 0000000..c1c5de2 --- /dev/null +++ b/slides/courses/9/main.tex @@ -0,0 +1,116 @@ +%\documentclass[notes,usenames,dvipsnames]{beamer} +%\documentclass[notes]{beamer} % print frame + notes +%\documentclass[notes=only]{beamer} % only notes +\documentclass[usenames,dvipsnames]{beamer} % only frames +\usepackage[outputdir=out]{minted} +\usepackage{pgfpages} +%\setbeameroption{show notes on second screen} +%\setbeameroption{show notes} +%subfigures +\usepackage{caption} +\usepackage{subcaption} + +%tables packages +\usepackage{multirow} + +% math +\usepackage{amsmath} + +% bash command +\usepackage{graphicx} +\usepackage{listings} +% varbatim for ascii figures +\usepackage[T1]{fontenc} +\usepackage[utf8]{inputenc} +%\usepackage{verbatim} +\usepackage{lipsum} % for context +\usepackage{fancyvrb} +\usepackage{varwidth} +\usepackage{circuitikz} +\ctikzset{logic ports=ieee} +\usepackage{listings} +% \lstset{language=[Motorola68k]Assembler,basicstyle=\ttfamily,keywordstyle=\color{blue}} + +\usepackage{shellesc} +\usepackage{adjustbox} + +\newsavebox{\asciigcn} + +% notes prefixed in pympress +\addtobeamertemplate{note page}{}{\thispdfpagelabel{notes:\insertframenumber}} +%theme used +\usetheme{Madrid} +%Information to be included in the title page: +\title[Computer Architecture] %optional +{Computer Architecture} + +\subtitle{Course no. 9 - Microcoded CPU} + +\author[Ștefan-Dan Ciocîrlan] % (optional, for multiple authors) +{} + +\institute[NUSTPB] % (optional) +{ + \inst{}% + National University of Science and Technology\\ + POLITEHNICA Bucharest +} + +\date[NUSTPB 2024] % (optional) +{Computer Architecture} + +\logo{ +\includegraphics[height=0.9cm]{../../media/LOGO_UNSTPB_en.png} +\includegraphics[height=0.9cm]{../../media/logoACSQ.jpeg} +} + + +% Roman numerals +\newcommand*{\rom}[1]{\expandafter\@slowromancap\romannumeral #1@} +%split +\usepackage{amsmath} +%colors +%\usepackage[usenames,dvipsnames]{color} %loaded by the dcoument class +%subfigure +\usepackage{subcaption} +% block over block uncover +\setbeamercovered{invisible} +%\setbeamercovered{transparent} + +%extra slide content +\AtBeginSection[] +{ + \begin{frame} + \frametitle{Content} + \tableofcontents[currentsection] + \end{frame} +} +%notes or not +%\setbeamertemplate{note page}[plain] + +\begin{document} + +\frame{\titlepage} + +\section{Microcoded Concepts} +\input{basic.tex} + +\section{Implementation} +\input{implementation.tex} + +\section{Minimal microinstruction coding} +\input{minimal.tex} + + + +\section{Q\&A} +\begin{frame} +\end{frame} + +%\begin{frame} +%\frametitle{Table of Contents} +%\tableofcontents +%\end{frame} + + +\end{document} \ No newline at end of file diff --git a/slides/courses/9/media/mpcuarchitecture.drawio b/slides/courses/9/media/mpcuarchitecture.drawio new file mode 100644 index 0000000..10ae216 --- /dev/null +++ b/slides/courses/9/media/mpcuarchitecture.drawio @@ -0,0 +1,85 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/slides/courses/9/media/mpcuarchitecture.png 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