dump-pipeline.vcd

$date
	Sun Jun  4 12:45:04 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module testbench $end
$scope module dut $end
$var wire 32 ! gpr_write_data_from_stage_writeback [31:0] $end
$var wire 1 " reset $end
$var wire 1 # system_clock $end
$var wire 1 $ write_enable $end
$var wire 1 % zero_output_stage_memory $end
$var wire 1 & zero_output $end
$var wire 5 ' temporary_register_stage_execution [4:0] $end
$var wire 5 ( temporary_register [4:0] $end
$var wire 5 ) source_register_stage_execution [4:0] $end
$var wire 5 * source_register [4:0] $end
$var wire 1 + shift_upper $end
$var wire 1 , register_write_stage_writeback $end
$var wire 1 - register_write_stage_memory $end
$var wire 1 . register_write_stage_execution $end
$var wire 1 / register_write $end
$var wire 1 0 register_destination_stage_execution $end
$var wire 1 1 register_destination $end
$var wire 32 2 program_counter_plus4_stage_decode [31:0] $end
$var wire 32 3 program_counter_plus4 [31:0] $end
$var wire 32 4 program_counter [31:0] $end
$var wire 6 5 opcode [5:0] $end
$var wire 1 6 memory_write_stage_memory $end
$var wire 1 7 memory_write_stage_execution $end
$var wire 1 8 memory_write $end
$var wire 1 9 memory_to_register_stage_writeback $end
$var wire 1 : memory_to_register_stage_memory $end
$var wire 1 ; memory_to_register_stage_execution $end
$var wire 1 < memory_to_register $end
$var wire 1 = memory_read_stage_execution $end
$var wire 1 > memory_read $end
$var wire 1 ? jump_stage_memory $end
$var wire 1 @ jump_stage_execution $end
$var wire 32 A jump_address_stage_memory [31:0] $end
$var wire 32 B jump_address_stage_execution [31:0] $end
$var wire 32 C jump_address [31:0] $end
$var wire 1 D jump $end
$var wire 32 E instruction_stage_decode [31:0] $end
$var wire 32 F instruction [31:0] $end
$var wire 16 G immediate [15:0] $end
$var wire 32 H gpr_write_data [31:0] $end
$var wire 5 I gpr_write_address_stage_writeback [4:0] $end
$var wire 5 J gpr_write_address_stage_memory [4:0] $end
$var wire 5 K gpr_write_address_stage_execution [4:0] $end
$var wire 5 L gpr_write_address [4:0] $end
$var wire 32 M gpr_data_out_2_stage_memory [31:0] $end
$var wire 32 N gpr_data_out_2_stage_execution [31:0] $end
$var wire 32 O gpr_data_out_2 [31:0] $end
$var wire 32 P gpr_data_out_1_stage_execution [31:0] $end
$var wire 32 Q gpr_data_out_1 [31:0] $end
$var wire 6 R function_code_stage_execution [5:0] $end
$var wire 6 S function_code [5:0] $end
$var wire 32 T extended_immediate_stage_execution [31:0] $end
$var wire 32 U extended_immediate [31:0] $end
$var wire 5 V destination_register_stage_execution [4:0] $end
$var wire 5 W destination_register [4:0] $end
$var wire 32 X data_memory_out_stage_writeback [31:0] $end
$var wire 32 Y data_memory_out [31:0] $end
$var wire 1 Z branch_ne $end
$var wire 1 [ branch_eq_stage_memory $end
$var wire 1 \ branch_eq_stage_execution $end
$var wire 1 ] branch_eq $end
$var wire 32 ^ branch_address_stage_memory [31:0] $end
$var wire 32 _ branch_address_stage_execution [31:0] $end
$var wire 32 ` branch_address [31:0] $end
$var wire 1 a alu_source_stage_execution $end
$var wire 1 b alu_source $end
$var wire 32 c alu_result_stage_writeback [31:0] $end
$var wire 32 d alu_result_stage_memory [31:0] $end
$var wire 32 e alu_result [31:0] $end
$var wire 2 f alu_opcode_stage_execution [1:0] $end
$var wire 2 g alu_opcode [1:0] $end
$var wire 4 h alu_control_signal [3:0] $end
$var reg 1 i flush_stage_decode $end
$var reg 1 j flush_stage_execution $end
$var reg 1 k flush_stage_fetch $end
$var reg 2 l forward_a [1:0] $end
$var reg 2 m forward_b [1:0] $end
$var reg 32 n forward_data1_stage_execution [31:0] $end
$var reg 32 o forward_data2_stage_execution [31:0] $end
$var reg 1 p should_branch $end
$var reg 1 q stall_stage_ifid $end
$scope module ALU $end
$var wire 32 r operand_a [31:0] $end
$var wire 32 s operand_b [31:0] $end
$var wire 1 & zero_output $end
$var wire 32 t subtraction_output [31:0] $end
$var wire 1 u overflow_subtraction $end
$var wire 1 v overflow_signal $end
$var wire 1 w overflow_addition $end
$var wire 1 x less_than_signal $end
$var wire 4 y control_input [3:0] $end
$var wire 32 z addition_output [31:0] $end
$var reg 32 { result_output [31:0] $end
$upscope $end
$scope module ALUC $end
$var wire 2 | alu_operation [1:0] $end
$var wire 6 } function_code [5:0] $end
$var reg 4 ~ alu_control_signal [3:0] $end
$var reg 4 !" alu_opcode [3:0] $end
$upscope $end
$scope module GPR $end
$var wire 5 "" read_address_1 [4:0] $end
$var wire 5 #" read_address_2 [4:0] $end
$var wire 1 # system_clock $end
$var wire 5 $" write_address [4:0] $end
$var wire 32 %" write_data [31:0] $end
$var wire 1 , write_enable $end
$var wire 32 &" read_data_2 [31:0] $end
$var wire 32 '" read_data_1 [31:0] $end
$var integer 32 (" i [31:0] $end
$scope begin register[0] $end
$var wire 32 )" registers_ [31:0] $end
$upscope $end
$scope begin register[1] $end
$var wire 32 *" registers_ [31:0] $end
$upscope $end
$scope begin register[2] $end
$var wire 32 +" registers_ [31:0] $end
$upscope $end
$scope begin register[3] $end
$var wire 32 ," registers_ [31:0] $end
$upscope $end
$scope begin register[4] $end
$var wire 32 -" registers_ [31:0] $end
$upscope $end
$scope begin register[5] $end
$var wire 32 ." registers_ [31:0] $end
$upscope $end
$scope begin register[6] $end
$var wire 32 /" registers_ [31:0] $end
$upscope $end
$scope begin register[7] $end
$var wire 32 0" registers_ [31:0] $end
$upscope $end
$scope begin register[8] $end
$var wire 32 1" registers_ [31:0] $end
$upscope $end
$scope begin register[9] $end
$var wire 32 2" registers_ [31:0] $end
$upscope $end
$scope begin register[10] $end
$var wire 32 3" registers_ [31:0] $end
$upscope $end
$scope begin register[11] $end
$var wire 32 4" registers_ [31:0] $end
$upscope $end
$scope begin register[12] $end
$var wire 32 5" registers_ [31:0] $end
$upscope $end
$scope begin register[13] $end
$var wire 32 6" registers_ [31:0] $end
$upscope $end
$scope begin register[14] $end
$var wire 32 7" registers_ [31:0] $end
$upscope $end
$scope begin register[15] $end
$var wire 32 8" registers_ [31:0] $end
$upscope $end
$scope begin register[16] $end
$var wire 32 9" registers_ [31:0] $end
$upscope $end
$scope begin register[17] $end
$var wire 32 :" registers_ [31:0] $end
$upscope $end
$scope begin register[18] $end
$var wire 32 ;" registers_ [31:0] $end
$upscope $end
$scope begin register[19] $end
$var wire 32 <" registers_ [31:0] $end
$upscope $end
$scope begin register[20] $end
$var wire 32 =" registers_ [31:0] $end
$upscope $end
$scope begin register[21] $end
$var wire 32 >" registers_ [31:0] $end
$upscope $end
$scope begin register[22] $end
$var wire 32 ?" registers_ [31:0] $end
$upscope $end
$scope begin register[23] $end
$var wire 32 @" registers_ [31:0] $end
$upscope $end
$scope begin register[24] $end
$var wire 32 A" registers_ [31:0] $end
$upscope $end
$scope begin register[25] $end
$var wire 32 B" registers_ [31:0] $end
$upscope $end
$scope begin register[26] $end
$var wire 32 C" registers_ [31:0] $end
$upscope $end
$scope begin register[27] $end
$var wire 32 D" registers_ [31:0] $end
$upscope $end
$scope begin register[28] $end
$var wire 32 E" registers_ [31:0] $end
$upscope $end
$scope begin register[29] $end
$var wire 32 F" registers_ [31:0] $end
$upscope $end
$scope begin register[30] $end
$var wire 32 G" registers_ [31:0] $end
$upscope $end
$scope begin register[31] $end
$var wire 32 H" registers_ [31:0] $end
$upscope $end
$upscope $end
$scope module IDU $end
$var wire 6 I" opcode [5:0] $end
$var reg 2 J" alu_opcode [1:0] $end
$var reg 1 b alu_source $end
$var reg 1 ] branch_eq $end
$var reg 1 Z branch_ne $end
$var reg 1 D jump $end
$var reg 1 > memory_read $end
$var reg 1 < memory_to_register $end
$var reg 1 8 memory_write $end
$var reg 1 1 register_destination $end
$var reg 1 / register_write $end
$var reg 1 + shift_upper $end
$upscope $end
$scope module IFU $end
$var wire 1 p branch $end
$var wire 32 K" branch_address [31:0] $end
$var wire 32 L" instruction [31:0] $end
$var wire 1 ? jump $end
$var wire 32 M" jump_address [31:0] $end
$var wire 1 " reset $end
$var wire 1 q stall_stage_ifid $end
$var wire 1 # system_clock $end
$var wire 10 N" memory_index [9:0] $end
$var wire 32 O" memory_data_out [31:0] $end
$var reg 32 P" program_counter [31:0] $end
$scope module memory $end
$var wire 10 Q" address [9:0] $end
$var wire 32 R" data_out [31:0] $end
$var wire 1 # system_clock $end
$var integer 32 S" i [31:0] $end
$upscope $end
$upscope $end
$scope module decoded_ex_mem_latch $end
$var wire 1 T" hold $end
$var wire 3 U" input_signal [2:0] $end
$var wire 1 i reset $end
$var wire 1 # system_clock $end
$var reg 3 V" output_signal [2:0] $end
$upscope $end
$scope module ex_mem_latch $end
$var wire 1 W" hold $end
$var wire 135 X" input_signal [134:0] $end
$var wire 1 j reset $end
$var wire 1 # system_clock $end
$var reg 135 Y" output_signal [134:0] $end
$upscope $end
$scope module id_ex_latch $end
$var wire 1 q hold $end
$var wire 124 Z" input_signal [123:0] $end
$var wire 1 i reset $end
$var wire 1 # system_clock $end
$var reg 124 [" output_signal [123:0] $end
$upscope $end
$scope module if_id_latch $end
$var wire 1 q hold $end
$var wire 64 \" input_signal [63:0] $end
$var wire 1 k reset $end
$var wire 1 # system_clock $end
$var reg 64 ]" output_signal [63:0] $end
$upscope $end
$scope module jump_branch_latch $end
$var wire 1 ^" hold $end
$var wire 67 _" input_signal [66:0] $end
$var wire 1 i reset $end
$var wire 1 # system_clock $end
$var reg 67 `" output_signal [66:0] $end
$upscope $end
$scope module mem_wb_latch $end
$var wire 1 a" hold $end
$var wire 71 b" input_signal [70:0] $end
$var wire 1 c" reset $end
$var wire 1 # system_clock $end
$var reg 71 d" output_signal [70:0] $end
$upscope $end
$scope module memory $end
$var wire 32 e" address [31:0] $end
$var wire 32 f" read_data [31:0] $end
$var wire 1 # system_clock $end
$var wire 32 g" write_data [31:0] $end
$var wire 1 6 write_enable $end
$upscope $end
$scope module rs_latch $end
$var wire 1 q hold $end
$var wire 5 h" input_signal [4:0] $end
$var wire 1 i" reset $end
$var wire 1 # system_clock $end
$var reg 5 j" output_signal [4:0] $end
$upscope $end
$scope module sign_extension $end
$var wire 1 k" extension_type $end
$var wire 16 l" immediate [15:0] $end
$var wire 32 m" extended_value [31:0] $end
$upscope $end
$scope module zero_latch $end
$var wire 1 n" hold $end
$var wire 1 & input_signal $end
$var wire 1 o" reset $end
$var wire 1 # system_clock $end
$var reg 1 % output_signal $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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bx00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx _"
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b10000110100000000110000000010010011 \"
bx ["
bx Z"
bx Y"
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bx V"
bx U"
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b10000000000 S"
b110100000000110000000010010011 R"
b0 Q"
b0 P"
b110100000000110000000010010011 O"
b0 N"
bx M"
b110100000000110000000010010011 L"
bx K"
bx J"
bx I"
b0 H"
b0 G"
b0 F"
b0 E"
b0 D"
b0 C"
b0 B"
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b0 @"
b0 ?"
b0 >"
b0 ="
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b0 9"
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b0 2"
b0 1"
b0 0"
b0 /"
b0 ."
b0 -"
b0 ,"
b0 +"
b0 *"
b0 )"
b100000 ("
bx '"
bx &"
bx %"
bx $"
bx #"
bx ""
bx !"
bx ~
bx }
bx |
bx {
bx z
bx y
xx
xw
xv
xu
bx t
bx s
bx r
xq
xp
bx o
bx n
bx m
bx l
xk
xj
xi
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bx f
bx e
bx d
bx c
xb
xa
bx `
bx _
bx ^
x]
x\
x[
xZ
bx Y
bx X
bx W
bx V
bx U
bx T
bx S
bx R
bx Q
bx P
bx O
bx N
bx M
bx L
bx K
bx J
bx I
bx H
bx G
b110100000000110000000010010011 F
bx E
xD
bx00 C
bx B
bx A
x@
x?
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x=
x<
x;
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x9
x8
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bx 5
b0 4
b100 3
bx 2
x1
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bx *
bx )
bx (
bx '
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bx !
$end
#5
b10010111 `
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08
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b0 g
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0q
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b0 O
b0 &"
b11 L
b10010011 U
b10010011 m"
b1101 5
b1101 I"
b10011 S
b0 *
b0 ""
b0 h"
b11 (
b11 #"
b1001000010011000000000000000000000000000000000000000000000000000000000000000000011000000001100000000000000000000000010010011 Z"
b0 W
b10010011 G
b10010011 l"
b110000000010010011000000000000000000000000000100101110 _"
b11000000001001001100 C
b110100000001100000000010101110 F
b110100000001100000000010101110 L"
b110100000001100000000010101110 O"
b110100000001100000000010101110 R"
b1 N"
b1 Q"
b110100000000110000000010010011 E
b100 2
bx00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx X"
bx00 B
b100000110100000001100000000010101110 \"
b1000 3
b100 4
b100 P"
b10000110100000000110000000010010011 ]"
bx00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx `"
0j
0i
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1#
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0#
#15
0&
b10010011 e
b10010011 {
b0 m
b0 l
0v
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1u
b110 L
b10101110 U
b10101110 m"
b0 o
b11111111111111111111111101101101 t
b10010011 z
b0 n
b0 r
b110 !"
b10 h
b10 y
b10 ~
b10010011 s
b101110 S
b1001000101110000000000000000000000000000000000000000000000000000000000000000000110000000011000000000000000000000000010101110 Z"
b110 (
b110 #"
b10101110 G
b10101110 l"
b110000000001010111000 C
bx00 A
bx00 M"
b10010011 T
b11 K
b0 V
b11 '
b0 N
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b10011 R
b10011 }
b0 f
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b11000000001001001100 B
b100100110000000000000000000000000000000000011000000000000011000000001001001100000000000000000000000000010010111 X"
0@
b110100000001100000000010101110 E
b1100000000010101110000000000000000000000000000101101100 _"
b10110110 `
b1000 2
b11001100100000000100001 F
b11001100100000000100001 L"
b11001100100000000100001 O"
b11001100100000000100001 R"
b10 N"
b10 Q"
bx00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Y"
b1001000010011000000000000000000000000000000000000000000000000000000000000000000011000000001100000000000000000000000010010011 ["
b0 )
b0 j"
b110000000010010011000000000000000000000000000100101110 `"
b100000110100000001100000000010101110 ]"
b110000000000011001100100000000100001 \"
b1100 3
b1000 4
b1000 P"
1#
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b1000 L
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b10101110 e
b10101110 {
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b100000000100001 U
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b0 5
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b100001 S
b11 *
b11 ""
b11 h"
b1000110100001000000000000000000000000000000000000000000000000000000000000000000110010000100000000000000000000100000000100001 Z"
b1000 W
b100000000100001 G
b100000000100001 l"
b1100110010000000010000100 C
b11111111111111111111111101010010 t
b10101110 z
b10101110 s
b10 !"
b11001100100100000100011 F
b11001100100100000100011 L"
b11001100100100000100011 O"
b11001100100100000100011 R"
b11 N"
b11 Q"
b11001100100000000100001 E
b11001100100000000100001000000000000000000001000000001011010 _"
b100000000101101 `
b1100 2
b10110110 _
b110000000001010111000 B
b10101110 T
b101011100000000000000000000000000000000000110000000000000110000000001010111000000000000000000000000000010110110 X"
b110 K
b110 '
b101110 R
b101110 }
b10010111 ^
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b11000000001001001100 M"
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1-
b1000000000000011001100100100000100011 \"
b10000 3
b1100 4
b1100 P"
b110000000000011001100100000000100001 ]"
b1100000000010101110000000000000000000000000000101101100 `"
b1001000101110000000000000000000000000000000000000000000000000000000000000000000110000000011000000000000000000000000010101110 ["
0%
b100100110000000000000000000000000000000000011000000000000011000000001001001100000000000000000000000000010010111 Y"
b100 V"
1#
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b10101110 o
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b1 m
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b10010011 !
b10010011 %"
b10010011 H
b10010011 t
b10010011 z
b0 s
b100011 S
b1000110100011000000000000000000000000000000000000000000000000000000000000000000110010010100100000000000000000100100000100011 Z"
b1001 W
b100100000100011 G
b100100000100011 l"
b1100110010010000010001100 C
b11 I
b11 $"
b10010011 c
09
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b10110110 ^
b10110110 K"
b110000000001010111000 A
b110000000001010111000 M"
b110 J
b10xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000001010111000110 b"
b10101110 d
b10101110 e"
b100000000100001 T
b1000 K
b1000 V
b100001 R
b100001 }
b10 f
b10 |
10
0a
b100000000101101 _
b100100110000000000000000000000001010111001000000000001100110010000000010000100000000000000000000100000000101101 X"
b1100110010000000010000100 B
b11001100100100000100011 E
b11001100100100000100011000000000000000000001001000001100110 _"
b100100000110011 `
b10000 2
b1001010100000000000100001 F
b1001010100000000000100001 L"
b1001010100000000000100001 O"
b1001010100000000000100001 R"
b100 N"
b100 Q"
b10xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000001001001100011 d"
b101011100000000000000000000000000000000000110000000000000110000000001010111000000000000000000000000000010110110 Y"
b1000110100001000000000000000000000000000000000000000000000000000000000000000000110010000100000000000000000000100000000100001 ["
b11 )
b11 j"
b11001100100000000100001000000000000000000001000000001011010 `"
b1000000000000011001100100100000100011 ]"
b1010000000001001010100000000000100001 \"
b10100 3
b10000 4
b10000 P"
1#
#40
0#
#45
1&
b0 e
b0 {
b10 m
b0 l
b0 L
b100001 U
b100001 m"
b110 h
b110 y
b110 ~
b100001 S
b1001 *
b1001 ""
b1001 h"
b1010 (
b1010 #"
b0 W
b100001 G
b100001 l"
b100101010000000000010000100 C
b110 !"
b0 t
b0 z
b0 n
b0 r
b10101110 o
b10101110 !
b10101110 %"
b10101110 H
b10101100000010010000000000010000 F
b10101100000010010000000000010000 L"
b10101100000010010000000000010000 O"
b10101100000010010000000000010000 R"
b101 N"
b101 Q"
b1001010100000000000100001 E
b1001010100000000000100001000000000000000000000000000001101010 _"
b110101 `
b10100 2
b1000110100001000000000000000000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000100001 Z"
b0 Q
b0 '"
b100100000110011 _
b1100110010010000010001100 B
b100100000100011 T
b1010111001001000000001100110010010000010001100000000000000000000100100000110011 X"
b1001 K
b1001 V
b100011 R
b100011 }
b100000000101101 ^
b100000000101101 K"
b1100110010000000010000100 A
b1100110010000000010000100 M"
b1000 J
b10101110 M
b10101110 g"
b10xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000001001001101000 b"
b10010011 d
b10010011 e"
b110 I
b110 $"
b10101110 c
b1100010101100000010010000000000010000 \"
b11000 3
b10100 4
b10100 P"
b1010000000001001010100000000000100001 ]"
b10010011 ,"
b11001100100100000100011000000000000000000001001000001100110 `"
b1000110100011000000000000000000000000000000000000000000000000000000000000000000110010010100100000000000000000100100000100011 ["
b100100110000000000000000000000001010111001000000000001100110010000000010000100000000000000000000100000000101101 Y"
b10xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000001010111000110 d"
1#
#50
0#
#55
0/
1b
b0 g
b0 J"
18
b0 m
b1 l
b0 o
b10 h
b10 y
b10 ~
b10000 U
b10000 m"
b10010011 !
b10010011 %"
b10010011 H
b10 !"
b101011 5
b101011 I"
b10000 S
b0 *
b0 ""
b0 h"
b11100010000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000010000 Z"
b1001 (
b1001 #"
b10000 G
b10000 l"
b1001000000000001000000 C
b1000 I
b1000 $"
b10010011 c
b100100000110011 ^
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