From 0a6c1822d16d114733b84efac539d65b3f449fbc Mon Sep 17 00:00:00 2001 From: qinjun-li Date: Tue, 3 Sep 2024 13:38:34 +0800 Subject: [PATCH 1/2] [rocketv] Supplement vector related csr modification. --- rocketv/src/CSR.scala | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/rocketv/src/CSR.scala b/rocketv/src/CSR.scala index 41ef748a2..e6b8715c8 100644 --- a/rocketv/src/CSR.scala +++ b/rocketv/src/CSR.scala @@ -1701,17 +1701,20 @@ class CSR(val parameter: CSRParameter) val newVType = Mux1H( Seq( (vsetvli || vsetivli) -> io.inst(0)(27, 20), - vsetvl -> io.wbRegRS2.get(7, 0) + vsetvl -> io.wbRegRS2.get ) ) + val newTypMSBValid: Bool = (newVType >> 8).asUInt.orR // todo: xLen -> vector.elen - val vlmulIllList = - Seq(0.U, 1.U, 2.U, 3.U) ++ Option.when(xLen >= 16)(7.U) ++ Option.when(xLen >= 32)(6.U) ++ Option.when( - xLen >= 64 - )(5.U) + val vlmulIllList = Seq(0.U, 1.U, 2.U, 3.U) ++ Option.when(xLen >= 16)(7.U) ++ + Option.when(xLen >= 32)(6.U) ++ Option.when(xLen >= 64)(5.U) val vlmulIll: Bool = vlmulIllList.map(_ === newVType(2, 0)).reduce(_ || _) + val vSewIllList = Seq(0.U) ++ Option.when(xLen >= 16)(1.U) ++ + Option.when(xLen >= 32)(2.U) ++ Option.when(xLen >= 64)(3.U) + val vsewIll = vSewIllList.map(_ === newVType(5, 3)).reduce(_ || _) + val vsetIll = vlmulIll && !newTypMSBValid && vsewIll // vlmax = vlen * lmul / sew - val vlmax: UInt = (true.B << (log2Ceil(vLen) - 6) << (newVType(2, 0) + 3.U) >> newVType(5, 3)).asUInt + val vlmax: UInt = (true.B << (log2Ceil(vLen) - 6) << (newVType(2, 0) + 3.U) >> newVType(5, 3)).asUInt // set vl val setVL = Mux1H( Seq( @@ -1721,9 +1724,9 @@ class CSR(val parameter: CSRParameter) vsetivli -> io.inst(0)(19, 15) ) ) - setVlReadData := Mux(io.retire(0) && io.vectorCsr.getOrElse(false.B) && vlmulIll, setVL, 0.U) + setVlReadData := Mux(io.retire(0) && io.vectorCsr.getOrElse(false.B) && vsetIll, setVL, 0.U) when(io.retire(0) && io.vectorCsr.get) { - when(vlmulIll) { + when(vsetIll) { vector.get.states("vl") := setVL vector.get.states("vlmul") := newVType(2, 0) vector.get.states("vsew") := newVType(5, 3) @@ -1744,6 +1747,9 @@ class CSR(val parameter: CSRParameter) when(decoded_addr(CSRs.vxrm)) { vector.get.states("vxrm") := wdata } + when(decoded_addr(CSRs.vxsat)) { + vector.get.states("vxsat") := wdata + } when(decoded_addr(CSRs.vcsr)) { vector.get.states("vxrm") := wdata(2, 1) vector.get.states("vxsat") := wdata(0) From da079ecef68b64b352da144835f2997038ca5b10 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Wed, 4 Sep 2024 14:24:04 +0800 Subject: [PATCH 2/2] [script] copy daidir for vcs-emu-trace Signed-off-by: Avimitin --- script/emu/src/Main.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/script/emu/src/Main.scala b/script/emu/src/Main.scala index 1f15325da..850935771 100644 --- a/script/emu/src/Main.scala +++ b/script/emu/src/Main.scala @@ -242,6 +242,16 @@ object Main: ) ) ) + + if finalEmuType.get == "vcs-emu-trace" then + val libPath = emulator / os.up / os.up / "lib" + val daidirPath = + os.walk(libPath) + .filter(path => os.isDir(path)) + .filter(path => path.segments.toSeq.last.endsWith(".daidir")) + .last + os.copy.into(daidirPath, outputPath, followLinks = true) + Logger.info(s"Output saved under ${outputPath}") end run