From 5fc316a9d0b7f360d293850eec3035ded8461aa2 Mon Sep 17 00:00:00 2001 From: Avimitin Date: Mon, 19 Aug 2024 14:41:31 +0800 Subject: [PATCH] [env] remove sequencer-vector ENV should be maintained in downstream project. Signed-off-by: Avimitin --- env/sequencer-vector/link.ld | 14 --- env/sequencer-vector/riscv_test.h | 156 -------------------------- macros/sequencer-vector/test_macros.h | 24 ---- 3 files changed, 194 deletions(-) delete mode 100644 env/sequencer-vector/link.ld delete mode 100644 env/sequencer-vector/riscv_test.h delete mode 100644 macros/sequencer-vector/test_macros.h diff --git a/env/sequencer-vector/link.ld b/env/sequencer-vector/link.ld deleted file mode 100644 index daf534e..0000000 --- a/env/sequencer-vector/link.ld +++ /dev/null @@ -1,14 +0,0 @@ -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -SECTIONS -{ - . = 0x1000; - .text.init : { *(.text.init) } - . = ALIGN(0x1000); - .text : { *(.text) } - . = ALIGN(0x1000); - .data : { *(.data) } - .bss : { *(.bss) } - _end = .; -} diff --git a/env/sequencer-vector/riscv_test.h b/env/sequencer-vector/riscv_test.h deleted file mode 100644 index fa8d9e1..0000000 --- a/env/sequencer-vector/riscv_test.h +++ /dev/null @@ -1,156 +0,0 @@ -// See LICENSE for license details. - -#ifndef _ENV_PHYSICAL_SINGLE_CORE_H -#define _ENV_PHYSICAL_SINGLE_CORE_H - -#include "../encoding.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64UV \ - .macro init; \ - RVTEST_VECTOR_ENABLE; \ - .endm - -#define RVTEST_RV32UV \ - .macro init; \ - RVTEST_VECTOR_ENABLE; \ - .endm - -#define INIT_XREG \ - li x1, 0; \ - li x2, 0; \ - li x3, 0; \ - li x4, 0; \ - li x5, 0; \ - li x6, 0; \ - li x7, 0; \ - li x8, 0; \ - li x9, 0; \ - li x10, 0; \ - li x11, 0; \ - li x12, 0; \ - li x13, 0; \ - li x14, 0; \ - li x15, 0; \ - li x16, 0; \ - li x17, 0; \ - li x18, 0; \ - li x19, 0; \ - li x20, 0; \ - li x21, 0; \ - li x22, 0; \ - li x23, 0; \ - li x24, 0; \ - li x25, 0; \ - li x26, 0; \ - li x27, 0; \ - li x28, 0; \ - li x29, 0; \ - li x30, 0; \ - li x31, 0; - -#define INIT_PMP \ - la t0, 1f; \ - csrw mtvec, t0; \ - /* Set up a PMP to permit all accesses */ \ - li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \ - csrw pmpaddr0, t0; \ - li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ - csrw pmpcfg0, t0; \ - .align 2; \ -1: - -#define INIT_SATP \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi satp, 0; \ - .align 2; \ -1: - -#define DELEGATE_NO_TRAPS \ - csrwi mie, 0; \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi medeleg, 0; \ - csrwi mideleg, 0; \ - .align 2; \ -1: - -#define RVTEST_ENABLE_SUPERVISOR \ - li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ - csrs mstatus, a0; \ - li a0, SIP_SSIP | SIP_STIP; \ - csrs mideleg, a0; \ - -#define RVTEST_ENABLE_MACHINE \ - li a0, MSTATUS_MPP; \ - csrs mstatus, a0; \ - -#define RVTEST_FP_ENABLE \ - li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ - csrs mstatus, a0; \ - csrwi fcsr, 0 - -#define RVTEST_VECTOR_ENABLE \ - li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ - (MSTATUS_FS & (MSTATUS_FS >> 1)); \ - csrs mstatus, a0; \ - csrwi fcsr, 0; \ - csrwi vcsr, 0; - -#define RISCV_MULTICORE_DISABLE \ - csrr a0, mhartid; \ - 1: bnez a0, 1b - -#define EXTRA_TVEC_USER -#define EXTRA_TVEC_MACHINE -#define EXTRA_INIT -#define EXTRA_INIT_TIMER - -#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ - -#define RVTEST_CODE_BEGIN \ - .section .text.init; \ - .align 6; \ - .weak stvec_handler; \ - .weak mtvec_handler; \ - .globl _start; \ -_start: \ - /* reset vector */ \ - j reset_vector; \ - .align 2; \ -reset_vector: \ - INIT_XREG; \ - RISCV_MULTICORE_DISABLE; \ - init; \ - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -// Write our custom CSR msimend to exit simulation. -#define RVTEST_CODE_END csrwi 0x7cc, 0 - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#define RVTEST_PASS -#define RVTEST_FAIL - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN \ - EXTRA_DATA \ - .align 4; .global begin_signature; begin_signature: - -#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: - -#endif diff --git a/macros/sequencer-vector/test_macros.h b/macros/sequencer-vector/test_macros.h deleted file mode 100644 index d69dd9d..0000000 --- a/macros/sequencer-vector/test_macros.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef __TEST_MACROS_SCALAR_H -#define __TEST_MACROS_SCALAR_H - - -#----------------------------------------------------------------------- -# Helper macros -#----------------------------------------------------------------------- - -#define TEST_CASE( testnum, testreg, correctval, code... ) - -#----------------------------------------------------------------------- -# Pass and fail code (assumes test num is in TESTNUM) -#----------------------------------------------------------------------- - -#define TEST_PASSFAIL - - -#----------------------------------------------------------------------- -# Test data section -#----------------------------------------------------------------------- - -#define TEST_DATA - -#endif \ No newline at end of file