diff --git a/Makefrag b/Makefrag
index b6f3b9a..925c1fd 100644
--- a/Makefrag
+++ b/Makefrag
@@ -215,6 +215,12 @@ tests = \
   vasubu_vx-9 \
   vbrev8_v-0 \
   vbrev_v-0 \
+  vclmul_vv-0 \
+  vclmul_vx-0 \
+  vclmul_vx-1 \
+  vclmulh_vv-0 \
+  vclmulh_vx-0 \
+  vclmulh_vx-1 \
   vclz_v-0 \
   vcompress_vm-0 \
   vcpop_m-0 \
diff --git a/generator/insn_vdvs2rs1vm.go b/generator/insn_vdvs2rs1vm.go
index 39b1993..0bceab9 100644
--- a/generator/insn_vdvs2rs1vm.go
+++ b/generator/insn_vdvs2rs1vm.go
@@ -9,12 +9,14 @@ import (
 func (i *Insn) genCodeVdVs2Rs1Vm(pos int) []string {
 	vdWidening := strings.HasPrefix(i.Name, "vw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wx")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(vdWidening || vs2Widening, allSEWs[:len(allSEWs)-1], allSEWs)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),
diff --git a/generator/insn_vdvs2vs1vm.go b/generator/insn_vdvs2vs1vm.go
index 5f65162..904b5b3 100644
--- a/generator/insn_vdvs2vs1vm.go
+++ b/generator/insn_vdvs2vs1vm.go
@@ -8,6 +8,7 @@ import (
 
 func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 	float := strings.HasPrefix(i.Name, "vf") || strings.HasPrefix(i.Name, "vmf")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdWidening := strings.HasPrefix(i.Name, "vw") || strings.HasPrefix(i.Name, "vfw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wv")
 	vdSize := iff(vdWidening, 2, 1)
@@ -15,8 +16,9 @@ func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 
 	sews := iff(float, floatSEWs, allSEWs)
 	sews = iff(vdWidening || vs2Widening, sews[:len(sews)-1], sews)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),