From 58d29bf86c1a19d2b9e7b3fbff9e1dc9f2799214 Mon Sep 17 00:00:00 2001
From: Basil Hussain <basilhussain@users.noreply.github.com>
Date: Fri, 22 Nov 2024 20:54:49 +0000
Subject: [PATCH 1/2] Add support for CH32V002/004/005/006/007

---
 devices/0x21-CH32V00x.yaml | 68 +++++++++++++++++++++++++++++++++-----
 1 file changed, 60 insertions(+), 8 deletions(-)

diff --git a/devices/0x21-CH32V00x.yaml b/devices/0x21-CH32V00x.yaml
index e785e0d..cc327d5 100644
--- a/devices/0x21-CH32V00x.yaml
+++ b/devices/0x21-CH32V00x.yaml
@@ -5,9 +5,9 @@ device_type: 0x21
 support_net: false
 support_usb: false
 support_serial: true
-description: CH32V00x (RISC-V2A) Series
+description: CH32V00x (RISC-V2A/V2C) Series
 config_registers:
-  # Ref: section "16.5 User Option Bytes" of RM manual
+  # Ref: section 16.5 (CH32V003) & 18.5 (CH32V00x) "User Option Bytes" of RM manual
   - offset: 0x00
     name: RDPR_USER
     description: RDPR, nRDPR, USER, nUSER
@@ -16,7 +16,7 @@ config_registers:
     fields:
       - bit_range: [7, 0]
         name: RDPR
-        description: Read Protection. 0xA5 for unprotected, otherwise read-protected (ignoring WRP)
+        description: Read Protection. 0xA5 for unprotected, otherwise read-protected (ignoring WRPR)
         explaination:
           0xa5: Unprotected
           _: Protected
@@ -58,7 +58,9 @@ config_registers:
         name: DATA1
   - offset: 0x08
     name: WRPR
-    # Each bit is used to control the write-protect status of 1 sector (1K bytes/sector)
+    # Each bit is used to control the write-protect status of sectors as follows:
+    #   CH32V003: 1 sector (1K/sector), max 16K (WRPR3/4 reserved)
+    #   CH32V002/004/005/006/007: 2 sectors (1K/sector), max 64K
     description: Flash memory write protection status
     type: u32
     reset: 0xFFFFFFFF
@@ -66,16 +68,66 @@ config_registers:
       0xFFFFFFFF: Unprotected
       _: Some 1K sections are protected
 variants:
+  - name: CH32V002A4M6
+    chip_id: 0x22
+    flash_size: 16K
+  - name: CH32V002D4U6
+    chip_id: 0x23
+    flash_size: 16K
+  - name: CH32V002F4P6
+    chip_id: 0x20
+    flash_size: 16K
+  - name: CH32V002F4U6
+    chip_id: 0x21
+    flash_size: 16K
+  - name: CH32V002J4M6
+    chip_id: 0x24
+    flash_size: 16K
+  - name: CH32V003A4M6
+    chip_id: 0x32
+    flash_size: 16K
   - name: CH32V003F4P6
     chip_id: 0x30
     flash_size: 16K
   - name: CH32V003F4U6
     chip_id: 0x31
     flash_size: 16K
-  - name: CH32V003A4M6
-    chip_id: 0x32
-    flash_size: 16K
   - name: CH32V003J4M6
     chip_id: 0x33
     flash_size: 16K
-  # TODO: add CH32V002, 004 & 006 - chip IDs unknown at present
+  - name: CH32V004F6P1
+    chip_id: 0x40
+    flash_size: 32K
+  - name: CH32V004F6U1
+    chip_id: 0x41
+    flash_size: 32K
+  - name: CH32V005D6U6
+    chip_id: 0x53
+    flash_size: 32K
+  - name: CH32V005E6R6
+    chip_id: 0x50
+    flash_size: 32K
+  - name: CH32V005F6P6
+    chip_id: 0x52
+    flash_size: 32K
+  - name: CH32V005F6U6
+    chip_id: 0x51
+    flash_size: 32K
+  - name: CH32V006E8R6
+    chip_id: 0x61
+    flash_size: 62K
+  - name: CH32V006F8P6
+    chip_id: 0x63
+    flash_size: 62K
+  - name: CH32V006F8U6
+    chip_id: 0x62
+    flash_size: 62K
+  - name: CH32V006K8U6
+    chip_id: 0x60
+    flash_size: 62K
+  - name: CH32V007E8R6
+    chip_id: 0x71
+    flash_size: 62K
+  - name: CH32V007K8U6
+    chip_id: 0x72
+    flash_size: 62K

From f87e430a074b1e56cd22cd155268607d304b947b Mon Sep 17 00:00:00 2001
From: Basil Hussain <basilhussain@users.noreply.github.com>
Date: Fri, 22 Nov 2024 21:29:10 +0000
Subject: [PATCH 2/2] Add support for CH32M007

---
 devices/0x21-CH32V00x.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/devices/0x21-CH32V00x.yaml b/devices/0x21-CH32V00x.yaml
index cc327d5..4aa9a65 100644
--- a/devices/0x21-CH32V00x.yaml
+++ b/devices/0x21-CH32V00x.yaml
@@ -131,3 +131,7 @@ variants:
   - name: CH32V007K8U6
     chip_id: 0x72
     flash_size: 62K
+  - name: CH32M007G8R6
+    chip_id: 0x70
+    flash_size: 62K
+  # TODO: add CH32M007E8R6, CH32M007E8U6 when chip IDs known.