diff --git a/build.zig b/build.zig index 109b812fe..be62c168a 100644 --- a/build.zig +++ b/build.zig @@ -28,6 +28,7 @@ const DriverClass = struct { const Clock = enum { meson, + imx, }; const I2cHost = enum { @@ -227,6 +228,14 @@ fn addClockDriver( }; driver.addCSourceFiles(.{ .files = files }); }, + .imx => { + const files: []const []const u8 = &.{ + "drivers/clk/imx/clk.c", + "drivers/clk/imx/clk-imx.c", + "drivers/clk/imx/clk-imx8mq.c", + }; + driver.addCSourceFiles(.{ .files = files }); + }, } const common_src_files = .{ "clk-operations.c" }; @@ -457,7 +466,7 @@ pub fn build(b: *std.Build) void { const clk_config = b.addSystemCommand(&.{ "python", - b.fmt("drivers/clk/{s}/create_clk_config.py", .{ class.name }), + "drivers/clk/create_clk_config.py", dtb_path, clk_conf_include_option, }); // Creates a system command which runs the python interpreter diff --git a/drivers/clk/meson/create_clk_config.py b/drivers/clk/create_clk_config.py similarity index 91% rename from drivers/clk/meson/create_clk_config.py rename to drivers/clk/create_clk_config.py index 34b0ad016..f1255ccec 100644 --- a/drivers/clk/meson/create_clk_config.py +++ b/drivers/clk/create_clk_config.py @@ -2,15 +2,13 @@ # Copyright 2024, UNSW # SPDX-License-Identifier: BSD-2-Clause -# -# The template is stolen from Bill's pinmux driver import os import sys from typing import List from devicetree import edtlib, dtlib -supported_compat_str_board = { "hardkernel,odroid-c4" } +supported_compat_str_board = { "hardkernel,odroid-c4", "fsl,imx8mm-evk", "fsl,imx8mq" } debug_parser = True clock_list = {} @@ -67,7 +65,8 @@ def extract_clocks(dt: dtlib.DT, node: dtlib.Node) -> List: for clk_id in clock_ids: add_clock(clk_id, 0, 0) for pnode in pnodes: - extract_clocks(dt, pnode) + if pnode != node: + extract_clocks(dt, pnode) if "max-frequency" in props: max_frequency = node.props["max-frequency"].to_nums() @@ -79,7 +78,8 @@ def extract_clocks(dt: dtlib.DT, node: dtlib.Node) -> List: if (clk_rate): add_clock(clk_id, clk_rate, 0) for pnode in pnodes: - extract_clocks(dt, pnode) + if pnode != node: + extract_clocks(dt, pnode) if "assigned-clocks" in props and "assigned-clock-parents" in props: assigned_clocks, pnodes = parse_clock_list(devicetree, node.props["assigned-clocks"].to_nums()) @@ -88,11 +88,11 @@ def extract_clocks(dt: dtlib.DT, node: dtlib.Node) -> List: if (pclk_id): add_clock(clk_id, 0, pclk_id) for pnode in pnodes: - extract_clocks(dt, pnode) + if pnode != node: + extract_clocks(dt, pnode) for pnode in ppnodes: - extract_clocks(dt, pnode) - - return enabled_clks + if pnode != node: + extract_clocks(dt, pnode) def write_configs_to_headerfile(path: str) -> None: with open(path + '/clk_config.h', "w") as f: @@ -106,6 +106,7 @@ def write_configs_to_headerfile(path: str) -> None: f.write("static struct clk_cfg clk_configs[] = {{\n{}\n}};".format(",\n".join(clk_cfg_strs))) if __name__ == "__main__": + supported = False devicetree = dtlib.DT(sys.argv[1], force=True) for compat_str in devicetree.root.props["compatible"].to_strings(): if compat_str in supported_compat_str_board: @@ -116,7 +117,6 @@ def write_configs_to_headerfile(path: str) -> None: log_error_parser("this board is not supported.") exit(1) - enabled_clks = [] for node in devicetree.node_iter(): props = list(node.props.keys()) diff --git a/drivers/clk/imx/clk-imx.c b/drivers/clk/imx/clk-imx.c new file mode 100644 index 000000000..09d69acfd --- /dev/null +++ b/drivers/clk/imx/clk-imx.c @@ -0,0 +1,283 @@ +#include +#include +#include + +#define PLL_FRAC_DENOM 0x1000000 + +static int clk_gate2_enable(struct clk *clk) +{ + struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); + + return regmap_update_bits(clk->base, data->offset, data->bit_idx, 2, 0x3); +} + +static int clk_gate2_disable(struct clk *clk) +{ + struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); + + return regmap_update_bits(clk->base, data->offset, data->bit_idx, 2, 0); +} + +static int clk_gate2_is_enabled(struct clk *clk) +{ + struct clk_gate_data *data = (struct clk_gate_data *)(clk->data); + + if (regmap_read_bits(clk->base, data->offset, data->bit_idx, 2) == 0x3) + return 1; + + return 0; +} + +const struct clk_ops clk_gate2_ops = { + .enable = clk_gate2_enable, + .disable = clk_gate2_disable, + /* .disable_unused = clk_gate2_disable_unused, */ + .is_enabled = clk_gate2_is_enabled, +}; + +static unsigned long clk_pll_recalc_rate(const struct clk *clk, + unsigned long prate) +{ + /* TODO: This function is derived from Linux codebase, but seems wrong + * according to the datasheet as PLL_REFCLK_DIV_VAL[5:10] is never used. */ + struct clk_frac_pll_data *data = (struct clk_frac_pll_data *)(clk->data); + uint64_t temp_rate = prate; + uint64_t rate; + + /* Output Divider value is (n + 1) * 2 */ + uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, 0, 5); + output_div_val = (output_div_val + 1 ) * 2; + + /* Valid Frac Divider value is 1 to 2^24 */ + uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, 24); + + /* Valid Int Divider value is 1 to 32 */ + uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, 7); + + temp_rate *= prate; + temp_rate *= frac_div_val; + do_div(temp_rate, PLL_FRAC_DENOM); + do_div(temp_rate, output_div_val); + + /* Frac Divider value is (n) */ + rate = prate * 8 * (int_div_val + 1); + do_div(rate, output_div_val); + rate += temp_rate; + + return rate; +} + +const struct clk_ops clk_frac_pll_ops = { + /* .prepare = clk_pll_prepare, */ + /* .unprepare = clk_pll_unprepare, */ + /* .is_prepared = clk_pll_is_prepared, */ + .recalc_rate = clk_pll_recalc_rate, + /* .round_rate = clk_pll_round_rate, */ + /* .set_rate = clk_pll_set_rate, */ +}; + +static unsigned long clk_sscg_pll_recalc_rate(const struct clk *clk, + unsigned long prate) +{ + struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data); + uint64_t temp_rate = prate; + + uint32_t divr1 = regmap_read_bits(clk->base, data->offset + 0x8, 25, 3); + uint32_t divr2 = regmap_read_bits(clk->base, data->offset + 0x8, 19, 6); + uint32_t divf1 = regmap_read_bits(clk->base, data->offset + 0x8, 13, 6); + uint32_t divf2 = regmap_read_bits(clk->base, data->offset + 0x8, 7, 6); + uint32_t divq = regmap_read_bits(clk->base, data->offset + 0x8, 1, 6); + + if (regmap_read_bits(clk->base, data->offset, 4, 1)) { + temp_rate = prate; + } else if (regmap_read_bits(clk->base, data->offset, 5, 1)) { + temp_rate *= divf2; + do_div(temp_rate, (divr2 + 1) * (divq + 1)); + } else { + temp_rate *= 2; + temp_rate *= (divf1 + 1) * (divf2 + 1); + do_div(temp_rate, (divr1 + 1) * (divr2 + 1) * (divq + 1)); + } + + return 0; +} + +static uint8_t clk_sscg_pll_get_parent(const struct clk *clk) +{ + struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data); + uint8_t ret = 0; + + if (regmap_read_bits(clk->base, data->offset, 4, 1)) { + ret = data->bypass2; + } else if (regmap_read_bits(clk->base, data->offset, 5, 1)) { + ret = data->bypass1; + } + + return ret; +} + +static int clk_sscg_pll_set_parent(struct clk *clk, uint8_t index) +{ + /* struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data); */ + + /* TODO: This operation is based on `setup.bypass` instead of index passed from callee */ + + return 0; +} + +const struct clk_ops clk_sscg_pll_ops = { + /* .prepare = clk_sscg_pll_prepare, */ + /* .unprepare = clk_sscg_pll_unprepare, */ + /* .is_prepared = clk_sscg_pll_is_prepared, */ + .recalc_rate = clk_sscg_pll_recalc_rate, + /* .set_rate = clk_sscg_pll_set_rate, */ + .set_parent = clk_sscg_pll_set_parent, + .get_parent = clk_sscg_pll_get_parent, + /* .determine_rate = clk_sscg_pll_determine_rate, */ +}; + +static unsigned long imx8m_clk_core_slice_recalc_rate(const struct clk *clk, + unsigned long prate) +{ + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); + + uint32_t div_val = regmap_read_bits(clk->base, data->offset, data->div_shift, data->div_width); + /* Divider value is n+1 */ + return DIV_ROUND_UP_ULL((uint64_t)prate, div_val + 1); +} + +static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk) +{ + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); + + uint32_t num_parents = clk->hw.init->num_parents; + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); + + if (val >= num_parents) + return -1; + + return val; +} + +static int imx8m_clk_core_slice_set_parent(struct clk *clk, uint8_t index) +{ + struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data); + + /* + * write twice to make sure non-target interface + * SEL_A/B point the same clk input. + */ + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + + return 0; +} + +const struct clk_ops clk_core_slice_ops = { + .recalc_rate = imx8m_clk_core_slice_recalc_rate, + /* .round_rate = imx8m_clk_core_slice_round_rate, */ + /* .set_rate = imx8m_clk_core_slice_set_rate, */ + /* .determine_rate = imx8m_clk_core_slice_determine_rate, */ + .get_parent = imx8m_clk_core_slice_get_parent, + .set_parent = imx8m_clk_core_slice_set_parent, +}; + +static unsigned long imx8m_clk_common_slice_recalc_rate(const struct clk *clk, + unsigned long prate) +{ + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); + + uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); + /* Divider value is n+1 */ + unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); + + uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width); + /* Divider value is n+1 */ + return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); +} + +static uint8_t imx8m_clk_common_slice_get_parent(const struct clk *clk) +{ + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); + + uint32_t num_parents = clk->hw.init->num_parents; + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); + + if (val >= num_parents) + return -1; + + return val; +} + +static int imx8m_clk_common_slice_set_parent(struct clk *clk, uint8_t index) +{ + struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data); + + /* + * write twice to make sure non-target interface + * SEL_A/B point the same clk input. + */ + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + + return 0; +} + +const struct clk_ops clk_common_slice_ops = { + .recalc_rate = imx8m_clk_common_slice_recalc_rate, + /* .round_rate = imx8m_clk_common_slice_round_rate, */ + /* .set_rate = imx8m_clk_common_slice_set_rate, */ + /* .determine_rate = imx8m_clk_common_slice_determine_rate, */ + .get_parent = imx8m_clk_common_slice_get_parent, + .set_parent = imx8m_clk_common_slice_set_parent, +}; + +static unsigned long imx8m_clk_bus_slice_recalc_rate(const struct clk *clk, + unsigned long prate) +{ + struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); + + uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width); + /* Divider value is n+1 */ + unsigned long prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1); + + uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width); + /* Divider value is n+1 */ + return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1); +} + +static uint8_t imx8m_clk_bus_slice_get_parent(const struct clk *clk) +{ + struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); + + uint32_t num_parents = clk->hw.init->num_parents; + uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask); + + if (val >= num_parents) + return -1; + + return val; +} + +static int imx8m_clk_bus_slice_set_parent(struct clk *clk, uint8_t index) +{ + struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data); + + /* + * write twice to make sure non-target interface + * SEL_A/B point the same clk input. + */ + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index); + + return 0; +} + +const struct clk_ops clk_bus_slice_ops = { + .recalc_rate = imx8m_clk_bus_slice_recalc_rate, + /* .round_rate = imx8m_clk_composite_divider_round_rate, */ + /* .set_rate = imx8m_clk_composite_divider_set_rate, */ + /* .determine_rate = imx8m_divider_determine_rate, */ + .get_parent = imx8m_clk_bus_slice_get_parent, + .set_parent = imx8m_clk_bus_slice_set_parent, +}; diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c new file mode 100644 index 000000000..059c51b43 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mq.c @@ -0,0 +1,1518 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017-2018 NXP. + * + * Derived from: https://github.com/torvalds/linux/blob/75b607fab38d149f232f01eae5e6392b394dd659/drivers/clk/imx/clk-imx8mm.c + */ + +#include +#include +#include +#include +#include +#include +#include + + +static struct clk_parent_data pll_ref_sels[] = { + { .name = "osc_25m", }, + { .name = "osc_27m", }, + { .name = "hdmi_phy_27m", }, + { .name = "dummy", }, +}; + +static struct clk_parent_data arm_pll_bypass_sels[] = { + { .name = "arm_pll", }, + { .name = "arm_pll_ref_sel", }, +}; + +static struct clk_parent_data gpu_pll_bypass_sels[] = { + { .name = "gpu_pll", }, + { .name = "gpu_pll_ref_sel", }, +}; + +static struct clk_parent_data vpu_pll_bypass_sels[] = { + { .name = "vpu_pll", }, + { .name = "vpu_pll_ref_sel", }, +}; + +static struct clk_parent_data audio_pll1_bypass_sels[] = { + { .name = "audio_pll1", }, + { .name = "audio_pll1_ref_sel", }, +}; + +static struct clk_parent_data audio_pll2_bypass_sels[] = { + { .name = "audio_pll2", }, + { .name = "audio_pll2_ref_sel", }, +}; + +static struct clk_parent_data video_pll1_bypass_sels[] = { + { .name = "video_pll1", }, + { .name = "video_pll1_ref_sel", }, +}; + +static struct clk_parent_data sys3_pll_out_sels[] = { + { .name = "sys3_pll1_ref_sel", }, +}; + +static struct clk_parent_data dram_pll_out_sels[] = { + { .name = "dram_pll1_ref_sel", }, +}; + +static struct clk_parent_data video2_pll_out_sels[] = { + { .name = "video2_pll1_ref_sel", }, +}; + +static struct clk_parent_data imx8mq_a53_sels[] = { + { .name = "osc_25m", }, + { .name = "arm_pll_out", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll1_out", }, + { .name = "sys3_pll_out", }, +}; + +static struct clk_parent_data imx8mq_a53_core_sels[] = { + { .name = "arm_a53_div", }, + { .name = "arm_pll_out", }, +}; + +static struct clk_parent_data imx8mq_arm_m4_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys1_pll_800m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "sys3_pll_out", }, +}; + +static struct clk_parent_data imx8mq_vpu_sels[] = { + { .name = "osc_25m", }, + { .name = "arm_pll_out", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll1_out", }, + { .name = "vpu_pll_out", }, +}; + +static struct clk_parent_data imx8mq_gpu_core_sels[] = { + { .name = "osc_25m", }, + { .name = "gpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_gpu_shader_sels[] = { + { .name = "osc_25m", }, + { .name = "gpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_main_axi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_333m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys2_pll_1000m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_enet_axi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys2_pll_200m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "sys3_pll_out", }, +}; + +static struct clk_parent_data imx8mq_nand_usdhc_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_133m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "audio_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_vpu_bus_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "vpu_pll_out", }, + { .name = "audio_pll2_out", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_disp_axi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll2_out", }, + { .name = "clk_ext1", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_disp_apb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_40m", }, + { .name = "audio_pll2_out", }, + { .name = "clk_ext1", }, + { .name = "clk_ext3", }, +}; + +static struct clk_parent_data imx8mq_disp_rtrm_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, +}; + +static struct clk_parent_data imx8mq_usb_bus_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_200m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext4", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_gpu_axi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "gpu_pll_out", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_gpu_ahb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "gpu_pll_out", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_noc_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys2_pll_500m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_noc_apb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_333m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_800m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_ahb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_133m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_audio_ahb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys2_pll_166m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_dsi_ahb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_dram_alt_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys1_pll_100m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll1_out", }, + { .name = "sys1_pll_266m", }, +}; + +static struct clk_parent_data imx8mq_dram_apb_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_vpu_g1_sels[] = { + { .name = "osc_25m", }, + { .name = "vpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_100m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_vpu_g2_sels[] = { + { .name = "osc_25m", }, + { .name = "vpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_100m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_disp_dtrc_sels[] = { + { .name = "osc_25m", }, + { .name = "vpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_disp_dc8000_sels[] = { + { .name = "osc_25m", }, + { .name = "vpu_pll_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_pcie1_ctrl_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_333m", }, + { .name = "sys3_pll_out", }, +}; + +static struct clk_parent_data imx8mq_pcie1_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_500m", }, + { .name = "clk_ext1", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_pcie1_aux_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_200m", }, +}; + +static struct clk_parent_data imx8mq_dc_pixel_sels[] = { + { .name = "osc_25m", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "audio_pll1_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_lcdif_pixel_sels[] = { + { .name = "osc_25m", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "audio_pll1_out", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_sai1_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext1", }, + { .name = "clk_ext2", }, +}; + +static struct clk_parent_data imx8mq_sai2_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, +}; + +static struct clk_parent_data imx8mq_sai3_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_sai4_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext1", }, + { .name = "clk_ext2", }, +}; + +static struct clk_parent_data imx8mq_sai5_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, +}; + +static struct clk_parent_data imx8mq_sai6_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_spdif1_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, +}; + +static struct clk_parent_data imx8mq_spdif2_sels[] = { + { .name = "osc_25m", }, + { .name = "audio_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, + { .name = "sys1_pll_133m", }, + { .name = "osc_27m", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_enet_ref_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_160m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "clk_ext4", }, +}; + +static struct clk_parent_data imx8mq_enet_timer_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "audio_pll1_out", }, + { .name = "clk_ext1", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_enet_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys2_pll_500m", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_nand_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_500m", }, + { .name = "audio_pll1_out", }, + { .name = "sys1_pll_400m", }, + { .name = "audio_pll2_out", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_qspi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_500m", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_266m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_usdhc1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_266m", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_usdhc2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_266m", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_i2c1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_133m", }, +}; + +static struct clk_parent_data imx8mq_i2c2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_133m", }, +}; + +static struct clk_parent_data imx8mq_i2c3_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_133m", }, +}; + +static struct clk_parent_data imx8mq_i2c4_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "audio_pll2_out", }, + { .name = "sys1_pll_133m", }, +}; + +static struct clk_parent_data imx8mq_uart1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "clk_ext4", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_uart2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_uart3_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "clk_ext4", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_uart4_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_usb_core_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_100m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_200m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_usb_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_100m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_200m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_gic_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_200m", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_ecspi1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_ecspi2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_pwm1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext1", }, + { .name = "sys1_pll_80m", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_pwm2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext1", }, + { .name = "sys1_pll_80m", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_pwm3_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "sys1_pll_80m", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_pwm4_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext2", }, + { .name = "sys1_pll_80m", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_gpt1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys1_pll_80m", }, + { .name = "audio_pll1_out", }, + { .name = "clk_ext1", }, +}; + +static struct clk_parent_data imx8mq_wdog_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_133m", }, + { .name = "sys1_pll_160m", }, + { .name = "vpu_pll_out", }, + { .name = "sys2_pll_125m", }, + { .name = "sys3_pll_out", }, + { .name = "sys1_pll_80m", }, + { .name = "sys2_pll_166m", }, +}; + +static struct clk_parent_data imx8mq_wrclk_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_40m", }, + { .name = "vpu_pll_out", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys1_pll_100m", }, +}; + +static struct clk_parent_data imx8mq_dsi_core_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_dsi_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "clk_ext2", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_dsi_dbi_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_dsi_esc_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_csi1_core_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_csi1_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "clk_ext2", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_csi1_esc_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_csi2_core_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_csi2_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_125m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "clk_ext2", }, + { .name = "audio_pll2_out", }, + { .name = "video_pll1_out", }, +}; + +static struct clk_parent_data imx8mq_csi2_esc_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_1000m", }, + { .name = "sys3_pll_out", }, + { .name = "clk_ext3", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_pcie2_ctrl_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_250m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_266m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys2_pll_500m", }, + { .name = "sys2_pll_333m", }, + { .name = "sys3_pll_out", }, +}; + +static struct clk_parent_data imx8mq_pcie2_phy_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_100m", }, + { .name = "sys2_pll_500m", }, + { .name = "clk_ext1", }, + { .name = "clk_ext2", }, + { .name = "clk_ext3", }, + { .name = "clk_ext4", }, + { .name = "sys1_pll_400m", }, +}; + +static struct clk_parent_data imx8mq_pcie2_aux_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys2_pll_50m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_100m", }, + { .name = "sys1_pll_80m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_200m", }, +}; + +static struct clk_parent_data imx8mq_ecspi3_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_40m", }, + { .name = "sys1_pll_160m", }, + { .name = "sys1_pll_800m", }, + { .name = "sys3_pll_out", }, + { .name = "sys2_pll_250m", }, + { .name = "audio_pll2_out", }, +}; + +static struct clk_parent_data imx8mq_dram_core_sels[] = { + { .name = "dram_pll_out", }, + { .name = "dram_alt_root", }, +}; + +static struct clk_parent_data imx8mq_clko1_sels[] = { + { .name = "osc_25m", }, + { .name = "sys1_pll_800m", }, + { .name = "osc_27m", }, + { .name = "sys1_pll_200m", }, + { .name = "audio_pll2_out", }, + { .name = "sys2_pll_500m", }, + { .name = "vpu_pll_out", }, + { .name = "sys1_pll_80m", }, +}; + +static struct clk_parent_data imx8mq_clko2_sels[] = { + { .name = "osc_25m", }, + { .name = "sys2_pll_200m", }, + { .name = "sys1_pll_400m", }, + { .name = "sys2_pll_166m", }, + { .name = "sys3_pll_out", }, + { .name = "audio_pll1_out", }, + { .name = "video_pll1_out", }, + { .name = "ckil", }, +}; + +static struct clk_parent_data pllout_monitor_sels[] = { + { .name = "osc_25m", }, + { .name = "osc_27m", }, + { .name = "dummy", }, + { .name = "dummy", }, + { .name = "ckil", }, + { .name = "audio_pll1_out_monitor", }, + { .name = "audio_pll2_out_monitor", }, + { .name = "video_pll1_out_monitor", }, + { .name = "gpu_pll_out_monitor", }, + { .name = "vpu_pll_out_monitor", }, + { .name = "arm_pll_out_monitor", }, + { .name = "sys_pll1_out_monitor", }, + { .name = "sys_pll2_out_monitor", }, + { .name = "sys_pll3_out_monitor", }, + { .name = "dram_pll_out_monitor", }, + { .name = "video_pll2_out_monitor", }, +}; + + +static IMX_CLK_SOURCE(dummy, 0); +static IMX_CLK_SOURCE(ckil, 0x8000); +static IMX_CLK_SOURCE(osc_25m, 0x17d7840); +static IMX_CLK_SOURCE(osc_27m, 0x19bfcc0); +static IMX_CLK_SOURCE(clk_ext1, 0x7ed6b40); +static IMX_CLK_SOURCE(clk_ext2, 0x7ed6b40); +static IMX_CLK_SOURCE(clk_ext3, 0x7ed6b40); +static IMX_CLK_SOURCE(clk_ext4, 0x7ed6b40); + +static IMX_CLK_MUX(arm_pll_ref_sel, CCM_ANALOG_BASE, 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(gpu_pll_ref_sel, CCM_ANALOG_BASE, 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(vpu_pll_ref_sel, CCM_ANALOG_BASE, 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll1_ref_sel, CCM_ANALOG_BASE, 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(audio_pll2_ref_sel, CCM_ANALOG_BASE, 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video_pll1_ref_sel, CCM_ANALOG_BASE, 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(sys3_pll1_ref_sel, CCM_ANALOG_BASE, 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(dram_pll1_ref_sel, CCM_ANALOG_BASE, 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); +static IMX_CLK_MUX(video2_pll1_ref_sel, CCM_ANALOG_BASE, 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + +static IMX_CLK_DIV(arm_pll_ref_div, { &arm_pll_ref_sel }, CCM_ANALOG_BASE, 0x28, 5, 6); +static IMX_CLK_DIV(gpu_pll_ref_div, { &gpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x18, 5, 6); +static IMX_CLK_DIV(vpu_pll_ref_div, { &vpu_pll_ref_sel }, CCM_ANALOG_BASE, 0x20, 5, 6); +static IMX_CLK_DIV(audio_pll1_ref_div, { &audio_pll1_ref_sel }, CCM_ANALOG_BASE, 0x0, 5, 6); +static IMX_CLK_DIV(audio_pll2_ref_div, { &audio_pll2_ref_sel }, CCM_ANALOG_BASE, 0x8, 5, 6); +static IMX_CLK_DIV(video_pll1_ref_div, { &video_pll1_ref_sel }, CCM_ANALOG_BASE, 0x10, 5, 6); + +static IMX_CLK_FRAC_PLL(arm_pll, { &arm_pll_ref_div }, CCM_ANALOG_BASE, 0x28); +static IMX_CLK_FRAC_PLL(gpu_pll, { &gpu_pll_ref_div }, CCM_ANALOG_BASE, 0x18); +static IMX_CLK_FRAC_PLL(vpu_pll, { &vpu_pll_ref_div }, CCM_ANALOG_BASE, 0x20); +static IMX_CLK_FRAC_PLL(audio_pll1, { &audio_pll1_ref_div }, CCM_ANALOG_BASE, 0x0); +static IMX_CLK_FRAC_PLL(audio_pll2, { &audio_pll2_ref_div }, CCM_ANALOG_BASE, 0x8); +static IMX_CLK_FRAC_PLL(video_pll1, { &video_pll1_ref_div }, CCM_ANALOG_BASE, 0x10); + +/* PLL bypass out */ +static IMX_CLK_MUX_FLAGS(arm_pll_bypass, CCM_ANALOG_BASE, 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); +static IMX_CLK_MUX(gpu_pll_bypass, CCM_ANALOG_BASE, 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); +static IMX_CLK_MUX(vpu_pll_bypass, CCM_ANALOG_BASE, 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); +static IMX_CLK_MUX(audio_pll1_bypass, CCM_ANALOG_BASE, 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); +static IMX_CLK_MUX(audio_pll2_bypass, CCM_ANALOG_BASE, 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); +static IMX_CLK_MUX(video_pll1_bypass, CCM_ANALOG_BASE, 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); + +/* PLL OUT GATE */ +static IMX_CLK_GATE(arm_pll_out, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x28, 21); +static IMX_CLK_GATE(gpu_pll_out, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x18, 21); +static IMX_CLK_GATE(vpu_pll_out, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x20, 21); +static IMX_CLK_GATE(audio_pll1_out, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x0, 21); +static IMX_CLK_GATE(audio_pll2_out, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x8, 21); +static IMX_CLK_GATE(video_pll1_out, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x10, 21); + +static IMX_CLK_FIXED(sys1_pll_out, 800000000); +static IMX_CLK_FIXED(sys2_pll_out, 1000000000); +static IMX_CLK_SSCG_PLL(sys3_pll_out, sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x48, CLK_IS_CRITICAL); +static IMX_CLK_SSCG_PLL(dram_pll_out, dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); +static IMX_CLK_SSCG_PLL(video2_pll_out, video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, CCM_ANALOG_BASE, 0x54, 0); + +/* SYS PLL1 fixed output */ +static IMX_CLK_FIXED_FACTOR(sys1_pll_40m, { &sys1_pll_out }, 1, 20); +static IMX_CLK_FIXED_FACTOR(sys1_pll_80m, { &sys1_pll_out }, 1, 10); +static IMX_CLK_FIXED_FACTOR(sys1_pll_100m, { &sys1_pll_out }, 1, 8); +static IMX_CLK_FIXED_FACTOR(sys1_pll_133m, { &sys1_pll_out }, 1, 6); +static IMX_CLK_FIXED_FACTOR(sys1_pll_160m, { &sys1_pll_out }, 1, 5); +static IMX_CLK_FIXED_FACTOR(sys1_pll_200m, { &sys1_pll_out }, 1, 4); +static IMX_CLK_FIXED_FACTOR(sys1_pll_266m, { &sys1_pll_out }, 1, 3); +static IMX_CLK_FIXED_FACTOR(sys1_pll_400m, { &sys1_pll_out }, 1, 2); +static IMX_CLK_FIXED_FACTOR(sys1_pll_800m, { &sys1_pll_out }, 1, 1); + +/* SYS PLL2 fixed output */ +static IMX_CLK_FIXED_FACTOR(sys2_pll_50m, { &sys2_pll_out }, 1, 20); +static IMX_CLK_FIXED_FACTOR(sys2_pll_100m, { &sys2_pll_out }, 1, 10); +static IMX_CLK_FIXED_FACTOR(sys2_pll_125m, { &sys2_pll_out }, 1, 8); +static IMX_CLK_FIXED_FACTOR(sys2_pll_166m, { &sys2_pll_out }, 1, 6); +static IMX_CLK_FIXED_FACTOR(sys2_pll_200m, { &sys2_pll_out }, 1, 5); +static IMX_CLK_FIXED_FACTOR(sys2_pll_250m, { &sys2_pll_out }, 1, 4); +static IMX_CLK_FIXED_FACTOR(sys2_pll_333m, { &sys2_pll_out }, 1, 3); +static IMX_CLK_FIXED_FACTOR(sys2_pll_500m, { &sys2_pll_out }, 1, 2); +static IMX_CLK_FIXED_FACTOR(sys2_pll_1000m, { &sys2_pll_out }, 1, 1); + +static IMX_CLK_DIV(audio_pll1_out_monitor, { &audio_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 0, 3); +static IMX_CLK_DIV(audio_pll2_out_monitor, { &audio_pll2_bypass }, CCM_ANALOG_BASE, 0x78, 4, 3); +static IMX_CLK_DIV(video_pll1_out_monitor, { &video_pll1_bypass }, CCM_ANALOG_BASE, 0x78, 8, 3); +static IMX_CLK_DIV(gpu_pll_out_monitor, { &gpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 12, 3); +static IMX_CLK_DIV(vpu_pll_out_monitor, { &vpu_pll_bypass }, CCM_ANALOG_BASE, 0x78, 16, 3); +static IMX_CLK_DIV(arm_pll_out_monitor, { &arm_pll_bypass }, CCM_ANALOG_BASE, 0x78, 20, 3); +static IMX_CLK_DIV(sys_pll1_out_monitor, { &sys1_pll_out }, CCM_ANALOG_BASE, 0x7c, 0, 3); +static IMX_CLK_DIV(sys_pll2_out_monitor, { &sys2_pll_out }, CCM_ANALOG_BASE, 0x7c, 4, 3); +static IMX_CLK_DIV(sys_pll3_out_monitor, { &sys3_pll_out }, CCM_ANALOG_BASE, 0x7c, 8, 3); +static IMX_CLK_DIV(dram_pll_out_monitor, { &dram_pll_out }, CCM_ANALOG_BASE, 0x7c, 12, 3); +static IMX_CLK_DIV(video_pll2_out_monitor, { &video2_pll_out }, CCM_ANALOG_BASE, 0x7c, 16, 3); +static IMX_CLK_MUX(pllout_monitor_sel, CCM_ANALOG_BASE, 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels)); +static IMX_CLK_GATE(pllout_monitor_clk2, { &pllout_monitor_sel }, CCM_ANALOG_BASE, 0x74, 4); + +/* CORE */ +static IMX_CLK_COMPOSITE_CORE(arm_a53_div, imx8mq_a53_sels, CCM_BASE, 0x8000); + +static IMX_CLK_COMPOSITE_CORE(arm_m4_core, imx8mq_arm_m4_sels, CCM_BASE, 0x8080); +static IMX_CLK_COMPOSITE_CORE(vpu_core, imx8mq_vpu_sels, CCM_BASE, 0x8100); +static IMX_CLK_COMPOSITE_CORE(gpu_core, imx8mq_gpu_core_sels, CCM_BASE, 0x8180); +static IMX_CLK_COMPOSITE(gpu_shader, imx8mq_gpu_shader_sels, CCM_BASE, 0x8200); + +/* CORE SEL */ +static IMX_CLK_MUX2(arm_a53_core, CCM_BASE, 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)); + +/* BUS */ +static IMX_CLK_COMPOSITE_BUS(main_axi, imx8mq_main_axi_sels, CCM_BASE, 0x8800); +static IMX_CLK_COMPOSITE_BUS(enet_axi, imx8mq_enet_axi_sels, CCM_BASE, 0x8880); +static IMX_CLK_COMPOSITE_BUS(nand_usdhc_bus, imx8mq_nand_usdhc_sels, CCM_BASE, 0x8900); +static IMX_CLK_COMPOSITE_BUS(vpu_bus, imx8mq_vpu_bus_sels, CCM_BASE, 0x8980); +static IMX_CLK_COMPOSITE_BUS(disp_axi, imx8mq_disp_axi_sels, CCM_BASE, 0x8a00); +static IMX_CLK_COMPOSITE_BUS(disp_apb, imx8mq_disp_apb_sels, CCM_BASE, 0x8a80); +static IMX_CLK_COMPOSITE_BUS(disp_rtrm, imx8mq_disp_rtrm_sels, CCM_BASE, 0x8b00); +static IMX_CLK_COMPOSITE_BUS(usb_bus, imx8mq_usb_bus_sels, CCM_BASE, 0x8b80); +static IMX_CLK_COMPOSITE_BUS(gpu_axi, imx8mq_gpu_axi_sels, CCM_BASE, 0x8c00); +static IMX_CLK_COMPOSITE_BUS(gpu_ahb, imx8mq_gpu_ahb_sels, CCM_BASE, 0x8c80); +static IMX_CLK_COMPOSITE_BUS(noc, imx8mq_noc_sels, CCM_BASE, 0x8d00); +static IMX_CLK_COMPOSITE_BUS(noc_apb, imx8mq_noc_apb_sels, CCM_BASE, 0x8d80); + +/* AHB */ +/* AHB clock is used by the AHB bus therefore marked as critical */ +static IMX_CLK_COMPOSITE_BUS(ahb, imx8mq_ahb_sels, CCM_BASE, 0x9000); +static IMX_CLK_COMPOSITE_BUS(audio_ahb, imx8mq_audio_ahb_sels, CCM_BASE, 0x9100); + +/* IPG */ +static IMX_CLK_DIV2(ipg_root, { &ahb }, CCM_BASE, 0x9080, 0, 1); +static IMX_CLK_DIV2(ipg_audio_root, { &audio_ahb }, CCM_BASE, 0x9180, 0, 1); + +/* + * DRAM clocks are manipulated from TF-A outside clock framework. + * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE + * as div value should always be read from hardware + */ +static IMX_CLK_MUX2_FLAGS(dram_core_clk, CCM_BASE, 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); +static IMX_CLK_COMPOSITE_FW_MANAGED(dram_alt, imx8mq_dram_alt_sels, CCM_BASE, 0xa000); +static IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(dram_apb, imx8mq_dram_apb_sels, CCM_BASE, 0xa080); + +/* IP */ +static IMX_CLK_COMPOSITE(vpu_g1, imx8mq_vpu_g1_sels, CCM_BASE, 0xa100); +static IMX_CLK_COMPOSITE(vpu_g2, imx8mq_vpu_g2_sels, CCM_BASE, 0xa180); +static IMX_CLK_COMPOSITE(disp_dtrc, imx8mq_disp_dtrc_sels, CCM_BASE, 0xa200); +static IMX_CLK_COMPOSITE(disp_dc8000, imx8mq_disp_dc8000_sels, CCM_BASE, 0xa280); +static IMX_CLK_COMPOSITE(pcie1_ctrl, imx8mq_pcie1_ctrl_sels, CCM_BASE, 0xa300); +static IMX_CLK_COMPOSITE(pcie1_phy, imx8mq_pcie1_phy_sels, CCM_BASE, 0xa380); +static IMX_CLK_COMPOSITE(pcie1_aux, imx8mq_pcie1_aux_sels, CCM_BASE, 0xa400); +static IMX_CLK_COMPOSITE(dc_pixel, imx8mq_dc_pixel_sels, CCM_BASE, 0xa480); +static IMX_CLK_COMPOSITE(lcdif_pixel, imx8mq_lcdif_pixel_sels, CCM_BASE, 0xa500); +static IMX_CLK_COMPOSITE(sai1, imx8mq_sai1_sels, CCM_BASE, 0xa580); +static IMX_CLK_COMPOSITE(sai2, imx8mq_sai2_sels, CCM_BASE, 0xa600); +static IMX_CLK_COMPOSITE(sai3, imx8mq_sai3_sels, CCM_BASE, 0xa680); +static IMX_CLK_COMPOSITE(sai4, imx8mq_sai4_sels, CCM_BASE, 0xa700); +static IMX_CLK_COMPOSITE(sai5, imx8mq_sai5_sels, CCM_BASE, 0xa780); +static IMX_CLK_COMPOSITE(sai6, imx8mq_sai6_sels, CCM_BASE, 0xa800); +static IMX_CLK_COMPOSITE(spdif1, imx8mq_spdif1_sels, CCM_BASE, 0xa880); +static IMX_CLK_COMPOSITE(spdif2, imx8mq_spdif2_sels, CCM_BASE, 0xa900); +static IMX_CLK_COMPOSITE(enet_ref, imx8mq_enet_ref_sels, CCM_BASE, 0xa980); +static IMX_CLK_COMPOSITE(enet_timer, imx8mq_enet_timer_sels, CCM_BASE, 0xaa00); +static IMX_CLK_COMPOSITE(enet_phy, imx8mq_enet_phy_sels, CCM_BASE, 0xaa80); +static IMX_CLK_COMPOSITE(nand, imx8mq_nand_sels, CCM_BASE, 0xab00); +static IMX_CLK_COMPOSITE(qspi, imx8mq_qspi_sels, CCM_BASE, 0xab80); +static IMX_CLK_COMPOSITE(usdhc1, imx8mq_usdhc1_sels, CCM_BASE, 0xac00); +static IMX_CLK_COMPOSITE(usdhc2, imx8mq_usdhc2_sels, CCM_BASE, 0xac80); +static IMX_CLK_COMPOSITE(i2c1, imx8mq_i2c1_sels, CCM_BASE, 0xad00); +static IMX_CLK_COMPOSITE(i2c2, imx8mq_i2c2_sels, CCM_BASE, 0xad80); +static IMX_CLK_COMPOSITE(i2c3, imx8mq_i2c3_sels, CCM_BASE, 0xae00); +static IMX_CLK_COMPOSITE(i2c4, imx8mq_i2c4_sels, CCM_BASE, 0xae80); +static IMX_CLK_COMPOSITE(uart1, imx8mq_uart1_sels, CCM_BASE, 0xaf00); +static IMX_CLK_COMPOSITE(uart2, imx8mq_uart2_sels, CCM_BASE, 0xaf80); +static IMX_CLK_COMPOSITE(uart3, imx8mq_uart3_sels, CCM_BASE, 0xb000); +static IMX_CLK_COMPOSITE(uart4, imx8mq_uart4_sels, CCM_BASE, 0xb080); +static IMX_CLK_COMPOSITE(usb_core_ref, imx8mq_usb_core_sels, CCM_BASE, 0xb100); +static IMX_CLK_COMPOSITE(usb_phy_ref, imx8mq_usb_phy_sels, CCM_BASE, 0xb180); +static IMX_CLK_COMPOSITE(gic, imx8mq_gic_sels, CCM_BASE, 0xb200); +static IMX_CLK_COMPOSITE(ecspi1, imx8mq_ecspi1_sels, CCM_BASE, 0xb280); +static IMX_CLK_COMPOSITE(ecspi2, imx8mq_ecspi2_sels, CCM_BASE, 0xb300); +static IMX_CLK_COMPOSITE(pwm1, imx8mq_pwm1_sels, CCM_BASE, 0xb380); +static IMX_CLK_COMPOSITE(pwm2, imx8mq_pwm2_sels, CCM_BASE, 0xb400); +static IMX_CLK_COMPOSITE(pwm3, imx8mq_pwm3_sels, CCM_BASE, 0xb480); +static IMX_CLK_COMPOSITE(pwm4, imx8mq_pwm4_sels, CCM_BASE, 0xb500); +static IMX_CLK_COMPOSITE(gpt1, imx8mq_gpt1_sels, CCM_BASE, 0xb580); +static IMX_CLK_COMPOSITE(wdog, imx8mq_wdog_sels, CCM_BASE, 0xb900); +static IMX_CLK_COMPOSITE(wrclk, imx8mq_wrclk_sels, CCM_BASE, 0xb980); +static IMX_CLK_COMPOSITE(clko1, imx8mq_clko1_sels, CCM_BASE, 0xba00); +static IMX_CLK_COMPOSITE(clko2, imx8mq_clko2_sels, CCM_BASE, 0xba80); +static IMX_CLK_COMPOSITE(dsi_core, imx8mq_dsi_core_sels, CCM_BASE, 0xbb00); +static IMX_CLK_COMPOSITE(dsi_phy_ref, imx8mq_dsi_phy_sels, CCM_BASE, 0xbb80); +static IMX_CLK_COMPOSITE(dsi_dbi, imx8mq_dsi_dbi_sels, CCM_BASE, 0xbc00); +static IMX_CLK_COMPOSITE(dsi_esc, imx8mq_dsi_esc_sels, CCM_BASE, 0xbc80); +static IMX_CLK_COMPOSITE(dsi_ahb, imx8mq_dsi_ahb_sels, CCM_BASE, 0x9200); +static IMX_CLK_DIV2(dsi_ipg_div, { &dsi_ahb }, CCM_BASE, 0x9280, 0, 6); +static IMX_CLK_COMPOSITE(csi1_core, imx8mq_csi1_core_sels, CCM_BASE, 0xbd00); +static IMX_CLK_COMPOSITE(csi1_phy_ref, imx8mq_csi1_phy_sels, CCM_BASE, 0xbd80); +static IMX_CLK_COMPOSITE(csi1_esc, imx8mq_csi1_esc_sels, CCM_BASE, 0xbe00); +static IMX_CLK_COMPOSITE(csi2_core, imx8mq_csi2_core_sels, CCM_BASE, 0xbe80); +static IMX_CLK_COMPOSITE(csi2_phy_ref, imx8mq_csi2_phy_sels, CCM_BASE, 0xbf00); +static IMX_CLK_COMPOSITE(csi2_esc, imx8mq_csi2_esc_sels, CCM_BASE, 0xbf80); +static IMX_CLK_COMPOSITE(pcie2_ctrl, imx8mq_pcie2_ctrl_sels, CCM_BASE, 0xc000); +static IMX_CLK_COMPOSITE(pcie2_phy, imx8mq_pcie2_phy_sels, CCM_BASE, 0xc080); +static IMX_CLK_COMPOSITE(pcie2_aux, imx8mq_pcie2_aux_sels, CCM_BASE, 0xc100); +static IMX_CLK_COMPOSITE(ecspi3, imx8mq_ecspi3_sels, CCM_BASE, 0xc180); + +static IMX_CLK_GATE4(ecspi1_root_clk, { &ecspi1 }, CCM_BASE, 0x4070, 0); +static IMX_CLK_GATE4(ecspi2_root_clk, { &ecspi2 }, CCM_BASE, 0x4080, 0); +static IMX_CLK_GATE4(ecspi3_root_clk, { &ecspi3 }, CCM_BASE, 0x4090, 0); +static IMX_CLK_GATE4(enet1_root_clk, { &enet_axi }, CCM_BASE, 0x40a0, 0); +static IMX_CLK_GATE4(gpio1_root_clk, { &ipg_root }, CCM_BASE, 0x40b0, 0); +static IMX_CLK_GATE4(gpio2_root_clk, { &ipg_root }, CCM_BASE, 0x40c0, 0); +static IMX_CLK_GATE4(gpio3_root_clk, { &ipg_root }, CCM_BASE, 0x40d0, 0); +static IMX_CLK_GATE4(gpio4_root_clk, { &ipg_root }, CCM_BASE, 0x40e0, 0); +static IMX_CLK_GATE4(gpio5_root_clk, { &ipg_root }, CCM_BASE, 0x40f0, 0); +static IMX_CLK_GATE4(gpt1_root_clk, { &gpt1 }, CCM_BASE, 0x4100, 0); +static IMX_CLK_GATE4(i2c1_root_clk, { &i2c1 }, CCM_BASE, 0x4170, 0); +static IMX_CLK_GATE4(i2c2_root_clk, { &i2c2 }, CCM_BASE, 0x4180, 0); +static IMX_CLK_GATE4(i2c3_root_clk, { &i2c3 }, CCM_BASE, 0x4190, 0); +static IMX_CLK_GATE4(i2c4_root_clk, { &i2c4 }, CCM_BASE, 0x41a0, 0); +static IMX_CLK_GATE4(mu_root_clk, { &ipg_root }, CCM_BASE, 0x4210, 0); +static IMX_CLK_GATE4(ocotp_root_clk, { &ipg_root }, CCM_BASE, 0x4220, 0); +static IMX_CLK_GATE4(pcie1_root_clk, { &pcie1_ctrl }, CCM_BASE, 0x4250, 0); +static IMX_CLK_GATE4(pcie2_root_clk, { &pcie2_ctrl }, CCM_BASE, 0x4640, 0); +static IMX_CLK_GATE4(pwm1_root_clk, { &pwm1 }, CCM_BASE, 0x4280, 0); +static IMX_CLK_GATE4(pwm2_root_clk, { &pwm2 }, CCM_BASE, 0x4290, 0); +static IMX_CLK_GATE4(pwm3_root_clk, { &pwm3 }, CCM_BASE, 0x42a0, 0); +static IMX_CLK_GATE4(pwm4_root_clk, { &pwm4 }, CCM_BASE, 0x42b0, 0); +static IMX_CLK_GATE4(qspi_root_clk, { &qspi }, CCM_BASE, 0x42f0, 0); + +static IMX_CLK_GATE2_SHARED2(nand_root_clk, { &nand }, CCM_BASE, 0x4300, 0, &share_count_nand); +static IMX_CLK_GATE2_SHARED2(nand_usdhc_rawnand_clk, { &nand_usdhc_bus }, CCM_BASE, 0x4300, 0, &share_count_nand); +static IMX_CLK_GATE2_SHARED2(sai1_root_clk, { &sai1 }, CCM_BASE, 0x4330, 0, &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai1_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4330, 0, &share_count_sai1); +static IMX_CLK_GATE2_SHARED2(sai2_root_clk, { &sai2 }, CCM_BASE, 0x4340, 0, &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai2_ipg_clk, { &ipg_root }, CCM_BASE, 0x4340, 0, &share_count_sai2); +static IMX_CLK_GATE2_SHARED2(sai3_root_clk, { &sai3 }, CCM_BASE, 0x4350, 0, &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai3_ipg_clk, { &ipg_root }, CCM_BASE, 0x4350, 0, &share_count_sai3); +static IMX_CLK_GATE2_SHARED2(sai4_root_clk, { &sai4 }, CCM_BASE, 0x4360, 0, &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai4_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4360, 0, &share_count_sai4); +static IMX_CLK_GATE2_SHARED2(sai5_root_clk, { &sai5 }, CCM_BASE, 0x4370, 0, &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai5_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4370, 0, &share_count_sai5); +static IMX_CLK_GATE2_SHARED2(sai6_root_clk, { &sai6 }, CCM_BASE, 0x4380, 0, &share_count_sai6); +static IMX_CLK_GATE2_SHARED2(sai6_ipg_clk, { &ipg_audio_root }, CCM_BASE, 0x4380, 0, &share_count_sai6); +static IMX_CLK_GATE4(uart1_root_clk, { &uart1 }, CCM_BASE, 0x4490, 0); +static IMX_CLK_GATE4(uart2_root_clk, { &uart2 }, CCM_BASE, 0x44a0, 0); +static IMX_CLK_GATE4(uart3_root_clk, { &uart3 }, CCM_BASE, 0x44b0, 0); +static IMX_CLK_GATE4(uart4_root_clk, { &uart4 }, CCM_BASE, 0x44c0, 0); +static IMX_CLK_GATE4(usb1_ctrl_root_clk, { &usb_bus }, CCM_BASE, 0x44d0, 0); +static IMX_CLK_GATE4(usb2_ctrl_root_clk, { &usb_bus }, CCM_BASE, 0x44e0, 0); +static IMX_CLK_GATE4(usb1_phy_root_clk, { &usb_phy_ref }, CCM_BASE, 0x44f0, 0); +static IMX_CLK_GATE4(usb2_phy_root_clk, { &usb_phy_ref }, CCM_BASE, 0x4500, 0); +static IMX_CLK_GATE4(usdhc1_root_clk, { &usdhc1 }, CCM_BASE, 0x4510, 0); +static IMX_CLK_GATE4(usdhc2_root_clk, { &usdhc2 }, CCM_BASE, 0x4520, 0); +static IMX_CLK_GATE4(wdog1_root_clk, { &wdog }, CCM_BASE, 0x4530, 0); +static IMX_CLK_GATE4(wdog2_root_clk, { &wdog }, CCM_BASE, 0x4540, 0); +static IMX_CLK_GATE4(wdog3_root_clk, { &wdog }, CCM_BASE, 0x4550, 0); +static IMX_CLK_GATE2_FLAGS(vpu_g1_root_clk, { &vpu_g1 }, CCM_BASE, 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +static IMX_CLK_GATE4(gpu_root_clk, { &gpu_core }, CCM_BASE, 0x4570, 0); +static IMX_CLK_GATE2_FLAGS(vpu_g2_root_clk, { &vpu_g2 }, CCM_BASE, 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +static IMX_CLK_GATE2_SHARED2(disp_root_clk, { &disp_dc8000 }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_axi_root_clk, { &disp_axi }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_apb_root_clk, { &disp_apb }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE2_SHARED2(disp_rtrm_root_clk, { &disp_rtrm }, CCM_BASE, 0x45d0, 0, &share_count_dcss); +static IMX_CLK_GATE4(tmu_root_clk, { &ipg_root }, CCM_BASE, 0x4620, 0); +static IMX_CLK_GATE2_FLAGS(vpu_dec_root_clk, { &vpu_bus }, CCM_BASE, 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); +static IMX_CLK_GATE4(csi1_root_clk, { &csi1_core }, CCM_BASE, 0x4650, 0); +static IMX_CLK_GATE4(csi2_root_clk, { &csi2_core }, CCM_BASE, 0x4660, 0); +static IMX_CLK_GATE4(sdma1_clk, { &ipg_root }, CCM_BASE, 0x43a0, 0); +static IMX_CLK_GATE4(sdma2_clk, { &ipg_audio_root }, CCM_BASE, 0x43b0, 0); + +static IMX_CLK_FIXED_FACTOR(gpt_3m, { &osc_25m }, 1, 8); +static IMX_CLK_FIXED_FACTOR(dram_alt_root, { &dram_alt }, 1, 4); + +/* hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core", */ +/* hws[IMX8MQ_CLK_A53_CORE]->clk, */ +/* hws[IMX8MQ_CLK_A53_CORE]->clk, */ +/* hws[IMX8MQ_ARM_PLL_OUT]->clk, */ +/* hws[IMX8MQ_CLK_A53_DIV]->clk); */ + +static struct clk *imx8mq_clks[IMX8MQ_CLK_END] = { + [IMX8MQ_CLK_DUMMY] = &dummy, + [IMX8MQ_CLK_32K] = &ckil, + [IMX8MQ_CLK_25M] = &osc_25m, + [IMX8MQ_CLK_27M] = &osc_27m, + [IMX8MQ_CLK_EXT1] = &clk_ext1, + [IMX8MQ_CLK_EXT2] = &clk_ext2, + [IMX8MQ_CLK_EXT3] = &clk_ext3, + [IMX8MQ_CLK_EXT4] = &clk_ext4, + [IMX8MQ_ARM_PLL_REF_SEL] = &arm_pll_ref_sel, + [IMX8MQ_GPU_PLL_REF_SEL] = &gpu_pll_ref_sel, + [IMX8MQ_VPU_PLL_REF_SEL] = &vpu_pll_ref_sel, + [IMX8MQ_AUDIO_PLL1_REF_SEL] = &audio_pll1_ref_sel, + [IMX8MQ_AUDIO_PLL2_REF_SEL] = &audio_pll2_ref_sel, + [IMX8MQ_VIDEO_PLL1_REF_SEL] = &video_pll1_ref_sel, + [IMX8MQ_SYS3_PLL1_REF_SEL] = &sys3_pll1_ref_sel, + [IMX8MQ_DRAM_PLL1_REF_SEL] = &dram_pll1_ref_sel, + [IMX8MQ_VIDEO2_PLL1_REF_SEL] = &video2_pll1_ref_sel, + [IMX8MQ_ARM_PLL_REF_DIV] = &arm_pll_ref_div, + [IMX8MQ_GPU_PLL_REF_DIV] = &gpu_pll_ref_div, + [IMX8MQ_VPU_PLL_REF_DIV] = &vpu_pll_ref_div, + [IMX8MQ_AUDIO_PLL1_REF_DIV] = &audio_pll1_ref_div, + [IMX8MQ_AUDIO_PLL2_REF_DIV] = &audio_pll2_ref_div, + [IMX8MQ_VIDEO_PLL1_REF_DIV] = &video_pll1_ref_div, + [IMX8MQ_ARM_PLL] = &arm_pll, + [IMX8MQ_GPU_PLL] = &gpu_pll, + [IMX8MQ_VPU_PLL] = &vpu_pll, + [IMX8MQ_AUDIO_PLL1] = &audio_pll1, + [IMX8MQ_AUDIO_PLL2] = &audio_pll2, + [IMX8MQ_VIDEO_PLL1] = &video_pll1, + [IMX8MQ_ARM_PLL_BYPASS] = &arm_pll_bypass, + [IMX8MQ_GPU_PLL_BYPASS] = &gpu_pll_bypass, + [IMX8MQ_VPU_PLL_BYPASS] = &vpu_pll_bypass, + [IMX8MQ_AUDIO_PLL1_BYPASS] = &audio_pll1_bypass, + [IMX8MQ_AUDIO_PLL2_BYPASS] = &audio_pll2_bypass, + [IMX8MQ_VIDEO_PLL1_BYPASS] = &video_pll1_bypass, + [IMX8MQ_ARM_PLL_OUT] = &arm_pll_out, + [IMX8MQ_GPU_PLL_OUT] = &gpu_pll_out, + [IMX8MQ_VPU_PLL_OUT] = &vpu_pll_out, + [IMX8MQ_AUDIO_PLL1_OUT] = &audio_pll1_out, + [IMX8MQ_AUDIO_PLL2_OUT] = &audio_pll2_out, + [IMX8MQ_VIDEO_PLL1_OUT] = &video_pll1_out, + [IMX8MQ_SYS1_PLL_OUT] = &sys1_pll_out, + [IMX8MQ_SYS2_PLL_OUT] = &sys2_pll_out, + [IMX8MQ_SYS3_PLL_OUT] = &sys3_pll_out, + [IMX8MQ_DRAM_PLL_OUT] = &dram_pll_out, + [IMX8MQ_VIDEO2_PLL_OUT] = &video2_pll_out, + [IMX8MQ_SYS1_PLL_40M] = &sys1_pll_40m, + [IMX8MQ_SYS1_PLL_80M] = &sys1_pll_80m, + [IMX8MQ_SYS1_PLL_100M] = &sys1_pll_100m, + [IMX8MQ_SYS1_PLL_133M] = &sys1_pll_133m, + [IMX8MQ_SYS1_PLL_160M] = &sys1_pll_160m, + [IMX8MQ_SYS1_PLL_200M] = &sys1_pll_200m, + [IMX8MQ_SYS1_PLL_266M] = &sys1_pll_266m, + [IMX8MQ_SYS1_PLL_400M] = &sys1_pll_400m, + [IMX8MQ_SYS1_PLL_800M] = &sys1_pll_800m, + [IMX8MQ_SYS2_PLL_50M] = &sys2_pll_50m, + [IMX8MQ_SYS2_PLL_100M] = &sys2_pll_100m, + [IMX8MQ_SYS2_PLL_125M] = &sys2_pll_125m, + [IMX8MQ_SYS2_PLL_166M] = &sys2_pll_166m, + [IMX8MQ_SYS2_PLL_200M] = &sys2_pll_200m, + [IMX8MQ_SYS2_PLL_250M] = &sys2_pll_250m, + [IMX8MQ_SYS2_PLL_333M] = &sys2_pll_333m, + [IMX8MQ_SYS2_PLL_500M] = &sys2_pll_500m, + [IMX8MQ_SYS2_PLL_1000M] = &sys2_pll_1000m, + [IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = &audio_pll1_out_monitor, + [IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = &audio_pll2_out_monitor, + [IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = &video_pll1_out_monitor, + [IMX8MQ_CLK_MON_GPU_PLL_DIV] = &gpu_pll_out_monitor, + [IMX8MQ_CLK_MON_VPU_PLL_DIV] = &vpu_pll_out_monitor, + [IMX8MQ_CLK_MON_ARM_PLL_DIV] = &arm_pll_out_monitor, + [IMX8MQ_CLK_MON_SYS_PLL1_DIV] = &sys_pll1_out_monitor, + [IMX8MQ_CLK_MON_SYS_PLL2_DIV] = &sys_pll2_out_monitor, + [IMX8MQ_CLK_MON_SYS_PLL3_DIV] = &sys_pll3_out_monitor, + [IMX8MQ_CLK_MON_DRAM_PLL_DIV] = &dram_pll_out_monitor, + [IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = &video_pll2_out_monitor, + [IMX8MQ_CLK_MON_SEL] = &pllout_monitor_sel, + [IMX8MQ_CLK_MON_CLK2_OUT] = &pllout_monitor_clk2, + [IMX8MQ_CLK_A53_DIV] = &arm_a53_div, + [IMX8MQ_CLK_A53_CG] = &arm_a53_div, + [IMX8MQ_CLK_A53_SRC] = &arm_a53_div, + [IMX8MQ_CLK_M4_CORE] = &arm_m4_core, + [IMX8MQ_CLK_VPU_CORE] = &vpu_core, + [IMX8MQ_CLK_GPU_CORE] = &gpu_core, + [IMX8MQ_CLK_GPU_SHADER] = &gpu_shader, + [IMX8MQ_CLK_M4_SRC] = &arm_m4_core, + [IMX8MQ_CLK_M4_CG] = &arm_m4_core, + [IMX8MQ_CLK_M4_DIV] = &arm_m4_core, + [IMX8MQ_CLK_VPU_SRC] = &vpu_core, + [IMX8MQ_CLK_VPU_CG] = &vpu_core, + [IMX8MQ_CLK_VPU_DIV] = &vpu_core, + [IMX8MQ_CLK_GPU_CORE_SRC] = &gpu_core, + [IMX8MQ_CLK_GPU_CORE_CG] = &gpu_core, + [IMX8MQ_CLK_GPU_CORE_DIV] = &gpu_core, + [IMX8MQ_CLK_GPU_SHADER_SRC] = &gpu_shader, + [IMX8MQ_CLK_GPU_SHADER_CG] = &gpu_shader, + [IMX8MQ_CLK_GPU_SHADER_DIV] = &gpu_shader, + [IMX8MQ_CLK_A53_CORE] = &arm_a53_core, + [IMX8MQ_CLK_MAIN_AXI] = &main_axi, + [IMX8MQ_CLK_ENET_AXI] = &enet_axi, + [IMX8MQ_CLK_NAND_USDHC_BUS] = &nand_usdhc_bus, + [IMX8MQ_CLK_VPU_BUS] = &vpu_bus, + [IMX8MQ_CLK_DISP_AXI] = &disp_axi, + [IMX8MQ_CLK_DISP_APB] = &disp_apb, + [IMX8MQ_CLK_DISP_RTRM] = &disp_rtrm, + [IMX8MQ_CLK_USB_BUS] = &usb_bus, + [IMX8MQ_CLK_GPU_AXI] = &gpu_axi, + [IMX8MQ_CLK_GPU_AHB] = &gpu_ahb, + [IMX8MQ_CLK_NOC] = &noc, + [IMX8MQ_CLK_NOC_APB] = &noc_apb, + [IMX8MQ_CLK_AHB] = &ahb, + [IMX8MQ_CLK_AUDIO_AHB] = &audio_ahb, + [IMX8MQ_CLK_IPG_ROOT] = &ipg_root, + [IMX8MQ_CLK_IPG_AUDIO_ROOT] = &ipg_audio_root, + [IMX8MQ_CLK_DRAM_CORE] = &dram_core_clk, + [IMX8MQ_CLK_DRAM_ALT] = &dram_alt, + [IMX8MQ_CLK_DRAM_APB] = &dram_apb, + [IMX8MQ_CLK_VPU_G1] = &vpu_g1, + [IMX8MQ_CLK_VPU_G2] = &vpu_g2, + [IMX8MQ_CLK_DISP_DTRC] = &disp_dtrc, + [IMX8MQ_CLK_DISP_DC8000] = &disp_dc8000, + [IMX8MQ_CLK_PCIE1_CTRL] = &pcie1_ctrl, + [IMX8MQ_CLK_PCIE1_PHY] = &pcie1_phy, + [IMX8MQ_CLK_PCIE1_AUX] = &pcie1_aux, + [IMX8MQ_CLK_DC_PIXEL] = &dc_pixel, + [IMX8MQ_CLK_LCDIF_PIXEL] = &lcdif_pixel, + [IMX8MQ_CLK_SAI1] = &sai1, + [IMX8MQ_CLK_SAI2] = &sai2, + [IMX8MQ_CLK_SAI3] = &sai3, + [IMX8MQ_CLK_SAI4] = &sai4, + [IMX8MQ_CLK_SAI5] = &sai5, + [IMX8MQ_CLK_SAI6] = &sai6, + [IMX8MQ_CLK_SPDIF1] = &spdif1, + [IMX8MQ_CLK_SPDIF2] = &spdif2, + [IMX8MQ_CLK_ENET_REF] = &enet_ref, + [IMX8MQ_CLK_ENET_TIMER] = &enet_timer, + [IMX8MQ_CLK_ENET_PHY_REF] = &enet_phy, + [IMX8MQ_CLK_NAND] = &nand, + [IMX8MQ_CLK_QSPI] = &qspi, + [IMX8MQ_CLK_USDHC1] = &usdhc1, + [IMX8MQ_CLK_USDHC2] = &usdhc2, + [IMX8MQ_CLK_I2C1] = &i2c1, + [IMX8MQ_CLK_I2C2] = &i2c2, + [IMX8MQ_CLK_I2C3] = &i2c3, + [IMX8MQ_CLK_I2C4] = &i2c4, + [IMX8MQ_CLK_UART1] = &uart1, + [IMX8MQ_CLK_UART2] = &uart2, + [IMX8MQ_CLK_UART3] = &uart3, + [IMX8MQ_CLK_UART4] = &uart4, + [IMX8MQ_CLK_USB_CORE_REF] = &usb_core_ref, + [IMX8MQ_CLK_USB_PHY_REF] = &usb_phy_ref, + [IMX8MQ_CLK_GIC] = &gic, + [IMX8MQ_CLK_ECSPI1] = &ecspi1, + [IMX8MQ_CLK_ECSPI2] = &ecspi2, + [IMX8MQ_CLK_PWM1] = &pwm1, + [IMX8MQ_CLK_PWM2] = &pwm2, + [IMX8MQ_CLK_PWM3] = &pwm3, + [IMX8MQ_CLK_PWM4] = &pwm4, + [IMX8MQ_CLK_GPT1] = &gpt1, + [IMX8MQ_CLK_WDOG] = &wdog, + [IMX8MQ_CLK_WRCLK] = &wrclk, + [IMX8MQ_CLK_CLKO1] = &clko1, + [IMX8MQ_CLK_CLKO2] = &clko2, + [IMX8MQ_CLK_DSI_CORE] = &dsi_core, + [IMX8MQ_CLK_DSI_PHY_REF] = &dsi_phy_ref, + [IMX8MQ_CLK_DSI_DBI] = &dsi_dbi, + [IMX8MQ_CLK_DSI_ESC] = &dsi_esc, + [IMX8MQ_CLK_DSI_AHB] = &dsi_ahb, + [IMX8MQ_CLK_DSI_IPG_DIV] = &dsi_ipg_div, + [IMX8MQ_CLK_CSI1_CORE] = &csi1_core, + [IMX8MQ_CLK_CSI1_PHY_REF] = &csi1_phy_ref, + [IMX8MQ_CLK_CSI1_ESC] = &csi1_esc, + [IMX8MQ_CLK_CSI2_CORE] = &csi2_core, + [IMX8MQ_CLK_CSI2_PHY_REF] = &csi2_phy_ref, + [IMX8MQ_CLK_CSI2_ESC] = &csi2_esc, + [IMX8MQ_CLK_PCIE2_CTRL] = &pcie2_ctrl, + [IMX8MQ_CLK_PCIE2_PHY] = &pcie2_phy, + [IMX8MQ_CLK_PCIE2_AUX] = &pcie2_aux, + [IMX8MQ_CLK_ECSPI3] = &ecspi3, + [IMX8MQ_CLK_ECSPI1_ROOT] = &ecspi1_root_clk, + [IMX8MQ_CLK_ECSPI2_ROOT] = &ecspi2_root_clk, + [IMX8MQ_CLK_ECSPI3_ROOT] = &ecspi3_root_clk, + [IMX8MQ_CLK_ENET1_ROOT] = &enet1_root_clk, + [IMX8MQ_CLK_GPIO1_ROOT] = &gpio1_root_clk, + [IMX8MQ_CLK_GPIO2_ROOT] = &gpio2_root_clk, + [IMX8MQ_CLK_GPIO3_ROOT] = &gpio3_root_clk, + [IMX8MQ_CLK_GPIO4_ROOT] = &gpio4_root_clk, + [IMX8MQ_CLK_GPIO5_ROOT] = &gpio5_root_clk, + [IMX8MQ_CLK_GPT1_ROOT] = &gpt1_root_clk, + [IMX8MQ_CLK_I2C1_ROOT] = &i2c1_root_clk, + [IMX8MQ_CLK_I2C2_ROOT] = &i2c2_root_clk, + [IMX8MQ_CLK_I2C3_ROOT] = &i2c3_root_clk, + [IMX8MQ_CLK_I2C4_ROOT] = &i2c4_root_clk, + [IMX8MQ_CLK_MU_ROOT] = &mu_root_clk, + [IMX8MQ_CLK_OCOTP_ROOT] = &ocotp_root_clk, + [IMX8MQ_CLK_PCIE1_ROOT] = &pcie1_root_clk, + [IMX8MQ_CLK_PCIE2_ROOT] = &pcie2_root_clk, + [IMX8MQ_CLK_PWM1_ROOT] = &pwm1_root_clk, + [IMX8MQ_CLK_PWM2_ROOT] = &pwm2_root_clk, + [IMX8MQ_CLK_PWM3_ROOT] = &pwm3_root_clk, + [IMX8MQ_CLK_PWM4_ROOT] = &pwm4_root_clk, + [IMX8MQ_CLK_QSPI_ROOT] = &qspi_root_clk, + [IMX8MQ_CLK_RAWNAND_ROOT] = &nand_root_clk, + [IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = &nand_usdhc_rawnand_clk, + [IMX8MQ_CLK_SAI1_ROOT] = &sai1_root_clk, + [IMX8MQ_CLK_SAI1_IPG] = &sai1_ipg_clk, + [IMX8MQ_CLK_SAI2_ROOT] = &sai2_root_clk, + [IMX8MQ_CLK_SAI2_IPG] = &sai2_ipg_clk, + [IMX8MQ_CLK_SAI3_ROOT] = &sai3_root_clk, + [IMX8MQ_CLK_SAI3_IPG] = &sai3_ipg_clk, + [IMX8MQ_CLK_SAI4_ROOT] = &sai4_root_clk, + [IMX8MQ_CLK_SAI4_IPG] = &sai4_ipg_clk, + [IMX8MQ_CLK_SAI5_ROOT] = &sai5_root_clk, + [IMX8MQ_CLK_SAI5_IPG] = &sai5_ipg_clk, + [IMX8MQ_CLK_SAI6_ROOT] = &sai6_root_clk, + [IMX8MQ_CLK_SAI6_IPG] = &sai6_ipg_clk, + [IMX8MQ_CLK_UART1_ROOT] = &uart1_root_clk, + [IMX8MQ_CLK_UART2_ROOT] = &uart2_root_clk, + [IMX8MQ_CLK_UART3_ROOT] = &uart3_root_clk, + [IMX8MQ_CLK_UART4_ROOT] = &uart4_root_clk, + [IMX8MQ_CLK_USB1_CTRL_ROOT] = &usb1_ctrl_root_clk, + [IMX8MQ_CLK_USB2_CTRL_ROOT] = &usb2_ctrl_root_clk, + [IMX8MQ_CLK_USB1_PHY_ROOT] = &usb1_phy_root_clk, + [IMX8MQ_CLK_USB2_PHY_ROOT] = &usb2_phy_root_clk, + [IMX8MQ_CLK_USDHC1_ROOT] = &usdhc1_root_clk, + [IMX8MQ_CLK_USDHC2_ROOT] = &usdhc2_root_clk, + [IMX8MQ_CLK_WDOG1_ROOT] = &wdog1_root_clk, + [IMX8MQ_CLK_WDOG2_ROOT] = &wdog2_root_clk, + [IMX8MQ_CLK_WDOG3_ROOT] = &wdog3_root_clk, + [IMX8MQ_CLK_VPU_G1_ROOT] = &vpu_g1_root_clk, + [IMX8MQ_CLK_GPU_ROOT] = &gpu_root_clk, + [IMX8MQ_CLK_VPU_G2_ROOT] = &vpu_g2_root_clk, + [IMX8MQ_CLK_DISP_ROOT] = &disp_root_clk, + [IMX8MQ_CLK_DISP_AXI_ROOT] = &disp_axi_root_clk, + [IMX8MQ_CLK_DISP_APB_ROOT] = &disp_apb_root_clk, + [IMX8MQ_CLK_DISP_RTRM_ROOT] = &disp_rtrm_root_clk, + [IMX8MQ_CLK_TMU_ROOT] = &tmu_root_clk, + [IMX8MQ_CLK_VPU_DEC_ROOT] = &vpu_dec_root_clk, + [IMX8MQ_CLK_CSI1_ROOT] = &csi1_root_clk, + [IMX8MQ_CLK_CSI2_ROOT] = &csi2_root_clk, + [IMX8MQ_CLK_SDMA1_ROOT] = &sdma1_clk, + [IMX8MQ_CLK_SDMA2_ROOT] = &sdma2_clk, + [IMX8MQ_GPT_3M_CLK] = &gpt_3m, + [IMX8MQ_CLK_DRAM_ALT_ROOT] = &dram_alt_root, +}; + +struct clk **get_clk_list(void) +{ + sddf_dprintf("get clk list\n"); + + return imx8mq_clks; +} diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c new file mode 100644 index 000000000..c16f3e876 --- /dev/null +++ b/drivers/clk/imx/clk.c @@ -0,0 +1,222 @@ +/* + * Copyright 2024, UNSW + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Terry Bai: tianyi.bai@unsw.edu.au + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +// Logging +/* #define DEBUG_DRIVER */ + +#ifdef DEBUG_DRIVER +#define LOG_DRIVER(...) do{ sddf_dprintf("CLK DRIVER|INFO: "); sddf_dprintf(__VA_ARGS__); }while(0) +#else +#define LOG_DRIVER(...) do{}while(0) +#endif + +#define LOG_DRIVER_ERR(...) do{ sddf_printf("CLK DRIVER|ERROR: "); sddf_printf(__VA_ARGS__); }while(0) + +#define CLIENT_CH 0 + +#define NUM_CLK_LIST IMX8MQ_CLK_END + +struct clk **clk_list; + +uintptr_t ccm_base; +uintptr_t ccm_analog_base; + +void clk_probe(struct clk *clk_list[]) +{ + int i; + for (i = 0; i < NUM_CLK_LIST; i++) { + if (!clk_list[i]) { + continue; + } + if (clk_list[i]->base == CCM_BASE) { + clk_list[i]->base = ccm_base; + } else if (clk_list[i]->base == CCM_ANALOG_BASE) { + clk_list[i]->base = ccm_analog_base; + } + if (clk_list[i] && clk_list[i]->hw.init->ops->init) { + clk_list[i]->hw.init->ops->init(clk_list[i]); + LOG_DRIVER("Initialise %s\n", clk_list[i]->hw.init->name); + } + } +} + +const struct clk *get_parent(const struct clk *clk) +{ + const struct clk_init_data *init = (struct clk_init_data *)clk->hw.init; + uint32_t num_parents = init->num_parents; + + if (init->parent_data) { + uint8_t parent_idx = num_parents > 1 ? init->ops->get_parent(clk) : 0; + struct clk_parent_data parent_data = init->parent_data[parent_idx]; + + if (parent_data.clk) { + return parent_data.clk; + } else if (sddf_strcmp(parent_data.name, "xtal") == 0) { + return NULL; + } + } + + if (num_parents > 0) { + return init->parent_clks[0]; + } + + return NULL; +} + +/* TODO: Should be just read from the structure, but need to update everytime when */ +/* related clocks are modified */ +unsigned long clk_get_rate(const struct clk *clk) +{ + const struct clk_init_data *init = (struct clk_init_data *)clk->hw.init; + unsigned long parent_rate = 0; + + const struct clk *parent_clk = get_parent(clk); + if (parent_clk) { + parent_rate = clk_get_rate(parent_clk); + } + + unsigned long rate = parent_rate; + if (init->ops->recalc_rate) { + rate = init->ops->recalc_rate(clk, parent_rate); + } + + return rate; +} + +uint32_t clk_enable(struct clk *clk) +{ + if (clk->hw.init->ops->enable != NULL) { + return clk->hw.init->ops->enable(clk); + } + + return CLK_INVALID_OP; +} + +uint32_t clk_disable(struct clk *clk) +{ + if (clk->hw.init->ops->disable != NULL) { + return clk->hw.init->ops->disable(clk); + } + + return CLK_INVALID_OP; +} + +uint32_t clk_set_rate(struct clk *clk, uint32_t rate) +{ + if (clk->hw.init->ops->init) { + clk->hw.init->ops->init(clk); + } + + const struct clk *pclk = get_parent(clk); + uint64_t prate = clk_get_rate(pclk); + if (clk->hw.init->ops->set_rate) { + /* TODO: determine_rate() needs to be implemented */ + LOG_DRIVER("set %s to %dHz\n", clk->hw.init->name, rate); + clk->hw.init->ops->set_rate(clk, rate, prate); + } else { + /* TODO: We only propagate one level right now */ + if (pclk->hw.init->ops->set_rate) { + const struct clk *ppclk = get_parent(pclk); + uint64_t pprate = clk_get_rate(ppclk); + /* TODO: determine_rate() needs to be implemented */ + LOG_DRIVER("set %s to %dHz\n", pclk->hw.init->name, rate); + pclk->hw.init->ops->set_rate(pclk, prate, pprate); + } + } + + return 0; +} + +void notified(microkit_channel ch) +{ + +} + +void init(void) +{ + + clk_list = get_clk_list(); + + clk_probe(clk_list); + + for (int i = 0; i < NUM_DEVICE_CLKS; i++) { + uint32_t idx = clk_configs[i].clk_id; + uint32_t rate = clk_configs[i].frequency; + + sddf_dprintf("idx: %u, frequency: 0x%x\n", idx, rate); + } +} + +microkit_msginfo protected(microkit_channel ch, microkit_msginfo msginfo) +{ + uint32_t ret = 0; + uint32_t argc = microkit_msginfo_get_count(msginfo); + + /* TODO: Check if the channel is valid */ + switch (microkit_msginfo_get_label(msginfo)) { + + case SDDF_CLK_ENABLE: { + if (argc != 1) { + LOG_DRIVER_ERR("Incorrect number of arguments %u != 1\n", argc); + ret = CLK_INCORRECT_ARGS; + break; + } + uint32_t clk_id = (uint32_t)microkit_mr_get(SDDF_CLK_PARAM_ID); + LOG_DRIVER("get request clk_enable(%d)\n", clk_id); + ret = clk_enable(clk_list[clk_id]); + break; + } + case SDDF_CLK_DISABLE: { + if (argc != 1) { + LOG_DRIVER_ERR("Incorrect number of arguments %u != 1\n", argc); + ret = CLK_INCORRECT_ARGS; + break; + } + uint32_t clk_id = (uint32_t)microkit_mr_get(SDDF_CLK_PARAM_ID); + LOG_DRIVER("get request clk_disable(%d)\n", clk_id); + ret = clk_disable(clk_list[clk_id]); + break; + } + case SDDF_CLK_GET_RATE: { + if (argc != 1) { + LOG_DRIVER_ERR("Incorrect number of arguments %u != 1\n", argc); + ret = CLK_INCORRECT_ARGS; + break; + } + uint32_t clk_id = (uint32_t)microkit_mr_get(SDDF_CLK_PARAM_ID); + ret = clk_get_rate(clk_list[clk_id]); + break; + } + case SDDF_CLK_SET_RATE: { + if (argc != 2) { + LOG_DRIVER_ERR("Incorrect number of arguments %u != 1\n", argc); + ret = CLK_INCORRECT_ARGS; + break; + } + uint32_t clk_id = (uint32_t)microkit_mr_get(SDDF_CLK_PARAM_ID); + uint32_t rate = (uint32_t)microkit_mr_get(SDDF_CLK_PARAM_RATE); + ret = clk_set_rate(clk_list[clk_id], rate); + break; + } + default: + LOG_DRIVER_ERR("Unknown request %lu to clockk driver from channel %u\n", microkit_msginfo_get_label(msginfo), ch); + ret = 5; + } + return microkit_msginfo_new(ret, 0); +} diff --git a/drivers/clk/imx/clk_driver.mk b/drivers/clk/imx/clk_driver.mk new file mode 100644 index 000000000..bfb9012fd --- /dev/null +++ b/drivers/clk/imx/clk_driver.mk @@ -0,0 +1,34 @@ +# +# Copyright 2024, UNSW +# +# SPDX-License-Identifier: BSD-2-Clause + +CLK_DRIVER_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +CLK_DRIVER_COMMON_DIR := $(SDDF)/drivers/clk +CLK_CONFIG_HEADER := $(BUILD_DIR)/clk_config.h +CLK_DRIVER_CONF_INC := $(SDDF)/include/sddf/clk +CLK_DRIVER_INC := $(CLK_DRIVER_DIR)/include + +CLK_DRIVER_OBJS := clk.o clk-operations.o clk-imx8mq.o clk-imx.o + +clk_driver.elf: $(CLK_DRIVER_OBJS) libsddf_util_debug.a + $(LD) $(LDFLAGS) $^ $(LIBS) -o $@ + + +$(CLK_DRIVER_OBJS): ${CLK_DRIVER_COMMON_DIR}/*.c ${CLK_DRIVER_DIR}/*.c $(CLK_CONFIG_HEADER) + $(CC) -c $(CFLAGS) \ + -I${CLK_DRIVER_INC} \ + -I${CLK_DRIVER_CONF_INC} \ + -I${CLK_DRIVER_COMMON_DIR} \ + -I${BUILD_DIR} \ + -I${UART_DRIVER_DIR}/include \ + -I${CLK_DRIVER_COMMON_DIR} $^ + +$(CLK_CONFIG_HEADER): $(DTS_FILE) + $(PYTHON) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(DTS_FILE) $(BUILD_DIR) + +clean:: + rm -f clk_driver.o + +clobber:: + rm -rf clk_driver.elf diff --git a/drivers/clk/imx/include/clk-imx.h b/drivers/clk/imx/include/clk-imx.h new file mode 100644 index 000000000..a99a81d62 --- /dev/null +++ b/drivers/clk/imx/include/clk-imx.h @@ -0,0 +1,342 @@ +#pragma once + +#include + +/* These two magic numbers are used to define static clock + * structures at compile time, and will be replaced with + * real base addresses in clk_probe(). + */ +#define CCM_BASE 0x1234 +#define CCM_ANALOG_BASE 0x5678 + +#define PCG_PREDIV_SHIFT 16 +#define PCG_PREDIV_WIDTH 3 +#define PCG_PREDIV_MAX 8 + +#define PCG_DIV_SHIFT 0 +#define PCG_CORE_DIV_WIDTH 3 +#define PCG_DIV_WIDTH 6 +#define PCG_DIV_MAX 64 + +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +#define PCG_CGC_SHIFT 28 + +struct clk_gate2 { + uint8_t bit_idx; + uint8_t cgr_val; + uint8_t cgr_mask; + uint8_t flags; + uint32_t *share_count; +}; + +struct clk_frac_pll_data { + uint32_t offset; +}; + +struct clk_sscg_pll_data { + /* struct clk_sscg_pll_setup setup; */ + uint32_t offset; + uint8_t parent; + uint8_t bypass1; + uint8_t bypass2; +}; + +/** + * Refer to section 5.1.5.4.1 Core clock slice in datasheet. + */ +struct clk_core_slice_data { + /* Common */ + uint32_t offset; + /* Mux */ + uint8_t mux_shift; + uint8_t mux_mask; + /* Gate */ + uint8_t gate_shift; + /* Divider */ + uint8_t div_shift; + uint8_t div_width; +}; + +/** + * Refer to section 5.1.5.4.2 Bus clock slice in datasheet. + */ +struct clk_bus_slice_data { + /* Common */ + uint32_t offset; + /* Mux */ + uint8_t mux_shift; + uint8_t mux_mask; + /* Gate */ + uint8_t gate_shift; + /* Prev Divider */ + uint8_t prevdiv_shift; + uint8_t prevdiv_width; + /* Post Divider */ + uint8_t postdiv_shift; + uint8_t postdiv_width; +}; + +/** + * Refer to section 5.1.5.4.3 Peripheral clock slice in datasheet. + */ +struct clk_common_slice_data { + /* Common */ + uint32_t offset; + /* Mux */ + uint8_t mux_shift; + uint8_t mux_mask; + /* Gate */ + uint8_t gate_shift; + /* Prev Divider */ + uint8_t prevdiv_shift; + uint8_t prevdiv_width; + /* Post Divider */ + uint8_t postdiv_shift; + uint8_t postdiv_width; +}; + +extern const struct clk_ops clk_gate2_ops; +extern const struct clk_ops clk_frac_pll_ops; +extern const struct clk_ops clk_sscg_pll_ops; +extern const struct clk_ops clk_core_slice_ops; +extern const struct clk_ops clk_bus_slice_ops; +extern const struct clk_ops clk_common_slice_ops; + +struct clk **get_clk_list(void); + +#define IMX_CLK_SOURCE(_name, _rate) \ +struct clk _name = { \ + .data = &(struct clk_source_data){ \ + .rate = (_rate), \ + }, \ + .hw.init = &(struct clk_init_data){ \ + .name = #_name, \ + .ops = &clk_source_ops, \ + } \ +} + +/* need to see difference between fixed clk and source clk */ +#define IMX_CLK_FIXED(_name, _rate) \ +IMX_CLK_SOURCE(_name, _rate) + +#define IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents, _init_flags) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_mux_data) { \ + .offset = (_offset), \ + .mask = MASK(_width), \ + .shift = (_shift), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_mux_ops, \ + .parent_data = (_parent_data), \ + .num_parents = (_num_parents), \ + .flags = (_init_flags), \ + }, \ +} + +#define IMX_CLK_MUX(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents) \ +IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents, 0) + +#define IMX_CLK_MUX2(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents) \ +IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents, CLK_OPS_PARENT_ENABLE) + +#define IMX_CLK_MUX2_FLAGS(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents, _flags) \ +IMX_CLK_MUX_FLAGS(_name, _base, _offset, _shift, _width, \ + _parent_data, _num_parents, _flags | CLK_OPS_PARENT_ENABLE) + +#define IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, \ + _shift, _width, _flags) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_div_data) { \ + .offset = (_offset), \ + .shift = (_shift), \ + .width = (_width), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_divider_ops, \ + .parent_clks = (const struct clk *[]) _parent_clks, \ + .num_parents = 1, \ + .flags = 0, \ + }, \ +} + +#define IMX_CLK_DIV(_name, _parent_clks, _base, _offset, \ + _shift, _width) \ +IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, _shift, _width, 0) + +#define IMX_CLK_DIV2(_name, _parent_clks, _base, _offset, \ + _shift, _width) \ +IMX_CLK_DIV_FLAGS(_name, _parent_clks, _base, _offset, _shift, \ + _width, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE) + + +#define IMX_CLK_FRAC_PLL(_name, _parent_clks, _base, _offset) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_frac_pll_data) { \ + .offset = (_offset), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_frac_pll_ops, \ + .parent_clks = (const struct clk *[]) _parent_clks, \ + .num_parents = 1, \ + }, \ +} + +#define IMX_CLK_GATE1(_name, _parent_clks, _base, _offset, _shift) \ +CLK_GATE(_name, _offset, _shift, 0, _parent_clks, 1, 0) + +#define IMX_CLK_GATE(_name, _parent_clks, _base, _offset, _shift) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_gate_data) { \ + .offset = (_offset), \ + .bit_idx = (_shift), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .parent_clks = (const struct clk *[]) _parent_clks, \ + .num_parents = 1, \ + }, \ +} + +#define IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, _flags) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_gate_data) { \ + .offset = (_offset), \ + .bit_idx = (_shift), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate2_ops, \ + .parent_clks = (const struct clk *[]) _parent_clks, \ + .num_parents = 1, \ + }, \ +} + +#define IMX_CLK_GATE2_SHARED2(_name, _parent_clks, _base, _offset, _shift, _shared_count) \ +IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) + +#define IMX_CLK_GATE4(_name, _parent_clks, _base, _offset, _shift) \ +IMX_CLK_GATE2_FLAGS(_name, _parent_clks, _base, _offset, _shift, 0) + +#define IMX_CLK_FIXED_FACTOR(_name, _parent_clks, _mult, _div) \ +CLK_FIXED_FACTOR(_name, _mult, _div, 0, _parent_clks, 1, CLK_SET_RATE_PARENT) + +#define IMX_CLK_SSCG_PLL(_name, _parent_data, _num_parents, _parent, \ + _bypass1, _bypass2, _base, _offset, _flags) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_sscg_pll_data) { \ + .offset = (_offset), \ + .parent = (_parent), \ + .bypass1 = (_bypass1), \ + .bypass2 = (_bypass2), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_sscg_pll_ops, \ + .parent_data = (_parent_data), \ + .num_parents = 1, \ + .flags = _flags, \ + }, \ +} + +#define IMX_CLK_COMPOSITE_CORE(_name, _parent_data, _base, _offset) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_core_slice_data) { \ + .offset = (_offset), \ + .mux_shift = PCG_PCS_SHIFT, \ + .mux_mask = PCG_PCS_MASK, \ + .div_shift = PCG_DIV_SHIFT, \ + .div_width = PCG_CORE_DIV_WIDTH, \ + .gate_shift = PCG_CGC_SHIFT, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_core_slice_ops, \ + .parent_data = (_parent_data), \ + .num_parents = ARRAY_SIZE(_parent_data), \ + .flags = (CLK_DIVIDER_ROUND_CLOSEST | \ + CLK_SET_RATE_NO_REPARENT | \ + CLK_OPS_PARENT_ENABLE) \ + }, \ +} + +#define IMX_CLK_COMPOSITE_BUS(_name, _parent_data, _base, _offset) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_bus_slice_data) { \ + .offset = (_offset), \ + .mux_shift = PCG_PCS_SHIFT, \ + .mux_mask = PCG_PCS_MASK, \ + .prevdiv_shift = PCG_PREDIV_SHIFT, \ + .prevdiv_width = PCG_PREDIV_WIDTH, \ + .postdiv_shift = PCG_DIV_SHIFT, \ + .postdiv_width = PCG_DIV_WIDTH, \ + .gate_shift = PCG_CGC_SHIFT, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_bus_slice_ops, \ + .parent_data = (_parent_data), \ + .num_parents = ARRAY_SIZE(_parent_data), \ + .flags = (CLK_DIVIDER_ROUND_CLOSEST | \ + CLK_SET_RATE_NO_REPARENT | \ + CLK_OPS_PARENT_ENABLE) \ + }, \ +} + +#define IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset,\ + _flags) \ +struct clk _name = { \ + .base = (_base), \ + .data = &(struct clk_common_slice_data) { \ + .offset = (_offset), \ + .mux_shift = PCG_PCS_SHIFT, \ + .mux_mask = PCG_PCS_MASK, \ + .prevdiv_shift = PCG_PREDIV_SHIFT, \ + .prevdiv_width = PCG_PREDIV_WIDTH, \ + .postdiv_shift = PCG_DIV_SHIFT, \ + .postdiv_width = PCG_DIV_WIDTH, \ + .gate_shift = PCG_CGC_SHIFT, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_common_slice_ops, \ + .parent_data = (_parent_data), \ + .num_parents = ARRAY_SIZE(_parent_data), \ + .flags = CLK_DIVIDER_ROUND_CLOSEST | \ + CLK_SET_RATE_NO_REPARENT | \ + CLK_OPS_PARENT_ENABLE | \ + (_flags), \ + }, \ +} + +#define IMX_CLK_COMPOSITE(_name, _parent_data, _base, _offset) \ +IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ + CLK_OPS_PARENT_ENABLE) + +#define IMX_CLK_COMPOSITE_FW_MANAGED(_name, _parent_data, _base, _offset) \ +IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ + (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE)) + +#define IMX_CLK_COMPOSITE_FW_MANAGED_CRITICAL(_name, _parent_data, _base, _offset) \ +IMX_CLK_COMPOSITE_FLAGS(_name, _parent_data, _base, _offset, \ + (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL)) diff --git a/drivers/clk/imx/include/imx8mq-bindings.h b/drivers/clk/imx/include/imx8mq-bindings.h new file mode 100644 index 000000000..2f74b3c6a --- /dev/null +++ b/drivers/clk/imx/include/imx8mq-bindings.h @@ -0,0 +1,430 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Source: https://github.com/torvalds/linux/blob/master/include/dt-bindings/clock/imx8mq-clock.h + */ + +#pragma once + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 115 + +/* AHB */ +#define IMX8MQ_CLK_AHB 116 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB 117 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 118 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 119 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 120 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 121 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 122 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 123 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 124 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 125 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 126 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 127 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 128 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 135 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 136 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 137 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 138 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 139 +/* NAND */ +#define IMX8MQ_CLK_NAND 140 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 141 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 142 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 143 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 144 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 145 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 146 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 147 +/* UART1 */ +#define IMX8MQ_CLK_UART1 148 +/* UART2 */ +#define IMX8MQ_CLK_UART2 149 +/* UART3 */ +#define IMX8MQ_CLK_UART3 150 +/* UART4 */ +#define IMX8MQ_CLK_UART4 151 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 152 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 153 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 154 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 155 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 156 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 157 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 158 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 159 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 160 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 161 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 162 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 163 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 164 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 165 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 166 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 167 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 168 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 169 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 170 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 171 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 172 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 173 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 174 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 175 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 176 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 177 +#define IMX8MQ_CLK_DRAM_ROOT 178 +#define IMX8MQ_CLK_ECSPI1_ROOT 179 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 183 +#define IMX8MQ_CLK_I2C1_ROOT 184 +#define IMX8MQ_CLK_I2C2_ROOT 185 +#define IMX8MQ_CLK_I2C3_ROOT 186 +#define IMX8MQ_CLK_I2C4_ROOT 187 +#define IMX8MQ_CLK_M4_ROOT 188 +#define IMX8MQ_CLK_PCIE1_ROOT 189 +#define IMX8MQ_CLK_PCIE2_ROOT 190 +#define IMX8MQ_CLK_PWM1_ROOT 191 +#define IMX8MQ_CLK_PWM2_ROOT 192 +#define IMX8MQ_CLK_PWM3_ROOT 193 +#define IMX8MQ_CLK_PWM4_ROOT 194 +#define IMX8MQ_CLK_QSPI_ROOT 195 +#define IMX8MQ_CLK_SAI1_ROOT 196 +#define IMX8MQ_CLK_SAI2_ROOT 197 +#define IMX8MQ_CLK_SAI3_ROOT 198 +#define IMX8MQ_CLK_SAI4_ROOT 199 +#define IMX8MQ_CLK_SAI5_ROOT 200 +#define IMX8MQ_CLK_SAI6_ROOT 201 +#define IMX8MQ_CLK_UART1_ROOT 202 +#define IMX8MQ_CLK_UART2_ROOT 203 +#define IMX8MQ_CLK_UART3_ROOT 204 +#define IMX8MQ_CLK_UART4_ROOT 205 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 206 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 207 +#define IMX8MQ_CLK_USB1_PHY_ROOT 208 +#define IMX8MQ_CLK_USB2_PHY_ROOT 209 +#define IMX8MQ_CLK_USDHC1_ROOT 210 +#define IMX8MQ_CLK_USDHC2_ROOT 211 +#define IMX8MQ_CLK_WDOG1_ROOT 212 +#define IMX8MQ_CLK_WDOG2_ROOT 213 +#define IMX8MQ_CLK_WDOG3_ROOT 214 +#define IMX8MQ_CLK_GPU_ROOT 215 +#define IMX8MQ_CLK_HEVC_ROOT 216 +#define IMX8MQ_CLK_AVC_ROOT 217 +#define IMX8MQ_CLK_VP9_ROOT 218 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 219 +#define IMX8MQ_CLK_DISP_ROOT 220 +#define IMX8MQ_CLK_HDMI_ROOT 221 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 222 +#define IMX8MQ_CLK_VPU_DEC_ROOT 223 +#define IMX8MQ_CLK_CSI1_ROOT 224 +#define IMX8MQ_CLK_CSI2_ROOT 225 +#define IMX8MQ_CLK_RAWNAND_ROOT 226 +#define IMX8MQ_CLK_SDMA1_ROOT 227 +#define IMX8MQ_CLK_SDMA2_ROOT 228 +#define IMX8MQ_CLK_VPU_G1_ROOT 229 +#define IMX8MQ_CLK_VPU_G2_ROOT 230 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 231 +#define IMX8MQ_SYS2_PLL_OUT 232 +#define IMX8MQ_SYS3_PLL_OUT 233 +#define IMX8MQ_DRAM_PLL_OUT 234 + +#define IMX8MQ_GPT_3M_CLK 235 + +#define IMX8MQ_CLK_IPG_ROOT 236 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237 +#define IMX8MQ_CLK_SAI1_IPG 238 +#define IMX8MQ_CLK_SAI2_IPG 239 +#define IMX8MQ_CLK_SAI3_IPG 240 +#define IMX8MQ_CLK_SAI4_IPG 241 +#define IMX8MQ_CLK_SAI5_IPG 242 +#define IMX8MQ_CLK_SAI6_IPG 243 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 244 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 245 + +#define IMX8MQ_CLK_TMU_ROOT 246 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 247 +#define IMX8MQ_CLK_DISP_APB_ROOT 248 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 249 + +#define IMX8MQ_CLK_OCOTP_ROOT 250 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 251 +#define IMX8MQ_CLK_DRAM_CORE 252 + +#define IMX8MQ_CLK_MU_ROOT 253 +#define IMX8MQ_VIDEO2_PLL_OUT 254 + +#define IMX8MQ_CLK_CLKO2 255 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256 + +#define IMX8MQ_CLK_CLKO1 257 +#define IMX8MQ_CLK_ARM 258 + +#define IMX8MQ_CLK_GPIO1_ROOT 259 +#define IMX8MQ_CLK_GPIO2_ROOT 260 +#define IMX8MQ_CLK_GPIO3_ROOT 261 +#define IMX8MQ_CLK_GPIO4_ROOT 262 +#define IMX8MQ_CLK_GPIO5_ROOT 263 + +#define IMX8MQ_CLK_SNVS_ROOT 264 +#define IMX8MQ_CLK_GIC 265 + +#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266 + +#define IMX8MQ_CLK_GPU_CORE 285 +#define IMX8MQ_CLK_GPU_SHADER 286 +#define IMX8MQ_CLK_M4_CORE 287 +#define IMX8MQ_CLK_VPU_CORE 288 + +#define IMX8MQ_CLK_A53_CORE 289 + +#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290 +#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291 +#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292 +#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293 +#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294 +#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295 +#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296 +#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297 +#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298 +#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299 +#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300 +#define IMX8MQ_CLK_MON_SEL 301 +#define IMX8MQ_CLK_MON_CLK2_OUT 302 + +#define IMX8MQ_CLK_END 303 diff --git a/drivers/clk/meson/clk.c b/drivers/clk/meson/clk.c index 414d8033d..925db7521 100644 --- a/drivers/clk/meson/clk.c +++ b/drivers/clk/meson/clk.c @@ -21,7 +21,7 @@ #include /* clock id bindings*/ // Logging -#define DEBUG_DRIVER +/* #define DEBUG_DRIVER */ #ifdef DEBUG_DRIVER #define LOG_DRIVER(...) do{ sddf_dprintf("CLK DRIVER|INFO: "); sddf_dprintf(__VA_ARGS__); }while(0) @@ -149,6 +149,7 @@ uint32_t clk_set_rate(struct clk *clk, uint32_t rate) int clk_msr_stat() { +#ifdef DEBUG_DRIVER unsigned long clk_freq; int i = 0; @@ -157,6 +158,7 @@ int clk_msr_stat() clk_freq = clk_msr(i); LOG_DRIVER("[%4d][%4ldHz] %s\n", i, clk_freq, clk_msr_list[i]); } +#endif return 0; } diff --git a/drivers/clk/meson/clk_driver.mk b/drivers/clk/meson/clk_driver.mk index bf730c526..6aff1dbb2 100644 --- a/drivers/clk/meson/clk_driver.mk +++ b/drivers/clk/meson/clk_driver.mk @@ -4,16 +4,16 @@ # SPDX-License-Identifier: BSD-2-Clause CLK_DRIVER_DIR := $(dir $(lastword $(MAKEFILE_LIST))) -CLK_DRIVER_OBJS := clk.o clk-operations.o clk-measure.o clk-meson.o sm1-clk.o - -clk_driver.elf: $(CLK_DRIVER_OBJS) libsddf_util_debug.a - $(LD) $(LDFLAGS) $^ $(LIBS) -o $@ - CLK_CONFIG_HEADER := $(BUILD_DIR)/clk_config.h CLK_DRIVER_CONF_INC := $(SDDF)/include/sddf/clk CLK_DRIVER_INC := $(CLK_DRIVER_DIR)/include CLK_DRIVER_COMMON_DIR := $(SDDF)/drivers/clk +CLK_DRIVER_OBJS := clk.o clk-operations.o clk-measure.o clk-meson.o sm1-clk.o + +clk_driver.elf: $(CLK_DRIVER_OBJS) libsddf_util_debug.a + $(LD) $(LDFLAGS) $^ $(LIBS) -o $@ + $(CLK_DRIVER_OBJS): ${CLK_DRIVER_COMMON_DIR}/*.c ${CLK_DRIVER_DIR}/*.c $(CLK_CONFIG_HEADER) $(CC) -c $(CFLAGS) \ -I${CLK_DRIVER_INC} \ @@ -22,8 +22,8 @@ $(CLK_DRIVER_OBJS): ${CLK_DRIVER_COMMON_DIR}/*.c ${CLK_DRIVER_DIR}/*.c $(CLK_CON -I${UART_DRIVER_DIR}/include \ -I${CLK_DRIVER_COMMON_DIR} $^ -$(CLK_CONFIG_HEADER): - $(PYTHON) $(CLK_DRIVER_DIR)/create_clk_config.py $(DTS_FILE) $(BUILD_DIR) +$(CLK_CONFIG_HEADER): $(DTS_FILE) + $(PYTHON) $(CLK_DRIVER_COMMON_DIR)/create_clk_config.py $(DTS_FILE) $(BUILD_DIR) clean:: rm -f clk_driver.o diff --git a/examples/clk/board/maaxboard/clk.system b/examples/clk/board/maaxboard/clk.system new file mode 100644 index 000000000..5d6f69373 --- /dev/null +++ b/examples/clk/board/maaxboard/clk.system @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/examples/clk/build.zig b/examples/clk/build.zig index a543474fa..583dd6a01 100644 --- a/examples/clk/build.zig +++ b/examples/clk/build.zig @@ -4,7 +4,7 @@ // const std = @import("std"); -const MicrokitBoard = enum { odroidc4 }; +const MicrokitBoard = enum { odroidc4, maaxboard }; const Target = struct { board: MicrokitBoard, @@ -21,6 +21,15 @@ const targets = [_]Target{ .abi = .none, }, }, + .{ + .board = MicrokitBoard.maaxboard, + .zig_target = std.Target.Query{ + .cpu_arch = .aarch64, + .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_a53 }, + .os_tag = .freestanding, + .abi = .none, + }, + }, }; fn findTarget(board: MicrokitBoard) std.Target.Query { @@ -87,10 +96,12 @@ pub fn build(b: *std.Build) void { const timer_driver_class = switch (microkit_board_option.?) { .odroidc4 => "meson", + .maaxboard => "imx", }; const clk_driver_class = switch (microkit_board_option.?) { .odroidc4 => "meson", + .maaxboard => "imx", }; const clk_driver = sddf_dep.artifact(b.fmt("driver_clk_{s}.elf", .{clk_driver_class})); const clk_driver_install = b.addInstallArtifact(clk_driver, .{ .dest_sub_path = "clk_driver.elf" }); diff --git a/examples/clk/client.c b/examples/clk/client.c index 7f69fd2f5..65894be3d 100644 --- a/examples/clk/client.c +++ b/examples/clk/client.c @@ -14,7 +14,7 @@ void init(void) { sddf_dprintf("--------------------\n"); - sddf_dprintf("Clock driver test\n"); + sddf_dprintf("Clock Driver Test\n"); #ifdef TEST_BOARD_odroidc4 sddf_dprintf("Test board: odroidc4\n"); @@ -30,7 +30,14 @@ void init(void) ret = sddf_clk_set_rate(CLK_DRIVER_CH, 10, 150000000); sddf_dprintf("ret_val: %x\n", ret); -#elif + +#elif TEST_BOARD_maaxboard + sddf_dprintf("Test board: maaxboard\n"); + + uint32_t ret = sddf_clk_enable(CLK_DRIVER_CH, 196); + sddf_dprintf("ret_val: %x\n", ret); + +#else sddf_dprintf("No tests for the target board\n", ret); #endif diff --git a/examples/clk/clk.mk b/examples/clk/clk.mk index 9e6aa92c2..df895982a 100644 --- a/examples/clk/clk.mk +++ b/examples/clk/clk.mk @@ -16,6 +16,12 @@ ifeq ($(strip $(MICROKIT_BOARD)), odroidc4) ARCH := aarch64 DRIVER_DIR := meson CPU := cortex-a55 +else ifeq ($(strip $(MICROKIT_BOARD)), maaxboard) + ARCH := aarch64 + DTS_FILE := $(TOP)/dts/maaxboard.dts + SYSTEM_FILE := ${TOP}/board/maaxboard/clk.system + DRIVER_DIR := imx + CPU := cortex-a53 else $(error Unsupported MICROKIT_BOARD given) endif diff --git a/examples/clk/dts/maaxboard.dts b/examples/clk/dts/maaxboard.dts new file mode 100644 index 000000000..434b0e863 --- /dev/null +++ b/examples/clk/dts/maaxboard.dts @@ -0,0 +1,1950 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright (C) 2017-2018 Pengutronix, Lucas Stach + * Copyright 2019 EMBEST + * Copyright 2022 Capgemini Engineering + * + * SPDX-License-Identifier: GPL-2.0-only + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This file is derived from a DTS file supplied by Avnet. + * + * The licenses of all input files to this process are compatible + * with GPL-2.0. + * + * The following commands were used to derive this file: + * > git clone https://github.com/Avnet/linux-imx.git + * > cd linux-imx + * > cpp -nostdinc -I include -I arch -undef -x assembler-with-cpp \ + * > arch/arm64/boot/dts/freescale/maaxboard-dcss-hdmi.dts temp.dts + * > dtc -o temp.dtb temp.dts + * > dtc -o maaxboard.dts temp.dtb + * > rm temp.dts temp.dtb + */ + +/dts-v1/; + +/ { + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Avnet Maaxboard"; + compatible = "avnet/embest,maaxboard\0fsl,imx8mq"; + + aliases { + csi0 = "/soc@0/bus@30800000/mipi_csi1@30a70000"; + csi1 = "/soc@0/bus@30800000/mipi_csi2@30b60000"; + ethernet0 = "/soc@0/bus@30800000/ethernet@30be0000"; + gpio0 = "/soc@0/bus@30000000/gpio@30200000"; + gpio1 = "/soc@0/bus@30000000/gpio@30210000"; + gpio2 = "/soc@0/bus@30000000/gpio@30220000"; + gpio3 = "/soc@0/bus@30000000/gpio@30230000"; + gpio4 = "/soc@0/bus@30000000/gpio@30240000"; + i2c0 = "/soc@0/bus@30800000/i2c@30a20000"; + i2c1 = "/soc@0/bus@30800000/i2c@30a30000"; + i2c2 = "/soc@0/bus@30800000/i2c@30a40000"; + i2c3 = "/soc@0/bus@30800000/i2c@30a50000"; + mmc0 = "/soc@0/bus@30800000/mmc@30b40000"; + mmc1 = "/soc@0/bus@30800000/mmc@30b50000"; + serial0 = "/soc@0/bus@30800000/serial@30860000"; + serial1 = "/soc@0/bus@30800000/serial@30890000"; + serial2 = "/soc@0/bus@30800000/serial@30880000"; + serial3 = "/soc@0/bus@30800000/serial@30a60000"; + spi0 = "/soc@0/bus@30800000/spi@30820000"; + spi1 = "/soc@0/bus@30800000/spi@30830000"; + spi2 = "/soc@0/bus@30800000/spi@30840000"; + }; + + clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "ckil"; + phandle = <0x15>; + }; + + clock-osc-25m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x17d7840>; + clock-output-names = "osc_25m"; + phandle = <0x16>; + }; + + clock-osc-27m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x19bfcc0>; + clock-output-names = "osc_27m"; + phandle = <0x17>; + }; + + clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x7ed6b40>; + clock-output-names = "clk_ext1"; + phandle = <0x18>; + }; + + clock-ext2 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x7ed6b40>; + clock-output-names = "clk_ext2"; + phandle = <0x19>; + }; + + clock-ext3 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x7ed6b40>; + clock-output-names = "clk_ext3"; + phandle = <0x1a>; + }; + + clock-ext4 { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x7ed6b40>; + clock-output-names = "clk_ext4"; + phandle = <0x1b>; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x00>; + clock-latency = <0xee6c>; + clocks = <0x02 0x102>; + enable-method = "psci"; + next-level-cache = <0x03>; + operating-points-v2 = <0x04>; + #cooling-cells = <0x02>; + nvmem-cells = <0x05>; + nvmem-cell-names = "speed_grade"; + cpu-idle-states = <0x06>; + phandle = <0x08>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x01>; + clock-latency = <0xee6c>; + clocks = <0x02 0x102>; + enable-method = "psci"; + next-level-cache = <0x03>; + operating-points-v2 = <0x04>; + #cooling-cells = <0x02>; + cpu-idle-states = <0x06>; + phandle = <0x09>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x02>; + clock-latency = <0xee6c>; + clocks = <0x02 0x102>; + enable-method = "psci"; + next-level-cache = <0x03>; + operating-points-v2 = <0x04>; + #cooling-cells = <0x02>; + cpu-idle-states = <0x06>; + phandle = <0x0a>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x03>; + clock-latency = <0xee6c>; + clocks = <0x02 0x102>; + enable-method = "psci"; + next-level-cache = <0x03>; + operating-points-v2 = <0x04>; + #cooling-cells = <0x02>; + cpu-idle-states = <0x06>; + phandle = <0x0b>; + }; + + l2-cache0 { + compatible = "cache"; + phandle = <0x03>; + }; + + idle-states { + entry-method = "psci"; + + cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10033>; + local-timer-stop; + entry-latency-us = <0x3e8>; + exit-latency-us = <0x2bc>; + min-residency-us = <0xa8c>; + wakeup-latency-us = <0x5dc>; + phandle = <0x06>; + }; + }; + }; + + opp-table { + compatible = "operating-points-v2"; + opp-shared; + phandle = <0x04>; + + opp-800000000 { + opp-hz = <0x00 0x2faf0800>; + opp-microvolt = <0xdbba0>; + opp-supported-hw = <0x0f 0x04>; + clock-latency-ns = <0x249f0>; + opp-suspend; + }; + + opp-1000000000 { + opp-hz = <0x00 0x3b9aca00>; + opp-microvolt = <0xdbba0>; + opp-supported-hw = <0x0e 0x03>; + clock-latency-ns = <0x249f0>; + opp-suspend; + }; + + opp-1300000000 { + opp-hz = <0x00 0x4d7c6d00>; + opp-microvolt = <0xf4240>; + opp-supported-hw = <0x0c 0x04>; + clock-latency-ns = <0x249f0>; + opp-suspend; + }; + + opp-1500000000 { + opp-hz = <0x00 0x59682f00>; + opp-microvolt = <0xf4240>; + opp-supported-hw = <0x08 0x03>; + clock-latency-ns = <0x249f0>; + opp-suspend; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <0x01 0x07 0x04>; + interrupt-parent = <0x07>; + interrupt-affinity = <0x08 0x09 0x0a 0x0b>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + thermal-zones { + + cpu-thermal { + polling-delay-passive = <0xfa>; + polling-delay = <0x7d0>; + thermal-sensors = <0x0c 0x00>; + + trips { + + cpu-alert { + temperature = <0x13880>; + hysteresis = <0x7d0>; + type = "passive"; + }; + + cpu-crit { + temperature = <0x17318>; + hysteresis = <0x7d0>; + type = "critical"; + }; + + trip0 { + temperature = <0x13880>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x0d>; + }; + + trip1 { + temperature = <0x14c08>; + hysteresis = <0x7d0>; + type = "passive"; + phandle = <0x0f>; + }; + }; + + cooling-maps { + + map0 { + trip = <0x0d>; + cooling-device = <0x0e 0x00 0x01 0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff 0x0a 0xffffffff 0xffffffff 0x0b 0xffffffff 0xffffffff>; + }; + + map1 { + trip = <0x0f>; + cooling-device = <0x0e 0x00 0x02>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>; + interrupt-parent = <0x07>; + arm,no-tick-in-suspend; + }; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <0x02 0xea 0x02 0x76 0x02 0x77 0x02 0x77 0x02 0xfc 0x02 0xfb 0x02 0x46 0x02 0x4d 0x02 0x48 0x02 0x4e 0x02 0x71 0x02 0x67 0x02 0x74 0x02 0x02 0x02 0x55 0x02 0x49>; + clock-names = "dram_pll\0dram_alt_src\0dram_apb_src\0dram_apb_pre_div\0dram_core\0dram_alt_root\0sys1_pll_40m\0sys1_pll_400m\0sys1_pll_100m\0sys1_pll_800m\0noc_div\0main_axi_src\0ahb_div\0osc_25m\0sys2_pll_333m\0sys1_pll_133m"; + interrupts = <0x00 0x66 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04>; + interrupt-name = "irq_busfreq_0\0irq_busfreq_1\0irq_busfreq_2\0irq_busfreq_3"; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x00 0x00 0x00 0x3e000000>; + dma-ranges = <0x40000000 0x00 0x40000000 0xc0000000>; + + caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + + bus@30000000 { + compatible = "fsl,imx8mq-aips-bus\0simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x30000000 0x30000000 0x400000>; + + sai@30010000 { + compatible = "fsl,imx8mq-sai\0fsl,imx6sx-sai"; + reg = <0x30010000 0x10000>; + interrupts = <0x00 0x5f 0x04>; + clocks = <0x02 0xee 0x02 0x00 0x02 0xc4 0x02 0x00 0x02 0x00>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3"; + dmas = <0x10 0x08 0x01 0x00 0x10 0x09 0x01 0x00>; + dma-names = "rx\0tx"; + fsl,dataline = <0x00 0xff 0xff>; + status = "disabled"; + }; + + sai@30030000 { + compatible = "fsl,imx8mq-sai\0fsl,imx6sx-sai"; + reg = <0x30030000 0x10000>; + interrupts = <0x00 0x5a 0x04>; + clocks = <0x02 0xf3 0x02 0x00 0x02 0xc9 0x02 0x00 0x02 0x00>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3"; + dmas = <0x10 0x04 0x18 0x00 0x10 0x05 0x18 0x00>; + dma-names = "rx\0tx"; + fsl,shared-interrupt; + status = "disabled"; + }; + + sai@30040000 { + compatible = "fsl,imx8mq-sai\0fsl,imx6sx-sai"; + reg = <0x30040000 0x10000>; + interrupts = <0x00 0x5a 0x04>; + clocks = <0x02 0xf2 0x02 0x00 0x02 0xc8 0x02 0x00 0x02 0x00>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3"; + dmas = <0x10 0x02 0x18 0x00 0x10 0x03 0x18 0x00>; + dma-names = "rx\0tx"; + fsl,shared-interrupt; + fsl,dataline = <0x00 0x0f 0x0f>; + status = "disabled"; + }; + + sai@30050000 { + compatible = "fsl,imx8mq-sai\0fsl,imx6sx-sai"; + reg = <0x30050000 0x10000>; + interrupts = <0x00 0x64 0x04>; + clocks = <0x02 0xf1 0x02 0x00 0x02 0xc7 0x02 0x00 0x02 0x00 0x02 0x1b 0x02 0x20>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3\0pll8k\0pll11k"; + dmas = <0x10 0x00 0x18 0x00 0x10 0x01 0x18 0x00>; + dma-names = "rx\0tx"; + fsl,dataline = <0x00 0x00 0x0f>; + status = "okay"; + assigned-clocks = <0x02 0x84>; + assigned-clock-parents = <0x02 0x1b>; + assigned-clock-rates = <0x1770000>; + phandle = <0x55>; + }; + + gpio@30200000 { + compatible = "fsl,imx8mq-gpio\0fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <0x00 0x40 0x04 0x00 0x41 0x04>; + clocks = <0x02 0x103>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + gpio-ranges = <0x11 0x00 0x0a 0x1e>; + phandle = <0x2e>; + }; + + gpio@30210000 { + compatible = "fsl,imx8mq-gpio\0fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <0x00 0x42 0x04 0x00 0x43 0x04>; + clocks = <0x02 0x104>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + gpio-ranges = <0x11 0x00 0x28 0x15>; + phandle = <0x43>; + }; + + gpio@30220000 { + compatible = "fsl,imx8mq-gpio\0fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <0x00 0x44 0x04 0x00 0x45 0x04>; + clocks = <0x02 0x105>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + gpio-ranges = <0x11 0x00 0x3d 0x1a>; + phandle = <0x30>; + }; + + gpio@30230000 { + compatible = "fsl,imx8mq-gpio\0fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <0x00 0x46 0x04 0x00 0x47 0x04>; + clocks = <0x02 0x106>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + gpio-ranges = <0x11 0x00 0x57 0x20>; + }; + + gpio@30240000 { + compatible = "fsl,imx8mq-gpio\0fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <0x00 0x48 0x04 0x00 0x49 0x04>; + clocks = <0x02 0x107>; + gpio-controller; + #gpio-cells = <0x02>; + interrupt-controller; + #interrupt-cells = <0x02>; + gpio-ranges = <0x11 0x00 0x77 0x1e>; + phandle = <0x23>; + }; + + tmu@30260000 { + compatible = "fsl,imx8mq-tmu"; + reg = <0x30260000 0x10000>; + interrupt = <0x00 0x31 0x04>; + clocks = <0x02 0xf6>; + little-endian; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00 0x23 0x01 0x29 0x02 0x2f 0x03 0x35 0x04 0x3d 0x05 0x43 0x06 0x4b 0x07 0x51 0x08 0x57 0x09 0x5f 0x0a 0x67 0x0b 0x6f 0x10000 0x1b 0x10001 0x23 0x10002 0x2b 0x10003 0x33 0x10004 0x3b 0x10005 0x43 0x10006 0x4b 0x10007 0x55 0x10008 0x5d 0x10009 0x67 0x1000a 0x70 0x20000 0x17 0x20001 0x23 0x20002 0x2d 0x20003 0x37 0x20004 0x41 0x20005 0x4b 0x20006 0x57 0x20007 0x63 0x20008 0x6f 0x30000 0x15 0x30001 0x21 0x30002 0x2d 0x30003 0x39 0x30004 0x45 0x30005 0x53 0x30006 0x5f 0x30007 0x71>; + #thermal-sensor-cells = <0x00>; + phandle = <0x0c>; + + throttle-cfgs { + + devfreq { + throttle,max_state = <0x02>; + #cooling-cells = <0x02>; + phandle = <0x0e>; + }; + }; + }; + + watchdog@30280000 { + compatible = "fsl,imx8mq-wdt\0fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <0x00 0x4e 0x04>; + clocks = <0x02 0xd4>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x12>; + fsl,ext-reset-output; + }; + + watchdog@30290000 { + compatible = "fsl,imx8mq-wdt\0fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <0x00 0x4f 0x04>; + clocks = <0x02 0xd5>; + status = "disabled"; + }; + + watchdog@302a0000 { + compatible = "fsl,imx8mq-wdt\0fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <0x00 0x0a 0x04>; + clocks = <0x02 0xd6>; + status = "disabled"; + }; + + sdma@302c0000 { + compatible = "fsl,imx8mq-sdma\0fsl,imx7d-sdma"; + reg = <0x302c0000 0x10000>; + interrupts = <0x00 0x67 0x04>; + clocks = <0x02 0xe4 0x02 0xe4>; + clock-names = "ipg\0ahb"; + #dma-cells = <0x03>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + phandle = <0x10>; + }; + + lcdif@30320000 { + compatible = "fsl,imx8mq-lcdif\0fsl,imx28-lcdif"; + reg = <0x30320000 0x10000>; + clocks = <0x02 0x80>; + clock-names = "pix"; + assigned-clocks = <0x02 0x80 0x02 0x24 0x02 0x21>; + assigned-clock-parents = <0x02 0x25 0x02 0x23 0x02 0x03>; + interrupts = <0x00 0x05 0x04>; + status = "disabled"; + }; + + iomuxc@30330000 { + compatible = "fsl,imx8mq-iomuxc"; + reg = <0x30330000 0x10000>; + pinctrl-names = "default"; + pinctrl-0 = <0x13>; + phandle = <0x11>; + + imx8mq-evk { + + gpio_ledsgrp { + fsl,pins = <0x3c 0x2a4 0x00 0x00 0x00 0x19 0x48 0x2b0 0x00 0x00 0x00 0x19>; + phandle = <0x53>; + }; + + gpio_keysgrp { + fsl,pins = <0x110 0x378 0x00 0x05 0x00 0x56 0x10c 0x374 0x00 0x05 0x00 0x56>; + phandle = <0x54>; + }; + + uart1grp { + fsl,pins = <0x234 0x49c 0x4f4 0x00 0x00 0x49 0x238 0x4a0 0x00 0x00 0x00 0x49>; + phandle = <0x24>; + }; + + uart4grp { + fsl,pins = <0x24c 0x4b4 0x50c 0x00 0x02 0x49 0x250 0x4b8 0x00 0x00 0x00 0x49 0x210 0x478 0x508 0x01 0x01 0x49 0x20c 0x474 0x00 0x01 0x00 0x49 0x208 0x470 0x00 0x05 0x00 0x19>; + phandle = <0x36>; + }; + + wlangrp { + fsl,pins = <0xec 0x354 0x00 0x05 0x00 0x19 0xd0 0x338 0x00 0x05 0x00 0x19 0x28 0x290 0x00 0x05 0x00 0x05>; + phandle = <0x57>; + }; + + reg3V3wfgrp { + fsl,pins = <0xf0 0x358 0x00 0x05 0x00 0x19>; + phandle = <0x56>; + }; + + usdhc1grp { + fsl,pins = <0xa0 0x308 0x00 0x00 0x00 0x83 0xa4 0x30c 0x00 0x00 0x00 0xc3 0xa8 0x310 0x00 0x00 0x00 0xc3 0xac 0x314 0x00 0x00 0x00 0xc3 0xb0 0x318 0x00 0x00 0x00 0xc3 0xb4 0x31c 0x00 0x00 0x00 0xc3 0x40 0x2a8 0x00 0x00 0x00 0x19>; + phandle = <0x3d>; + }; + + usdhc1grp100mhz { + fsl,pins = <0xa0 0x308 0x00 0x00 0x00 0x85 0xa4 0x30c 0x00 0x00 0x00 0xc5 0xa8 0x310 0x00 0x00 0x00 0xc5 0xac 0x314 0x00 0x00 0x00 0xc5 0xb0 0x318 0x00 0x00 0x00 0xc5 0xb4 0x31c 0x00 0x00 0x00 0xc5 0x40 0x2a8 0x00 0x00 0x00 0x19>; + phandle = <0x3e>; + }; + + usdhc1grp200mhz { + fsl,pins = <0xa0 0x308 0x00 0x00 0x00 0x87 0xa4 0x30c 0x00 0x00 0x00 0xc7 0xa8 0x310 0x00 0x00 0x00 0xc7 0xac 0x314 0x00 0x00 0x00 0xc7 0xb0 0x318 0x00 0x00 0x00 0xc7 0xb4 0x31c 0x00 0x00 0x00 0xc7 0x40 0x2a8 0x00 0x00 0x00 0x19>; + phandle = <0x3f>; + }; + + usdhc2grp { + fsl,pins = <0xd4 0x33c 0x00 0x00 0x00 0x83 0xd8 0x340 0x00 0x00 0x00 0xc3 0xdc 0x344 0x00 0x00 0x00 0xc3 0xe0 0x348 0x00 0x00 0x00 0xc3 0xe4 0x34c 0x00 0x00 0x00 0xc3 0xe8 0x350 0x00 0x00 0x00 0xc3>; + phandle = <0x40>; + }; + + i2c1grp { + fsl,pins = <0x214 0x47c 0x00 0x00 0x00 0x4000007f 0x218 0x480 0x00 0x00 0x00 0x4000007f>; + phandle = <0x2b>; + }; + + i2c4grp { + fsl,pins = <0x22c 0x494 0x00 0x00 0x00 0x4000007f 0x230 0x498 0x00 0x00 0x00 0x4000007f>; + phandle = <0x35>; + }; + + csi1grp { + fsl,pins = <0x13c 0x3a4 0x00 0x05 0x00 0x19 0x12c 0x394 0x00 0x05 0x00 0x19>; + phandle = <0x2f>; + }; + + pmicirq { + fsl,pins = <0x44 0x2ac 0x00 0x00 0x00 0x19>; + phandle = <0x2c>; + }; + + wdoggrp { + fsl,pins = <0x30 0x298 0x00 0x01 0x00 0xc6>; + phandle = <0x12>; + }; + + fec1grp { + fsl,pins = <0x68 0x2d0 0x00 0x00 0x00 0x03 0x6c 0x2d4 0x4c0 0x00 0x01 0x23 0x70 0x2d8 0x00 0x00 0x00 0x1f 0x74 0x2dc 0x00 0x00 0x00 0x1f 0x78 0x2e0 0x00 0x00 0x00 0x1f 0x7c 0x2e4 0x00 0x00 0x00 0x1f 0x9c 0x304 0x00 0x00 0x00 0x91 0x98 0x300 0x00 0x00 0x00 0x91 0x94 0x2fc 0x00 0x00 0x00 0x91 0x90 0x2f8 0x00 0x00 0x00 0x91 0x84 0x2ec 0x00 0x00 0x00 0x1f 0x8c 0x2f4 0x00 0x00 0x00 0x91 0x88 0x2f0 0x00 0x00 0x00 0x91 0x80 0x2e8 0x00 0x00 0x00 0x1f 0x4c 0x2b4 0x00 0x00 0x00 0x19>; + phandle = <0x46>; + }; + + hoggrp { + fsl,pins = <0x134 0x39c 0x00 0x05 0x00 0x19 0x138 0x3a0 0x00 0x05 0x00 0x19 0x114 0x37c 0x00 0x05 0x00 0x19 0x118 0x380 0x00 0x05 0x00 0x19 0x130 0x398 0x00 0x05 0x00 0x19 0x34 0x29c 0x00 0x00 0x00 0x19 0x120 0x388 0x00 0x05 0x00 0x19 0xfc 0x364 0x00 0x05 0x00 0x19 0x108 0x370 0x00 0x05 0x00 0x19 0x11c 0x384 0x00 0x05 0x00 0x19>; + phandle = <0x13>; + }; + + ecspi1grp { + fsl,pins = <0x200 0x468 0x00 0x05 0x00 0x19 0x1f8 0x460 0x00 0x00 0x00 0x19 0x1fc 0x464 0x00 0x00 0x00 0x19 0x1f4 0x45c 0x00 0x00 0x00 0x19>; + phandle = <0x22>; + }; + + i2c2grp { + fsl,pins = <0x21c 0x484 0x00 0x00 0x00 0x4000007f 0x220 0x488 0x00 0x00 0x00 0x4000007f>; + phandle = <0x32>; + }; + + i2c3grp { + fsl,pins = <0x224 0x48c 0x00 0x00 0x00 0x4000007f 0x228 0x490 0x00 0x00 0x00 0x4000007f>; + phandle = <0x34>; + }; + + uart2grp { + fsl,pins = <0x23c 0x4a4 0x4fc 0x00 0x00 0x49 0x240 0x4a8 0x00 0x00 0x00 0x49>; + phandle = <0x25>; + }; + + pwm2_grp { + fsl,pins = <0x5c 0x2c4 0x00 0x05 0x00 0x06>; + phandle = <0x1f>; + }; + + pwm4_grp { + fsl,pins = <0x64 0x2cc 0x00 0x05 0x00 0x06>; + phandle = <0x20>; + }; + + sai2grp { + fsl,pins = <0x1bc 0x424 0x00 0x00 0x00 0xd6 0x1c0 0x428 0x00 0x00 0x00 0xd6 0x1b8 0x420 0x00 0x00 0x00 0xd6 0x1c4 0x42c 0x00 0x00 0x00 0xd6>; + phandle = <0x26>; + }; + }; + }; + + syscon@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr\0fsl,imx6q-iomuxc-gpr\0syscon\0simple-mfd"; + reg = <0x30340000 0x10000>; + phandle = <0x39>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0x01>; + mux-reg-masks = <0x34 0x04>; + phandle = <0x29>; + }; + }; + + ocotp-ctrl@30350000 { + compatible = "fsl,imx8mq-ocotp\0syscon"; + reg = <0x30350000 0x10000>; + clocks = <0x02 0xfa>; + #address-cells = <0x01>; + #size-cells = <0x01>; + + speed-grade@10 { + reg = <0x10 0x04>; + phandle = <0x05>; + }; + + mac-address@640 { + reg = <0x90 0x06>; + phandle = <0x45>; + }; + }; + + syscon@30360000 { + compatible = "fsl,imx8mq-anatop\0syscon"; + reg = <0x30360000 0x10000>; + interrupts = <0x00 0x31 0x04>; + }; + + caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0x00 0x14 0x04>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + + snvs@30370000 { + compatible = "fsl,sec-v4.0-mon\0syscon\0simple-mfd"; + reg = <0x30370000 0x10000>; + phandle = <0x14>; + + snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <0x14>; + offset = <0x34>; + interrupts = <0x00 0x13 0x04 0x00 0x14 0x04>; + clocks = <0x02 0x108>; + clock-names = "snvs-rtc"; + }; + + snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <0x14>; + interrupts = <0x00 0x04 0x04>; + clocks = <0x02 0x108>; + clock-names = "snvs"; + linux,keycode = <0x74>; + wakeup-source; + status = "okay"; + }; + }; + + clock-controller@30380000 { + compatible = "fsl,imx8mq-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <0x00 0x55 0x04 0x00 0x56 0x04>; + #clock-cells = <0x01>; + clocks = <0x15 0x16 0x17 0x18 0x19 0x1a 0x1b>; + clock-names = "ckil\0osc_25m\0osc_27m\0clk_ext1\0clk_ext2\0clk_ext3\0clk_ext4"; + assigned-clocks = <0x02 0x69 0x02 0x75 0x02 0x19 0x02 0x1e>; + assigned-clock-parents = <0x02 0x4c 0x02 0x56>; + assigned-clock-rates = <0x00 0x00 0x2ee00000 0x2b110000>; + phandle = <0x02>; + }; + + reset-controller@30390000 { + compatible = "fsl,imx8mq-src\0syscon"; + reg = <0x30390000 0x10000>; + #reset-cells = <0x01>; + phandle = <0x28>; + }; + + gpc@303a0000 { + compatible = "fsl,imx8mq-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <0x07>; + interrupt-controller; + broken-wake-request-signals; + #interrupt-cells = <0x03>; + phandle = <0x01>; + + pgc { + #address-cells = <0x01>; + #size-cells = <0x00>; + + power-domain@0 { + #power-domain-cells = <0x00>; + reg = <0x00>; + phandle = <0x27>; + }; + + power-domain@1 { + #power-domain-cells = <0x00>; + reg = <0x01>; + power-domains = <0x1c>; + phandle = <0x50>; + }; + + power-domain@2 { + #power-domain-cells = <0x00>; + reg = <0x02>; + }; + + power-domain@3 { + #power-domain-cells = <0x00>; + reg = <0x03>; + phandle = <0x4e>; + }; + + power-domain@4 { + #power-domain-cells = <0x00>; + reg = <0x04>; + }; + + power-domain@5 { + #power-domain-cells = <0x00>; + reg = <0x05>; + clocks = <0x02 0xd7 0x02 0x66 0x02 0x6f 0x02 0x70>; + power-supply = <0x1d>; + phandle = <0x4b>; + }; + + power-domain@6 { + #power-domain-cells = <0x00>; + reg = <0x06>; + power-supply = <0x1e>; + phandle = <0x51>; + }; + + power-domain@7 { + #power-domain-cells = <0x00>; + reg = <0x07>; + }; + + power-domain@8 { + #power-domain-cells = <0x00>; + reg = <0x08>; + phandle = <0x38>; + }; + + power-domain@9 { + #power-domain-cells = <0x00>; + reg = <0x09>; + phandle = <0x44>; + }; + + power-domain@a { + #power-domain-cells = <0x00>; + reg = <0x0a>; + phandle = <0x1c>; + }; + }; + }; + }; + + bus@30400000 { + compatible = "fsl,imx8mq-aips-bus\0simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x30400000 0x30400000 0x400000>; + + pwm@30660000 { + compatible = "fsl,imx8mq-pwm\0fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <0x00 0x51 0x04>; + clocks = <0x02 0xbf 0x02 0xbf>; + clock-names = "ipg\0per"; + #pwm-cells = <0x02>; + status = "disabled"; + }; + + pwm@30670000 { + compatible = "fsl,imx8mq-pwm\0fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <0x00 0x52 0x04>; + clocks = <0x02 0xc0 0x02 0xc0>; + clock-names = "ipg\0per"; + #pwm-cells = <0x02>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x1f>; + }; + + pwm@30680000 { + compatible = "fsl,imx8mq-pwm\0fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <0x00 0x53 0x04>; + clocks = <0x02 0xc1 0x02 0xc1>; + clock-names = "ipg\0per"; + #pwm-cells = <0x02>; + status = "disabled"; + }; + + pwm@30690000 { + compatible = "fsl,imx8mq-pwm\0fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <0x00 0x54 0x04>; + clocks = <0x02 0xc2 0x02 0xc2>; + clock-names = "ipg\0per"; + #pwm-cells = <0x02>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x20>; + }; + + timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = <0x00 0x2f 0x04>; + clocks = <0x16>; + clock-names = "per"; + }; + }; + + bus@30800000 { + compatible = "fsl,imx8mq-aips-bus\0simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x30800000 0x30800000 0x400000 0x8000000 0x8000000 0x10000000>; + + spdif@30810000 { + compatible = "fsl,imx8mm-spdif\0fsl,imx35-spdif"; + reg = <0x30810000 0x10000>; + interrupts = <0x00 0x06 0x04>; + clocks = <0x02 0xec 0x02 0x02 0x02 0x87 0x02 0x00 0x02 0x00 0x02 0x00 0x02 0xec 0x02 0x00 0x02 0x00 0x02 0x00>; + clock-names = "core\0rxtx0\0rxtx1\0rxtx2\0rxtx3\0rxtx4\0rxtx5\0rxtx6\0rxtx7\0spba"; + dmas = <0x21 0x08 0x12 0x00 0x21 0x09 0x12 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + spi@30820000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "fsl,imx8mq-ecspi\0fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <0x00 0x1f 0x04>; + clocks = <0x02 0xb3 0x02 0xb3>; + clock-names = "ipg\0per"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x22>; + fsl,spi-num-chipselects = <0x01>; + cs-gpios = <0x23 0x09 0x00>; + + spidev@0 { + compatible = "fsl,spidev\0semtech,sx1301"; + reg = <0x00>; + spi-max-frequency = <0x1e8480>; + }; + }; + + spi@30830000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "fsl,imx8mq-ecspi\0fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <0x00 0x20 0x04>; + clocks = <0x02 0xb4 0x02 0xb4>; + clock-names = "ipg\0per"; + status = "disabled"; + }; + + spi@30840000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "fsl,imx8mq-ecspi\0fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <0x00 0x21 0x04>; + clocks = <0x02 0xb5 0x02 0xb5>; + clock-names = "ipg\0per"; + status = "disabled"; + }; + + serial@30860000 { + compatible = "fsl,imx8mq-uart\0fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <0x00 0x1a 0x04>; + clocks = <0x02 0xca 0x02 0xca>; + clock-names = "ipg\0per"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x24>; + assigned-clocks = <0x02 0x94>; + assigned-clock-parents = <0x02 0x02>; + }; + + serial@30880000 { + compatible = "fsl,imx8mq-uart\0fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <0x00 0x1c 0x04>; + clocks = <0x02 0xcc 0x02 0xcc>; + clock-names = "ipg\0per"; + status = "disabled"; + }; + + serial@30890000 { + compatible = "fsl,imx8mq-uart\0fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <0x00 0x1b 0x04>; + clocks = <0x02 0xcb 0x02 0xcb>; + clock-names = "ipg\0per"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x25>; + assigned-clocks = <0x02 0x95>; + assigned-clock-parents = <0x02 0x02>; + }; + + spdif@308a0000 { + compatible = "fsl,imx8mm-spdif\0fsl,imx35-spdif"; + reg = <0x308a0000 0x10000>; + interrupts = <0x00 0x0d 0x04>; + clocks = <0x02 0xec 0x02 0x02 0x02 0x88 0x02 0x00 0x02 0x00 0x02 0x00 0x02 0xec 0x02 0x00 0x02 0x00 0x02 0x00>; + clock-names = "core\0rxtx0\0rxtx1\0rxtx2\0rxtx3\0rxtx4\0rxtx5\0rxtx6\0rxtx7\0spba"; + dmas = <0x21 0x10 0x12 0x00 0x21 0x11 0x12 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + sai@308b0000 { + #sound-dai-cells = <0x00>; + compatible = "fsl,imx8mq-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <0x00 0x60 0x04>; + clocks = <0x02 0xef 0x02 0x00 0x02 0xc5 0x02 0x00 0x02 0x00>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3"; + dmas = <0x21 0x0a 0x18 0x00 0x21 0x0b 0x18 0x00>; + dma-names = "rx\0tx"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x26>; + assigned-clocks = <0x02 0x82>; + assigned-clock-parents = <0x02 0x1b>; + assigned-clock-rates = <0x1770000>; + phandle = <0x59>; + }; + + sai@308c0000 { + compatible = "fsl,imx8mq-sai\0fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <0x00 0x32 0x04>; + clocks = <0x02 0xf0 0x02 0x00 0x02 0xc6 0x02 0x00 0x02 0x00>; + clock-names = "bus\0mclk0\0mclk1\0mclk2\0mclk3"; + dmas = <0x21 0x0c 0x18 0x00 0x21 0x0d 0x18 0x00>; + dma-names = "rx\0tx"; + status = "disabled"; + }; + + crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <0x01>; + #size-cells = <0x01>; + reg = <0x30900000 0x40000>; + ranges = <0x00 0x30900000 0x40000>; + interrupts = <0x00 0x5b 0x04>; + clocks = <0x02 0x74 0x02 0xec>; + clock-names = "aclk\0ipg"; + + jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <0x00 0x69 0x04>; + }; + + jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <0x00 0x6a 0x04>; + }; + + jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <0x00 0x72 0x04>; + }; + }; + + dphy@30a00300 { + compatible = "fsl,imx8mq-mipi-dphy"; + reg = <0x30a00300 0x100>; + clocks = <0x02 0xa4>; + clock-names = "phy_ref"; + assigned-clocks = <0x02 0xa4>; + assigned-clock-parents = <0x02 0x25>; + assigned-clock-rates = <0x16e3600>; + #phy-cells = <0x00>; + power-domains = <0x27>; + status = "disabled"; + phandle = <0x2a>; + }; + + mipi_dsi@30a00000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30a00000 0x300>; + clocks = <0x02 0xa3 0x02 0xf4 0x02 0xf5 0x02 0xa4 0x02 0x23 0x02 0x80>; + clock-names = "core\0rx_esc\0tx_esc\0phy_ref\0video_pll\0lcdif"; + assigned-clocks = <0x02 0xa4 0x02 0xa3 0x02 0xf4 0x02 0xf5>; + assigned-clock-parents = <0x02 0x25 0x02 0x4c 0x02 0x47>; + assigned-clock-rates = <0x19bfcc0 0xfdad680 0x4c4b400 0x1312d00>; + interrupts = <0x00 0x22 0x04>; + power-domains = <0x27>; + resets = <0x28 0x15 0x28 0x17 0x28 0x18 0x28 0x19>; + reset-names = "byte\0dpi\0esc\0pclk"; + mux-controls = <0x29 0x00>; + phys = <0x2a>; + phy-names = "dphy"; + status = "disabled"; + }; + + i2c@30a20000 { + compatible = "fsl,imx8mq-i2c\0fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <0x00 0x23 0x04>; + clocks = <0x02 0xb8>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + clock-frequency = <0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x2b>; + + pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <0x2c>; + clocks = <0x2d>; + clock-names = "osc"; + clock-output-names = "pmic_clk"; + interrupt-parent = <0x2e>; + interrupts = <0x07 0x01>; + interrupt-names = "irq"; + rohm,reset-snvs-powered; + + regulators { + + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <0xaae60>; + regulator-max-microvolt = <0x13d620>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <0x4e2>; + rohm,dvs-run-voltage = <0xdbba0>; + rohm,dvs-idle-voltage = <0xcf850>; + rohm,dvs-suspend-voltage = <0xc3500>; + }; + + BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <0xaae60>; + regulator-max-microvolt = <0x13d620>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <0x4e2>; + rohm,dvs-run-voltage = <0xf4240>; + rohm,dvs-idle-voltage = <0xdbba0>; + }; + + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <0xaae60>; + regulator-max-microvolt = <0x13d620>; + regulator-boot-on; + rohm,dvs-run-voltage = <0xf4240>; + regulator-enable-ramp-delay = <0xb4>; + phandle = <0x1d>; + }; + + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <0xaae60>; + regulator-max-microvolt = <0x13d620>; + rohm,dvs-run-voltage = <0xf4240>; + regulator-boot-on; + regulator-enable-ramp-delay = <0xb4>; + phandle = <0x1e>; + }; + + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <0x2dc6c0>; + regulator-max-microvolt = <0x325aa0>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1cfde0>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <0x124f80>; + regulator-max-microvolt = <0x13d620>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <0x2dc6c0>; + regulator-max-microvolt = <0x325aa0>; + regulator-boot-on; + regulator-always-on; + }; + + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xdbba0>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <0x1b7740>; + regulator-max-microvolt = <0x1cfde0>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <0x2625a0>; + regulator-max-microvolt = <0x27ac40>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <0xdbba0>; + regulator-max-microvolt = <0xf4240>; + regulator-boot-on; + regulator-always-on; + }; + + LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <0x2dc6c0>; + regulator-max-microvolt = <0x325aa0>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x2f>; + clocks = <0x02 0xff>; + clock-names = "csi_mclk"; + csi_id = <0x00>; + pwn-gpios = <0x30 0x0e 0x00>; + rst-gpios = <0x30 0x12 0x00>; + mclk = <0x16e3600>; + mclk_source = <0x00>; + + port { + + endpoint { + remote-endpoint = <0x31>; + phandle = <0x3a>; + }; + }; + }; + }; + + i2c@30a30000 { + compatible = "fsl,imx8mq-i2c\0fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <0x00 0x24 0x04>; + clocks = <0x02 0xb9>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + clock-frequency = <0x61a80>; + pinctrl-names = "default"; + pinctrl-0 = <0x32>; + + wm8960@1a { + #sound-dai-cells = <0x00>; + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <0x33>; + clock-names = "mclk"; + wlf,shared-lrclk; + phandle = <0x5a>; + }; + }; + + i2c@30a40000 { + compatible = "fsl,imx8mq-i2c\0fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <0x00 0x25 0x04>; + clocks = <0x02 0xba>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "okay"; + clock-frequency = <0x186a0>; + pinctrl-names = "default"; + pinctrl-0 = <0x34>; + }; + + i2c@30a50000 { + compatible = "fsl,imx8mq-i2c\0fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <0x00 0x26 0x04>; + clocks = <0x02 0xbb>; + #address-cells = <0x01>; + #size-cells = <0x00>; + status = "disabled"; + clock-frequency = <0x61a80>; + pinctrl-names = "default"; + pinctrl-0 = <0x35>; + }; + + serial@30a60000 { + compatible = "fsl,imx8mq-uart\0fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <0x00 0x1d 0x04>; + clocks = <0x02 0xcd 0x02 0xcd>; + clock-names = "ipg\0per"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x36>; + assigned-clocks = <0x02 0x97>; + assigned-clock-parents = <0x02 0x47>; + fsl,uart-has-rtscts; + resets = <0x37>; + }; + + mipi_csi1@30a70000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30a70000 0x1000>; + interrupts = <0x00 0x2c 0x04>; + clocks = <0x02 0xa7 0x02 0xa9 0x02 0xa8>; + clock-names = "clk_core\0clk_esc\0clk_pxl"; + assigned-clocks = <0x02 0xa7 0x02 0xa8 0x02 0xa9>; + assigned-clock-rates = <0x7ed6b40 0x5f5e100 0x3ef1480>; + power-domains = <0x38>; + csis-phy-reset = <0x28 0x4c 0x07>; + phy-gpr = <0x39 0x88>; + status = "okay"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + port { + + endpoint@0 { + remote-endpoint = <0x3a>; + data-lanes = <0x01 0x02>; + bus-type = <0x04>; + phandle = <0x31>; + }; + + endpoint@1 { + remote-endpoint = <0x3b>; + phandle = <0x3c>; + }; + }; + }; + + csi1_bridge@30a90000 { + compatible = "fsl,imx8mq-csi\0fsl,imx6s-csi"; + reg = <0x30a90000 0x10000>; + interrupts = <0x00 0x2a 0x04>; + clocks = <0x02 0x00 0x02 0xe0 0x02 0x00>; + clock-names = "disp-axi\0csi_mclk\0disp_dcic"; + status = "okay"; + fsl,mipi-mode; + fsl,two-8bit-sensor-mode; + + port { + + endpoint { + remote-endpoint = <0x3c>; + phandle = <0x3b>; + }; + }; + }; + + mu@30aa0000 { + compatible = "fsl,imx8mq-mu\0fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <0x00 0x58 0x04>; + clocks = <0x02 0xfd>; + clock-names = "mu"; + #mbox-cells = <0x02>; + phandle = <0x52>; + }; + + mmc@30b40000 { + compatible = "fsl,imx8mq-usdhc\0fsl,imx7d-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <0x00 0x16 0x04>; + clocks = <0x02 0xec 0x02 0x69 0x02 0xd2>; + clock-names = "ipg\0ahb\0per"; + assigned-clocks = <0x02 0x8e>; + assigned-clock-rates = <0x17d78400>; + fsl,tuning-start-tap = <0x14>; + fsl,tuning-step = <0x02>; + bus-width = <0x04>; + status = "okay"; + pinctrl-names = "default\0state_100mhz\0state_200mhz"; + pinctrl-0 = <0x3d>; + pinctrl-1 = <0x3e>; + pinctrl-2 = <0x3f>; + non-removable; + no-sdio; + no-1-8-v; + }; + + mmc@30b50000 { + compatible = "fsl,imx8mq-usdhc\0fsl,imx7d-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <0x00 0x17 0x04>; + clocks = <0x02 0xec 0x02 0x69 0x02 0xd3>; + clock-names = "ipg\0ahb\0per"; + fsl,tuning-start-tap = <0x14>; + fsl,tuning-step = <0x02>; + bus-width = <0x04>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x40>; + vmmc-supply = <0x41>; + mmc-pwrseq = <0x42>; + no-1-8-v; + non-removable; + pm-ignore-notify; + keep-power-in-suspend; + #address-cells = <0x01>; + #size-cells = <0x00>; + + bcrmf@1 { + reg = <0x01>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <0x43>; + interrupts = <0x0c 0x08>; + interrupt-names = "host-wake"; + }; + }; + + mipi_csi2@30b60000 { + compatible = "fsl,mxc-mipi-csi2_yav"; + reg = <0x30b60000 0x1000>; + interrupts = <0x00 0x2d 0x04>; + clocks = <0x02 0xaa 0x02 0xac 0x02 0xab>; + clock-names = "clk_core\0clk_esc\0clk_pxl"; + assigned-clocks = <0x02 0xaa 0x02 0xab 0x02 0xac>; + assigned-clock-rates = <0x7ed6b40 0x5f5e100 0x3ef1480>; + power-domains = <0x44>; + csis-phy-reset = <0x28 0x50 0x07>; + phy-gpr = <0x39 0xa4>; + status = "disabled"; + }; + + csi2_bridge@30b80000 { + compatible = "fsl,imx8mq-csi\0fsl,imx6s-csi"; + reg = <0x30b80000 0x10000>; + interrupts = <0x00 0x2b 0x04>; + clocks = <0x02 0x00 0x02 0xe1 0x02 0x00>; + clock-names = "disp-axi\0csi_mclk\0disp_dcic"; + status = "disabled"; + }; + + spi@30bb0000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "fsl,imx8mq-qspi\0fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000 0x8000000 0x10000000>; + reg-names = "QuadSPI\0QuadSPI-memory"; + interrupts = <0x00 0x6b 0x04>; + clocks = <0x02 0xc3 0x02 0xc3>; + clock-names = "qspi_en\0qspi"; + status = "disabled"; + }; + + sdma@30bd0000 { + compatible = "fsl,imx8mq-sdma\0fsl,imx7d-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = <0x00 0x02 0x04>; + clocks = <0x02 0xe3 0x02 0x74>; + clock-names = "ipg\0ahb"; + #dma-cells = <0x03>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + phandle = <0x21>; + }; + + ethernet@30be0000 { + compatible = "fsl,imx8mq-fec\0fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <0x00 0x76 0x04 0x00 0x77 0x04 0x00 0x78 0x04>; + clocks = <0x02 0xb6 0x02 0xb6 0x02 0x8a 0x02 0x89 0x02 0x8b>; + clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out"; + fsl,num-tx-queues = <0x03>; + fsl,num-rx-queues = <0x03>; + nvmem-cells = <0x45>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <0x39 0x10 0x03>; + fsl,wakeup_irq = <0x02>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <0x46>; + phy-mode = "rgmii-id"; + phy-handle = <0x47>; + fsl,magic-packet; + phy-reset-gpios = <0x2e 0x09 0x01>; + + mdio { + #address-cells = <0x01>; + #size-cells = <0x00>; + + ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x04>; + at803x,eee-disabled; + phandle = <0x47>; + }; + }; + }; + }; + + bus@32c00000 { + compatible = "fsl,imx8mq-aips-bus\0simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges = <0x32c00000 0x32c00000 0x400000>; + + hdmi@32c00000 { + reg = <0x32c00000 0x100000 0x32e40000 0x40000>; + interrupts = <0x00 0x10 0x04 0x00 0x19 0x04>; + interrupt-names = "plug_in\0plug_out"; + compatible = "cdn,imx8mq-hdmi"; + lane-mapping = <0xe4>; + status = "okay"; + + port@1 { + + endpoint { + remote-endpoint = <0x48>; + phandle = <0x4a>; + }; + }; + }; + + interrupt-controller@32e2d000 { + compatible = "fsl,imx8m-irqsteer\0fsl,imx-irqsteer"; + reg = <0x32e2d000 0x1000>; + interrupts = <0x00 0x12 0x04>; + clocks = <0x02 0xf8>; + clock-names = "ipg"; + fsl,channel = <0x00>; + fsl,num-irqs = <0x40>; + interrupt-controller; + #interrupt-cells = <0x01>; + status = "okay"; + phandle = <0x49>; + }; + + display-controller@32e00000 { + #address-cells = <0x01>; + #size-cells = <0x00>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000 0x32e2f000 0x1000>; + interrupts = <0x06 0x08 0x09 0x10 0x11>; + interrupt-names = "ctx_ld\0ctxld_kick\0vblank\0dtrc_ch1\0dtrc_ch2"; + interrupt-parent = <0x49>; + clocks = <0x02 0xf8 0x02 0xf7 0x02 0xf9 0x02 0xfe 0x02 0x7a 0x02 0x10a 0x02 0x10b>; + clock-names = "apb\0axi\0rtrm\0pix\0dtrc\0pll_src\0pll_phy_ref"; + assigned-clocks = <0x02 0x6b 0x02 0x6d 0x02 0x10a>; + assigned-clock-parents = <0x02 0x4e 0x02 0x4e 0x02 0x03>; + assigned-clock-rates = <0x2faf0800 0x17d78400>; + status = "okay"; + + port@0 { + + endpoint { + remote-endpoint = <0x4a>; + phandle = <0x48>; + }; + }; + }; + }; + + gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x40000>; + interrupts = <0x00 0x03 0x04>; + clocks = <0x02 0xd7 0x02 0x66 0x02 0x6f 0x02 0x70>; + clock-names = "core\0shader\0bus\0reg"; + assigned-clocks = <0x02 0x61 0x02 0x64 0x02 0x6f 0x02 0x70 0x02 0x10>; + assigned-clock-parents = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x0f>; + assigned-clock-rates = <0x2faf0800 0x2faf0800 0x2faf0800 0x2faf0800 0x00>; + power-domains = <0x4b>; + status = "disabled"; + }; + + usb@38100000 { + compatible = "fsl,imx8mq-dwc3\0snps,dwc3"; + reg = <0x38100000 0x10000>; + clocks = <0x02 0xce 0x02 0x98 0x02 0x01>; + clock-names = "bus_early\0ref\0suspend"; + assigned-clocks = <0x02 0x6e 0x02 0x98>; + assigned-clock-parents = <0x02 0x56 0x02 0x48>; + assigned-clock-rates = <0x1dcd6500 0x5f5e100>; + interrupts = <0x00 0x28 0x04>; + phys = <0x4c 0x4c>; + phy-names = "usb2-phy\0usb3-phy"; + usb3-resume-missing-cas; + snps,power-down-scale = <0x02>; + status = "okay"; + dr_mode = "host"; + }; + + usb-phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x381f0040 0x40>; + clocks = <0x02 0xd0>; + clock-names = "phy"; + assigned-clocks = <0x02 0x99>; + assigned-clock-parents = <0x02 0x48>; + assigned-clock-rates = <0x5f5e100>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x4c>; + }; + + usb@38200000 { + compatible = "fsl,imx8mq-dwc3\0snps,dwc3"; + reg = <0x38200000 0x10000>; + clocks = <0x02 0xcf 0x02 0x98 0x02 0x01>; + clock-names = "bus_early\0ref\0suspend"; + assigned-clocks = <0x02 0x6e 0x02 0x98>; + assigned-clock-parents = <0x02 0x56 0x02 0x48>; + assigned-clock-rates = <0x1dcd6500 0x5f5e100>; + interrupts = <0x00 0x29 0x04>; + phys = <0x4d 0x4d>; + phy-names = "usb2-phy\0usb3-phy"; + power-domains = <0x4e>; + usb3-resume-missing-cas; + snps,power-down-scale = <0x02>; + status = "okay"; + dr_mode = "host"; + }; + + usb-phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x382f0040 0x40>; + clocks = <0x02 0xd1>; + clock-names = "phy"; + assigned-clocks = <0x02 0x99>; + assigned-clock-parents = <0x02 0x48>; + assigned-clock-rates = <0x5f5e100>; + #phy-cells = <0x00>; + status = "okay"; + phandle = <0x4d>; + }; + + dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh\0fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <0x00 0x0c 0x04 0x00 0x0c 0x04 0x00 0x0c 0x04 0x00 0x0c 0x04>; + interrupt-names = "gpmi0\0gpmi1\0gpmi2\0gpmi3"; + #dma-cells = <0x01>; + dma-channels = <0x04>; + clocks = <0x02 0x100>; + phandle = <0x4f>; + }; + + gpmi-nand@33002000 { + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <0x01>; + #size-cells = <0x01>; + reg = <0x33002000 0x2000 0x33004000 0x4000>; + reg-names = "gpmi-nand\0bch"; + interrupts = <0x00 0x0e 0x04>; + interrupt-names = "bch"; + clocks = <0x02 0xe2 0x02 0x100>; + clock-names = "gpmi_io\0gpmi_bch_apb"; + dmas = <0x4f 0x00>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie@33800000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33800000 0x400000 0x1ff00000 0x80000>; + reg-names = "dbi\0config"; + #address-cells = <0x03>; + #size-cells = <0x02>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x00 0x1ff80000 0x00 0x10000 0x82000000 0x00 0x18000000 0x18000000 0x00 0x7f00000>; + num-lanes = <0x01>; + num-viewport = <0x04>; + interrupts = <0x00 0x7a 0x04 0x00 0x7f 0x04>; + interrupt-names = "msi\0dma"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x07 0x00 0x7d 0x04 0x00 0x00 0x00 0x02 0x07 0x00 0x7c 0x04 0x00 0x00 0x00 0x03 0x07 0x00 0x7b 0x04 0x00 0x00 0x00 0x04 0x07 0x00 0x7a 0x04>; + fsl,max-link-speed = <0x02>; + power-domains = <0x50>; + resets = <0x28 0x1a 0x28 0x1c 0x28 0x1d>; + reset-names = "pciephy\0apps\0turnoff"; + status = "disabled"; + }; + + pcie@33c00000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33c00000 0x400000 0x27f00000 0x80000>; + reg-names = "dbi\0config"; + #address-cells = <0x03>; + #size-cells = <0x02>; + device_type = "pci"; + ranges = <0x81000000 0x00 0x00 0x27f80000 0x00 0x10000 0x82000000 0x00 0x20000000 0x20000000 0x00 0x7f00000>; + num-lanes = <0x01>; + num-viewport = <0x04>; + interrupts = <0x00 0x4a 0x04 0x00 0x50 0x04>; + interrupt-names = "msi\0dma"; + #interrupt-cells = <0x01>; + interrupt-map-mask = <0x00 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x07 0x00 0x4d 0x04 0x00 0x00 0x00 0x02 0x07 0x00 0x4c 0x04 0x00 0x00 0x00 0x03 0x07 0x00 0x4b 0x04 0x00 0x00 0x00 0x04 0x07 0x00 0x4a 0x04>; + fsl,max-link-speed = <0x02>; + power-domains = <0x50>; + resets = <0x28 0x22 0x28 0x24 0x28 0x25>; + reset-names = "pciephy\0apps\0turnoff"; + status = "disabled"; + }; + + interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x38800000 0x10000 0x38880000 0xc0000 0x31000000 0x2000 0x31010000 0x2000 0x31020000 0x2000>; + #interrupt-cells = <0x03>; + interrupt-controller; + interrupts = <0x01 0x09 0x04>; + interrupt-parent = <0x07>; + phandle = <0x07>; + }; + + ddr-pmu@3d800000 { + compatible = "fsl,imx8mq-ddr-pmu\0fsl,imx8m-ddr-pmu"; + reg = <0x3d800000 0x400000>; + interrupt-parent = <0x07>; + interrupts = <0x00 0x62 0x04>; + }; + + vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x38300000 0x200000>; + reg-names = "regs_hantro"; + interrupts = <0x00 0x07 0x04 0x00 0x08 0x04>; + interrupt-names = "irq_hantro_g1\0irq_hantro_g2"; + clocks = <0x02 0xe5 0x02 0xe6 0x02 0xdf>; + clock-names = "clk_hantro_g1\0clk_hantro_g2\0clk_hantro_bus"; + assigned-clocks = <0x02 0x78 0x02 0x79 0x02 0x6a>; + assigned-clock-parents = <0x02 0x16 0x02 0x16 0x02 0x4e>; + assigned-clock-rates = <0x23c34600 0x23c34600 0x2faf0800>; + power-domains = <0x51>; + status = "okay"; + }; + }; + + gpu3d@38000000 { + compatible = "fsl,imx8mq-gpu\0fsl,imx6q-gpu"; + reg = <0x00 0x38000000 0x00 0x40000 0x00 0x40000000 0x00 0xc0000000 0x00 0x00 0x00 0x10000000>; + reg-names = "iobase_3d\0phys_baseaddr\0contiguous_mem"; + interrupts = <0x00 0x03 0x04>; + interrupt-names = "irq_3d"; + clocks = <0x02 0xd7 0x02 0x66 0x02 0x6f 0x02 0x70>; + clock-names = "gpu3d_clk\0gpu3d_shader_clk\0gpu3d_axi_clk\0gpu3d_ahb_clk"; + assigned-clocks = <0x02 0x61 0x02 0x64 0x02 0x6f 0x02 0x70>; + assigned-clock-parents = <0x02 0x11 0x02 0x11 0x02 0x11 0x02 0x11>; + assigned-clock-rates = <0x2faf0800 0x2faf0800 0x2faf0800 0x2faf0800>; + power-domains = <0x4b>; + status = "okay"; + }; + + rpmsg { + compatible = "fsl,imx8mq-rpmsg"; + mbox-names = "tx\0rx\0rxdb"; + mboxes = <0x52 0x00 0x01 0x52 0x01 0x01 0x52 0x03 0x01>; + status = "disabled"; + }; + + chosen { + stdout-path = "/soc@0/bus@30800000/serial@30860000"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x00 0x40000000 0x00 0x80000000>; + }; + + reserved-memory { + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x3c000000>; + alloc-ranges = <0x00 0x40000000 0x00 0x40000000>; + linux,cma-default; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <0x53>; + status = "okay"; + + sys_led { + label = "sys_led"; + gpios = <0x2e 0x05 0x00>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + usr_led { + label = "usr_led"; + gpios = <0x2e 0x08 0x00>; + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <0x54>; + + home { + label = "home Button"; + gpios = <0x30 0x07 0x01>; + linux,code = <0x66>; + gpio-key,wakeup; + }; + + back { + label = "back Button"; + gpios = <0x30 0x06 0x01>; + linux,code = <0x19c>; + }; + }; + + gpiomem { + compatible = "maaxboard,maaxboard-gpiomem"; + status = "okay"; + }; + + sound-hdmi { + compatible = "fsl,imx8mq-evk-cdnhdmi\0fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <0x55>; + protocol = <0x01>; + hdmi-out; + constraint-rate = <0xac44 0x15888 0x2b110 0x7d00 0xbb80 0x17700 0x2ee00>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <0x01>; + #size-cells = <0x00>; + + regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01>; + pinctrl-names = "default"; + pinctrl-0 = <0x56>; + regulator-name = "WF_3V3"; + regulator-min-microvolt = <0x325aa0>; + regulator-max-microvolt = <0x325aa0>; + gpio = <0x43 0x14 0x00>; + regulator-always-on; + enable-active-high; + phandle = <0x41>; + }; + }; + + sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <0x57>; + reset-gpios = <0x43 0x13 0x01>; + phandle = <0x42>; + }; + + bt_reset { + compatible = "gpio-reset"; + reset-gpios = <0x23 0x0b 0x01>; + reset-delay-us = <0x3e8>; + reset-post-delay-ms = <0x28>; + #reset-cells = <0x00>; + phandle = <0x37>; + }; + + clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x8000>; + clock-output-names = "pmic_osc"; + phandle = <0x2d>; + }; + + sound-wm8960 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8960-sound-audio"; + simple-audio-card,bitclock-master = <0x58>; + simple-audio-card,frame-master = <0x58>; + simple-audio-card,format = "i2s"; + status = "okay"; + simple-audio-card,widgets = "Microphone\0Mic Jack\0Line\0Line In\0Line\0Line Out\0Speaker\0Speaker\0Headphone\0Headphone Jack"; + simple-audio-card,routing = "Headphone Jack\0HP_L\0Headphone Jack\0HP_R\0Speaker\0SPK_LP\0Speaker\0SPK_LN\0Speaker\0SPK_RP\0Speaker\0SPK_RN\0LINPUT1\0Mic Jack\0LINPUT3\0Mic Jack\0RINPUT1\0Mic Jack\0RINPUT2\0Mic Jack\0Mic Jack\0MICB"; + + simple-audio-card,cpu { + sound-dai = <0x59>; + }; + + simple-audio-card,codec { + sound-dai = <0x5a>; + clocks = <0x33>; + phandle = <0x58>; + }; + }; + + wm8960_mclk { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "wm8960-mclk"; + phandle = <0x33>; + }; +};