From 74f82be0eb5f6fdd0af93b42fe1dcf6115104da2 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 8 Sep 2023 11:26:34 +0300 Subject: [PATCH] m2k: Remove dac last_sample_hold control axi_dac_interpolate - Remove last sample hold control axi_ad9963 - Remove last sample hold control and set as default the last sample hold functionality plus code optimization changes. --- library/axi_ad9963/axi_ad9963.v | 9 ------ library/axi_ad9963/axi_ad9963_if.v | 30 +++---------------- library/axi_ad9963/axi_ad9963_tx.v | 4 --- library/axi_ad9963/axi_ad9963_tx_channel.v | 3 -- .../axi_dac_interpolate/axi_dac_interpolate.v | 13 +++----- .../axi_dac_interpolate_reg.v | 29 ++++++++---------- projects/m2k/common/m2k_bd.tcl | 1 - 7 files changed, 20 insertions(+), 69 deletions(-) diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v index 0ed6b77e0c..c1b8455123 100644 --- a/library/axi_ad9963/axi_ad9963.v +++ b/library/axi_ad9963/axi_ad9963.v @@ -107,8 +107,6 @@ module axi_ad9963 #( input dma_valid_q, input dac_dunf, - input hold_last_sample, - // axi interface input s_axi_aclk, @@ -169,8 +167,6 @@ module axi_ad9963 #( wire up_rack_tx_s; wire up_adc_ce; wire up_dac_ce; - wire valid_out_q_s; - wire valid_out_i_s; // signal name changes @@ -208,10 +204,7 @@ module axi_ad9963 #( .adc_status (adc_status_s), .up_adc_ce(up_adc_ce), .dac_data (dac_data_s), - .out_valid_q (valid_out_q_s), - .out_valid_i (valid_out_i_s), .up_dac_ce(up_dac_ce), - .tx_sample_hold (hold_last_sample), .up_clk (up_clk), .up_adc_dld (up_adc_dld_s), .up_adc_dwdata (up_adc_dwdata_s), @@ -288,12 +281,10 @@ module axi_ad9963 #( .dac_valid_i (dac_valid_i), .dac_data_i (dac_data_i), .dma_valid_i (dma_valid_i), - .out_valid_i (valid_out_i_s), .dac_enable_q (dac_enable_q), .dac_valid_q (dac_valid_q), .dac_data_q (dac_data_q), .dma_valid_q (dma_valid_q), - .out_valid_q (valid_out_q_s), .dac_dunf(dac_dunf), .up_dac_ce(up_dac_ce), .up_rstn (up_rstn), diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v index 145f2aa2ed..de4e4f137e 100644 --- a/library/axi_ad9963/axi_ad9963_if.v +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -73,11 +73,8 @@ module axi_ad9963_if #( // transmit data path interface - input out_valid_q, - input out_valid_i, input [23:0] dac_data, input up_dac_ce, - input tx_sample_hold, // delay interface @@ -93,9 +90,6 @@ module axi_ad9963_if #( // internal registers reg [11:0] rx_data_p = 0; - reg [11:0] tx_data_p = 'd0; - reg [11:0] tx_data_n = 'd0; - reg [23:0] constant_sample = 'd0; // internal signals @@ -103,6 +97,8 @@ module axi_ad9963_if #( wire [11:0] rx_data_n_s; wire rx_iq_p_s; wire rx_iq_n_s; + wire [11:0] tx_data_p; + wire [11:0] tx_data_n; wire div_clk; @@ -119,26 +115,8 @@ module axi_ad9963_if #( end end - always @(posedge dac_clk) begin - if (dac_rst == 1'b1) begin - tx_data_p <= 24'd0; - tx_data_n <= 24'd0; - constant_sample <= 24'd0; - end else begin - if(out_valid_i == 1'b1) begin - tx_data_p <= dac_data[11: 0]; - constant_sample[11: 0] <= tx_sample_hold ? dac_data[11: 0] : 12'd0; - end else begin - tx_data_p <= constant_sample[11:0] ; - end - if(out_valid_q == 1'b1) begin - tx_data_n <= dac_data[23:12]; - constant_sample[23:12] <= tx_sample_hold ? dac_data[23:12] : 12'd0; - end else begin - tx_data_n <= constant_sample[23:12]; - end - end - end + assign tx_data_p = dac_data[11: 0]; + assign tx_data_n = dac_data[23:12]; always @(posedge adc_clk) begin if (adc_rst == 1'b1) begin diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v index a428345e9b..0fe50071ba 100644 --- a/library/axi_ad9963/axi_ad9963_tx.v +++ b/library/axi_ad9963/axi_ad9963_tx.v @@ -68,12 +68,10 @@ module axi_ad9963_tx #( output reg dac_valid_i, input [15:0] dac_data_i, input dma_valid_i, - output out_valid_i, output dac_enable_q, output reg dac_valid_q, input [15:0] dac_data_q, input dma_valid_q, - output out_valid_q, input dac_dunf, output up_dac_ce, @@ -147,7 +145,6 @@ module axi_ad9963_tx #( .dac_data_sync (dac_data_sync_s), .dac_dds_format (dac_dds_format_s), .dma_valid (dma_valid_i), - .out_data_valid (out_valid_i), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq), @@ -181,7 +178,6 @@ module axi_ad9963_tx #( .dac_data_sync (dac_data_sync_s), .dac_dds_format (dac_dds_format_s), .dma_valid (dma_valid_q), - .out_data_valid (out_valid_q), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq), diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v index 0db035e376..4eb549d816 100644 --- a/library/axi_ad9963/axi_ad9963_tx_channel.v +++ b/library/axi_ad9963/axi_ad9963_tx_channel.v @@ -58,7 +58,6 @@ module axi_ad9963_tx_channel #( output reg [11:0] dac_data_out, input [11:0] dac_data_in, input dma_valid, - output out_data_valid, // processor interface @@ -113,8 +112,6 @@ module axi_ad9963_tx_channel #( wire [15:0] dac_iqcor_coeff_1_s; wire [15:0] dac_iqcor_coeff_2_s; - assign out_data_valid = dac_iqcor_valid_s; - // dac iq correction always @(posedge dac_clk) begin diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v index 2077b10177..131893f206 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -58,7 +58,6 @@ module axi_dac_interpolate #( output [15:0] dac_int_data_b, output dac_valid_out_a, output dac_valid_out_b, - output hold_last_sample, output underflow, input [ 1:0] trigger_i, @@ -152,8 +151,7 @@ module axi_dac_interpolate #( wire underflow_a; wire underflow_b; - wire [ 1:0] lsample_hold_config; - wire sync_stop_channels; + wire stop_sync_channels; // signal name changes @@ -206,9 +204,6 @@ module axi_dac_interpolate #( low_level_trigger <= ~trigger_i_m3 & low_level; end - assign hold_last_sample = lsample_hold_config[0]; - assign sync_stop_channels = lsample_hold_config[1]; - assign underflow = underflow_a | underflow_b; axi_dac_interpolate_filter #( @@ -220,7 +215,7 @@ module axi_dac_interpolate #( .dac_data (dac_data_a), .dac_valid (dac_valid_a), .dac_valid_out (dac_valid_out_a), - .sync_stop_channels (sync_stop_channels), + .sync_stop_channels (stop_sync_channels), .dac_enable (dac_enable_a), .dac_int_data (dac_int_data_a), @@ -249,7 +244,7 @@ module axi_dac_interpolate #( .dac_data (dac_data_b), .dac_valid (dac_valid_b), .dac_valid_out (dac_valid_out_b), - .sync_stop_channels (sync_stop_channels), + .sync_stop_channels (stop_sync_channels), .underflow (underflow_b), .dac_enable (dac_enable_b), @@ -285,7 +280,7 @@ module axi_dac_interpolate #( .dac_correction_coefficient_a(dac_correction_coefficient_a), .dac_correction_coefficient_b(dac_correction_coefficient_b), .trigger_config (trigger_config), - .lsample_hold_config (lsample_hold_config), + .stop_sync_channels (stop_sync_channels), .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v index 01fecec1e8..f741c729a2 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate_reg.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate_reg.v @@ -45,12 +45,12 @@ module axi_dac_interpolate_reg( output [ 2:0] dac_filter_mask_b, output dma_transfer_suspend, output start_sync_channels, + output stop_sync_channels, output dac_correction_enable_a, output dac_correction_enable_b, output [15:0] dac_correction_coefficient_a, output [15:0] dac_correction_coefficient_b, output [19:0] trigger_config, - output [ 1:0] lsample_hold_config, // bus interface input up_rstn, @@ -67,24 +67,26 @@ module axi_dac_interpolate_reg( // internal registers - reg [31:0] up_version = 32'h00020100; + reg [31:0] up_version = {16'h0002, /* MAJOR */ + 8'h02, /* MINOR */ + 8'h00}; /* PATCH */ reg [31:0] up_scratch = 32'h0; reg [31:0] up_interpolation_ratio_a = 32'h0; reg [ 2:0] up_filter_mask_a = 3'h0; reg [31:0] up_interpolation_ratio_b = 32'h0; reg [ 2:0] up_filter_mask_b = 3'h0; - reg [1:0] up_flags = 2'h2; + reg [2:0] up_flags = 3'h2; reg [1:0] up_config = 2'h0; reg [15:0] up_correction_coefficient_a = 16'h0; reg [15:0] up_correction_coefficient_b = 16'h0; reg [19:0] up_trigger_config = 20'h0; - reg [ 1:0] up_lsample_hold_config = 2'h0; - wire [ 1:0] flags; + wire [ 2:0] flags; assign dma_transfer_suspend = flags[0]; assign start_sync_channels = flags[1]; + assign stop_sync_channels = flags[2]; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 0) begin @@ -99,7 +101,6 @@ module axi_dac_interpolate_reg( up_correction_coefficient_a <= 'd0; up_correction_coefficient_b <= 'd0; up_trigger_config <= 'd0; - up_lsample_hold_config <= 'h0; end else begin up_wack <= up_wreq; if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin @@ -118,7 +119,7 @@ module axi_dac_interpolate_reg( up_filter_mask_b <= up_wdata[2:0]; end if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin - up_flags <= {30'h0,up_wdata[1:0]}; + up_flags <= {29'h0,up_wdata[2:0]}; end if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin up_config <= up_wdata[1:0]; @@ -132,9 +133,6 @@ module axi_dac_interpolate_reg( if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin up_trigger_config <= up_wdata[19:0]; end - if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin - up_lsample_hold_config <= up_wdata[1:0]; - end end end @@ -154,12 +152,11 @@ module axi_dac_interpolate_reg( 5'h11: up_rdata <= {29'h0,up_filter_mask_a}; 5'h12: up_rdata <= up_interpolation_ratio_b; 5'h13: up_rdata <= {29'h0,up_filter_mask_b}; - 5'h14: up_rdata <= {30'h0,up_flags}; + 5'h14: up_rdata <= {29'h0,up_flags}; 5'h15: up_rdata <= {30'h0,up_config}; 5'h16: up_rdata <= {16'h0,up_correction_coefficient_a}; 5'h17: up_rdata <= {16'h0,up_correction_coefficient_b}; 5'h18: up_rdata <= {12'h0,up_trigger_config}; - 5'h19: up_rdata <= {30'h0,up_lsample_hold_config}; default: up_rdata <= 0; endcase end else begin @@ -169,7 +166,7 @@ module axi_dac_interpolate_reg( end up_xfer_cntrl #( - .DATA_WIDTH(128) + .DATA_WIDTH(127) ) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), @@ -178,8 +175,7 @@ module axi_dac_interpolate_reg( up_correction_coefficient_b,// 16 up_correction_coefficient_a,// 16 up_trigger_config, // 20 - up_lsample_hold_config, // 2 - up_flags, // 2 + up_flags, // 3 up_interpolation_ratio_b, // 32 up_interpolation_ratio_a, // 32 up_filter_mask_b, // 3 @@ -193,8 +189,7 @@ module axi_dac_interpolate_reg( dac_correction_coefficient_b, // 16 dac_correction_coefficient_a, // 16 trigger_config, // 20 - lsample_hold_config, // 2 - flags, // 2 + flags, // 3 dac_interpolation_ratio_b, // 32 dac_interpolation_ratio_a, // 32 dac_filter_mask_b, // 3 diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl index dcc15a5deb..5a5c68e2a7 100644 --- a/projects/m2k/common/m2k_bd.tcl +++ b/projects/m2k/common/m2k_bd.tcl @@ -265,7 +265,6 @@ ad_connect axi_dac_interpolate/trigger_la logic_analyzer/trigger_out_adc ad_connect axi_dac_interpolate/dac_valid_out_a axi_ad9963/dma_valid_i ad_connect axi_dac_interpolate/dac_valid_out_b axi_ad9963/dma_valid_q -ad_connect axi_dac_interpolate/hold_last_sample axi_ad9963/hold_last_sample ad_connect /axi_ad9963/tx_data txd ad_connect /axi_ad9963/tx_iq txiq