From 4104f549b9ec311eb792857b834ff515cfaa20a3 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Tue, 17 Oct 2023 17:15:36 -0300 Subject: [PATCH] i3c_controller: clean-up, add debug parameter Invert speed grade values order. Remove clk_div module. Add DEBUG_IGNORE_NACK parameter to ignore when a transfer is NACKed, useful for testing without a peripheral on the bus, Signed-off-by: Jorge Marques --- docs/regmap/adi_regmap_i3c_controller.txt | 14 ++-- .../i3c_controller_core/Makefile | 2 - .../i3c_controller_bit_mod.v | 22 ++--- .../i3c_controller_clk_div.v | 80 ------------------- .../i3c_controller_core/i3c_controller_core.v | 21 ++--- .../i3c_controller_core_hw.tcl | 2 - .../i3c_controller_core_ip.tcl | 8 +- .../i3c_controller_phy_sda.v | 58 -------------- .../i3c_controller_core/i3c_controller_word.v | 73 ++++++++--------- .../interfaces/i3c_controller_rtl.xml | 41 ++++++++-- projects/ad405x_i3c_ardz/coraz7s/system_top.v | 18 ++++- 11 files changed, 120 insertions(+), 219 deletions(-) delete mode 100644 library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v delete mode 100644 library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v diff --git a/docs/regmap/adi_regmap_i3c_controller.txt b/docs/regmap/adi_regmap_i3c_controller.txt index 593e5343b4..223575d476 100644 --- a/docs/regmap/adi_regmap_i3c_controller.txt +++ b/docs/regmap/adi_regmap_i3c_controller.txt @@ -421,14 +421,14 @@ ENDREG FIELD [0] 0x?? OPS_MODE -WO +RW Set 0 to private transfers, 1 to offload. ENDFIELD FIELD [4:1] 0x?? OPS_OFFLOAD_LENGTH -WO +RW Offload commands length. ENDFIELD @@ -438,10 +438,10 @@ OPS_SPEED_GRADE RW Sets the speed grade in push-pull mode. Speed with 100MHz driver clock are: -00: 12.50MHz -01: 6.25MHz -10: 3.12MHz -11: 1.56MHz (default) +00: 1.56MHz (default) +01: 3.12MHz +10: 6.25MHz +11: 12.50MHz ENDFIELD [5] 0x0 @@ -595,6 +595,8 @@ The state can also be overwritten to explicit attach device (e.g. has static add A slot cannot be recycled, when the device is detached, it still keeps its slot in case it is attached again, effectively, only its IBIs are rejectedin the detached state. +The controller cannot be detached, instead, poll OPS_STATUS_NOP to identify if the +controller is doing free/not doing any procedure before recondiguring it. ENDFIELD FIELD diff --git a/library/i3c_controller/i3c_controller_core/Makefile b/library/i3c_controller/i3c_controller_core/Makefile index 735b7256a5..46666c00b3 100644 --- a/library/i3c_controller/i3c_controller_core/Makefile +++ b/library/i3c_controller/i3c_controller_core/Makefile @@ -8,12 +8,10 @@ LIBRARY_NAME := i3c_controller_core GENERIC_DEPS += i3c_controller_core.v GENERIC_DEPS += i3c_controller_framing.v -GENERIC_DEPS += i3c_controller_phy_sda.v GENERIC_DEPS += i3c_controller_word.v GENERIC_DEPS += i3c_controller_word_cmd.v GENERIC_DEPS += i3c_controller_bit_mod.v GENERIC_DEPS += i3c_controller_bit_mod_cmd.v -GENERIC_DEPS += i3c_controller_clk_div.v XILINX_DEPS += i3c_controller_core_constr.ttcl XILINX_DEPS += i3c_controller_core_ip.tcl diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v index 7aeb20e506..5bdc24d5cf 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v @@ -49,10 +49,10 @@ module i3c_controller_bit_mod ( // Indicates that the bus is not transfering, // is different from bus idle because does not wait 200us after Stop. output cmd_nop, - // 0: 12.50MHz - // 1: 6.25MHz - // 2: 3.12MHz - // 3: 1.56MHz + // 0: 1.56MHz + // 1: 3.12MHz + // 2: 6.25MHz + // 3: 12.50MHz input [1:0] scl_pp_sg, // SCL Push-pull speed grade output rx, @@ -62,8 +62,8 @@ module i3c_controller_bit_mod ( // Bus drive signals - output reg sdo, output scl, + output reg sdo, input sdi, output t ); @@ -75,7 +75,7 @@ module i3c_controller_bit_mod ( reg sr; reg scl_high_reg; - wire scl_high = count[pp_sg+2]; + wire scl_high = count[5-pp_sg]; wire sdo_w; wire t_w; @@ -85,7 +85,7 @@ module i3c_controller_bit_mod ( for (i = 0; i < 4; i = i+1) begin assign scl_end_multi[i] = &count[i+2:0]; end - assign scl_end = scl_end_multi[pp_sg]; + assign scl_end = scl_end_multi[3-pp_sg]; assign cmd_ready = (scl_end | !transfer) & reset_n; @@ -95,12 +95,12 @@ module i3c_controller_bit_mod ( always @(posedge clk) begin if (!reset_n) begin cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01}; - pp_sg <= 2'b11; + pp_sg <= 2'b00; end else begin if (cmd_ready) begin if (cmd_valid) begin cmd_r <= cmd; - pp_sg <= cmd[1] ? scl_pp_sg : 2'b11; + pp_sg <= cmd[1] ? scl_pp_sg : 2'b00; end else begin cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01}; end @@ -138,8 +138,8 @@ module i3c_controller_bit_mod ( assign rx = rx_raw; assign rx_valid = ~scl_high_reg & scl_high; - assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[pp_sg+1] : 1'b1) : - sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[pp_sg+1] : 1'b0) : + assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[4-pp_sg] : 1'b1) : + sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[4-pp_sg] : 1'b0) : sm == `MOD_BIT_CMD_WRITE_ ? st[0] : sm == `MOD_BIT_CMD_ACK_SDR_ ? (scl_high ? rx : 1'b1) : sm == `MOD_BIT_CMD_ACK_IBI_ ? (scl_high ? 1'b1 : 1'b0) : diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v b/library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v deleted file mode 100644 index 4eb63f4a9d..0000000000 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v +++ /dev/null @@ -1,80 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -/** - * Select clock clk/4 (sel=0) or clk/1 (sel=1) output. - */ - -`timescale 1ns/100ps -`default_nettype none - -module i3c_controller_clk_div #( - parameter SIM_DEVICE = "7SERIES", - parameter CLK_DIV = "4" -) ( - input wire reset_n, - input wire sel, - input wire cmd_ready, - input wire clk, - output wire clk_out -); - wire clk_1; - - generate if (SIM_DEVICE == "7SERIES") begin - BUFR #( - .BUFR_DIVIDE(CLK_DIV) - ) i_BUFR ( - .O(clk_1), - .CE(reset_n), - .CLR(!reset_n), - .I(clk)); - end else if (SIM_DEVICE == "ULTRASCALE") begin - BUFGCE_DIV #( - .BUFGCE_DIVIDE(CLK_DIV) - ) i_BUFGCE_DIV ( - .O(clk_1), - .CE(reset_n), - .CLR(!reset_n), - .I(clk)); - end - endgenerate - - BUFGMUX #( - ) i_BUFGMUX ( - .O(clk_out), - .I0(clk_1), - .I1(clk), - .S(sel)); - -endmodule diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v index f6a9060674..533e238e2f 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v @@ -92,8 +92,10 @@ module i3c_controller_core #( // I3C bus signals - output scl, - inout sda + output i3c_scl, + output i3c_sdo, + input i3c_sdi, + output i3c_t ); wire clk_out; wire [`MOD_BIT_CMD_WIDTH:0] cmd; @@ -224,17 +226,10 @@ module i3c_controller_core #( .rx_raw(rx_raw), .rx_valid(rx_valid), .cmd_nop(cmd_nop), - .scl(scl), - .sdi(sdi_bit), - .sdo(sdo_bit), - .t(t)); - - i3c_controller_phy_sda #( - ) i_i3c_controller_phy_sda ( - .sdo(sdo_bit), - .sdi(sdi_bit), - .t(t), - .sda(sda)); + .scl(i3c_scl), + .sdo(i3c_sdo), + .sdi(i3c_sdi), + .t(i3c_t)); assign ibi = {ibi_da, ibi_mdb}; assign ibi_valid = ibi_tick; diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl b/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl index 7922a7acc4..a75d463752 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl @@ -7,12 +7,10 @@ set_module_property ELABORATION_CALLBACK p_elaboration ad_ip_files i3c_controller_core [list \ i3c_controller_core.v \ i3c_controller_framing.v \ - i3c_controller_phy_sda.v \ i3c_controller_word.v \ i3c_controller_word_cmd.v \ i3c_controller_bit_mod.v \ i3c_controller_bit_mod_cmd.v \ - i3c_controller_clk_div.v \ ] # parameters diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl b/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl index 61f92649b4..98be1d698b 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl @@ -6,12 +6,10 @@ adi_ip_files i3c_controller_core [list \ "i3c_controller_core_constr.ttcl" \ "i3c_controller_core.v" \ "i3c_controller_framing.v" \ - "i3c_controller_phy_sda.v" \ "i3c_controller_word.v" \ "i3c_controller_word_cmd.v" \ "i3c_controller_bit_mod.v" \ "i3c_controller_bit_mod_cmd.v" \ - "i3c_controller_clk_div.v" \ ] adi_ip_properties_lite i3c_controller_core @@ -27,8 +25,10 @@ adi_add_bus "i3c" "master" \ "analog.com:interface:i3c_controller_rtl:1.0" \ "analog.com:interface:i3c_controller:1.0" \ { - {"scl" "SCL"} \ - {"sda" "SDA"} \ + {"i3c_scl" "SCL"} \ + {"i3c_sdo" "SDO"} \ + {"i3c_sdi" "SDI"} \ + {"i3c_t" "T"} \ } adi_add_bus_clock "clk" "i3c" "reset_n" diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v b/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v deleted file mode 100644 index e53a27dbbf..0000000000 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v +++ /dev/null @@ -1,58 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -/** - * Tristate, p 'HIGH for push-pull SDA, and 'LOW for open-drain. - */ - -`timescale 1ns/100ps - -module i3c_controller_phy_sda ( - input sdo, - output sdi, - input t, - inout sda -); - // TODO: Add Intel tristate primitive, select dependin on target. - IOBUF #( - ) IOBUF_inst ( - .O(sdi), - .IO(sda), - .I(sdo), - .T(t) - ); - // Same as, but sometimes Xilinx was not inferring IOBUF from this... - //assign sda = ~t ? sdi : 1'bZ; - //assign sdo = sda; -endmodule diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v index 72a0fbbd8e..525288d76a 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v @@ -38,47 +38,49 @@ */ `timescale 1ns/100ps -`default_nettype none +`default_nettype wire `include "i3c_controller_word_cmd.v" `include "i3c_controller_bit_mod_cmd.v" -module i3c_controller_word ( - input wire clk, - input wire reset_n, +module i3c_controller_word #( + parameter DEBUG_IGNORE_NACK = 0 +) ( + input clk, + input reset_n, // Word command output reg cmdw_nack, // NACK is HIGH when an ACK is not satisfied in the I3C bus, acts as reset. - output wire cmdw_ready, - input wire cmdw_valid, - input wire [`CMDW_HEADER_WIDTH+8:0] cmdw, + output cmdw_ready, + input cmdw_valid, + input [`CMDW_HEADER_WIDTH+8:0] cmdw, - input wire cmdw_rx_ready, - output reg cmdw_rx_valid, - output wire [7:0] cmdw_rx, + input cmdw_rx_ready, + output reg cmdw_rx_valid, + output [7:0] cmdw_rx, // Bit Modulation Command - output wire [`MOD_BIT_CMD_WIDTH:0] cmd, - output wire cmd_valid, - input wire cmd_ready, + output [`MOD_BIT_CMD_WIDTH:0] cmd, + output cmd_valid, + input cmd_ready, // RX and ACK - input wire rx, - input wire rx_valid, + input rx, + input rx_valid, // IBI interface - output reg arbitration_valid, - input wire ibi_bcr_2, - output reg ibi_requested, - input wire ibi_requested_auto, - output reg ibi_tick, - output wire [6:0] ibi_da, - input wire ibi_da_attached, - output wire [7:0] ibi_mdb, + output reg arbitration_valid, + input ibi_bcr_2, + output reg ibi_requested, + input ibi_requested_auto, + output reg ibi_tick, + output [6:0] ibi_da, + input ibi_da_attached, + output [7:0] ibi_mdb, // DAA interface @@ -87,10 +89,9 @@ module i3c_controller_word ( // uP accessible info - input wire [1:0] rmap_ibi_config + input [1:0] rmap_ibi_config ); wire ibi_enable; - wire ibi_auto; wire [`CMDW_HEADER_WIDTH:0] cmdw_header; @@ -107,14 +108,11 @@ module i3c_controller_word ( reg do_ack; // Peripheral did NACK? reg do_rx_t; // Peripheral end Message at T in Read Data? - reg rx_sampled; reg sg; reg [`MOD_BIT_CMD_WIDTH:2] cmd_r; reg cmd_wr; reg [5:0] i; - reg [5:0] i_reg; - reg [5:0] i_reg_2; reg [5:0] i_; // # of Bit Modulation Commands - 1 per word always @(sm) begin @@ -331,13 +329,17 @@ module i3c_controller_word ( `CMDW_TARGET_ADDR_PP, `CMDW_BCAST_7E_W1, `CMDW_BCAST_7E_W0: begin - if (do_ack & rx !== 1'b0) begin - sm <= `CMDW_STOP_OD; - smt <= setup; - cmdw_nack <= 1'b1; // Tick - // Due to NACK'ED STOP inheriting NACK'ED word i value, - // this flag makes sm goto get after STOP cmd. - cmdw_nacked <= 1'b1; + // Debug parameter to pretend all ACK bits have been ACKed, + // useful for bus testing without a part. + if (!DEBUG_IGNORE_NACK) begin + if (do_ack & rx !== 1'b0) begin + sm <= `CMDW_STOP_OD; + smt <= setup; + cmdw_nack <= 1'b1; // Tick + // Due to NACK'ED STOP inheriting NACK'ED word i value, + // this flag makes sm goto get after STOP cmd. + cmdw_nacked <= 1'b1; + end end end `CMDW_MSG_RX: begin @@ -411,7 +413,6 @@ module i3c_controller_word ( assign ibi_da = ibi_da_reg [8:2]; assign ibi_mdb = ibi_mdb_reg[8:1]; assign ibi_enable = rmap_ibi_config[0]; - assign ibi_auto = rmap_ibi_config[1]; assign cmd_valid = smt == transfer; assign cmd = {cmd_r, sg, cmd_wr}; endmodule diff --git a/library/i3c_controller/interfaces/i3c_controller_rtl.xml b/library/i3c_controller/interfaces/i3c_controller_rtl.xml index 0170f249d8..67c626e5ac 100644 --- a/library/i3c_controller/interfaces/i3c_controller_rtl.xml +++ b/library/i3c_controller/interfaces/i3c_controller_rtl.xml @@ -28,20 +28,51 @@ - SDA - Serial data + SDO + Serial data out required 1 - inout + out + + + required + 1 + in + + + + + SDI + Serial data in + + + required + 1 + in required 1 - inout + out + + + + + T + 3-State enable + + + required + 1 + out + + + required + 1 + in - 0 diff --git a/projects/ad405x_i3c_ardz/coraz7s/system_top.v b/projects/ad405x_i3c_ardz/coraz7s/system_top.v index d9fae2f3bb..a12c16a666 100644 --- a/projects/ad405x_i3c_ardz/coraz7s/system_top.v +++ b/projects/ad405x_i3c_ardz/coraz7s/system_top.v @@ -71,11 +71,23 @@ module system_top ( wire [63:0] gpio_o; wire [63:0] gpio_t; + wire i3c_controller_0_sdo; + wire i3c_controller_0_sdi; + wire i3c_controller_0_t; + // instantiations assign gpio_i[31:8] = gpio_o[31:8]; assign gpio_i[63:33] = gpio_o[63:33]; + ad_iobuf #( + .DATA_WIDTH(1) + ) i_iobuf_sda ( + .dio_t(i3c_controller_0_t), + .dio_i(i3c_controller_0_sdo), + .dio_o(i3c_controller_0_sdi), + .dio_p(i3c_controller_0_sda)); + ad_iobuf #( .DATA_WIDTH(2) ) i_iobuf_buttons ( @@ -135,7 +147,9 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), - .i3c_controller_0_scl(i3c_controller_0_scl), - .i3c_controller_0_sda(i3c_controller_0_sda)); + .i3c_controller_0_scl (i3c_controller_0_scl), + .i3c_controller_0_sdi (i3c_controller_0_sdi), + .i3c_controller_0_sdo (i3c_controller_0_sdo), + .i3c_controller_0_t (i3c_controller_0_t)); endmodule