From 2f46018abcc10cca0a6be43750cdbfb9766e7284 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Thu, 3 Oct 2024 10:19:32 +0300 Subject: [PATCH] docs/library/util_sigma_delta_spi: Add documentation Signed-off-by: Iulia Moldovan --- docs/library/index.rst | 1 + docs/library/util_sigma_delta_spi/index.rst | 75 +++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 docs/library/util_sigma_delta_spi/index.rst diff --git a/docs/library/index.rst b/docs/library/index.rst index c0262594ff..6fb804183b 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -91,6 +91,7 @@ Utilities util_pack/util_cpack2 util_pack/util_upack2 util_rfifo/index + util_sigma_delta_spi/index util_var_fifo/index util_wfifo/index xilinx/index diff --git a/docs/library/util_sigma_delta_spi/index.rst b/docs/library/util_sigma_delta_spi/index.rst new file mode 100644 index 0000000000..f798f385f9 --- /dev/null +++ b/docs/library/util_sigma_delta_spi/index.rst @@ -0,0 +1,75 @@ +.. _util_sigma_delta_spi: + +Util Sigma Delta SPI +=============================================================================== + +.. hdl-component-diagram:: + +ADCs from the :adi:`ADI <>` Sigma-Delta converter family use a low-level +communication protocol that multiplexes the SPI bus MISO signal and the data +ready interrupt signal over the same physical wire (DOUT/RDY). + +The :git-hdl:`Sigma-Delta SPI Util ` peripheral +can be used to de-multiplex these signals inside a FPGA. + +Files +------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/util_sigma_delta_spi/util_sigma_delta_spi.v` + - Verilog source for the peripheral + * - :git-hdl:`library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl` + - Tcl script to generate the Vivado IP Integrator project for the peripheral + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + :path: library/util_sigma_delta_spi + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + :path: library/util_sigma_delta_spi + +Detailed Description +-------------------------------------------------------------------------------- + +The :git-hdl:`Sigma-Delta SPI Util ` peripheral +monitors the SPI bus that is connected to the ``s_spi`` interface for the +converter's data ready condition. + +The ``m_spi`` interface is directly connected to the ``s_spi`` interface. +In a typical configuration, the ``s_spi`` interface is connected to a SPI +controller and the ``m_spi`` interface is connected to external SPI bus pins. + +The ``data_ready`` signal is high-level active and will be asserted as long as +the data ready condition is detected. + +For example, it can be connected to an interrupt controller to start an +interrupt service routine that will read the converted data sample from +the ADC, or it can be connected to a HDL block, like the +:ref:`SPI Engine Offload ` block that will generate a SPI +transaction to read the converted signal. + +The data ready condition is only detected if the chip-select signal (which is +connected to the converter) is asserted and the ``spi_active`` signal is +de-asserted and both signals have been in that state for **at least** +``IDLE_TIMEOUT`` clock cycles. + +The timeout is used to avoid spurious signal detection and the ``IDLE_TIMEOUT`` +parameter should be configured so that the period it takes to complete +``IDLE_TIMEOUT`` clock cycles with the ``clk`` clock, is larger than the +"CS falling edge to DOUT/RDY active time" +and "SCLK inactive edge to DOUT/RDY high/low" +as specified in the data sheet for the converter. + +References +-------------------------------------------------------------------------------- + +* HDL IP core at :git-hdl:`library/util_sigma_delta_spi`