Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Verilog/SystemVerilog 格式化后格式很怪异 #78

Open
wa-kakalala opened this issue Apr 25, 2024 · 0 comments
Open

Verilog/SystemVerilog 格式化后格式很怪异 #78

wa-kakalala opened this issue Apr 25, 2024 · 0 comments

Comments

@wa-kakalala
Copy link

格式化后格式很怪异

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant