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atemsys.c
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atemsys.c
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/*-----------------------------------------------------------------------------
* atemsys.c
* Copyright (c) 2009 - 2024 acontis technologies GmbH, Weingarten, Germany
* All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
*
* NOTE! This copyright does *not* cover user programs that use kernel
* services by normal system calls - this is merely considered normal use
* of the kernel, and does *not* fall under the heading of "derived work".
* Also note that the GPL below is copyrighted by the Free Software
* Foundation, but the instance of code that it refers to (the Linux
* kernel) is copyrighted by me and others who actually wrote it.
*
* Also note that the only valid version of the GPL as far as the kernel
* is concerned is _this_ particular version of the license (ie v2, not
* v2.2 or v3.x or whatever), unless explicitly otherwise stated.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Response Paul Bussmann
* Description Provides usermode access to:
* - PCI configuration space
* - Device IO memory
* - Contiguous DMA memory
* - Single device interrupt
*
*
* The driver should be used in the following way:
*
* - Make sure this driver's device node is present. I.e. call "mknod /dev/atemsys c 101 0"
*
* - open()
* Open driver (There can be more then one file descriptor active in parallel).
*
* - close()
* Close driver. Free resources, if any were allocated.
*
* - ioctl(ATEMSYS_IOCTL_PCI_FIND_DEVICE)
* Scan for PCI Devices.
* Input: VendorID, DeviceID, InstanceNo
* Output: BusNo, DevNo, FuncNo
*
* - ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE)
* Configures PCI device. This ioctl pins the given PCI device to the current filedescriptor.
* Input: BusNo, DevNo, FuncNo
* Output: Physical IO base address, IO area length, IRQ number
* The device must be released explicitly in order to configure the next device. The ioctl gets
* errno EBUSY if the device is in use by another device driver.
*
* - ioctl(ATEMSYS_IOCTL_PCI_RELEASE_DEVICE)
* Release PCI device and free resources assigned to PCI device (interrupt, DMA memory, ...).
*
* - mmap(0, dwSize, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, fd, 0);
* Allocates and maps DMA memory of size dwSize. Note that the last parameter (offset) must be 0.
* Input: Length in byte
* Output: Pointer to the allocated memory and DMA physical address. On success this address is
* written into the first 4 bytes of the allocated memory.
*
* - mmap(0, IOphysSize, PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED, fd, IOphysAddr);
* Maps IO memory of size IOphysSize.
* PCI device:
* First call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE). The IOphysAddr and IOphysSize
* parameter must corespond with the base IO address and size returned by
* ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE), or the ioctl will fail.
* Non-PCI device:
* Don't call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE) before and just pass
* IOphysAddr and IOphysSize. There are no checks done.
* Input: Phys.IO base address, IO area length in byte
* Output: Pointer to the mapped IO memory.
* The user should call dev_munmap() if the requested DMA memory is not needed anymore. In any cases
* the allocated / mapped memory is released / unmapped if the module is unloaded.
*
* - ioctl(ATEMSYS_IOCTL_INT_CONNECT)
* Connect an ISR to the device's interrupt.
* If the parameter is USE_PCI_INT, then the IRQ is taken from the selected PCI device.
* So in this case you have to call ioctl(ATEMSYS_IOCTL_PCI_CONF_DEVICE) first, or it will fail.
* Input: IRQ-Number or USE_PCI_INT
* Output: none
* The device interrupt is active if this ioctl succeeds. The caller should do a read() on the file
* descriptor. The read call unblocks if an interrupt is received. If the read is unblocked, the
* interrupt is disabled on the (A)PIC and the caller must acknowledge the interrupt on the device
* (write to mmaped IO register). If the next read() is executed, the interrupt is enabled again
* on the (A)PIC. So a missing interrupt acknowledge will held the INT line active and interrupt
* trashing will happen (ISR is called again, read() unblocks, ...).
* Note that this ioctl will fail with errno EPERM if the interrupt line is shared.
* PCI device:
* The ioctl will try to use Message Signaled Interrupts (MSI) if supported
* by the PCI device. By definition, interrupts are never shared with MSI and MSI are mandatory
* for PCI-Express :).
*
* - ioctl(ATEMSYS_IOCTL_INT_DISCONNECT)
* Disconnect from device's interrupt.
*
* - ioctl(ATEMSYS_IOCTL_INT_INFO)
* Query used interrupt number.
*
* - read()
* see ioctl(ATEMSYS_IOCTL_INT_CONNECT)
*
*
* Changes see atemsys.h
*
*----------------------------------------------------------------------------*/
#define ATEMSYS_C
#include <linux/module.h>
#include "atemsys.h"
#include <linux/pci.h>
#include <linux/platform_device.h>
#if !(defined NO_IRQ) && (defined __aarch64__)
#define NO_IRQ ((unsigned int)(-1))
#endif
#if (defined CONFIG_XENO_COBALT)
#include <rtdm/driver.h>
#else
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/semaphore.h>
#include <linux/mutex.h>
#include <linux/sched.h>
#include <linux/smp.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,00))
#include <linux/sched/signal.h>
#endif
#include <linux/irq.h>
#include <linux/list.h>
#if (defined CONFIG_OF)
#include <linux/of_device.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,13,0))
#include <linux/uaccess.h>
#else
#include <asm/uaccess.h>
#endif
#include <asm/current.h>
#include <linux/compat.h>
#include <linux/slab.h>
#include <linux/device.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0))
#include <linux/dma-direct.h>
#endif
#if (defined CONFIG_DTC)
#include <linux/of.h>
#include <linux/of_irq.h>
#endif /* CONFIG_DTC */
#endif /* CONFIG_XENO_COBALT */
#if ((defined CONFIG_OF) \
&& (LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) /* not tested */))
#define INCLUDE_ATEMSYS_DT_DRIVER 1
#include <linux/etherdevice.h>
#include <linux/clk.h>
#include <linux/phy.h>
#include <linux/clk/clk-conf.h>
#include <linux/pinctrl/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/of_mdio.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_net.h>
#include <linux/delay.h>
#include <linux/kthread.h>
#include <linux/wait.h>
#include <asm/param.h>
#include <linux/of_gpio.h>
#include <linux/reset.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,5,0))
#include <linux/of_platform.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0) /* not tested */)
#define INCLUDE_ATEMSYS_DT_REGISTER_NETDEVICE 1
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
struct _ATEMSYS_T_DRV_DESC_PRIVATE;
int RegisterEthernetDriverAsNetDevice(struct device_node* pDevNode, struct _ATEMSYS_T_DRV_DESC_PRIVATE* pDrvDesc);
#endif
#endif /* CONFIG_OF */
#if ((defined CONFIG_PCI) \
&& (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0) /* not tested */))
#define INCLUDE_ATEMSYS_PCI_DRIVER 1
#include <linux/aer.h>
#endif
#if !(defined HAVE_IRQ_TO_DESC) && !(defined CONFIG_HAVE_DOVETAIL) && !(defined CONFIG_IRQ_PIPELINE)
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,1))
#define INCLUDE_IRQ_TO_DESC
#endif
#else
#if HAVE_IRQ_TO_DESC
#define INCLUDE_IRQ_TO_DESC
#endif
#endif
/* legacy support */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,13,0))
#define wait_queue_entry_t wait_queue_t
#endif
#ifndef VM_RESERVED
#define VM_RESERVED (VM_DONTEXPAND | VM_DONTDUMP)
#endif
/* define this if IO memory should also be mapped into the kernel (for debugging only) */
#undef DEBUG_IOREMAP
MODULE_AUTHOR("acontis technologies GmbH <[email protected]>");
MODULE_DESCRIPTION("Generic usermode PCI driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(ATEMSYS_VERSION_STR);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18))
#error "At least kernel version 2.6.18 is needed to compile!"
#endif
static char* AllowedPciDevices = "PCI_ANY_ID";
module_param(AllowedPciDevices, charp, 0000);
MODULE_PARM_DESC(AllowedPciDevices, "Bind only pci devices in semicolon separated list e.g. AllowedPciDevices=\"0000:01:00.0\", empty string will turn off atemsys_pci driver.");
/* Workaround for older kernels */
/* from 'linux/kern_levels.h' */
/* integer equivalents of KERN_<LEVEL> */
#ifndef LOGLEVEL_ERR
#define LOGLEVEL_ERR 3 /* error conditions */
#endif
#ifndef LOGLEVEL_WARNING
#define LOGLEVEL_WARNING 4 /* warning conditions */
#endif
#ifndef LOGLEVEL_INFO
#define LOGLEVEL_INFO 6 /* informational */
#endif
#ifndef LOGLEVEL_DEBUG
#define LOGLEVEL_DEBUG 7 /* debug-level messages */
#endif
static int loglevel = LOGLEVEL_INFO;
module_param(loglevel, int, 0);
MODULE_PARM_DESC(loglevel, "Set log level default LOGLEVEL_INFO, see /include/linux/kern_levels.h");
#ifdef INCLUDE_ATEMSYS_DT_REGISTER_NETDEVICE
static bool bRegisterDtbNetDevice = false;
module_param(bRegisterDtbNetDevice, bool, false);
MODULE_PARM_DESC(bRegisterDtbNetDevice, "Register netdevice on device tree nodes (dsa driver support)");
#endif
#if (defined CONFIG_XENO_COBALT)
#define PRINTK(prio, str, ...) rtdm_printk(prio ATEMSYS_DEVICE_NAME ": " str, ##__VA_ARGS__)
#else
#define PRINTK(prio, str, ...) printk(prio ATEMSYS_DEVICE_NAME ": " str, ##__VA_ARGS__)
#endif /* CONFIG_XENO_COBALT */
#define ERR(str, ...) (LOGLEVEL_ERR <= loglevel)? PRINTK(KERN_ERR, str, ##__VA_ARGS__) :0
#define WRN(str, ...) (LOGLEVEL_WARNING <= loglevel)? PRINTK(KERN_WARNING, str, ##__VA_ARGS__) :0
#define INF(str, ...) (LOGLEVEL_INFO <= loglevel)? PRINTK(KERN_INFO, str, ##__VA_ARGS__) :0
#define DBG(str, ...) (LOGLEVEL_DEBUG <= loglevel)? PRINTK(KERN_INFO, str, ##__VA_ARGS__) :0
#ifndef PAGE_UP
#define PAGE_UP(addr) (((addr)+((PAGE_SIZE)-1))&(~((PAGE_SIZE)-1)))
#endif
#ifndef PAGE_DOWN
#define PAGE_DOWN(addr) ((addr)&(~((PAGE_SIZE)-1)))
#endif
/* Comments: for kernel 2.6.18 add DMA_BIT_MASK*/
#ifndef DMA_BIT_MASK
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#endif
#ifndef HAVE_ACCESS_OK_TYPE
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0))
#define HAVE_ACCESS_OK_TYPE 0
#else
#define HAVE_ACCESS_OK_TYPE 1
#endif
#endif
#if HAVE_ACCESS_OK_TYPE
#define ACCESS_OK(type, addr, size) access_ok(type, addr, size)
#else
#define ACCESS_OK(type, addr, size) access_ok(addr, size)
#endif
#if ((defined CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,18,0)) && !(defined CONFIG_XENO_COBALT))
#define OF_DMA_CONFIGURE(dev, of_node) of_dma_configure(dev, of_node, true)
#elif ((defined CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)) && !(defined CONFIG_XENO_COBALT))
#define OF_DMA_CONFIGURE(dev, of_node) of_dma_configure(dev, of_node)
#elif ((defined CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)) && !(defined CONFIG_XENO_COBALT))
#define OF_DMA_CONFIGURE(dev, of_node) of_dma_configure(dev)
#else
#define OF_DMA_CONFIGURE(dev, of_node)
#endif
typedef struct _ATEMSYS_T_IRQ_DESC
{
u32 irq;
atomic_t count;
atomic_t totalCount;
#if (defined CONFIG_XENO_COBALT)
rtdm_irq_t irq_handle;
rtdm_event_t irq_event;
#else
atomic_t irqStatus;
wait_queue_head_t q;
#endif /* CONFIG_XENO_COBALT */
#if (defined INCLUDE_IRQ_TO_DESC)
bool irq_is_level;
#endif
} ATEMSYS_T_IRQ_DESC;
struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE;
struct _ATEMSYS_T_DRV_DESC_PRIVATE;
typedef struct _ATEMSYS_T_DEVICE_DESC
{
struct list_head list;
#if (defined CONFIG_PCI)
struct pci_dev* pPcidev;
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE* pPciDrvDesc;
#endif
#endif
struct platform_device* pPlatformDev;
#if (defined INCLUDE_ATEMSYS_DT_DRIVER)
struct _ATEMSYS_T_DRV_DESC_PRIVATE* pDrvDesc;
#endif
ATEMSYS_T_IRQ_DESC irqDesc;
/* supported features */
bool bSupport64BitDma;
} ATEMSYS_T_DEVICE_DESC;
typedef struct _ATEMSYS_T_MMAP_DESC
{
struct list_head list;
ATEMSYS_T_DEVICE_DESC* pDevDesc;
dma_addr_t dmaAddr;
void* pVirtAddr;
size_t len;
} ATEMSYS_T_MMAP_DESC;
#if (defined CONFIG_OF)
#define ATEMSYS_DT_DRIVER_NAME "atemsys"
/* udev auto-loading support via DTB */
static const struct of_device_id atemsys_ids[] = {
{ .compatible = ATEMSYS_DT_DRIVER_NAME },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atemsys_ids);
#endif /* CONFIG_OF */
#define ATEMSYS_MAX_NUMBER_DRV_INSTANCES 10
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
typedef struct _ATEMSYS_T_PCI_DRV_DESC_PRIVATE
{
struct pci_dev* pPciDev;
int nPciDomain;
int nPciBus;
int nPciDev;
int nPciFun;
unsigned short wVendorId;
unsigned short wDevice;
unsigned short wRevision;
unsigned short wSubsystem_vendor;
unsigned short wSubsystem_device;
ATEMSYS_T_PCI_MEMBAR aBars[ATEMSYS_PCI_MAXBAR];
int nBarCnt;
ATEMSYS_T_DEVICE_DESC* pDevDesc;
unsigned int dwIndex;
} ATEMSYS_T_PCI_DRV_DESC_PRIVATE;
static ATEMSYS_T_PCI_DRV_DESC_PRIVATE* S_apPciDrvDescPrivate[ATEMSYS_MAX_NUMBER_DRV_INSTANCES];
#endif
#if (defined INCLUDE_ATEMSYS_DT_DRIVER)
#define ATEMSYS_MAX_NUMBER_OF_CLOCKS 10
typedef struct
{
void __iomem* pbyBase;
__u64 qwPhys;
__u32 dwSize;
} ATEMSYS_T_IOMEM;
typedef struct _ATEMSYS_T_DRV_DESC_PRIVATE
{
int nDev_id;
struct net_device* netdev;
struct platform_device* pPDev;
struct device_node* pDevNode;
/* storage and identification */
ATEMSYS_T_MAC_INFO MacInfo;
/* powermanagement */
struct reset_control* pResetCtl;
/* clocks */
const char* clk_ids[ATEMSYS_MAX_NUMBER_OF_CLOCKS];
struct clk* clks[ATEMSYS_MAX_NUMBER_OF_CLOCKS];
int nCountClk;
/* PHY */
ATEMSYS_T_PHY_INFO PhyInfo;
phy_interface_t PhyInterface;
struct device_node* pPhyNode;
struct device_node* pMdioNode;
struct device_node* pMdioDevNode; /* node for own mdio bus */
struct phy_device* pPhyDev;
struct regulator* pPhyRegulator;
struct task_struct* etx_thread_StartPhy;
struct task_struct* etx_thread_StopPhy;
/* PHY reset*/
int nPhyResetGpioPin;
bool bPhyResetGpioActiveHigh;
int nPhyResetDuration;
int nPhyResetPostDelay;
/* mdio */
ATEMSYS_T_MDIO_ORDER MdioOrder;
struct mii_bus* pMdioBus;
struct mutex mdio_order_mutex;
struct mutex mdio_mutex;
wait_queue_head_t mdio_wait_queue;
int mdio_wait_queue_cnt;
#ifdef CONFIG_TI_K3_UDMA
/* Ti CPSWG Channel, Flow & Ring */
#define ATEMSYS_UDMA_CHANNELS 10
void* apvTxChan[ATEMSYS_UDMA_CHANNELS];
int anTxIrq[ATEMSYS_UDMA_CHANNELS];
void* apvRxChan[ATEMSYS_UDMA_CHANNELS];
int anRxIrq[ATEMSYS_UDMA_CHANNELS];
#endif /*#ifdef CONFIG_TI_K3_UDMA*/
#define IOMEMLIST_LENGTH 20
ATEMSYS_T_IOMEM oIoMemList[IOMEMLIST_LENGTH];
/* frame descriptor of the EcMaster connection */
ATEMSYS_T_DEVICE_DESC* pDevDesc;
} ATEMSYS_T_DRV_DESC_PRIVATE;
static ATEMSYS_T_DRV_DESC_PRIVATE* S_apDrvDescPrivate[ATEMSYS_MAX_NUMBER_DRV_INSTANCES];
static int StartPhyThread(void* pvData);
static int StopPhyThread(void* pvData);
static int CleanUpEthernetDriverOnRelease(ATEMSYS_T_DEVICE_DESC* pDevDesc);
static int GetMacInfoIoctl(ATEMSYS_T_DEVICE_DESC* pDevDesc, unsigned long ioctlParam);
static int PhyStartStopIoctl( unsigned long ioctlParam);
static int GetMdioOrderIoctl(unsigned long ioctlParam);
static int ReturnMdioOrderIoctl(unsigned long ioctlParam);
static int GetPhyInfoIoctl(unsigned long ioctlParam);
static int PhyResetIoctl(unsigned long ioctlParam);
static int ResetPhyViaGpio(ATEMSYS_T_DRV_DESC_PRIVATE* pDrvDescPrivate);
static int EthernetDriverRemove(struct platform_device* pPDev);
static int EthernetDriverProbe(struct platform_device* pPDev);
#if (defined CONFIG_XENO_COBALT)
static int StartPhy(struct platform_device* pPDev);
static int StopPhy(struct platform_device* pPDev);
typedef struct _ATEMSYS_T_WORKER_THREAD_DESC
{
struct task_struct* etx_thread;
int (* pfNextTask)(void*);
void* pNextTaskData;
struct mutex WorkerTask_mutex;
bool bWorkerTaskShutdown;
bool bWorkerTaskRunning;
} ATEMSYS_T_WORKER_THREAD_DESC;
static ATEMSYS_T_WORKER_THREAD_DESC S_oAtemsysWorkerThreadDesc;
static int AtemsysWorkerThread(void* data)
{
void* pWorkerTaskData = NULL;
int (* pfWorkerTask)(void*);
pfWorkerTask = NULL;
S_oAtemsysWorkerThreadDesc.bWorkerTaskRunning = true;
for (;;)
{
mutex_lock(&S_oAtemsysWorkerThreadDesc.WorkerTask_mutex);
if (S_oAtemsysWorkerThreadDesc.bWorkerTaskShutdown)
{
mutex_unlock(&S_oAtemsysWorkerThreadDesc.WorkerTask_mutex);
break;
}
pfWorkerTask = S_oAtemsysWorkerThreadDesc.pfNextTask;
pWorkerTaskData = S_oAtemsysWorkerThreadDesc.pNextTaskData;
S_oAtemsysWorkerThreadDesc.pfNextTask = NULL;
S_oAtemsysWorkerThreadDesc.pNextTaskData = NULL;
mutex_unlock(&S_oAtemsysWorkerThreadDesc.WorkerTask_mutex);
if ((NULL != pfWorkerTask) && (NULL != pWorkerTaskData))
{
pfWorkerTask(pWorkerTaskData);
}
msleep(100);
}
S_oAtemsysWorkerThreadDesc.bWorkerTaskRunning = false;
return 0;
}
#endif /* #if (defined CONFIG_XENO_COBALT) */
#endif /* INCLUDE_ATEMSYS_DT_DRIVER */
static void dev_munmap(struct vm_area_struct* vma);
#if (defined CONFIG_XENO_COBALT)
static int dev_interrupt_handler(rtdm_irq_t* irq_handle);
#else
static irqreturn_t dev_interrupt_handler(int nIrq, void* pParam);
#endif /* CONFIG_XENO_COBALT */
static struct vm_operations_struct mmap_vmop =
{
.close = dev_munmap,
};
static DEFINE_MUTEX(S_mtx);
static ATEMSYS_T_DEVICE_DESC S_DevNode;
static struct class* S_pDevClass;
static struct device* S_pDev;
static struct platform_device* S_pPlatformDev = NULL;
#if !(defined CONFIG_XENO_COBALT)
static void dev_enable_irq(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* enable/disable level type interrupts, not edge type interrupts */
#if (defined INCLUDE_IRQ_TO_DESC)
if (pIrqDesc->irq_is_level)
#endif
{
atomic_inc(&pIrqDesc->irqStatus);
enable_irq(pIrqDesc->irq);
}
}
static void dev_disable_irq(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* enable/disable level type interrupts, not edge type interrupts */
#if (defined INCLUDE_IRQ_TO_DESC)
if (!pIrqDesc->irq_is_level) return;
#endif
if (atomic_read(&pIrqDesc->irqStatus) > 0)
{
disable_irq_nosync(pIrqDesc->irq);
atomic_dec(&pIrqDesc->irqStatus);
}
}
static int dev_irq_disabled(ATEMSYS_T_IRQ_DESC* pIrqDesc)
{
/* only level type interrupts get disabled */
#if (defined INCLUDE_IRQ_TO_DESC)
if (!pIrqDesc->irq_is_level) return 0;
#endif
if (atomic_read(&pIrqDesc->irqStatus) == 0)
{
return 1;
}
return 0;
}
#endif /* !CONFIG_XENO_COBALT */
#if (!defined __arm__) && (!defined __aarch64__)
static void* dev_dma_alloc(u32 dwLen, dma_addr_t* pDmaAddr)
{
unsigned long virtAddr;
unsigned long tmpAddr;
u32 tmpSize;
virtAddr = __get_free_pages(GFP_KERNEL | GFP_DMA, get_order(dwLen));
if (! virtAddr)
{
ERR("mmap: __get_free_pages failed\n");
return NULL;
}
tmpAddr = virtAddr;
tmpSize = dwLen;
while (tmpSize > 0)
{
SetPageReserved( virt_to_page(tmpAddr) );
tmpAddr += PAGE_SIZE;
tmpSize -= PAGE_SIZE;
}
*pDmaAddr = virt_to_phys((void*) virtAddr);
return (void*) virtAddr;
}
static void dev_dma_free(u32 dwLen, void* virtAddr)
{
unsigned long tmpAddr = (unsigned long) virtAddr;
u32 tmpSize = dwLen;
while (tmpSize > 0)
{
ClearPageReserved( virt_to_page(tmpAddr) );
tmpAddr += PAGE_SIZE;
tmpSize -= PAGE_SIZE;
}
free_pages((unsigned long) virtAddr, get_order(dwLen));
}
#endif /* !__arm__ */
static void dev_munmap(struct vm_area_struct* vma)
{
ATEMSYS_T_MMAP_DESC* pMmapDesc = (ATEMSYS_T_MMAP_DESC*) vma->vm_private_data;
INF("dev_munmap: 0x%px -> 0x%px (%d)\n",
(void*) pMmapDesc->pVirtAddr, (void*)(unsigned long)pMmapDesc->dmaAddr, (int) pMmapDesc->len);
if (0 == pMmapDesc->dmaAddr) { INF("dev_munmap: 0 == pMmapDesc->dmaAddr!\n"); return; }
if (NULL == pMmapDesc->pVirtAddr) { INF("dev_munmap: NULL == pMmapDesc->pVirtAddr!\n"); return; }
/* free DMA memory */
#if (defined CONFIG_PCI)
if (pMmapDesc->pDevDesc->pPcidev == NULL)
#endif
{
#if (defined __arm__) || (defined __aarch64__)
dmam_free_coherent(&pMmapDesc->pDevDesc->pPlatformDev->dev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#else
dev_dma_free(pMmapDesc->len, pMmapDesc->pVirtAddr);
#endif
}
#if (defined CONFIG_PCI)
else
{
#if ((defined __aarch64__) \
|| (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)) \
|| ((defined __arm__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0))) \
|| ((defined __amd64__) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,14,0))) )
dma_free_coherent(&pMmapDesc->pDevDesc->pPcidev->dev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#else
pci_free_consistent(pMmapDesc->pDevDesc->pPcidev, pMmapDesc->len, pMmapDesc->pVirtAddr, pMmapDesc->dmaAddr);
#endif /* __aarch64__ */
}
#endif /* CONFIG_PCI */
kfree(pMmapDesc);
}
#if (defined CONFIG_PCI)
/*
* Lookup PCI device
*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
{
struct pci_dev* dev = NULL;
for_each_pci_dev(dev) {
if (pci_domain_nr(dev->bus) == 0 &&
(dev->bus->number == bus && dev->devfn == devfn))
return dev;
}
return dev;
}
#endif
static int dev_pci_select_device(ATEMSYS_T_DEVICE_DESC* pDevDesc, ATEMSYS_T_PCI_SELECT_DESC* pPciDesc, size_t size)
{
int nRetVal = -EFAULT;
s32 nPciBus, nPciDev, nPciFun, nPciDomain;
switch (size)
{
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_0_00 oPciDesc_v1_0_00;
nRetVal = copy_from_user(&oPciDesc_v1_0_00, (ATEMSYS_T_PCI_SELECT_DESC_v1_0_00*)pPciDesc, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00));
if (0 != nRetVal)
{
ERR("dev_pci_select_device failed: %d\n", nRetVal);
goto Exit;
}
nPciBus = oPciDesc_v1_0_00.nPciBus;
nPciDev = oPciDesc_v1_0_00.nPciDev;
nPciFun = oPciDesc_v1_0_00.nPciFun;
nPciDomain = 0;
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_3_05 oPciDesc_v1_3_05;
nRetVal = copy_from_user(&oPciDesc_v1_3_05, (ATEMSYS_T_PCI_SELECT_DESC_v1_3_05*)pPciDesc, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05));
if (0 != nRetVal)
{
ERR("dev_pci_select_device failed: %d\n", nRetVal);
goto Exit;
}
nPciBus = oPciDesc_v1_3_05.nPciBus;
nPciDev = oPciDesc_v1_3_05.nPciDev;
nPciFun = oPciDesc_v1_3_05.nPciFun;
nPciDomain = oPciDesc_v1_3_05.nPciDomain;
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12):
{
ATEMSYS_T_PCI_SELECT_DESC_v1_4_12 oPciDesc_v1_4_12;
nRetVal = copy_from_user(&oPciDesc_v1_4_12, (ATEMSYS_T_PCI_SELECT_DESC_v1_4_12*)pPciDesc, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12));
if (0 != nRetVal)
{
ERR("dev_pci_select_device failed: %d\n", nRetVal);
goto Exit;
}
nPciBus = oPciDesc_v1_4_12.nPciBus;
nPciDev = oPciDesc_v1_4_12.nPciDev;
nPciFun = oPciDesc_v1_4_12.nPciFun;
nPciDomain = oPciDesc_v1_4_12.nPciDomain;
} break;
default:
{
nRetVal = -EFAULT;
ERR("pci_conf: EFAULT\n");
goto Exit;
}
}
/* Lookup for pci_dev object */
pDevDesc->pPcidev = NULL;
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
pDevDesc->pPciDrvDesc = NULL;
{
unsigned int i = 0;
for (i = 0; i < ATEMSYS_MAX_NUMBER_DRV_INSTANCES; i++)
{
ATEMSYS_T_PCI_DRV_DESC_PRIVATE* pDrvInstance = S_apPciDrvDescPrivate[i];
if ( (pDrvInstance != NULL)
&& (pDrvInstance->nPciDomain == nPciDomain)
&& (pDrvInstance->nPciBus == nPciBus)
&& (pDrvInstance->nPciDev == nPciDev)
&& (pDrvInstance->nPciFun == nPciFun))
{
if (pDrvInstance->pDevDesc != NULL)
{
ERR("dev_pci_select_device: device \"%s\" in use by another instance?\n", pci_name(pDrvInstance->pPciDev));
nRetVal = -EBUSY;
goto Exit;
}
pDevDesc->pPcidev = pDrvInstance->pPciDev;
pDevDesc->pPciDrvDesc = pDrvInstance;
pDrvInstance->pDevDesc = pDevDesc;
INF("pci_select: from pci driver %04x:%02x:%02x.%x\n", (u32)nPciDomain, (u32)nPciBus, (u32)nPciDev, (u32)nPciFun);
break;
}
}
}
if (pDevDesc->pPcidev == NULL)
#endif
{
pDevDesc->pPcidev = pci_get_domain_bus_and_slot(nPciDomain, nPciBus, PCI_DEVFN(nPciDev, nPciFun));
INF("pci_select: %04x:%02x:%02x.%x\n", (u32)nPciDomain, (u32)nPciBus, (u32)nPciDev, (u32)nPciFun);
}
if (pDevDesc->pPcidev == NULL)
{
WRN("pci_select: PCI-Device %04x:%02x:%02x.%x not found\n",
(unsigned) nPciDomain, (unsigned) nPciBus, (unsigned) nPciDev, (unsigned) nPciFun);
goto Exit;
}
nRetVal = DRIVER_SUCCESS;
Exit:
return nRetVal;
}
static int DefaultPciSettings(struct pci_dev* pPciDev)
{
int nRetVal = -EIO;
int nRes = -EIO;
/* Turn on Memory-Write-Invalidate if it is supported by the device*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24))
pci_set_mwi(pPciDev);
#else
pci_try_set_mwi(pPciDev);
#endif
/* remove wrong dma_coherent bit on ARM systems */
#if ((defined __aarch64__) || (defined __arm__))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0))
#if (defined CONFIG_PHYS_ADDR_T_64BIT)
if (is_device_dma_coherent(&pPciDev->dev))
{
pPciDev->dev.archdata.dma_coherent = false;
INF("%s: DefaultPciSettings: Clear device.archdata dma_coherent bit!\n", pci_name(pPciDev));
}
#endif
#endif
#if (LINUX_VERSION_CODE > KERNEL_VERSION(5,0,0))
#if ((defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)))
if (0 != pPciDev->dev.dma_coherent)
{
pPciDev->dev.dma_coherent = 0;
INF("%s: DefaultPciSettings: Clear device dma_coherent bit!\n", pci_name(pPciDev));
}
#endif
#endif
#endif
#if ((LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0)) || !(defined __aarch64__))
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,55))
nRes = dma_set_coherent_mask(&pPciDev->dev, DMA_BIT_MASK(32));
#else
nRes = dma_set_mask_and_coherent(&pPciDev->dev, DMA_BIT_MASK(32));
#endif
if (nRes)
#endif
{
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,55))
nRes = dma_set_coherent_mask(&pPciDev->dev, DMA_BIT_MASK(64));
#else
nRes = dma_set_mask_and_coherent(&pPciDev->dev, DMA_BIT_MASK(64));
#endif
if (nRes)
{
ERR("%s: DefaultPciSettings: dma_set_mask_and_coherent failed\n", pci_name(pPciDev));
nRetVal = nRes;
goto Exit;
}
}
pci_set_master(pPciDev);
/* Try to enable MSI (Message Signaled Interrupts). MSI's are non shared, so we can
* use interrupt mode, also if we have a non exclusive interrupt line with legacy
* interrupts.
*/
if (pci_enable_msi(pPciDev))
{
INF("%s: DefaultPciSettings: legacy INT configured\n", pci_name(pPciDev));
}
else
{
INF("%s: DefaultPciSettings: MSI configured\n", pci_name(pPciDev));
}
nRetVal = 0;
Exit:
return nRetVal;
}
/*
* See also kernel/Documentation/PCI/pci.txt for the recommended PCI initialization sequence
*/
static int ioctl_pci_configure_device(ATEMSYS_T_DEVICE_DESC* pDevDesc, unsigned long ioctlParam, size_t size)
{
int nRetVal = -EIO;
int nRc;
int i;
unsigned long ioBase;
s32 nBar = 0;
u32 dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
ATEMSYS_T_PCI_SELECT_DESC_v1_4_12 oPciDesc;
memset(&oPciDesc, 0, sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12));
switch (size)
{
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_0_00):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,0,0);
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_3_05):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,3,5);
} break;
case sizeof(ATEMSYS_T_PCI_SELECT_DESC_v1_4_12):
{
dwAtemsysApiVersion = EC_ATEMSYSVERSION(1,4,12);
} break;
default:
{
nRetVal = -EIO;
ERR("pci_conf: Invalid parameter\n");
goto Exit;
}
}
if (pDevDesc->pPcidev != NULL)
{
WRN("pci_conf: error call ioctl(ATEMSYS_IOCTL_PCI_RELEASE_DEVICE) first\n");
goto Exit;
}
if (dev_pci_select_device(pDevDesc, (ATEMSYS_T_PCI_SELECT_DESC*)ioctlParam, size) != DRIVER_SUCCESS)
{
goto Exit;
}
#if (defined INCLUDE_ATEMSYS_PCI_DRIVER)
if (NULL != pDevDesc->pPciDrvDesc)
{
for (i = 0; i < pDevDesc->pPciDrvDesc->nBarCnt ; i++)
{
if ((EC_ATEMSYSVERSION(1,4,12) != dwAtemsysApiVersion) && (pDevDesc->pPciDrvDesc->aBars[i].qwIOMem > 0xFFFFFFFF))
{
ERR("pci_conf: 64-Bit IO address not supported\n");
INF("pci_conf: Update LinkLayer for 64-Bit IO address support!\n");
nRetVal = -ENODEV;
goto Exit;
}
oPciDesc.aBar[i].qwIOMem = pDevDesc->pPciDrvDesc->aBars[i].qwIOMem;
oPciDesc.aBar[i].dwIOLen = pDevDesc->pPciDrvDesc->aBars[i].dwIOLen;
}
oPciDesc.nBarCnt = pDevDesc->pPciDrvDesc->nBarCnt;
oPciDesc.dwIrq = (u32)pDevDesc->pPcidev->irq;
}
else
#endif
{
/* enable device */
nRc = pci_enable_device(pDevDesc->pPcidev);
if (nRc < 0)
{
ERR("pci_conf: pci_enable_device failed\n");
pDevDesc->pPcidev = NULL;
goto Exit;
}
/* Check if IO-memory is in use by another driver */
nRc = pci_request_regions(pDevDesc->pPcidev, ATEMSYS_DEVICE_NAME);
if (nRc < 0)
{
ERR("pci_conf: device \"%s\" in use by another driver?\n", pci_name(pDevDesc->pPcidev));
pDevDesc->pPcidev = NULL;
nRetVal = -EBUSY;
goto Exit;
}
/* find the memory BAR */
for (i = 0; i < ATEMSYS_PCI_MAXBAR ; i++)
{
if (pci_resource_flags(pDevDesc->pPcidev, i) & IORESOURCE_MEM)
{
/* IO area address */
ioBase = pci_resource_start(pDevDesc->pPcidev, i);
if ((EC_ATEMSYSVERSION(1,4,12) != dwAtemsysApiVersion) && (ioBase > 0xFFFFFFFF))
{
ERR("pci_conf: 64-Bit IO address not supported\n");
pci_release_regions(pDevDesc->pPcidev);
pDevDesc->pPcidev = NULL;
nRetVal = -ENODEV;
goto Exit;
}
/* IO area length */
oPciDesc.aBar[nBar].dwIOLen = pci_resource_len(pDevDesc->pPcidev, i);
oPciDesc.aBar[nBar].qwIOMem = ioBase;
nBar++;
}
}
nRc = DefaultPciSettings(pDevDesc->pPcidev);
if (nRc)
{
pci_release_regions(pDevDesc->pPcidev);
pDevDesc->pPcidev = NULL;
goto Exit;
}
/* number of memory BARs */
/* assigned IRQ */
oPciDesc.nBarCnt = nBar;