From f243937d796a6d54ffbcbd30348c97661f94944e Mon Sep 17 00:00:00 2001 From: Thibaut Lorrain Date: Sun, 17 Nov 2024 20:39:27 +0100 Subject: [PATCH 1/2] add intellij/rustrover files to gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 90a35c8..4f38a9c 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,4 @@ /example/target **/*.rs.bk Cargo.lock +.idea From 5cada2522fbfb7637d99ac4126f3444b553e0bf9 Mon Sep 17 00:00:00 2001 From: Thibaut Lorrain Date: Sun, 17 Nov 2024 20:41:11 +0100 Subject: [PATCH 2/2] Fix SPI comunication This fixes #25. Any try to call the `init` function will fail with an `UnsupportedChip` error without this (using the defautl `sync` feature). Previous attempts were made to fix this (#28 and #38) but these where made before `embedded-hal` `1.0.0` and currently have conflicts preventing their merge (and can't directly be used in a project using `embedded-hal` `1.0.0` closes #28 --- src/spi.rs | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/spi.rs b/src/spi.rs index 0bd69e3..f8e5584 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -4,6 +4,7 @@ use core::future::Future; #[cfg(feature = "sync")] use embedded_hal::delay::DelayNs; +use embedded_hal::spi::Operation; #[cfg(feature = "sync")] use embedded_hal::spi::SpiDevice; #[cfg(feature = "async")] @@ -157,9 +158,9 @@ where fn write_register(&mut self, register: u8, payload: u8) -> Result<(), Error> { // If the first bit is 0, the register is written. - let transfer = [register & 0x7f, payload]; + let data = [register & 0x7f, payload]; self.spi - .transfer(&mut [], &transfer) + .write(&data) .map_err(|e| Error::Bus(SPIError::SPI(e)))?; Ok(()) } @@ -251,8 +252,11 @@ where register: u8, data: &mut [u8], ) -> Result<(), Error>> { - self.spi - .transfer(data, &[register]) + self.spi + .transaction(&mut [ + Operation::Write(&[register]), + Operation::Read(data) + ]) .await .map_err(|e| Error::Bus(SPIError::SPI(e)))?; Ok(())