From 49dcbfa19f04c7be1784d1eaff7099b40baca841 Mon Sep 17 00:00:00 2001 From: GHA Date: Sun, 17 Nov 2024 16:09:26 +0000 Subject: [PATCH] update 392a0c7aca0e56d644e7f22d972ee7dd8ce2c237 --- .nojekyll | 0 articles/10/index.html | 198 +++ articles/13/index.html | 186 +++ articles/15/index.html | 199 +++ articles/2/index.html | 212 +++ articles/26/index.html | 202 +++ articles/31/index.html | 206 +++ articles/33/index.html | 197 +++ articles/4/index.html | 190 +++ articles/7/index.html | 189 +++ articles/9/index.html | 189 +++ articles/index.html | 508 +++++++ articles/index.xml | 110 ++ cores/21/index.html | 211 +++ cores/24/index.html | 205 +++ cores/36/index.html | 212 +++ cores/index.html | 280 ++++ cores/index.xml | 47 + ...4c0d783408f3c34ea51aabdadcd1da566e657b.css | 1 + favicon.ico | Bin 0 -> 198 bytes img/favicon/android-chrome-192x192.png | Bin 0 -> 6607 bytes img/favicon/android-chrome-512x512.png | Bin 0 -> 17214 bytes img/favicon/apple-touch-icon.png | Bin 0 -> 6810 bytes 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tools/index.html create mode 100644 tools/index.xml create mode 100644 welcome/index.html diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 00000000..e69de29b diff --git a/articles/10/index.html b/articles/10/index.html new file mode 100644 index 00000000..f0b58eed --- /dev/null +++ b/articles/10/index.html @@ -0,0 +1,198 @@ + + + + + + + + + + + + VHDL News + + | + + Learning FPGA programming, key points for a software developer + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
+ +
+ + + +
+ + +
+
+ + + + + + + diff --git a/articles/13/index.html b/articles/13/index.html new file mode 100644 index 00000000..80c630ca --- /dev/null +++ b/articles/13/index.html @@ -0,0 +1,186 @@ + + + + + + + + + + + + VHDL News + + | + + Open Source Formal Verification in VHDL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+
+ + + Open Source Formal Verification in VHDL + + @Ahmad-Zaklouta +
+
+ + #13 + 1 + 0 + + · + 2020/09/07 + + +
+ +
+ + + +
+ +
+
+ + + + + + + diff --git a/articles/15/index.html b/articles/15/index.html new file mode 100644 index 00000000..c0c99ee6 --- /dev/null +++ b/articles/15/index.html @@ -0,0 +1,199 @@ + + + + + + + + + + + + VHDL News + + | + + SusanaCanel - Proyectos VHDL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+
+ + + SusanaCanel - Proyectos VHDL + + @umarcor +
+
+ + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
+ +
+ + + +
+

Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos.

+ +
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+ + + + + + + diff --git a/articles/2/index.html b/articles/2/index.html new file mode 100644 index 00000000..64427063 --- /dev/null +++ b/articles/2/index.html @@ -0,0 +1,212 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+
+ + +
+ +
+ + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
+ +
+ + + +
+
+

During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently:

+
    +
  • How is verification done?
    • +
  • What frameworks are used? Are they used together?
    • +
  • What are the dominant coding styles? Would people align to those if they knew?
    • +
+

Knowing these would help the development of VUnit [1]; where do we put our efforts? do we add functionality or reuse functionality from others? where does it make sense to create tighter integrations with other tools? can we avoid spending time on endless indentation and casing discussions? Just let a tool fix it and move on.

+

It’s not hard to find strong opinions in every possible direction, but we are looking for more solid facts. Facts can be found where data is, and one of the biggest pile of easy accessible data is GitHub. For that reason, we have mined GitHub for relevant information about HDL projects and processed that data to find the most interesting facts.

+

The full story and the code used to derive these facts are part of an open science project, also hosted on GitHub and you can read it as it evolves. As with any open-source project we encourage contributions and suggestions on other interesting facts that we should derive.

+

– Lars Asplund https://www.linkedin.com/pulse/what-can-github-tell-us-hdl-industry-lars-asplund/

+
+ +
+
+ + + + + + + diff --git a/articles/26/index.html b/articles/26/index.html new file mode 100644 index 00000000..ff643072 --- /dev/null +++ b/articles/26/index.html @@ -0,0 +1,202 @@ + + + + + + + + + + + + VHDL News + + | + + Mixed HDL on Fomu, with GHDL and Yosys + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
+ +
+ + + +
+

Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink.

+

NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile.

+ +
+
+ + + + + + + diff --git a/articles/31/index.html b/articles/31/index.html new file mode 100644 index 00000000..99d1c6c2 --- /dev/null +++ b/articles/31/index.html @@ -0,0 +1,206 @@ + + + + + + + + + + + + VHDL News + + | + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
+ +
+ + + +
+

@rodrigomelo9:

+
+

Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA

+
+
+

Links to slides (and coming soon the recording) of the mini crash course about VHDL:

+ +
+ +
+
+ + + + + + + diff --git a/articles/33/index.html b/articles/33/index.html new file mode 100644 index 00000000..9948da91 --- /dev/null +++ b/articles/33/index.html @@ -0,0 +1,197 @@ + + + + + + + + + + + + VHDL News + + | + + OSVVM & UVVM: Differences and Unification + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
+ +
+ + + +
+
+

As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM.

+

At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM.

+

Let me explain why OSVVM is the right methodology to go forward with.

+

https://www.linkedin.com/posts/jimwilliamlewis_osvvm-uvvm-differences-and-unification-activity-6859020534492090368-5KIN

+
+ +
+
+ + + + + + + diff --git a/articles/4/index.html b/articles/4/index.html new file mode 100644 index 00000000..90d497cd --- /dev/null +++ b/articles/4/index.html @@ -0,0 +1,190 @@ + + + + + + + + + + + + VHDL News + + | + + Addressing VHDL Verification Challenges with OSVVM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
+ +
+ + + +
+

An introduction to the capabilities of OSVVM utility and verification component libraries.

+ +
+
+ + + + + + + diff --git a/articles/7/index.html b/articles/7/index.html new file mode 100644 index 00000000..4ce405d1 --- /dev/null +++ b/articles/7/index.html @@ -0,0 +1,189 @@ + + + + + + + + + + + + VHDL News + + | + + Create your own VVC for UVVM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+
+ + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
+
+ + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
+ +
+ + + +
+ +
+
+ + + + + + + diff --git a/articles/9/index.html b/articles/9/index.html new file mode 100644 index 00000000..5e63bd55 --- /dev/null +++ b/articles/9/index.html @@ -0,0 +1,189 @@ + + + + + + + + + + + + VHDL News + + | + + What’s new in VHDL-2019 - VHDLwhiz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+
+ + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
+
+ + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
+ +
+ + + +
+ +
+
+ + + + + + + diff --git a/articles/index.html b/articles/index.html new file mode 100644 index 00000000..50bc6a1c --- /dev/null +++ b/articles/index.html @@ -0,0 +1,508 @@ + + + + + + + + + + + + VHDL News + + | + + Articles + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ +

References to elaborated readings such as docs, papers, books, guides, wikis, etc.

+
+ + + +
+
+ + + OSVVM & UVVM: Differences and Unification + + @umarcor +
+
+ + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
+ +
+ + + + +
+
+ + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + + @umarcor +
+
+ + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
+ +
+ + + + +
+
+ + + Mixed HDL on Fomu, with GHDL and Yosys + + @umarcor +
+
+ + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
+ +
+ + + + +
+
+ + + SusanaCanel - Proyectos VHDL + + @umarcor +
+
+ + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
+ +
+ + + + +
+
+ + + Open Source Formal Verification in VHDL + + @Ahmad-Zaklouta +
+
+ + #13 + 1 + 0 + + · + 2020/09/07 + + +
+ +
+ + + + +
+
+ + + Learning FPGA programming, key points for a software developer + + @eine +
+
+ + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
+ +
+ + + + +
+
+ + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
+
+ + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
+ +
+ + + + +
+
+ + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
+
+ + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
+ +
+ + + + +
+
+ + + Addressing VHDL Verification Challenges with OSVVM + + @tmeissner +
+
+ + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
+ +
+ + + + +
+
+ + + What Can GitHub Tell Us About the HDL Industry? + + @eine +
+
+ + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
+ +
+ + + + +
+
+ + + + diff --git a/articles/index.xml b/articles/index.xml new file mode 100644 index 00000000..a6769e9b --- /dev/null +++ b/articles/index.xml @@ -0,0 +1,110 @@ + + + + Articles on VHDL News + https://vhdl.github.io/news/articles/ + Recent content in Articles on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + Open Source Formal Verification in VHDL + https://vhdl.github.io/news/articles/13/ + Mon, 07 Sep 2020 09:57:20 +0000 + + https://vhdl.github.io/news/articles/13/ + + + + + Learning FPGA programming, key points for a software developer + https://vhdl.github.io/news/articles/10/ + Tue, 01 Sep 2020 16:45:34 +0000 + + https://vhdl.github.io/news/articles/10/ + dev.to/targeted Learning FPGA programming, key points for a software developer (part 1, the time) Learning FPGA programming, key points for a software developer (part 2, registered logic) Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior) + + + + What’s new in VHDL-2019 - VHDLwhiz + https://vhdl.github.io/news/articles/9/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/articles/9/ + + + + + Create your own VVC for UVVM + https://vhdl.github.io/news/articles/7/ + Wed, 19 Aug 2020 12:13:59 +0000 + + https://vhdl.github.io/news/articles/7/ + + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/cores/21/index.html b/cores/21/index.html new file mode 100644 index 00000000..bb757017 --- /dev/null +++ b/cores/21/index.html @@ -0,0 +1,211 @@ + + + + + + + + + + + + VHDL News + + | + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
+ +
+ + + +
+
+

Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools

+

Speakers: Anton Blanchard, IBM & Tristan Gingold, CERN

+

Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux.

+

From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs.

+

This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project.

+
+ +
+
+ + + + + + + diff --git a/cores/24/index.html b/cores/24/index.html new file mode 100644 index 00000000..b8bbd1d7 --- /dev/null +++ b/cores/24/index.html @@ -0,0 +1,205 @@ + + + + + + + + + + + + VHDL News + + | + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
+ +
+ + + +
+

Cryptography IP-cores & tests written in VHDL / Verilog.

+

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

+

The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.

+ +
+
+ + + + + + + diff --git a/cores/36/index.html b/cores/36/index.html new file mode 100644 index 00000000..a530ac0d --- /dev/null +++ b/cores/36/index.html @@ -0,0 +1,212 @@ + + + + + + + + + + + + VHDL News + + | + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + +
+ +
+ + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
+ +
+ + + +
+

+
+

The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz.

+

Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.

+

:interrobang: Want to know more? Check out the project’s rationale.

+

:books: For detailed information take a look at the NEORV32 documentation (online at GitHub-pages).

+

:label: The project’s change log is available in CHANGELOG.md. To see the changes between official releases visit the project’s release page.

+

:package: Exemplary setups targeting various FPGA boards and toolchains to get you started.

+

:kite: Supported by upstream Zephyr OS and FreeRTOS.

+

:bulb: Feel free to open a new issue or start a new discussion if you have questions, comments, ideas or if something is not working as expected. Or have a chat on our gitter channel. See how to contribute.

+

:rocket: Check out the quick links or directly jump to the User Guide to get started setting up your NEORV32 setup!

+
+ +
+
+ + + + + + + diff --git a/cores/index.html b/cores/index.html new file mode 100644 index 00000000..effa8241 --- /dev/null +++ b/cores/index.html @@ -0,0 +1,280 @@ + + + + + + + + + + + + VHDL News + + | + + Cores + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ +

Similar to opencores.org, freerangefactory.org/core or librecores.org, yet another attempt at building a registry of open source VHDL cores, simulation models and implementation constraints.

+
+ + + +
+
+ + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + + @umarcor +
+
+ + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
+ +
+ + + + +
+
+ + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + + @tmeissner +
+
+ + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
+ +
+ + + + +
+
+ + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + + @umarcor +
+
+ + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
+ +
+ + + + +
+
+ + + + diff --git a/cores/index.xml b/cores/index.xml new file mode 100644 index 00000000..5401443e --- /dev/null +++ b/cores/index.xml @@ -0,0 +1,47 @@ + + + + Cores on VHDL News + https://vhdl.github.io/news/cores/ + Recent content in Cores on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. 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  • S3k`>N6Ixf%IJBmjqI13l#q7vkT2KYQc=JLAdqW^A Xw)!mVSzHh8aK#TSxyN + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/index.html b/index.html new file mode 100644 index 00000000..2d5b1234 --- /dev/null +++ b/index.html @@ -0,0 +1,1351 @@ + + + + + + + + + + + + + VHDL News + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
    + +
    + + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
    + +
    + + + + +
    + +
    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
    + +
    + + + + +
    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
    + +
    + + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
    + +
    + + + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    + +
    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
    + +
    + + + + +
    + +
    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
    + +
    + + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
    + +
    + + + + +
    +
    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
    + +
    + + + + +
    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
    + +
    + + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
    + +
    + + + + +
    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
    + +
    + + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
    +
    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    +
    + + + Open Source Formal Verification in VHDL + + @Ahmad-Zaklouta +
    +
    + + #13 + 1 + 0 + + · + 2020/09/07 + + +
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    + + + + +
    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
    + +
    + + + + +
    +
    + + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
    +
    + + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
    + +
    + + + + +
    + +
    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
    + +
    + + + + +
    +
    + + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
    +
    + + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
    + +
    + + + + +
    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + + +
    + +
    + + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
    + +
    + + + + +
    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    +
    + + + + diff --git a/index.xml b/index.xml new file mode 100644 index 00000000..b6a80424 --- /dev/null +++ b/index.xml @@ -0,0 +1,335 @@ + + + + VHDL News + https://vhdl.github.io/news/ + Recent content on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + Welcome to VHDL News + https://vhdl.github.io/news/welcome/ + Mon, 01 Jan 0001 00:00:00 +0000 + + https://vhdl.github.io/news/welcome/ + Welcome to VHDL News Hacker News VHDL News is a bit different from other community sites, and we&rsquo;d appreciate it if you&rsquo;d take a minute to read the following as well as the guidelines. +The community of hardware designers is small, open source HDL is a niche compared to other technology communities, and open source VHDL is a subset of the latter. Users/developers are typically lacking time to write proper docs and/or detailed articles to let their projects be known. + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + Open Source Formal Verification in VHDL + https://vhdl.github.io/news/articles/13/ + Mon, 07 Sep 2020 09:57:20 +0000 + + https://vhdl.github.io/news/articles/13/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + Learning FPGA programming, key points for a software developer + https://vhdl.github.io/news/articles/10/ + Tue, 01 Sep 2020 16:45:34 +0000 + + https://vhdl.github.io/news/articles/10/ + dev.to/targeted Learning FPGA programming, key points for a software developer (part 1, the time) Learning FPGA programming, key points for a software developer (part 2, registered logic) Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior) + + + + What’s new in VHDL-2019 - VHDLwhiz + https://vhdl.github.io/news/articles/9/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/articles/9/ + + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + Create your own VVC for UVVM + https://vhdl.github.io/news/articles/7/ + Wed, 19 Aug 2020 12:13:59 +0000 + + https://vhdl.github.io/news/articles/7/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/past/11/index.html b/past/11/index.html new file mode 100644 index 00000000..9ef37595 --- /dev/null +++ b/past/11/index.html @@ -0,0 +1,212 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + +
    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + +
    +

    The third part was published:

    +
    +

    In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time.

    +

    Number of standard VHDL verification frameworks on GitHub over time

    +

    Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. However, when separating professional and academic users we’re starting to see interesting differences and anomalies in the data.

    +

    The full story and the code used to derive these facts are part of an open science project. Everything can be reviewed and the results can be repeated. We encourage contributions and suggestions on other interesting facts that we should derive.

    +

    – Lars Asplund linkedin.com/pulse/what-can-github-tell-us-hdl-industry-part-3-lars-asplund/

    +
    + +
    +
    + + + + + + + diff --git a/past/14/index.html b/past/14/index.html new file mode 100644 index 00000000..8d56177f --- /dev/null +++ b/past/14/index.html @@ -0,0 +1,210 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + +
    +

    The fourth part was published:

    +
    +

    In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? Especially when most professionals on GitHub don’t share their professional work but rather private projects.

    +

    The first part of this is to accurately establish whether a user on GitHub is a professional or not when the public profile doesn’t share such information. This was a bit of manual work but there are many other sources to that information: copyright notices, Git logs, LinkedIn, Google etc. In the end, only a small fraction of the users couldn’t be identified.

    +

    Second, this study do not expect, nor assume, that the work published by professionals on GitHub is the work produced at their companies. What we study is their practices. Those practices can be the same as the ones used at work or they may choose differently when they can decide on their own. Either way would lead to interesting conclusions. So which one is it? To figure out that we need to analyze where this study is statistically consistent with the Wilson study and where they are significantly different. This is the main theme of the next post but also this week’s findings are touching on the concepts of consistency and significant differences.

    +

    This week we’re looking for anomalies in the data with focus on regional differences. As it turns out only UVM has an even global adoption that is statistically consistent with the global distribution of VHDL users. The other frameworks have global presence but are significantly under and/or over represented in some regions.

    +

    For more information jump directly to the anomaly section of the study or read the full story from the beginning.

    +

    The code used to derive these facts is part of an open science project. Everything can be reviewed and the results can be repeated. We encourage contributions and suggestions on other interesting facts that we should derive.

    +

    – Lars Asplund linkedin.com/pulse/what-can-github-tell-us-hdl-industry-part-4-lars-asplund/

    +
    + +
    +
    + + + + + + + diff --git a/past/17/index.html b/past/17/index.html new file mode 100644 index 00000000..8b61db7b --- /dev/null +++ b/past/17/index.html @@ -0,0 +1,198 @@ + + + + + + + + + + + + VHDL News + + | + + How to convert vhdl to other formats + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
    + +
    + + + +
    +
    +

    I made a list of “How to convert vhdl to …” in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed.

    +

    The format translation can be done with the yosys’s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated).

    +

    In the following examples, ghdl is being used, in what I believe, is the most straightforward way. See ghdl-yosys-plugin#usage for a workflow more adequate for larger projects.

    +
    + +
    +
    + + + + + + + diff --git a/past/19/index.html b/past/19/index.html new file mode 100644 index 00000000..da7930d5 --- /dev/null +++ b/past/19/index.html @@ -0,0 +1,189 @@ + + + + + + + + + + + + VHDL News + + | + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + + + + diff --git a/past/22/index.html b/past/22/index.html new file mode 100644 index 00000000..06ce7cbc --- /dev/null +++ b/past/22/index.html @@ -0,0 +1,197 @@ + + + + + + + + + + + + VHDL News + + | + + VHDL needs you! + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    +
    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
    + +
    + + + +
    +
    +

    Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications.

    +

    Although many people think that the standards community is driven by vendors, that is a mistake noawadays. The working group consists of volunteers, mostly from the user community. At the same time, many people think they are not skilled enough. That’s another mistake. We need all skills, including users who can say ‘I will use that feature if you make it!’. While we always need experienced VHDL users to participate, currently we also need LaTeX users to help out.

    +

    The most immediate task is to migrate existing sources to LaTeX, with minimum to none style/typo fixes; before actual language changes are considered. If you know LaTeX, we need your help! No matter how little or very experienced you are, there is a task for you!

    +

    Find the guidelines for joining the workgroup at TWiki > P1076 > Participating. You can also get in touch with some VASG members at gitter.im/vhdl/General.

    +
    + +
    +
    + + + + + + + diff --git a/past/3/index.html b/past/3/index.html new file mode 100644 index 00000000..6850217f --- /dev/null +++ b/past/3/index.html @@ -0,0 +1,213 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + +
    +
    +

    During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently:

    +
      +
    • How is verification done?
      • +
    • What frameworks are used? Are they used together?
      • +
    • What are the dominant coding styles? Would people align to those if they knew?
      • +
    +

    Knowing these would help the development of VUnit [1]; where do we put our efforts? do we add functionality or reuse functionality from others? where does it make sense to create tighter integrations with other tools? can we avoid spending time on endless indentation and casing discussions? Just let a tool fix it and move on.

    +

    It’s not hard to find strong opinions in every possible direction, but we are looking for more solid facts. Facts can be found where data is, and one of the biggest pile of easy accessible data is GitHub. For that reason, we have mined GitHub for relevant information about HDL projects and processed that data to find the most interesting facts.

    +

    In the first chapter of this series, verification practices are discussed.

    +

    The full story and the code used to derive these facts are also hosted on GitHub and you can read it as it evolves. As with any open-source project we encourage contributions, suggestions, and reviews.

    +

    – Lars Asplund https://www.linkedin.com/pulse/what-can-github-tell-us-hdl-industry-lars-asplund/

    +
    + +
    +
    + + + + + + + diff --git a/past/32/index.html b/past/32/index.html new file mode 100644 index 00000000..853601c6 --- /dev/null +++ b/past/32/index.html @@ -0,0 +1,210 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
    + +
    + + + +
    +

    The fifth part was published, titled Wilson Study Comparison:

    +
    +

    Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks.

    +

    The figure below shows the verification landscape when combining the data from GitHub with that of the Wilson study. The confidence intervals (as indicated by the arrows) are narrower for UVM, OSVVM and UVVM because of the larger sample sizes reached when combining data from two studies. The data for VUnit and cocotb builds solely on GitHub which results in wider confidence intervals. This doesn’t change the fact that these two frameworks play a significant role in contemporary verification practices.

    +

    +

    Before reaching this result it is important to also consider any biases involved and other explanations for the data we see. That and more can be found in the Wilson study comparison section of our study.

    +

    The next post will conclude this series and present our conclusions. In addition, we will also discuss the future of open source verification tools.

    +

    The code used to derive these facts are part of an open science project. Everything can be reviewed and the results can be repeated. We encourage contributions and suggestions on other interesting facts that we should derive.

    +

    – Lars Asplund linkedin.com/pulse/what-can-github-tell-us-hdl-industry-part-5-lars-asplund

    +
    + +
    +
    + + + + + + + diff --git a/past/35/index.html b/past/35/index.html new file mode 100644 index 00000000..652efe51 --- /dev/null +++ b/past/35/index.html @@ -0,0 +1,207 @@ + + + + + + + + + + + + VHDL News + + | + + CHIPS Alliance Announces Xilinx as its Newest Member + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
    + +
    + + + +
    +
    +

    Xilinx to continue to drive forward open source FPGA innovation

    +

    SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud.

    +

    “Xilinx has long been an advocate of open standards and open source,” said Tomas Evensen, CTO Open Source at Xilinx. “As a member of the CHIPS Alliance, we look forward to continuing to spearhead open FPGA initiatives to give everyone the opportunity to innovate faster and do more with their designs.”

    +

    Xilinx collaborated with longstanding CHIPS Alliance members Antmicro and Google to develop the FPGA Interchange Format, which helps to lower design barriers by enabling interoperability between open and closed source FPGA toolchains. Xilinx designed its RapidWright open source platform to work with the Interchange Format. RapidWright enables users to customize implementations to their unique challenges and provides a design methodology using pre-implemented modules with a gateway to back-end tools in Vivado.

    +

    “As the inventor of the FPGA, Xilinx is one of the key companies driving forward innovation in this market,” said Rob Mains, General Manager at CHIPS Alliance. “Xilinx has already been working closely with several CHIPS Alliance members around open source efforts, so it’s great to have them under the CHIPS Alliance umbrella as we plan to boost our FPGA efforts this year.”

    +
    + +
    +
    + + + + + + + diff --git a/past/6/index.html b/past/6/index.html new file mode 100644 index 00000000..3e1dcf78 --- /dev/null +++ b/past/6/index.html @@ -0,0 +1,214 @@ + + + + + + + + + + + + VHDL News + + | + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + +
    +

    The second article/chapter was published:

    +
    +

    In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we’re looking into what standard verification frameworks are being used. The main conclusions are that:

    +
      +
    • VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub.
      • +
    • Most repositories using more than one framework use VUnit and OSVVM.
      • +
    • More than half of the repositories using OSVVM also use VUnit.
      • +
    • UVM is not combined with any other framework.
      • +
    +

    The full story and the code used to derive these facts are part of an open science project. Everything can be reviewed and the results can be repeated. We encourage contributions and suggestions on other interesting facts that we should derive.

    +

    – Lars Asplund https://www.linkedin.com/pulse/what-can-github-tell-us-hdl-industry-part-2-lars-asplund/

    +
    + +
    +
    + + + + + + + diff --git a/past/8/index.html b/past/8/index.html new file mode 100644 index 00000000..05fa822e --- /dev/null +++ b/past/8/index.html @@ -0,0 +1,196 @@ + + + + + + + + + + + + VHDL News + + | + + First VHDL-2019 examples on EDA playground + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
    + +
    + + + +
    +

    First examples of VHDL-2019 on EDA playground supported by Riviera Pro:

    +
      +
    • some of the new features of the std.env package
      • +
    • private and alias in protected types
      • +
    + +
    +
    + + + + + + + diff --git a/past/index.html b/past/index.html new file mode 100644 index 00000000..45f207b8 --- /dev/null +++ b/past/index.html @@ -0,0 +1,538 @@ + + + + + + + + + + + + VHDL News + + | + + Past + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + +

    Main category for content that is not specific enough to fit in the other categories.

    +
    + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
    + +
    + + + + +
    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
    + +
    + + + + +
    +
    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
    + +
    + + + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
    + +
    + + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
    + +
    + + + + +
    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
    + +
    + + + + +
    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    +
    + + + + diff --git a/past/index.xml b/past/index.xml new file mode 100644 index 00000000..5089f1bc --- /dev/null +++ b/past/index.xml @@ -0,0 +1,117 @@ + + + + Past on VHDL News + https://vhdl.github.io/news/past/ + Recent content in Past on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/show/16/index.html b/show/16/index.html new file mode 100644 index 00000000..fb58a078 --- /dev/null +++ b/show/16/index.html @@ -0,0 +1,198 @@ + + + + + + + + + + + + VHDL News + + | + + Combining VUnit tests with cocotb components + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
    + +
    + + + +
    + +
    +
    + + + + + + + diff --git a/show/30/index.html b/show/30/index.html new file mode 100644 index 00000000..2cdc6b90 --- /dev/null +++ b/show/30/index.html @@ -0,0 +1,209 @@ + + + + + + + + + + + + VHDL News + + | + + Open Source Verification Bundle (OSVB) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + +
    +
    +

    OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. The purpose of this bundle is twofold:

    +
      +
    • +

      Allow users of any of the frameworks/methodologies to share some plumbing with others, so that communities can share testbenches written in any framework without having to learn a new workflow from scratch.

      +
      • +
    • +

      Reduce the maintenance burden of the projects by focusing on the features which are unique to a particular framework/methodology, instead of reinventing the wheel.

      +
      • +
    +
    + +
    +
    + + + + + + + diff --git a/show/5/index.html b/show/5/index.html new file mode 100644 index 00000000..499f903e --- /dev/null +++ b/show/5/index.html @@ -0,0 +1,202 @@ + + + + + + + + + + + + VHDL News + + | + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + +
    +

    A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys).

    +

    This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. You can comment out failing assertions if you want to have a successful proof or simulation if you want. You can change them to see what happens.

    + +
    +
    + + + + + + + diff --git a/show/index.html b/show/index.html new file mode 100644 index 00000000..cd36795b --- /dev/null +++ b/show/index.html @@ -0,0 +1,280 @@ + + + + + + + + + + + + VHDL News + + | + + Show + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + +

    Equivalent to Show HN.

    +
    + + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + + +
    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
    + +
    + + + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + + +
    +
    + + + + diff --git a/show/index.xml b/show/index.xml new file mode 100644 index 00000000..43749934 --- /dev/null +++ b/show/index.xml @@ -0,0 +1,42 @@ + + + + Show on VHDL News + https://vhdl.github.io/news/show/ + Recent content in Show on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/sitemap.xml b/sitemap.xml new file mode 100644 index 00000000..a7e2ea9d --- /dev/null +++ b/sitemap.xml @@ -0,0 +1,760 @@ + + + + + https://vhdl.github.io/news/welcome/ + + + + https://vhdl.github.io/news/past/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/show/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/articles/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tools/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/cores/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/ + 2022-02-05T15:46:32+00:00 + 0 + + + + https://vhdl.github.io/news/tags/cfu/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/cpu/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/custom-function/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/gdb/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/neoled/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/neorv32/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/cores/36/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/ocd/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/pwm/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/riscv/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/soc/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/spi/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/stream/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/trng/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/twi/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/vhdl/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/wishbone/ + 2022-02-05T15:46:32+00:00 + + + + https://vhdl.github.io/news/tags/chipalliance/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/past/35/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/fpga/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/interchange/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/rapidwright/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/schema/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/xilinx/ + 2022-02-05T15:33:11+00:00 + + + + https://vhdl.github.io/news/tags/methodology/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tags/osvvm/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/articles/33/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tags/unification/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tags/uvvm/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tags/verification/ + 2021-10-30T02:23:50+00:00 + + + + https://vhdl.github.io/news/tags/cocotb/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/tags/study/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/tags/uvm/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/tags/vunit/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/past/32/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/tags/wilson/ + 2021-10-27T22:36:39+00:00 + + + + https://vhdl.github.io/news/tags/foss/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/tags/ghdl/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/articles/31/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/tags/simulation/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/tags/synthesis/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/tags/workshop/ + 2021-10-21T15:39:55+00:00 + + + + https://vhdl.github.io/news/tags/iverilog/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/show/30/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/osvb/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/renode/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/svunit/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/verilator/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/yosys/ + 2021-10-20T01:13:27+00:00 + + + + https://vhdl.github.io/news/tags/dfu-util/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/eccprog/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/eda/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/fritzing/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/ghdl-yosys-plugin/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/graphviz/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/gtkwave/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/icesprog/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/icestorm/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/kicad/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tools/27/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/msys2/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/nextpnr/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/ngspice/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/openfpgaloader/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/openocd/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/package/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/prjtrellis/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/windows/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/yices2/ + 2021-01-19T06:41:45+00:00 + + + + https://vhdl.github.io/news/tags/examples/ + 2020-12-02T05:34:29+00:00 + + + + https://vhdl.github.io/news/tags/fomu/ + 2020-12-02T05:34:29+00:00 + + + + https://vhdl.github.io/news/articles/26/ + 2020-12-02T05:34:29+00:00 + + + + https://vhdl.github.io/news/tags/verilog/ + 2020-12-02T05:34:29+00:00 + + + + https://vhdl.github.io/news/tags/assertions/ + 2020-11-30T19:50:15+00:00 + + + + https://vhdl.github.io/news/tags/cryptography/ + 2020-11-30T19:50:15+00:00 + + + + https://vhdl.github.io/news/tags/psl/ + 2020-11-30T19:50:15+00:00 + + + + https://vhdl.github.io/news/cores/24/ + 2020-11-30T19:50:15+00:00 + + + + https://vhdl.github.io/news/tools/23/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/debian/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/docker/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/podman/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/symbiyosys/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/z3/ + 2020-11-23T09:09:05+00:00 + + + + https://vhdl.github.io/news/tags/gitlab/ + 2020-11-13T14:39:38+00:00 + + + + https://vhdl.github.io/news/tags/latex/ + 2020-11-13T14:39:38+00:00 + + + + https://vhdl.github.io/news/tags/lrm/ + 2020-11-13T14:39:38+00:00 + + + + https://vhdl.github.io/news/tags/vasg/ + 2020-11-13T14:39:38+00:00 + + + + https://vhdl.github.io/news/past/22/ + 2020-11-13T14:39:38+00:00 + + + + https://vhdl.github.io/news/tags/microwatt/ + 2020-10-27T06:45:43+00:00 + + + + https://vhdl.github.io/news/cores/21/ + 2020-10-27T06:45:43+00:00 + + + + https://vhdl.github.io/news/tools/21/ + 2020-10-27T06:45:43+00:00 + + + + https://vhdl.github.io/news/tags/openisa/ + 2020-10-27T06:45:43+00:00 + + + + https://vhdl.github.io/news/tags/power/ + 2020-10-27T06:45:43+00:00 + + + + https://vhdl.github.io/news/tags/lpf/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tags/pcf/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tags/sdc/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tools/20/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tags/ucf/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tags/xdc/ + 2020-10-22T21:52:32+00:00 + + + + https://vhdl.github.io/news/tags/components/ + 2020-10-09T14:54:20+00:00 + + + + https://vhdl.github.io/news/tags/ice40/ + 2020-10-09T14:54:20+00:00 + + + + https://vhdl.github.io/news/tags/lattice/ + 2020-10-09T14:54:20+00:00 + + + + https://vhdl.github.io/news/past/19/ + 2020-10-09T14:54:20+00:00 + + + + https://vhdl.github.io/news/tags/container/ + 2020-10-09T08:48:50+00:00 + + + + https://vhdl.github.io/news/tools/18/ + 2020-10-09T08:48:50+00:00 + + + + https://vhdl.github.io/news/tags/programming/ + 2020-10-09T08:48:50+00:00 + + + + https://vhdl.github.io/news/tags/btor2/ + 2020-09-28T15:23:01+00:00 + + + + https://vhdl.github.io/news/tags/edif/ + 2020-09-28T15:23:01+00:00 + + + + https://vhdl.github.io/news/tags/firrtl/ + 2020-09-28T15:23:01+00:00 + + + + https://vhdl.github.io/news/past/17/ + 2020-09-28T15:23:01+00:00 + + + + https://vhdl.github.io/news/tags/smt2/ + 2020-09-28T15:23:01+00:00 + + + + https://vhdl.github.io/news/tags/co-simulation/ + 2020-09-28T06:09:01+00:00 + + + + https://vhdl.github.io/news/show/16/ + 2020-09-28T06:09:01+00:00 + + + + https://vhdl.github.io/news/tags/python/ + 2020-09-28T06:09:01+00:00 + + + + https://vhdl.github.io/news/tags/testing/ + 2020-09-28T06:09:01+00:00 + + + + https://vhdl.github.io/news/tags/altera/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/exercises/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/learning/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/modelsim/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/articles/15/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/teaching/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/videos/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/tags/youtube/ + 2020-09-18T03:59:05+00:00 + + + + https://vhdl.github.io/news/past/14/ + 2020-09-18T00:54:44+00:00 + + + + https://vhdl.github.io/news/articles/13/ + 2020-09-07T09:57:20+00:00 + + + + https://vhdl.github.io/news/past/11/ + 2020-09-02T21:33:51+00:00 + + + + https://vhdl.github.io/news/articles/10/ + 2020-09-01T16:45:34+00:00 + + + + https://vhdl.github.io/news/tags/ieee/ + 2020-08-28T17:27:03+00:00 + + + + https://vhdl.github.io/news/tags/vhdl-2019/ + 2020-08-28T17:27:03+00:00 + + + + https://vhdl.github.io/news/tags/vhdlwhiz/ + 2020-08-28T17:27:03+00:00 + + + + https://vhdl.github.io/news/articles/9/ + 2020-08-28T17:27:03+00:00 + + + + https://vhdl.github.io/news/tags/eda-playground/ + 2020-08-22T20:37:41+00:00 + + + + https://vhdl.github.io/news/past/8/ + 2020-08-22T20:37:41+00:00 + + + + https://vhdl.github.io/news/tags/riviera/ + 2020-08-22T20:37:41+00:00 + + + + https://vhdl.github.io/news/articles/7/ + 2020-08-19T12:13:59+00:00 + + + + https://vhdl.github.io/news/past/6/ + 2020-08-19T07:38:22+00:00 + + + + https://vhdl.github.io/news/show/5/ + 2020-08-18T16:31:26+00:00 + + + + https://vhdl.github.io/news/tags/formal-verification/ + 2020-08-18T16:31:26+00:00 + + + + https://vhdl.github.io/news/tags/functional-coverage/ + 2020-08-18T16:31:26+00:00 + + + + https://vhdl.github.io/news/articles/4/ + 2020-08-18T15:03:07+00:00 + + + + https://vhdl.github.io/news/tags/mentor/ + 2020-08-18T15:03:07+00:00 + + + + https://vhdl.github.io/news/past/3/ + 2020-08-18T14:51:44+00:00 + + + + https://vhdl.github.io/news/articles/2/ + 2020-08-18T14:51:02+00:00 + + + \ No newline at end of file diff --git a/tags/altera/index.html b/tags/altera/index.html new file mode 100644 index 00000000..f60819e5 --- /dev/null +++ b/tags/altera/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + altera + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + + + +
    +
    + + + + diff --git a/tags/altera/index.xml b/tags/altera/index.xml new file mode 100644 index 00000000..c532c3f8 --- /dev/null +++ b/tags/altera/index.xml @@ -0,0 +1,23 @@ + + + + altera on VHDL News + https://vhdl.github.io/news/tags/altera/ + Recent content in altera on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + \ No newline at end of file diff --git a/tags/assertions/index.html b/tags/assertions/index.html new file mode 100644 index 00000000..d58a1f16 --- /dev/null +++ b/tags/assertions/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + assertions + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
    + +
    + + + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
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    + + + + +
    +
    + + + + diff --git a/tags/assertions/index.xml b/tags/assertions/index.xml new file mode 100644 index 00000000..f404f5cf --- /dev/null +++ b/tags/assertions/index.xml @@ -0,0 +1,35 @@ + + + + assertions on VHDL News + https://vhdl.github.io/news/tags/assertions/ + Recent content in assertions on VHDL News + Hugo -- gohugo.io + Mon, 30 Nov 2020 19:50:15 +0000 + + + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/btor2/index.html b/tags/btor2/index.html new file mode 100644 index 00000000..a8bbc070 --- /dev/null +++ b/tags/btor2/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + btor2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
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    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    + + + + +
    +
    + + + + diff --git a/tags/btor2/index.xml b/tags/btor2/index.xml new file mode 100644 index 00000000..760dc77d --- /dev/null +++ b/tags/btor2/index.xml @@ -0,0 +1,25 @@ + + + + btor2 on VHDL News + https://vhdl.github.io/news/tags/btor2/ + Recent content in btor2 on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 15:23:01 +0000 + + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/cfu/index.html b/tags/cfu/index.html new file mode 100644 index 00000000..3d15eac7 --- /dev/null +++ b/tags/cfu/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + CFU + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/cfu/index.xml b/tags/cfu/index.xml new file mode 100644 index 00000000..e12ae779 --- /dev/null +++ b/tags/cfu/index.xml @@ -0,0 +1,24 @@ + + + + CFU on VHDL News + https://vhdl.github.io/news/tags/cfu/ + Recent content in CFU on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/chipalliance/index.html b/tags/chipalliance/index.html new file mode 100644 index 00000000..edd0ba30 --- /dev/null +++ b/tags/chipalliance/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + CHIPAlliance + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
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    + + + + diff --git a/tags/chipalliance/index.xml b/tags/chipalliance/index.xml new file mode 100644 index 00000000..886ea64e --- /dev/null +++ b/tags/chipalliance/index.xml @@ -0,0 +1,24 @@ + + + + CHIPAlliance on VHDL News + https://vhdl.github.io/news/tags/chipalliance/ + Recent content in CHIPAlliance on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + \ No newline at end of file diff --git a/tags/co-simulation/index.html b/tags/co-simulation/index.html new file mode 100644 index 00000000..8a44ebd2 --- /dev/null +++ b/tags/co-simulation/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + co-simulation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    + + + + diff --git a/tags/co-simulation/index.xml b/tags/co-simulation/index.xml new file mode 100644 index 00000000..41c17f02 --- /dev/null +++ b/tags/co-simulation/index.xml @@ -0,0 +1,23 @@ + + + + co-simulation on VHDL News + https://vhdl.github.io/news/tags/co-simulation/ + Recent content in co-simulation on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 06:09:01 +0000 + + + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + \ No newline at end of file diff --git a/tags/cocotb/index.html b/tags/cocotb/index.html new file mode 100644 index 00000000..8e28b79b --- /dev/null +++ b/tags/cocotb/index.html @@ -0,0 +1,487 @@ + + + + + + + + + + + + VHDL News + + | + + cocotb + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + + + diff --git a/tags/cocotb/index.xml b/tags/cocotb/index.xml new file mode 100644 index 00000000..3d87673c --- /dev/null +++ b/tags/cocotb/index.xml @@ -0,0 +1,95 @@ + + + + cocotb on VHDL News + https://vhdl.github.io/news/tags/cocotb/ + Recent content in cocotb on VHDL News + Hugo -- gohugo.io + Wed, 27 Oct 2021 22:36:39 +0000 + + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/components/index.html b/tags/components/index.html new file mode 100644 index 00000000..1b98907d --- /dev/null +++ b/tags/components/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + components + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + diff --git a/tags/components/index.xml b/tags/components/index.xml new file mode 100644 index 00000000..448e5b97 --- /dev/null +++ b/tags/components/index.xml @@ -0,0 +1,23 @@ + + + + components on VHDL News + https://vhdl.github.io/news/tags/components/ + Recent content in components on VHDL News + Hugo -- gohugo.io + Fri, 09 Oct 2020 14:54:20 +0000 + + + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + \ No newline at end of file diff --git a/tags/container/index.html b/tags/container/index.html new file mode 100644 index 00000000..d7815114 --- /dev/null +++ b/tags/container/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + container + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
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    + + + + diff --git a/tags/container/index.xml b/tags/container/index.xml new file mode 100644 index 00000000..f24441f7 --- /dev/null +++ b/tags/container/index.xml @@ -0,0 +1,23 @@ + + + + container on VHDL News + https://vhdl.github.io/news/tags/container/ + Recent content in container on VHDL News + Hugo -- gohugo.io + Fri, 09 Oct 2020 08:48:50 +0000 + + + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + \ No newline at end of file diff --git a/tags/cpu/index.html b/tags/cpu/index.html new file mode 100644 index 00000000..ffa1720f --- /dev/null +++ b/tags/cpu/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + cpu + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/cpu/index.xml b/tags/cpu/index.xml new file mode 100644 index 00000000..9e4b4d4c --- /dev/null +++ b/tags/cpu/index.xml @@ -0,0 +1,24 @@ + + + + cpu on VHDL News + https://vhdl.github.io/news/tags/cpu/ + Recent content in cpu on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/cryptography/index.html b/tags/cryptography/index.html new file mode 100644 index 00000000..c5be02ea --- /dev/null +++ b/tags/cryptography/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + cryptography + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
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    + + + + diff --git a/tags/cryptography/index.xml b/tags/cryptography/index.xml new file mode 100644 index 00000000..9d6102d1 --- /dev/null +++ b/tags/cryptography/index.xml @@ -0,0 +1,25 @@ + + + + cryptography on VHDL News + https://vhdl.github.io/news/tags/cryptography/ + Recent content in cryptography on VHDL News + Hugo -- gohugo.io + Mon, 30 Nov 2020 19:50:15 +0000 + + + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + \ No newline at end of file diff --git a/tags/custom-function/index.html b/tags/custom-function/index.html new file mode 100644 index 00000000..cd825ef3 --- /dev/null +++ b/tags/custom-function/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + custom-function + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/custom-function/index.xml b/tags/custom-function/index.xml new file mode 100644 index 00000000..3ef12355 --- /dev/null +++ b/tags/custom-function/index.xml @@ -0,0 +1,24 @@ + + + + custom-function on VHDL News + https://vhdl.github.io/news/tags/custom-function/ + Recent content in custom-function on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/debian/index.html b/tags/debian/index.html new file mode 100644 index 00000000..e634b48c --- /dev/null +++ b/tags/debian/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + debian + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + diff --git a/tags/debian/index.xml b/tags/debian/index.xml new file mode 100644 index 00000000..56372fc3 --- /dev/null +++ b/tags/debian/index.xml @@ -0,0 +1,26 @@ + + + + debian on VHDL News + https://vhdl.github.io/news/tags/debian/ + Recent content in debian on VHDL News + Hugo -- gohugo.io + Mon, 23 Nov 2020 09:09:05 +0000 + + + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/dfu-util/index.html b/tags/dfu-util/index.html new file mode 100644 index 00000000..7213a4bd --- /dev/null +++ b/tags/dfu-util/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + dfu-util + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
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    + + + + diff --git a/tags/docker/index.xml b/tags/docker/index.xml new file mode 100644 index 00000000..849252a2 --- /dev/null +++ b/tags/docker/index.xml @@ -0,0 +1,35 @@ + + + + docker on VHDL News + https://vhdl.github.io/news/tags/docker/ + Recent content in docker on VHDL News + Hugo -- gohugo.io + Mon, 23 Nov 2020 09:09:05 +0000 + + + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + \ No newline at end of file diff --git a/tags/eccprog/index.html b/tags/eccprog/index.html new file mode 100644 index 00000000..bbc22a72 --- /dev/null +++ b/tags/eccprog/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + eccprog + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/eccprog/index.xml b/tags/eccprog/index.xml new file mode 100644 index 00000000..6e3dab97 --- /dev/null +++ b/tags/eccprog/index.xml @@ -0,0 +1,23 @@ + + + + eccprog on VHDL News + https://vhdl.github.io/news/tags/eccprog/ + Recent content in eccprog on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/eda-playground/index.html b/tags/eda-playground/index.html new file mode 100644 index 00000000..e06bc41e --- /dev/null +++ b/tags/eda-playground/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + eda-playground + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/eda-playground/index.xml b/tags/eda-playground/index.xml new file mode 100644 index 00000000..bb429b63 --- /dev/null +++ b/tags/eda-playground/index.xml @@ -0,0 +1,24 @@ + + + + eda-playground on VHDL News + https://vhdl.github.io/news/tags/eda-playground/ + Recent content in eda-playground on VHDL News + Hugo -- gohugo.io + Sat, 22 Aug 2020 20:37:41 +0000 + + + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + \ No newline at end of file diff --git a/tags/eda/index.html b/tags/eda/index.html new file mode 100644 index 00000000..ef8b429a --- /dev/null +++ b/tags/eda/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + EDA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/eda/index.xml b/tags/eda/index.xml new file mode 100644 index 00000000..2026bb4c --- /dev/null +++ b/tags/eda/index.xml @@ -0,0 +1,23 @@ + + + + EDA on VHDL News + https://vhdl.github.io/news/tags/eda/ + Recent content in EDA on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/edif/index.html b/tags/edif/index.html new file mode 100644 index 00000000..84b10a5c --- /dev/null +++ b/tags/edif/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + edif + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/edif/index.xml b/tags/edif/index.xml new file mode 100644 index 00000000..efb03149 --- /dev/null +++ b/tags/edif/index.xml @@ -0,0 +1,25 @@ + + + + edif on VHDL News + https://vhdl.github.io/news/tags/edif/ + Recent content in edif on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 15:23:01 +0000 + + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/examples/index.html b/tags/examples/index.html new file mode 100644 index 00000000..4b0ba556 --- /dev/null +++ b/tags/examples/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + examples + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/examples/index.xml b/tags/examples/index.xml new file mode 100644 index 00000000..5f371916 --- /dev/null +++ b/tags/examples/index.xml @@ -0,0 +1,24 @@ + + + + examples on VHDL News + https://vhdl.github.io/news/tags/examples/ + Recent content in examples on VHDL News + Hugo -- gohugo.io + Wed, 02 Dec 2020 05:34:29 +0000 + + + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + \ No newline at end of file diff --git a/tags/exercises/index.html b/tags/exercises/index.html new file mode 100644 index 00000000..6e452031 --- /dev/null +++ b/tags/exercises/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + exercises + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
    +
    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/exercises/index.xml b/tags/exercises/index.xml new file mode 100644 index 00000000..33e93616 --- /dev/null +++ b/tags/exercises/index.xml @@ -0,0 +1,23 @@ + + + + exercises on VHDL News + https://vhdl.github.io/news/tags/exercises/ + Recent content in exercises on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + \ No newline at end of file diff --git a/tags/firrtl/index.html b/tags/firrtl/index.html new file mode 100644 index 00000000..b10cf2e1 --- /dev/null +++ b/tags/firrtl/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + firrtl + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/firrtl/index.xml b/tags/firrtl/index.xml new file mode 100644 index 00000000..66275181 --- /dev/null +++ b/tags/firrtl/index.xml @@ -0,0 +1,25 @@ + + + + firrtl on VHDL News + https://vhdl.github.io/news/tags/firrtl/ + Recent content in firrtl on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 15:23:01 +0000 + + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/fomu/index.html b/tags/fomu/index.html new file mode 100644 index 00000000..5cceb88c --- /dev/null +++ b/tags/fomu/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + fomu + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/fomu/index.xml b/tags/fomu/index.xml new file mode 100644 index 00000000..b4e1329a --- /dev/null +++ b/tags/fomu/index.xml @@ -0,0 +1,24 @@ + + + + fomu on VHDL News + https://vhdl.github.io/news/tags/fomu/ + Recent content in fomu on VHDL News + Hugo -- gohugo.io + Wed, 02 Dec 2020 05:34:29 +0000 + + + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + \ No newline at end of file diff --git a/tags/formal-verification/index.html b/tags/formal-verification/index.html new file mode 100644 index 00000000..f5c04cff --- /dev/null +++ b/tags/formal-verification/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + formal-verification + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/formal-verification/index.xml b/tags/formal-verification/index.xml new file mode 100644 index 00000000..6a0977fc --- /dev/null +++ b/tags/formal-verification/index.xml @@ -0,0 +1,24 @@ + + + + formal-verification on VHDL News + https://vhdl.github.io/news/tags/formal-verification/ + Recent content in formal-verification on VHDL News + Hugo -- gohugo.io + Tue, 18 Aug 2020 16:31:26 +0000 + + + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/foss/index.html b/tags/foss/index.html new file mode 100644 index 00000000..4b77af60 --- /dev/null +++ b/tags/foss/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + foss + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/foss/index.xml b/tags/foss/index.xml new file mode 100644 index 00000000..038e4477 --- /dev/null +++ b/tags/foss/index.xml @@ -0,0 +1,26 @@ + + + + foss on VHDL News + https://vhdl.github.io/news/tags/foss/ + Recent content in foss on VHDL News + Hugo -- gohugo.io + Thu, 21 Oct 2021 15:39:55 +0000 + + + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + \ No newline at end of file diff --git a/tags/fpga/index.html b/tags/fpga/index.html new file mode 100644 index 00000000..6176ed25 --- /dev/null +++ b/tags/fpga/index.html @@ -0,0 +1,301 @@ + + + + + + + + + + + + VHDL News + + | + + fpga + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
    + +
    + + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
    + +
    + + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + + +
    + +
    + + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/fpga/index.xml b/tags/fpga/index.xml new file mode 100644 index 00000000..83517797 --- /dev/null +++ b/tags/fpga/index.xml @@ -0,0 +1,54 @@ + + + + fpga on VHDL News + https://vhdl.github.io/news/tags/fpga/ + Recent content in fpga on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + Learning FPGA programming, key points for a software developer + https://vhdl.github.io/news/articles/10/ + Tue, 01 Sep 2020 16:45:34 +0000 + + https://vhdl.github.io/news/articles/10/ + dev.to/targeted Learning FPGA programming, key points for a software developer (part 1, the time) Learning FPGA programming, key points for a software developer (part 2, registered logic) Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior) + + + + \ No newline at end of file diff --git a/tags/fritzing/index.html b/tags/fritzing/index.html new file mode 100644 index 00000000..c114b97d --- /dev/null +++ b/tags/fritzing/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + fritzing + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/fritzing/index.xml b/tags/fritzing/index.xml new file mode 100644 index 00000000..8da091d6 --- /dev/null +++ b/tags/fritzing/index.xml @@ -0,0 +1,23 @@ + + + + fritzing on VHDL News + https://vhdl.github.io/news/tags/fritzing/ + Recent content in fritzing on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/functional-coverage/index.html b/tags/functional-coverage/index.html new file mode 100644 index 00000000..3bcdbc92 --- /dev/null +++ b/tags/functional-coverage/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + functional-coverage + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/functional-coverage/index.xml b/tags/functional-coverage/index.xml new file mode 100644 index 00000000..4ccc905d --- /dev/null +++ b/tags/functional-coverage/index.xml @@ -0,0 +1,24 @@ + + + + functional-coverage on VHDL News + https://vhdl.github.io/news/tags/functional-coverage/ + Recent content in functional-coverage on VHDL News + Hugo -- gohugo.io + Tue, 18 Aug 2020 16:31:26 +0000 + + + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/gdb/index.html b/tags/gdb/index.html new file mode 100644 index 00000000..f3220320 --- /dev/null +++ b/tags/gdb/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + gdb + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/gdb/index.xml b/tags/gdb/index.xml new file mode 100644 index 00000000..3bc2ceec --- /dev/null +++ b/tags/gdb/index.xml @@ -0,0 +1,24 @@ + + + + gdb on VHDL News + https://vhdl.github.io/news/tags/gdb/ + Recent content in gdb on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/ghdl-yosys-plugin/index.html b/tags/ghdl-yosys-plugin/index.html new file mode 100644 index 00000000..722fd476 --- /dev/null +++ b/tags/ghdl-yosys-plugin/index.html @@ -0,0 +1,259 @@ + + + + + + + + + + + + VHDL News + + | + + ghdl-yosys-plugin + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
    + +
    + + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    + + + + +
    +
    + + + + diff --git a/tags/ghdl-yosys-plugin/index.xml b/tags/ghdl-yosys-plugin/index.xml new file mode 100644 index 00000000..cf8d73de --- /dev/null +++ b/tags/ghdl-yosys-plugin/index.xml @@ -0,0 +1,43 @@ + + + + ghdl-yosys-plugin on VHDL News + https://vhdl.github.io/news/tags/ghdl-yosys-plugin/ + Recent content in ghdl-yosys-plugin on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/ghdl/index.html b/tags/ghdl/index.html new file mode 100644 index 00000000..da9f3714 --- /dev/null +++ b/tags/ghdl/index.html @@ -0,0 +1,637 @@ + + + + + + + + + + + + VHDL News + + | + + ghdl + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
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    + + + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + +
    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + +
    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
    + +
    + + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
    + +
    + + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/ghdl/index.xml b/tags/ghdl/index.xml new file mode 100644 index 00000000..7b364ce5 --- /dev/null +++ b/tags/ghdl/index.xml @@ -0,0 +1,140 @@ + + + + ghdl on VHDL News + https://vhdl.github.io/news/tags/ghdl/ + Recent content in ghdl on VHDL News + Hugo -- gohugo.io + Thu, 21 Oct 2021 15:39:55 +0000 + + + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/gitlab/index.html b/tags/gitlab/index.html new file mode 100644 index 00000000..0cf5445e --- /dev/null +++ b/tags/gitlab/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + GitLab + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
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    + + + + diff --git a/tags/gitlab/index.xml b/tags/gitlab/index.xml new file mode 100644 index 00000000..76a96008 --- /dev/null +++ b/tags/gitlab/index.xml @@ -0,0 +1,24 @@ + + + + GitLab on VHDL News + https://vhdl.github.io/news/tags/gitlab/ + Recent content in GitLab on VHDL News + Hugo -- gohugo.io + Fri, 13 Nov 2020 14:39:38 +0000 + + + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + \ No newline at end of file diff --git a/tags/graphviz/index.html b/tags/graphviz/index.html new file mode 100644 index 00000000..8bfc285f --- /dev/null +++ b/tags/graphviz/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + Graphviz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/graphviz/index.xml b/tags/graphviz/index.xml new file mode 100644 index 00000000..bc8c9b4c --- /dev/null +++ b/tags/graphviz/index.xml @@ -0,0 +1,23 @@ + + + + Graphviz on VHDL News + https://vhdl.github.io/news/tags/graphviz/ + Recent content in Graphviz on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/gtkwave/index.html b/tags/gtkwave/index.html new file mode 100644 index 00000000..2597ca91 --- /dev/null +++ b/tags/gtkwave/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + gtkwave + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + diff --git a/tags/gtkwave/index.xml b/tags/gtkwave/index.xml new file mode 100644 index 00000000..1866c951 --- /dev/null +++ b/tags/gtkwave/index.xml @@ -0,0 +1,35 @@ + + + + gtkwave on VHDL News + https://vhdl.github.io/news/tags/gtkwave/ + Recent content in gtkwave on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/ice40/index.html b/tags/ice40/index.html new file mode 100644 index 00000000..f9d2d834 --- /dev/null +++ b/tags/ice40/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + ice40 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + diff --git a/tags/ice40/index.xml b/tags/ice40/index.xml new file mode 100644 index 00000000..a3d56ef5 --- /dev/null +++ b/tags/ice40/index.xml @@ -0,0 +1,23 @@ + + + + ice40 on VHDL News + https://vhdl.github.io/news/tags/ice40/ + Recent content in ice40 on VHDL News + Hugo -- gohugo.io + Fri, 09 Oct 2020 14:54:20 +0000 + + + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + \ No newline at end of file diff --git a/tags/icesprog/index.html b/tags/icesprog/index.html new file mode 100644 index 00000000..88c259df --- /dev/null +++ b/tags/icesprog/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + icesprog + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/icesprog/index.xml b/tags/icesprog/index.xml new file mode 100644 index 00000000..8df19a15 --- /dev/null +++ b/tags/icesprog/index.xml @@ -0,0 +1,23 @@ + + + + icesprog on VHDL News + https://vhdl.github.io/news/tags/icesprog/ + Recent content in icesprog on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/icestorm/index.html b/tags/icestorm/index.html new file mode 100644 index 00000000..3e8ab058 --- /dev/null +++ b/tags/icestorm/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + icestorm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/icestorm/index.xml b/tags/icestorm/index.xml new file mode 100644 index 00000000..3382bb96 --- /dev/null +++ b/tags/icestorm/index.xml @@ -0,0 +1,35 @@ + + + + icestorm on VHDL News + https://vhdl.github.io/news/tags/icestorm/ + Recent content in icestorm on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/ieee/index.html b/tags/ieee/index.html new file mode 100644 index 00000000..787f5166 --- /dev/null +++ b/tags/ieee/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + ieee + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
    +
    + + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
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    + + + + diff --git a/tags/ieee/index.xml b/tags/ieee/index.xml new file mode 100644 index 00000000..70853a1b --- /dev/null +++ b/tags/ieee/index.xml @@ -0,0 +1,23 @@ + + + + ieee on VHDL News + https://vhdl.github.io/news/tags/ieee/ + Recent content in ieee on VHDL News + Hugo -- gohugo.io + Fri, 28 Aug 2020 17:27:03 +0000 + + + + + + What’s new in VHDL-2019 - VHDLwhiz + https://vhdl.github.io/news/articles/9/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/articles/9/ + + + + + \ No newline at end of file diff --git a/tags/index.html b/tags/index.html new file mode 100644 index 00000000..1150f43f --- /dev/null +++ b/tags/index.html @@ -0,0 +1,940 @@ + + + + + + + + + + + + VHDL News + + | + + Posts tagged with + + Tags + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + + diff --git a/tags/index.xml b/tags/index.xml new file mode 100644 index 00000000..203e5c83 --- /dev/null +++ b/tags/index.xml @@ -0,0 +1,1022 @@ + + + + Tags on VHDL News + https://vhdl.github.io/news/tags/ + Recent content in Tags on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + CFU + https://vhdl.github.io/news/tags/cfu/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/cfu/ + + + + + cpu + https://vhdl.github.io/news/tags/cpu/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/cpu/ + + + + + custom-function + https://vhdl.github.io/news/tags/custom-function/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/custom-function/ + + + + + gdb + https://vhdl.github.io/news/tags/gdb/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/gdb/ + + + + + NEOLED + https://vhdl.github.io/news/tags/neoled/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/neoled/ + + + + + neorv32 + https://vhdl.github.io/news/tags/neorv32/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/neorv32/ + + + + + OCD + https://vhdl.github.io/news/tags/ocd/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/ocd/ + + + + + PWM + https://vhdl.github.io/news/tags/pwm/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/pwm/ + + + + + riscv + https://vhdl.github.io/news/tags/riscv/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/riscv/ + + + + + soc + https://vhdl.github.io/news/tags/soc/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/soc/ + + + + + SPI + https://vhdl.github.io/news/tags/spi/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/spi/ + + + + + stream + https://vhdl.github.io/news/tags/stream/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/stream/ + + + + + TRNG + https://vhdl.github.io/news/tags/trng/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/trng/ + + + + + TWI + https://vhdl.github.io/news/tags/twi/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/twi/ + + + + + vhdl + https://vhdl.github.io/news/tags/vhdl/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/vhdl/ + + + + + wishbone + https://vhdl.github.io/news/tags/wishbone/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/tags/wishbone/ + + + + + CHIPAlliance + https://vhdl.github.io/news/tags/chipalliance/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/chipalliance/ + + + + + fpga + https://vhdl.github.io/news/tags/fpga/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/fpga/ + + + + + interchange + https://vhdl.github.io/news/tags/interchange/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/interchange/ + + + + + rapidwright + https://vhdl.github.io/news/tags/rapidwright/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/rapidwright/ + + + + + schema + https://vhdl.github.io/news/tags/schema/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/schema/ + + + + + xilinx + https://vhdl.github.io/news/tags/xilinx/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/tags/xilinx/ + + + + + methodology + https://vhdl.github.io/news/tags/methodology/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/tags/methodology/ + + + + + osvvm + https://vhdl.github.io/news/tags/osvvm/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/tags/osvvm/ + + + + + unification + https://vhdl.github.io/news/tags/unification/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/tags/unification/ + + + + + uvvm + https://vhdl.github.io/news/tags/uvvm/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/tags/uvvm/ + + + + + verification + https://vhdl.github.io/news/tags/verification/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/tags/verification/ + + + + + cocotb + https://vhdl.github.io/news/tags/cocotb/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/tags/cocotb/ + + + + + study + https://vhdl.github.io/news/tags/study/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/tags/study/ + + + + + uvm + https://vhdl.github.io/news/tags/uvm/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/tags/uvm/ + + + + + vunit + https://vhdl.github.io/news/tags/vunit/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/tags/vunit/ + + + + + wilson + https://vhdl.github.io/news/tags/wilson/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/tags/wilson/ + + + + + foss + https://vhdl.github.io/news/tags/foss/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/tags/foss/ + + + + + ghdl + https://vhdl.github.io/news/tags/ghdl/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/tags/ghdl/ + + + + + simulation + https://vhdl.github.io/news/tags/simulation/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/tags/simulation/ + + + + + synthesis + https://vhdl.github.io/news/tags/synthesis/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/tags/synthesis/ + + + + + workshop + https://vhdl.github.io/news/tags/workshop/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/tags/workshop/ + + + + + iverilog + https://vhdl.github.io/news/tags/iverilog/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/iverilog/ + + + + + osvb + https://vhdl.github.io/news/tags/osvb/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/osvb/ + + + + + renode + https://vhdl.github.io/news/tags/renode/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/renode/ + + + + + svunit + https://vhdl.github.io/news/tags/svunit/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/svunit/ + + + + + verilator + https://vhdl.github.io/news/tags/verilator/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/verilator/ + + + + + yosys + https://vhdl.github.io/news/tags/yosys/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/tags/yosys/ + + + + + dfu-util + https://vhdl.github.io/news/tags/dfu-util/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/dfu-util/ + + + + + eccprog + https://vhdl.github.io/news/tags/eccprog/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/eccprog/ + + + + + EDA + https://vhdl.github.io/news/tags/eda/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/eda/ + + + + + fritzing + https://vhdl.github.io/news/tags/fritzing/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/fritzing/ + + + + + ghdl-yosys-plugin + https://vhdl.github.io/news/tags/ghdl-yosys-plugin/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/ghdl-yosys-plugin/ + + + + + Graphviz + https://vhdl.github.io/news/tags/graphviz/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/graphviz/ + + + + + gtkwave + https://vhdl.github.io/news/tags/gtkwave/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/gtkwave/ + + + + + icesprog + https://vhdl.github.io/news/tags/icesprog/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/icesprog/ + + + + + icestorm + https://vhdl.github.io/news/tags/icestorm/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/icestorm/ + + + + + KiCad + https://vhdl.github.io/news/tags/kicad/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/kicad/ + + + + + MSYS2 + https://vhdl.github.io/news/tags/msys2/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/msys2/ + + + + + nextpnr + https://vhdl.github.io/news/tags/nextpnr/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/nextpnr/ + + + + + ngspice + https://vhdl.github.io/news/tags/ngspice/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/ngspice/ + + + + + openFPGALoader + https://vhdl.github.io/news/tags/openfpgaloader/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/openfpgaloader/ + + + + + OpenOCD + https://vhdl.github.io/news/tags/openocd/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/openocd/ + + + + + package + https://vhdl.github.io/news/tags/package/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/package/ + + + + + prjtrellis + https://vhdl.github.io/news/tags/prjtrellis/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/prjtrellis/ + + + + + Windows + https://vhdl.github.io/news/tags/windows/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/windows/ + + + + + yices2 + https://vhdl.github.io/news/tags/yices2/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tags/yices2/ + + + + + examples + https://vhdl.github.io/news/tags/examples/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/tags/examples/ + + + + + fomu + https://vhdl.github.io/news/tags/fomu/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/tags/fomu/ + + + + + verilog + https://vhdl.github.io/news/tags/verilog/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/tags/verilog/ + + + + + assertions + https://vhdl.github.io/news/tags/assertions/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/tags/assertions/ + + + + + cryptography + https://vhdl.github.io/news/tags/cryptography/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/tags/cryptography/ + + + + + psl + https://vhdl.github.io/news/tags/psl/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/tags/psl/ + + + + + debian + https://vhdl.github.io/news/tags/debian/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tags/debian/ + + + + + docker + https://vhdl.github.io/news/tags/docker/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tags/docker/ + + + + + podman + https://vhdl.github.io/news/tags/podman/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tags/podman/ + + + + + symbiyosys + https://vhdl.github.io/news/tags/symbiyosys/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tags/symbiyosys/ + + + + + z3 + https://vhdl.github.io/news/tags/z3/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tags/z3/ + + + + + GitLab + https://vhdl.github.io/news/tags/gitlab/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/tags/gitlab/ + + + + + LaTeX + https://vhdl.github.io/news/tags/latex/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/tags/latex/ + + + + + LRM + https://vhdl.github.io/news/tags/lrm/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/tags/lrm/ + + + + + VASG + https://vhdl.github.io/news/tags/vasg/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/tags/vasg/ + + + + + microwatt + https://vhdl.github.io/news/tags/microwatt/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tags/microwatt/ + + + + + openisa + https://vhdl.github.io/news/tags/openisa/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tags/openisa/ + + + + + power + https://vhdl.github.io/news/tags/power/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tags/power/ + + + + + lpf + https://vhdl.github.io/news/tags/lpf/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tags/lpf/ + + + + + pcf + https://vhdl.github.io/news/tags/pcf/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tags/pcf/ + + + + + sdc + https://vhdl.github.io/news/tags/sdc/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tags/sdc/ + + + + + ucf + https://vhdl.github.io/news/tags/ucf/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tags/ucf/ + + + + + xdc + https://vhdl.github.io/news/tags/xdc/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tags/xdc/ + + + + + components + https://vhdl.github.io/news/tags/components/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/tags/components/ + + + + + ice40 + https://vhdl.github.io/news/tags/ice40/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/tags/ice40/ + + + + + lattice + https://vhdl.github.io/news/tags/lattice/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/tags/lattice/ + + + + + container + https://vhdl.github.io/news/tags/container/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tags/container/ + + + + + programming + https://vhdl.github.io/news/tags/programming/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tags/programming/ + + + + + btor2 + https://vhdl.github.io/news/tags/btor2/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/tags/btor2/ + + + + + edif + https://vhdl.github.io/news/tags/edif/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/tags/edif/ + + + + + firrtl + https://vhdl.github.io/news/tags/firrtl/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/tags/firrtl/ + + + + + smt2 + https://vhdl.github.io/news/tags/smt2/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/tags/smt2/ + + + + + co-simulation + https://vhdl.github.io/news/tags/co-simulation/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/tags/co-simulation/ + + + + + python + https://vhdl.github.io/news/tags/python/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/tags/python/ + + + + + testing + https://vhdl.github.io/news/tags/testing/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/tags/testing/ + + + + + altera + https://vhdl.github.io/news/tags/altera/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/altera/ + + + + + exercises + https://vhdl.github.io/news/tags/exercises/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/exercises/ + + + + + learning + https://vhdl.github.io/news/tags/learning/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/learning/ + + + + + modelsim + https://vhdl.github.io/news/tags/modelsim/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/modelsim/ + + + + + teaching + https://vhdl.github.io/news/tags/teaching/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/teaching/ + + + + + videos + https://vhdl.github.io/news/tags/videos/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/videos/ + + + + + youtube + https://vhdl.github.io/news/tags/youtube/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/tags/youtube/ + + + + + ieee + https://vhdl.github.io/news/tags/ieee/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/tags/ieee/ + + + + + vhdl-2019 + https://vhdl.github.io/news/tags/vhdl-2019/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/tags/vhdl-2019/ + + + + + vhdlwhiz + https://vhdl.github.io/news/tags/vhdlwhiz/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/tags/vhdlwhiz/ + + + + + eda-playground + https://vhdl.github.io/news/tags/eda-playground/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/tags/eda-playground/ + + + + + riviera + https://vhdl.github.io/news/tags/riviera/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/tags/riviera/ + + + + + formal-verification + https://vhdl.github.io/news/tags/formal-verification/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/tags/formal-verification/ + + + + + functional-coverage + https://vhdl.github.io/news/tags/functional-coverage/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/tags/functional-coverage/ + + + + + mentor + https://vhdl.github.io/news/tags/mentor/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/tags/mentor/ + + + + + \ No newline at end of file diff --git a/tags/interchange/index.html b/tags/interchange/index.html new file mode 100644 index 00000000..4e35ed87 --- /dev/null +++ b/tags/interchange/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + interchange + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
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    + + + + diff --git a/tags/interchange/index.xml b/tags/interchange/index.xml new file mode 100644 index 00000000..4bbf8424 --- /dev/null +++ b/tags/interchange/index.xml @@ -0,0 +1,24 @@ + + + + interchange on VHDL News + https://vhdl.github.io/news/tags/interchange/ + Recent content in interchange on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + \ No newline at end of file diff --git a/tags/iverilog/index.html b/tags/iverilog/index.html new file mode 100644 index 00000000..77f9d163 --- /dev/null +++ b/tags/iverilog/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + iverilog + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    +
    + + + + diff --git a/tags/iverilog/index.xml b/tags/iverilog/index.xml new file mode 100644 index 00000000..1f66d1a0 --- /dev/null +++ b/tags/iverilog/index.xml @@ -0,0 +1,32 @@ + + + + iverilog on VHDL News + https://vhdl.github.io/news/tags/iverilog/ + Recent content in iverilog on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/kicad/index.html b/tags/kicad/index.html new file mode 100644 index 00000000..0080da7f --- /dev/null +++ b/tags/kicad/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + KiCad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/kicad/index.xml b/tags/kicad/index.xml new file mode 100644 index 00000000..81b98719 --- /dev/null +++ b/tags/kicad/index.xml @@ -0,0 +1,23 @@ + + + + KiCad on VHDL News + https://vhdl.github.io/news/tags/kicad/ + Recent content in KiCad on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/latex/index.html b/tags/latex/index.html new file mode 100644 index 00000000..be4d4f8c --- /dev/null +++ b/tags/latex/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + LaTeX + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
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    + + + + diff --git a/tags/latex/index.xml b/tags/latex/index.xml new file mode 100644 index 00000000..609cdc9f --- /dev/null +++ b/tags/latex/index.xml @@ -0,0 +1,24 @@ + + + + LaTeX on VHDL News + https://vhdl.github.io/news/tags/latex/ + Recent content in LaTeX on VHDL News + Hugo -- gohugo.io + Fri, 13 Nov 2020 14:39:38 +0000 + + + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + \ No newline at end of file diff --git a/tags/lattice/index.html b/tags/lattice/index.html new file mode 100644 index 00000000..b2ebeaef --- /dev/null +++ b/tags/lattice/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + lattice + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + diff --git a/tags/lattice/index.xml b/tags/lattice/index.xml new file mode 100644 index 00000000..3a146c2b --- /dev/null +++ b/tags/lattice/index.xml @@ -0,0 +1,23 @@ + + + + lattice on VHDL News + https://vhdl.github.io/news/tags/lattice/ + Recent content in lattice on VHDL News + Hugo -- gohugo.io + Fri, 09 Oct 2020 14:54:20 +0000 + + + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + \ No newline at end of file diff --git a/tags/learning/index.html b/tags/learning/index.html new file mode 100644 index 00000000..b8133bb3 --- /dev/null +++ b/tags/learning/index.html @@ -0,0 +1,226 @@ + + + + + + + + + + + + VHDL News + + | + + learning + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + + + +
    + +
    + + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
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    + + + + diff --git a/tags/learning/index.xml b/tags/learning/index.xml new file mode 100644 index 00000000..4fc0afaa --- /dev/null +++ b/tags/learning/index.xml @@ -0,0 +1,32 @@ + + + + learning on VHDL News + https://vhdl.github.io/news/tags/learning/ + Recent content in learning on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + Learning FPGA programming, key points for a software developer + https://vhdl.github.io/news/articles/10/ + Tue, 01 Sep 2020 16:45:34 +0000 + + https://vhdl.github.io/news/articles/10/ + dev.to/targeted Learning FPGA programming, key points for a software developer (part 1, the time) Learning FPGA programming, key points for a software developer (part 2, registered logic) Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior) + + + + \ No newline at end of file diff --git a/tags/lpf/index.html b/tags/lpf/index.html new file mode 100644 index 00000000..15c6d8aa --- /dev/null +++ b/tags/lpf/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + lpf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
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    + + + + diff --git a/tags/lpf/index.xml b/tags/lpf/index.xml new file mode 100644 index 00000000..8901bc42 --- /dev/null +++ b/tags/lpf/index.xml @@ -0,0 +1,23 @@ + + + + lpf on VHDL News + https://vhdl.github.io/news/tags/lpf/ + Recent content in lpf on VHDL News + Hugo -- gohugo.io + Thu, 22 Oct 2020 21:52:32 +0000 + + + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + \ No newline at end of file diff --git a/tags/lrm/index.html b/tags/lrm/index.html new file mode 100644 index 00000000..f8cf3314 --- /dev/null +++ b/tags/lrm/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + LRM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + VHDL needs you! + + @umarcor +
    +
    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/lrm/index.xml b/tags/lrm/index.xml new file mode 100644 index 00000000..f6829764 --- /dev/null +++ b/tags/lrm/index.xml @@ -0,0 +1,24 @@ + + + + LRM on VHDL News + https://vhdl.github.io/news/tags/lrm/ + Recent content in LRM on VHDL News + Hugo -- gohugo.io + Fri, 13 Nov 2020 14:39:38 +0000 + + + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + \ No newline at end of file diff --git a/tags/mentor/index.html b/tags/mentor/index.html new file mode 100644 index 00000000..d5032791 --- /dev/null +++ b/tags/mentor/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + mentor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
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    + + + + diff --git a/tags/mentor/index.xml b/tags/mentor/index.xml new file mode 100644 index 00000000..834adf88 --- /dev/null +++ b/tags/mentor/index.xml @@ -0,0 +1,23 @@ + + + + mentor on VHDL News + https://vhdl.github.io/news/tags/mentor/ + Recent content in mentor on VHDL News + Hugo -- gohugo.io + Tue, 18 Aug 2020 15:03:07 +0000 + + + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + \ No newline at end of file diff --git a/tags/methodology/index.html b/tags/methodology/index.html new file mode 100644 index 00000000..73e60141 --- /dev/null +++ b/tags/methodology/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + methodology + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + + + + diff --git a/tags/methodology/index.xml b/tags/methodology/index.xml new file mode 100644 index 00000000..eead6e6f --- /dev/null +++ b/tags/methodology/index.xml @@ -0,0 +1,24 @@ + + + + methodology on VHDL News + https://vhdl.github.io/news/tags/methodology/ + Recent content in methodology on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + \ No newline at end of file diff --git a/tags/microwatt/index.html b/tags/microwatt/index.html new file mode 100644 index 00000000..001aebc2 --- /dev/null +++ b/tags/microwatt/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + microwatt + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + + + diff --git a/tags/microwatt/index.xml b/tags/microwatt/index.xml new file mode 100644 index 00000000..c123a35e --- /dev/null +++ b/tags/microwatt/index.xml @@ -0,0 +1,38 @@ + + + + microwatt on VHDL News + https://vhdl.github.io/news/tags/microwatt/ + Recent content in microwatt on VHDL News + Hugo -- gohugo.io + Tue, 27 Oct 2020 06:45:43 +0000 + + + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + \ No newline at end of file diff --git a/tags/modelsim/index.html b/tags/modelsim/index.html new file mode 100644 index 00000000..6bc858d1 --- /dev/null +++ b/tags/modelsim/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + modelsim + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + + + diff --git a/tags/modelsim/index.xml b/tags/modelsim/index.xml new file mode 100644 index 00000000..222fd7b3 --- /dev/null +++ b/tags/modelsim/index.xml @@ -0,0 +1,23 @@ + + + + modelsim on VHDL News + https://vhdl.github.io/news/tags/modelsim/ + Recent content in modelsim on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + \ No newline at end of file diff --git a/tags/msys2/index.html b/tags/msys2/index.html new file mode 100644 index 00000000..7a6df94a --- /dev/null +++ b/tags/msys2/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + MSYS2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/msys2/index.xml b/tags/msys2/index.xml new file mode 100644 index 00000000..1d962b2d --- /dev/null +++ b/tags/msys2/index.xml @@ -0,0 +1,23 @@ + + + + MSYS2 on VHDL News + https://vhdl.github.io/news/tags/msys2/ + Recent content in MSYS2 on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/neoled/index.html b/tags/neoled/index.html new file mode 100644 index 00000000..7d685157 --- /dev/null +++ b/tags/neoled/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + NEOLED + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/neoled/index.xml b/tags/neoled/index.xml new file mode 100644 index 00000000..bd6d0830 --- /dev/null +++ b/tags/neoled/index.xml @@ -0,0 +1,24 @@ + + + + NEOLED on VHDL News + https://vhdl.github.io/news/tags/neoled/ + Recent content in NEOLED on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/neorv32/index.html b/tags/neorv32/index.html new file mode 100644 index 00000000..4468e5d8 --- /dev/null +++ b/tags/neorv32/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + neorv32 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/neorv32/index.xml b/tags/neorv32/index.xml new file mode 100644 index 00000000..d999ea75 --- /dev/null +++ b/tags/neorv32/index.xml @@ -0,0 +1,24 @@ + + + + neorv32 on VHDL News + https://vhdl.github.io/news/tags/neorv32/ + Recent content in neorv32 on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/nextpnr/index.html b/tags/nextpnr/index.html new file mode 100644 index 00000000..bdb85214 --- /dev/null +++ b/tags/nextpnr/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + nextpnr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + diff --git a/tags/nextpnr/index.xml b/tags/nextpnr/index.xml new file mode 100644 index 00000000..ce955814 --- /dev/null +++ b/tags/nextpnr/index.xml @@ -0,0 +1,35 @@ + + + + nextpnr on VHDL News + https://vhdl.github.io/news/tags/nextpnr/ + Recent content in nextpnr on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/ngspice/index.html b/tags/ngspice/index.html new file mode 100644 index 00000000..35a5ba57 --- /dev/null +++ b/tags/ngspice/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + ngspice + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/ngspice/index.xml b/tags/ngspice/index.xml new file mode 100644 index 00000000..3a2643ca --- /dev/null +++ b/tags/ngspice/index.xml @@ -0,0 +1,23 @@ + + + + ngspice on VHDL News + https://vhdl.github.io/news/tags/ngspice/ + Recent content in ngspice on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/ocd/index.html b/tags/ocd/index.html new file mode 100644 index 00000000..ac38b629 --- /dev/null +++ b/tags/ocd/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + OCD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/ocd/index.xml b/tags/ocd/index.xml new file mode 100644 index 00000000..d3643770 --- /dev/null +++ b/tags/ocd/index.xml @@ -0,0 +1,24 @@ + + + + OCD on VHDL News + https://vhdl.github.io/news/tags/ocd/ + Recent content in OCD on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/openfpgaloader/index.html b/tags/openfpgaloader/index.html new file mode 100644 index 00000000..6eb42490 --- /dev/null +++ b/tags/openfpgaloader/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + openFPGALoader + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + + + diff --git a/tags/openisa/index.xml b/tags/openisa/index.xml new file mode 100644 index 00000000..004f626c --- /dev/null +++ b/tags/openisa/index.xml @@ -0,0 +1,38 @@ + + + + openisa on VHDL News + https://vhdl.github.io/news/tags/openisa/ + Recent content in openisa on VHDL News + Hugo -- gohugo.io + Tue, 27 Oct 2020 06:45:43 +0000 + + + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + \ No newline at end of file diff --git a/tags/openocd/index.html b/tags/openocd/index.html new file mode 100644 index 00000000..c82feb0d --- /dev/null +++ b/tags/openocd/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + OpenOCD + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + + + + diff --git a/tags/osvb/index.xml b/tags/osvb/index.xml new file mode 100644 index 00000000..4f28ba69 --- /dev/null +++ b/tags/osvb/index.xml @@ -0,0 +1,23 @@ + + + + osvb on VHDL News + https://vhdl.github.io/news/tags/osvb/ + Recent content in osvb on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + \ No newline at end of file diff --git a/tags/osvvm/index.html b/tags/osvvm/index.html new file mode 100644 index 00000000..353b5193 --- /dev/null +++ b/tags/osvvm/index.html @@ -0,0 +1,511 @@ + + + + + + + + + + + + VHDL News + + | + + osvvm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
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    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
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    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    +
    + + + + diff --git a/tags/osvvm/index.xml b/tags/osvvm/index.xml new file mode 100644 index 00000000..b67b2f35 --- /dev/null +++ b/tags/osvvm/index.xml @@ -0,0 +1,105 @@ + + + + osvvm on VHDL News + https://vhdl.github.io/news/tags/osvvm/ + Recent content in osvvm on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/package/index.html b/tags/package/index.html new file mode 100644 index 00000000..45398e15 --- /dev/null +++ b/tags/package/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + package + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/package/index.xml b/tags/package/index.xml new file mode 100644 index 00000000..b7f2bb1d --- /dev/null +++ b/tags/package/index.xml @@ -0,0 +1,23 @@ + + + + package on VHDL News + https://vhdl.github.io/news/tags/package/ + Recent content in package on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/pcf/index.html b/tags/pcf/index.html new file mode 100644 index 00000000..0cf2cfa8 --- /dev/null +++ b/tags/pcf/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + pcf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
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    + + + + diff --git a/tags/pcf/index.xml b/tags/pcf/index.xml new file mode 100644 index 00000000..8389ab6f --- /dev/null +++ b/tags/pcf/index.xml @@ -0,0 +1,23 @@ + + + + pcf on VHDL News + https://vhdl.github.io/news/tags/pcf/ + Recent content in pcf on VHDL News + Hugo -- gohugo.io + Thu, 22 Oct 2020 21:52:32 +0000 + + + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + \ No newline at end of file diff --git a/tags/podman/index.html b/tags/podman/index.html new file mode 100644 index 00000000..60b935f7 --- /dev/null +++ b/tags/podman/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + podman + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + diff --git a/tags/podman/index.xml b/tags/podman/index.xml new file mode 100644 index 00000000..d82f993f --- /dev/null +++ b/tags/podman/index.xml @@ -0,0 +1,26 @@ + + + + podman on VHDL News + https://vhdl.github.io/news/tags/podman/ + Recent content in podman on VHDL News + Hugo -- gohugo.io + Mon, 23 Nov 2020 09:09:05 +0000 + + + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/power/index.html b/tags/power/index.html new file mode 100644 index 00000000..84035f0c --- /dev/null +++ b/tags/power/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + power + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
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    + + + + diff --git a/tags/power/index.xml b/tags/power/index.xml new file mode 100644 index 00000000..bfa8e442 --- /dev/null +++ b/tags/power/index.xml @@ -0,0 +1,38 @@ + + + + power on VHDL News + https://vhdl.github.io/news/tags/power/ + Recent content in power on VHDL News + Hugo -- gohugo.io + Tue, 27 Oct 2020 06:45:43 +0000 + + + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + \ No newline at end of file diff --git a/tags/prjtrellis/index.html b/tags/prjtrellis/index.html new file mode 100644 index 00000000..75b356a8 --- /dev/null +++ b/tags/prjtrellis/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + prjtrellis + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + + diff --git a/tags/prjtrellis/index.xml b/tags/prjtrellis/index.xml new file mode 100644 index 00000000..6aa27f5d --- /dev/null +++ b/tags/prjtrellis/index.xml @@ -0,0 +1,35 @@ + + + + prjtrellis on VHDL News + https://vhdl.github.io/news/tags/prjtrellis/ + Recent content in prjtrellis on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tags/programming/index.html b/tags/programming/index.html new file mode 100644 index 00000000..3082fd53 --- /dev/null +++ b/tags/programming/index.html @@ -0,0 +1,226 @@ + + + + + + + + + + + + VHDL News + + | + + programming + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
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    + + #10 + 1 + 0 + + · + 2020/09/01 + + + · + tags: learning, fpga, programming + +
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    + + + + diff --git a/tags/programming/index.xml b/tags/programming/index.xml new file mode 100644 index 00000000..89bb3466 --- /dev/null +++ b/tags/programming/index.xml @@ -0,0 +1,32 @@ + + + + programming on VHDL News + https://vhdl.github.io/news/tags/programming/ + Recent content in programming on VHDL News + Hugo -- gohugo.io + Fri, 09 Oct 2020 08:48:50 +0000 + + + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + Learning FPGA programming, key points for a software developer + https://vhdl.github.io/news/articles/10/ + Tue, 01 Sep 2020 16:45:34 +0000 + + https://vhdl.github.io/news/articles/10/ + dev.to/targeted Learning FPGA programming, key points for a software developer (part 1, the time) Learning FPGA programming, key points for a software developer (part 2, registered logic) Learning FPGA programming, key points for a software developer (part 3, code patterns and inferred behavior) + + + + \ No newline at end of file diff --git a/tags/psl/index.html b/tags/psl/index.html new file mode 100644 index 00000000..6e893320 --- /dev/null +++ b/tags/psl/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + psl + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
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    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
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    + + + + diff --git a/tags/psl/index.xml b/tags/psl/index.xml new file mode 100644 index 00000000..f7807fe2 --- /dev/null +++ b/tags/psl/index.xml @@ -0,0 +1,35 @@ + + + + psl on VHDL News + https://vhdl.github.io/news/tags/psl/ + Recent content in psl on VHDL News + Hugo -- gohugo.io + Mon, 30 Nov 2020 19:50:15 +0000 + + + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/pwm/index.html b/tags/pwm/index.html new file mode 100644 index 00000000..5e578d72 --- /dev/null +++ b/tags/pwm/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + PWM + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/pwm/index.xml b/tags/pwm/index.xml new file mode 100644 index 00000000..493fc067 --- /dev/null +++ b/tags/pwm/index.xml @@ -0,0 +1,24 @@ + + + + PWM on VHDL News + https://vhdl.github.io/news/tags/pwm/ + Recent content in PWM on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/python/index.html b/tags/python/index.html new file mode 100644 index 00000000..21785c91 --- /dev/null +++ b/tags/python/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + python + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    +
    + + + + diff --git a/tags/python/index.xml b/tags/python/index.xml new file mode 100644 index 00000000..e483553c --- /dev/null +++ b/tags/python/index.xml @@ -0,0 +1,23 @@ + + + + python on VHDL News + https://vhdl.github.io/news/tags/python/ + Recent content in python on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 06:09:01 +0000 + + + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + \ No newline at end of file diff --git a/tags/rapidwright/index.html b/tags/rapidwright/index.html new file mode 100644 index 00000000..0006dcd8 --- /dev/null +++ b/tags/rapidwright/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + rapidwright + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
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    + + + + +
    +
    + + + + diff --git a/tags/rapidwright/index.xml b/tags/rapidwright/index.xml new file mode 100644 index 00000000..06b2a246 --- /dev/null +++ b/tags/rapidwright/index.xml @@ -0,0 +1,24 @@ + + + + rapidwright on VHDL News + https://vhdl.github.io/news/tags/rapidwright/ + Recent content in rapidwright on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + \ No newline at end of file diff --git a/tags/renode/index.html b/tags/renode/index.html new file mode 100644 index 00000000..55fba0e1 --- /dev/null +++ b/tags/renode/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + renode + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/renode/index.xml b/tags/renode/index.xml new file mode 100644 index 00000000..afae61ec --- /dev/null +++ b/tags/renode/index.xml @@ -0,0 +1,23 @@ + + + + renode on VHDL News + https://vhdl.github.io/news/tags/renode/ + Recent content in renode on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + \ No newline at end of file diff --git a/tags/riscv/index.html b/tags/riscv/index.html new file mode 100644 index 00000000..3750de32 --- /dev/null +++ b/tags/riscv/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + riscv + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/riscv/index.xml b/tags/riscv/index.xml new file mode 100644 index 00000000..cc83d56c --- /dev/null +++ b/tags/riscv/index.xml @@ -0,0 +1,24 @@ + + + + riscv on VHDL News + https://vhdl.github.io/news/tags/riscv/ + Recent content in riscv on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/riviera/index.html b/tags/riviera/index.html new file mode 100644 index 00000000..f39daf3d --- /dev/null +++ b/tags/riviera/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + riviera + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
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    +
    + + + + diff --git a/tags/riviera/index.xml b/tags/riviera/index.xml new file mode 100644 index 00000000..77b1b4f9 --- /dev/null +++ b/tags/riviera/index.xml @@ -0,0 +1,24 @@ + + + + riviera on VHDL News + https://vhdl.github.io/news/tags/riviera/ + Recent content in riviera on VHDL News + Hugo -- gohugo.io + Sat, 22 Aug 2020 20:37:41 +0000 + + + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + \ No newline at end of file diff --git a/tags/schema/index.html b/tags/schema/index.html new file mode 100644 index 00000000..ec0c7493 --- /dev/null +++ b/tags/schema/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + schema + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/schema/index.xml b/tags/schema/index.xml new file mode 100644 index 00000000..eed15b89 --- /dev/null +++ b/tags/schema/index.xml @@ -0,0 +1,24 @@ + + + + schema on VHDL News + https://vhdl.github.io/news/tags/schema/ + Recent content in schema on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + \ No newline at end of file diff --git a/tags/sdc/index.html b/tags/sdc/index.html new file mode 100644 index 00000000..5e0b113a --- /dev/null +++ b/tags/sdc/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + sdc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/sdc/index.xml b/tags/sdc/index.xml new file mode 100644 index 00000000..146cd9b8 --- /dev/null +++ b/tags/sdc/index.xml @@ -0,0 +1,23 @@ + + + + sdc on VHDL News + https://vhdl.github.io/news/tags/sdc/ + Recent content in sdc on VHDL News + Hugo -- gohugo.io + Thu, 22 Oct 2020 21:52:32 +0000 + + + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + \ No newline at end of file diff --git a/tags/simulation/index.html b/tags/simulation/index.html new file mode 100644 index 00000000..8425dc58 --- /dev/null +++ b/tags/simulation/index.html @@ -0,0 +1,418 @@ + + + + + + + + + + + + VHDL News + + | + + simulation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
    + +
    + + + + +
    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
    + +
    + + + + +
    +
    + + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
    +
    + + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
    + +
    + + + + +
    + +
    + + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
    + +
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    +
    + + + + diff --git a/tags/simulation/index.xml b/tags/simulation/index.xml new file mode 100644 index 00000000..539ac361 --- /dev/null +++ b/tags/simulation/index.xml @@ -0,0 +1,86 @@ + + + + simulation on VHDL News + https://vhdl.github.io/news/tags/simulation/ + Recent content in simulation on VHDL News + Hugo -- gohugo.io + Thu, 21 Oct 2021 15:39:55 +0000 + + + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + Create your own VVC for UVVM + https://vhdl.github.io/news/articles/7/ + Wed, 19 Aug 2020 12:13:59 +0000 + + https://vhdl.github.io/news/articles/7/ + + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + \ No newline at end of file diff --git a/tags/smt2/index.html b/tags/smt2/index.html new file mode 100644 index 00000000..bd72b509 --- /dev/null +++ b/tags/smt2/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + smt2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    +
    + + + + diff --git a/tags/smt2/index.xml b/tags/smt2/index.xml new file mode 100644 index 00000000..94c0902a --- /dev/null +++ b/tags/smt2/index.xml @@ -0,0 +1,25 @@ + + + + smt2 on VHDL News + https://vhdl.github.io/news/tags/smt2/ + Recent content in smt2 on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 15:23:01 +0000 + + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/soc/index.html b/tags/soc/index.html new file mode 100644 index 00000000..1698db6a --- /dev/null +++ b/tags/soc/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + soc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/soc/index.xml b/tags/soc/index.xml new file mode 100644 index 00000000..80955a27 --- /dev/null +++ b/tags/soc/index.xml @@ -0,0 +1,24 @@ + + + + soc on VHDL News + https://vhdl.github.io/news/tags/soc/ + Recent content in soc on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/spi/index.html b/tags/spi/index.html new file mode 100644 index 00000000..384ba848 --- /dev/null +++ b/tags/spi/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + SPI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + +
    +
    + + + + diff --git a/tags/spi/index.xml b/tags/spi/index.xml new file mode 100644 index 00000000..6806a175 --- /dev/null +++ b/tags/spi/index.xml @@ -0,0 +1,24 @@ + + + + SPI on VHDL News + https://vhdl.github.io/news/tags/spi/ + Recent content in SPI on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/stream/index.html b/tags/stream/index.html new file mode 100644 index 00000000..b5c2b532 --- /dev/null +++ b/tags/stream/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + stream + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/stream/index.xml b/tags/stream/index.xml new file mode 100644 index 00000000..bc3e1c6c --- /dev/null +++ b/tags/stream/index.xml @@ -0,0 +1,24 @@ + + + + stream on VHDL News + https://vhdl.github.io/news/tags/stream/ + Recent content in stream on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/study/index.html b/tags/study/index.html new file mode 100644 index 00000000..f4d00823 --- /dev/null +++ b/tags/study/index.html @@ -0,0 +1,403 @@ + + + + + + + + + + + + VHDL News + + | + + study + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + + + +
    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/study/index.xml b/tags/study/index.xml new file mode 100644 index 00000000..853d84ac --- /dev/null +++ b/tags/study/index.xml @@ -0,0 +1,77 @@ + + + + study on VHDL News + https://vhdl.github.io/news/tags/study/ + Recent content in study on VHDL News + Hugo -- gohugo.io + Wed, 27 Oct 2021 22:36:39 +0000 + + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/svunit/index.html b/tags/svunit/index.html new file mode 100644 index 00000000..cb3741b4 --- /dev/null +++ b/tags/svunit/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + svunit + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
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    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    +
    + + + + diff --git a/tags/svunit/index.xml b/tags/svunit/index.xml new file mode 100644 index 00000000..75403723 --- /dev/null +++ b/tags/svunit/index.xml @@ -0,0 +1,23 @@ + + + + svunit on VHDL News + https://vhdl.github.io/news/tags/svunit/ + Recent content in svunit on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + \ No newline at end of file diff --git a/tags/symbiyosys/index.html b/tags/symbiyosys/index.html new file mode 100644 index 00000000..0bf67f3b --- /dev/null +++ b/tags/symbiyosys/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + symbiyosys + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + +
    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
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    + + + + +
    +
    + + + + diff --git a/tags/symbiyosys/index.xml b/tags/symbiyosys/index.xml new file mode 100644 index 00000000..72c40d37 --- /dev/null +++ b/tags/symbiyosys/index.xml @@ -0,0 +1,36 @@ + + + + symbiyosys on VHDL News + https://vhdl.github.io/news/tags/symbiyosys/ + Recent content in symbiyosys on VHDL News + Hugo -- gohugo.io + Mon, 23 Nov 2020 09:09:05 +0000 + + + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/synthesis/index.html b/tags/synthesis/index.html new file mode 100644 index 00000000..da5a4db4 --- /dev/null +++ b/tags/synthesis/index.html @@ -0,0 +1,460 @@ + + + + + + + + + + + + VHDL News + + | + + synthesis + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    + +
    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
    + +
    + + + + +
    + +
    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + + +
    + +
    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + +
    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
    + +
    + + + + +
    +
    + + + How to convert vhdl to other formats + + @tmeissner +
    +
    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    +
    + + + + diff --git a/tags/synthesis/index.xml b/tags/synthesis/index.xml new file mode 100644 index 00000000..1751c233 --- /dev/null +++ b/tags/synthesis/index.xml @@ -0,0 +1,98 @@ + + + + synthesis on VHDL News + https://vhdl.github.io/news/tags/synthesis/ + Recent content in synthesis on VHDL News + Hugo -- gohugo.io + Thu, 21 Oct 2021 15:39:55 +0000 + + + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/cores/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/cores/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/teaching/index.html b/tags/teaching/index.html new file mode 100644 index 00000000..ac024c4f --- /dev/null +++ b/tags/teaching/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + teaching + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + +
    +
    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + + + diff --git a/tags/teaching/index.xml b/tags/teaching/index.xml new file mode 100644 index 00000000..224fee74 --- /dev/null +++ b/tags/teaching/index.xml @@ -0,0 +1,23 @@ + + + + teaching on VHDL News + https://vhdl.github.io/news/tags/teaching/ + Recent content in teaching on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + \ No newline at end of file diff --git a/tags/testing/index.html b/tags/testing/index.html new file mode 100644 index 00000000..cb26b754 --- /dev/null +++ b/tags/testing/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + testing + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    + + + + diff --git a/tags/testing/index.xml b/tags/testing/index.xml new file mode 100644 index 00000000..f33065c9 --- /dev/null +++ b/tags/testing/index.xml @@ -0,0 +1,23 @@ + + + + testing on VHDL News + https://vhdl.github.io/news/tags/testing/ + Recent content in testing on VHDL News + Hugo -- gohugo.io + Mon, 28 Sep 2020 06:09:01 +0000 + + + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + \ No newline at end of file diff --git a/tags/trng/index.html b/tags/trng/index.html new file mode 100644 index 00000000..2eef2b7c --- /dev/null +++ b/tags/trng/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + TRNG + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/trng/index.xml b/tags/trng/index.xml new file mode 100644 index 00000000..1586bc8d --- /dev/null +++ b/tags/trng/index.xml @@ -0,0 +1,24 @@ + + + + TRNG on VHDL News + https://vhdl.github.io/news/tags/trng/ + Recent content in TRNG on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/twi/index.html b/tags/twi/index.html new file mode 100644 index 00000000..bff0f39b --- /dev/null +++ b/tags/twi/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + TWI + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/twi/index.xml b/tags/twi/index.xml new file mode 100644 index 00000000..6c8e331b --- /dev/null +++ b/tags/twi/index.xml @@ -0,0 +1,24 @@ + + + + TWI on VHDL News + https://vhdl.github.io/news/tags/twi/ + Recent content in TWI on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/ucf/index.html b/tags/ucf/index.html new file mode 100644 index 00000000..c5daffbc --- /dev/null +++ b/tags/ucf/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + ucf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
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    + + + + diff --git a/tags/ucf/index.xml b/tags/ucf/index.xml new file mode 100644 index 00000000..12fec8b0 --- /dev/null +++ b/tags/ucf/index.xml @@ -0,0 +1,23 @@ + + + + ucf on VHDL News + https://vhdl.github.io/news/tags/ucf/ + Recent content in ucf on VHDL News + Hugo -- gohugo.io + Thu, 22 Oct 2020 21:52:32 +0000 + + + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + \ No newline at end of file diff --git a/tags/unification/index.html b/tags/unification/index.html new file mode 100644 index 00000000..187afdc3 --- /dev/null +++ b/tags/unification/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + unification + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + + + + diff --git a/tags/unification/index.xml b/tags/unification/index.xml new file mode 100644 index 00000000..50b7a990 --- /dev/null +++ b/tags/unification/index.xml @@ -0,0 +1,24 @@ + + + + unification on VHDL News + https://vhdl.github.io/news/tags/unification/ + Recent content in unification on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + \ No newline at end of file diff --git a/tags/uvm/index.html b/tags/uvm/index.html new file mode 100644 index 00000000..2a3426c4 --- /dev/null +++ b/tags/uvm/index.html @@ -0,0 +1,403 @@ + + + + + + + + + + + + VHDL News + + | + + uvm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    +
    + + + + diff --git a/tags/uvm/index.xml b/tags/uvm/index.xml new file mode 100644 index 00000000..0d9bef94 --- /dev/null +++ b/tags/uvm/index.xml @@ -0,0 +1,77 @@ + + + + uvm on VHDL News + https://vhdl.github.io/news/tags/uvm/ + Recent content in uvm on VHDL News + Hugo -- gohugo.io + Wed, 27 Oct 2021 22:36:39 +0000 + + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/uvvm/index.html b/tags/uvvm/index.html new file mode 100644 index 00000000..73f092c2 --- /dev/null +++ b/tags/uvvm/index.html @@ -0,0 +1,511 @@ + + + + + + + + + + + + VHDL News + + | + + uvvm + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    +
    + + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
    +
    + + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
    + +
    + + + + +
    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    +
    + + + + diff --git a/tags/uvvm/index.xml b/tags/uvvm/index.xml new file mode 100644 index 00000000..17eb8c53 --- /dev/null +++ b/tags/uvvm/index.xml @@ -0,0 +1,105 @@ + + + + uvvm on VHDL News + https://vhdl.github.io/news/tags/uvvm/ + Recent content in uvvm on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + Create your own VVC for UVVM + https://vhdl.github.io/news/articles/7/ + Wed, 19 Aug 2020 12:13:59 +0000 + + https://vhdl.github.io/news/articles/7/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/vasg/index.html b/tags/vasg/index.html new file mode 100644 index 00000000..39d2c080 --- /dev/null +++ b/tags/vasg/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + VASG + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + VHDL needs you! + + @umarcor +
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    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
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    + + + + diff --git a/tags/vasg/index.xml b/tags/vasg/index.xml new file mode 100644 index 00000000..8173fc03 --- /dev/null +++ b/tags/vasg/index.xml @@ -0,0 +1,24 @@ + + + + VASG on VHDL News + https://vhdl.github.io/news/tags/vasg/ + Recent content in VASG on VHDL News + Hugo -- gohugo.io + Fri, 13 Nov 2020 14:39:38 +0000 + + + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + \ No newline at end of file diff --git a/tags/verification/index.html b/tags/verification/index.html new file mode 100644 index 00000000..a1a92982 --- /dev/null +++ b/tags/verification/index.html @@ -0,0 +1,694 @@ + + + + + + + + + + + + VHDL News + + | + + verification + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + +
    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
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    + +
    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    + +
    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + +
    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    +
    + + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
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    + + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
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    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
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    + + + Create your own VVC for UVVM + + @Ahmad-Zaklouta +
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    + + #7 + 1 + 6 + + · + 2020/08/19 + + + · + tags: verification, simulation, uvvm + +
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    + +
    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
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    + + #4 + 4 + 0 + + · + 2020/08/18 + + + · + tags: verification, simulation, osvvm, mentor + +
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    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + + + diff --git a/tags/verification/index.xml b/tags/verification/index.xml new file mode 100644 index 00000000..942e64b5 --- /dev/null +++ b/tags/verification/index.xml @@ -0,0 +1,154 @@ + + + + verification on VHDL News + https://vhdl.github.io/news/tags/verification/ + Recent content in verification on VHDL News + Hugo -- gohugo.io + Sat, 30 Oct 2021 02:23:50 +0000 + + + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What’s new in VHDL-2019 - VHDLwhiz + https://vhdl.github.io/news/articles/9/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/articles/9/ + + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + Create your own VVC for UVVM + https://vhdl.github.io/news/articles/7/ + Wed, 19 Aug 2020 12:13:59 +0000 + + https://vhdl.github.io/news/articles/7/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + Addressing VHDL Verification Challenges with OSVVM + https://vhdl.github.io/news/articles/4/ + Tue, 18 Aug 2020 15:03:07 +0000 + + https://vhdl.github.io/news/articles/4/ + An introduction to the capabilities of OSVVM utility and verification component libraries. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/verilator/index.html b/tags/verilator/index.html new file mode 100644 index 00000000..9d4fd579 --- /dev/null +++ b/tags/verilator/index.html @@ -0,0 +1,235 @@ + + + + + + + + + + + + VHDL News + + | + + verilator + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/verilator/index.xml b/tags/verilator/index.xml new file mode 100644 index 00000000..360e8420 --- /dev/null +++ b/tags/verilator/index.xml @@ -0,0 +1,32 @@ + + + + verilator on VHDL News + https://vhdl.github.io/news/tags/verilator/ + Recent content in verilator on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/verilog/index.html b/tags/verilog/index.html new file mode 100644 index 00000000..a26c411e --- /dev/null +++ b/tags/verilog/index.html @@ -0,0 +1,226 @@ + + + + + + + + + + + + VHDL News + + | + + verilog + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + + + How to convert vhdl to other formats + + @tmeissner +
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    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    + + + + diff --git a/tags/verilog/index.xml b/tags/verilog/index.xml new file mode 100644 index 00000000..994d907f --- /dev/null +++ b/tags/verilog/index.xml @@ -0,0 +1,35 @@ + + + + verilog on VHDL News + https://vhdl.github.io/news/tags/verilog/ + Recent content in verilog on VHDL News + Hugo -- gohugo.io + Wed, 02 Dec 2020 05:34:29 +0000 + + + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + \ No newline at end of file diff --git a/tags/vhdl-2019/index.html b/tags/vhdl-2019/index.html new file mode 100644 index 00000000..e85a7e8a --- /dev/null +++ b/tags/vhdl-2019/index.html @@ -0,0 +1,217 @@ + + + + + + + + + + + + VHDL News + + | + + vhdl-2019 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
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    + + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
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    + + #8 + 3 + 0 + + · + 2020/08/22 + + + · + tags: vhdl-2019, verification, eda-playground, riviera + +
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    + + + + diff --git a/tags/vhdl-2019/index.xml b/tags/vhdl-2019/index.xml new file mode 100644 index 00000000..5a67277d --- /dev/null +++ b/tags/vhdl-2019/index.xml @@ -0,0 +1,33 @@ + + + + vhdl-2019 on VHDL News + https://vhdl.github.io/news/tags/vhdl-2019/ + Recent content in vhdl-2019 on VHDL News + Hugo -- gohugo.io + Fri, 28 Aug 2020 17:27:03 +0000 + + + + + + What’s new in VHDL-2019 - VHDLwhiz + https://vhdl.github.io/news/articles/9/ + Fri, 28 Aug 2020 17:27:03 +0000 + + https://vhdl.github.io/news/articles/9/ + + + + + First VHDL-2019 examples on EDA playground + https://vhdl.github.io/news/past/8/ + Sat, 22 Aug 2020 20:37:41 +0000 + + https://vhdl.github.io/news/past/8/ + First examples of VHDL-2019 on EDA playground supported by Riviera Pro: + some of the new features of the std.env package private and alias in protected types + + + + \ No newline at end of file diff --git a/tags/vhdl/index.html b/tags/vhdl/index.html new file mode 100644 index 00000000..034f4655 --- /dev/null +++ b/tags/vhdl/index.html @@ -0,0 +1,409 @@ + + + + + + + + + + + + VHDL News + + | + + vhdl + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + #33 + 0 + 0 + + · + 2021/10/30 + + + · + tags: vhdl, verification, methodology, osvvm, uvvm, unification + +
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    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
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    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
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    + + + VHDL needs you! + + @umarcor +
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    + + #22 + 2 + 0 + + · + 2020/11/13 + + + · + tags: vhdl, LRM, VASG, LaTeX, GitLab + +
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    + + #19 + 2 + 1 + + · + 2020/10/09 + + + · + tags: lattice, ice40, vhdl, components, synthesis, ghdl-yosys-plugin + +
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    + + + + diff --git a/tags/vhdl/index.xml b/tags/vhdl/index.xml new file mode 100644 index 00000000..c1f978bf --- /dev/null +++ b/tags/vhdl/index.xml @@ -0,0 +1,86 @@ + + + + vhdl on VHDL News + https://vhdl.github.io/news/tags/vhdl/ + Recent content in vhdl on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + OSVVM & UVVM: Differences and Unification + https://vhdl.github.io/news/articles/33/ + Sat, 30 Oct 2021 02:23:50 +0000 + + https://vhdl.github.io/news/articles/33/ + As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM. +At this point OSVVM and UVVM are largely duplicating what each other is doing. This wastes valuable time and resources that could be better spent with all of us working toward a common goal. Lets be honest, the SystemVerilog community went though these same growing pains when Siemens, Cadence, and Synopsys came together to unify URM (Cadence), AVM (Siemens), OVM (Cadence + Siemens), and VMM (Synopsys) into UVM. + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + VHDL needs you! + https://vhdl.github.io/news/past/22/ + Fri, 13 Nov 2020 14:39:38 +0000 + + https://vhdl.github.io/news/past/22/ + Are you familiar or experienced with LaTeX? In preparation for the next revision, the VHDL Analysis and Standarisation Group (VASG) decided to migrate the sources of the IEEE Std 1076-2019 Language Reference Manual (LRM) from a closed source binary file based tool (Adobe FrameMaker) to an open source text based solution (LaTeX); together with using a forge (gitlab.com/IEEE-P1076) for coordinating and keeping track of the modifications. +Although many people think that the standards community is driven by vendors, that is a mistake noawadays. + + + + What are the chances of having sb_ice40_components_syn.vhd freely distributed for the benefit of the community? + https://vhdl.github.io/news/past/19/ + Fri, 09 Oct 2020 14:54:20 +0000 + + https://vhdl.github.io/news/past/19/ + + + + + \ No newline at end of file diff --git a/tags/vhdlwhiz/index.html b/tags/vhdlwhiz/index.html new file mode 100644 index 00000000..aa412272 --- /dev/null +++ b/tags/vhdlwhiz/index.html @@ -0,0 +1,184 @@ + + + + + + + + + + + + VHDL News + + | + + vhdlwhiz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + What’s new in VHDL-2019 - VHDLwhiz + + @tmeissner +
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    + + #9 + 2 + 0 + + · + 2020/08/28 + + + · + tags: vhdl-2019, ieee, verification, vhdlwhiz + +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + + #16 + 2 + 0 + + · + 2020/09/28 + + + + + umarcor/vunit-cocotb + + + + · + tags: vunit, cocotb, python, testing, verification, co-simulation, simulation, ghdl + +
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    + + #14 + 1 + 0 + + · + 2020/09/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #11 + 1 + 0 + + · + 2020/09/02 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #6 + 1 + 0 + + · + 2020/08/19 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #3 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + #2 + 3 + 0 + + · + 2020/08/18 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit + +
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    + + + + diff --git a/tags/vunit/index.xml b/tags/vunit/index.xml new file mode 100644 index 00000000..c30b631d --- /dev/null +++ b/tags/vunit/index.xml @@ -0,0 +1,95 @@ + + + + vunit on VHDL News + https://vhdl.github.io/news/tags/vunit/ + Recent content in vunit on VHDL News + Hugo -- gohugo.io + Wed, 27 Oct 2021 22:36:39 +0000 + + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + Combining VUnit tests with cocotb components + https://vhdl.github.io/news/show/16/ + Mon, 28 Sep 2020 06:09:01 +0000 + + https://vhdl.github.io/news/show/16/ + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 4) + https://vhdl.github.io/news/past/14/ + Fri, 18 Sep 2020 00:54:44 +0000 + + https://vhdl.github.io/news/past/14/ + The fourth part was published: + In part 3 of our GitHub study we presented the number of users on GitHub doing their VHDL verification with one or more of the analyzed frameworks: VUnit, OSVVM, UVVM, UVM, and cocotb. The results, especially that for the professional users, came as a bit of a surprise which lead to interesting discussions in the comments of the post. Can a study of professional users on GitHub really say something about professional practices behind company walls? + + + + What Can GitHub Tell Us About the HDL Industry? (Part 3) + https://vhdl.github.io/news/past/11/ + Wed, 02 Sep 2020 21:33:51 +0000 + + https://vhdl.github.io/news/past/11/ + The third part was published: + In the second article about our GitHub study we analyzed the popularity of standard verification frameworks in VHDL repositories. This time we extend on those findings by analyzing the Git history of those repositories to find the number of users and examine how that changed over time. + +Looking at users rather than repositories doesn’t have a drastic effect to the overall picture. VUnit is still the most commonly used verification framework on GitHub. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 2) + https://vhdl.github.io/news/past/6/ + Wed, 19 Aug 2020 07:38:22 +0000 + + https://vhdl.github.io/news/past/6/ + The second article/chapter was published: + In the first article about our GitHub study we focused on the presence of tests in HDL repositories. This time we&rsquo;re looking into what standard verification frameworks are being used. The main conclusions are that: + VUnit is the most used verification framework for professional and academic VHDL repositories on GitHub. Most repositories using more than one framework use VUnit and OSVVM. More than half of the repositories using OSVVM also use VUnit. + + + + What Can GitHub Tell Us About the HDL Industry? (Part 1) + https://vhdl.github.io/news/past/3/ + Tue, 18 Aug 2020 14:51:44 +0000 + + https://vhdl.github.io/news/past/3/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + What Can GitHub Tell Us About the HDL Industry? + https://vhdl.github.io/news/articles/2/ + Tue, 18 Aug 2020 14:51:02 +0000 + + https://vhdl.github.io/news/articles/2/ + During the last few years we’ve had many discussions within the VUnit community where we failed to reach a conclusion because we don’t fully know how people at large are working with design and verification. Some questions arise frequently: + How is verification done? What frameworks are used? Are they used together? What are the dominant coding styles? Would people align to those if they knew? Knowing these would help the development of VUnit [1]; where do we put our efforts? + + + + \ No newline at end of file diff --git a/tags/wilson/index.html b/tags/wilson/index.html new file mode 100644 index 00000000..7d0e1fbd --- /dev/null +++ b/tags/wilson/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + wilson + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #32 + 0 + 0 + + · + 2021/10/27 + + + + + LarsAsplund/github-facts + + + + · + tags: cocotb, osvvm, study, uvm, uvvm, verification, vunit, wilson + +
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    + + + + diff --git a/tags/wilson/index.xml b/tags/wilson/index.xml new file mode 100644 index 00000000..aff3d9ae --- /dev/null +++ b/tags/wilson/index.xml @@ -0,0 +1,24 @@ + + + + wilson on VHDL News + https://vhdl.github.io/news/tags/wilson/ + Recent content in wilson on VHDL News + Hugo -- gohugo.io + Wed, 27 Oct 2021 22:36:39 +0000 + + + + + + What Can GitHub Tell Us About the HDL Industry? (Part 5) + https://vhdl.github.io/news/past/32/ + Wed, 27 Oct 2021 22:36:39 +0000 + + https://vhdl.github.io/news/past/32/ + The fifth part was published, titled Wilson Study Comparison: + Part 5 of this series compares our GitHub-based research on the verification frameworks used for VHDL designs with the findings in the Wilson Research Group functional verification study. Our analysis shows that the derived GitHub data confirms the Wilson study results for UVM, OSVVM, and UVVM but it also shows that the Wilson study misses a large part of the overall picture by not including all commonly used frameworks. + + + + \ No newline at end of file diff --git a/tags/windows/index.html b/tags/windows/index.html new file mode 100644 index 00000000..d411068d --- /dev/null +++ b/tags/windows/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + Windows + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/windows/index.xml b/tags/windows/index.xml new file mode 100644 index 00000000..f069db54 --- /dev/null +++ b/tags/windows/index.xml @@ -0,0 +1,23 @@ + + + + Windows on VHDL News + https://vhdl.github.io/news/tags/windows/ + Recent content in Windows on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/wishbone/index.html b/tags/wishbone/index.html new file mode 100644 index 00000000..49d14469 --- /dev/null +++ b/tags/wishbone/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + wishbone + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #36 + 1 + 0 + + · + 2022/02/05 + + + + + stnolting/neorv32 + + + + · + tags: neorv32, riscv, vhdl, cpu, soc, wishbone, stream, custom-function, CFU, PWM, SPI, TRNG, NEOLED, TWI, gdb, OCD + +
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    + + + + diff --git a/tags/wishbone/index.xml b/tags/wishbone/index.xml new file mode 100644 index 00000000..f4adaeea --- /dev/null +++ b/tags/wishbone/index.xml @@ -0,0 +1,24 @@ + + + + wishbone on VHDL News + https://vhdl.github.io/news/tags/wishbone/ + Recent content in wishbone on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:46:32 +0000 + + + + + + NEORV32: 32-bit RISC-V soft-core CPU and microcontroller-like SoC in VHDL + https://vhdl.github.io/news/cores/36/ + Sat, 05 Feb 2022 15:46:32 +0000 + + https://vhdl.github.io/news/cores/36/ + The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom microcontroller that even fits into a Lattice iCE40 UltraPlus 5k low-power FPGA running at 24 MHz. +Special focus is paid on execution safety to provide defined and predictable behavior at any time. Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions are executed. + + + + \ No newline at end of file diff --git a/tags/workshop/index.html b/tags/workshop/index.html new file mode 100644 index 00000000..b9af56b9 --- /dev/null +++ b/tags/workshop/index.html @@ -0,0 +1,226 @@ + + + + + + + + + + + + VHDL News + + | + + workshop + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #31 + 0 + 0 + + · + 2021/10/21 + + + · + tags: vhdl, workshop, synthesis, simulation, fpga, foss, ghdl + +
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    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + + + + diff --git a/tags/workshop/index.xml b/tags/workshop/index.xml new file mode 100644 index 00000000..40adca09 --- /dev/null +++ b/tags/workshop/index.xml @@ -0,0 +1,36 @@ + + + + workshop on VHDL News + https://vhdl.github.io/news/tags/workshop/ + Recent content in workshop on VHDL News + Hugo -- gohugo.io + Thu, 21 Oct 2021 15:39:55 +0000 + + + + + + Joint ICTP, SAIFR and UNESP School on Systems-on-Chip, Embedded Microcontrollers and their Applications in Research and Industry + https://vhdl.github.io/news/articles/31/ + Thu, 21 Oct 2021 15:39:55 +0000 + + https://vhdl.github.io/news/articles/31/ + @rodrigomelo9: + Happy to help again in an Abdus Salam International Centre for Theoretical Physics (ICTP) workshop talking about #VHDL and #FOSS for #FPGA + Links to slides (and coming soon the recording) of the mini crash course about VHDL: + http://indico.ictp.it/event/9644/session/2/contribution/11/material/slides/ http://indico.ictp.it/event/9644/session/3/contribution/14/material/slides/ + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + \ No newline at end of file diff --git a/tags/xdc/index.html b/tags/xdc/index.html new file mode 100644 index 00000000..a0f58bca --- /dev/null +++ b/tags/xdc/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + xdc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
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    + + + + diff --git a/tags/xdc/index.xml b/tags/xdc/index.xml new file mode 100644 index 00000000..a637c135 --- /dev/null +++ b/tags/xdc/index.xml @@ -0,0 +1,23 @@ + + + + xdc on VHDL News + https://vhdl.github.io/news/tags/xdc/ + Recent content in xdc on VHDL News + Hugo -- gohugo.io + Thu, 22 Oct 2020 21:52:32 +0000 + + + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + \ No newline at end of file diff --git a/tags/xilinx/index.html b/tags/xilinx/index.html new file mode 100644 index 00000000..11aa7c4e --- /dev/null +++ b/tags/xilinx/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + xilinx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + #35 + 0 + 0 + + · + 2022/02/05 + + + + + SymbiFlow/fpga-interchange-schema + + + + · + tags: xilinx, CHIPAlliance, fpga, interchange, schema, rapidwright + +
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    + + + + diff --git a/tags/xilinx/index.xml b/tags/xilinx/index.xml new file mode 100644 index 00000000..a568df87 --- /dev/null +++ b/tags/xilinx/index.xml @@ -0,0 +1,24 @@ + + + + xilinx on VHDL News + https://vhdl.github.io/news/tags/xilinx/ + Recent content in xilinx on VHDL News + Hugo -- gohugo.io + Sat, 05 Feb 2022 15:33:11 +0000 + + + + + + CHIPS Alliance Announces Xilinx as its Newest Member + https://vhdl.github.io/news/past/35/ + Sat, 05 Feb 2022 15:33:11 +0000 + + https://vhdl.github.io/news/past/35/ + Xilinx to continue to drive forward open source FPGA innovation +SAN FRANCISCO, Feb. 3, 2022 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Xilinx, Inc. (NASDAQ: XLNX) has joined the CHIPS Alliance organization. Xilinx is a leader in adaptive computing, providing highly-flexible programmable silicon, enabled by a suite of advanced software and tools to drive rapid innovation across a wide span of industries and technologies – from consumer to cars to the cloud. + + + + \ No newline at end of file diff --git a/tags/yices2/index.html b/tags/yices2/index.html new file mode 100644 index 00000000..dc3c16b6 --- /dev/null +++ b/tags/yices2/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + yices2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + + + diff --git a/tags/yices2/index.xml b/tags/yices2/index.xml new file mode 100644 index 00000000..9a5ddd7c --- /dev/null +++ b/tags/yices2/index.xml @@ -0,0 +1,23 @@ + + + + yices2 on VHDL News + https://vhdl.github.io/news/tags/yices2/ + Recent content in yices2 on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + \ No newline at end of file diff --git a/tags/yosys/index.html b/tags/yosys/index.html new file mode 100644 index 00000000..13f20d6d --- /dev/null +++ b/tags/yosys/index.html @@ -0,0 +1,436 @@ + + + + + + + + + + + + VHDL News + + | + + yosys + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + +
    + + #30 + 0 + 0 + + · + 2021/10/20 + + + + + umarcor/osvb + + + + · + tags: osvb, vunit, svunit, cocotb, osvvm, uvvm, renode, ghdl, verilator, iverilog, yosys + +
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    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
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    + + #26 + 3 + 0 + + · + 2020/12/02 + + + + + im-tomu/fomu-workshop + + + + · + tags: vhdl, verilog, ghdl, yosys, synthesis, fomu, workshop, examples + +
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    + + #24 + 3 + 0 + + · + 2020/11/30 + + + + + tmeissner/cryptocores + + + + · + tags: vhdl, ghdl, psl, yosys, verification, assertions, cryptography + +
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    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
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    + + + How to convert vhdl to other formats + + @tmeissner +
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    + + #17 + 3 + 0 + + · + 2020/09/28 + + + · + tags: ghdl, ghdl-yosys-plugin, yosys, synthesis, verilog, btor2, smt2, edif, firrtl + +
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    + + #5 + 3 + 0 + + · + 2020/08/18 + + + + + tmeissner/psl_with_ghdl + + + + · + tags: psl, ghdl, yosys, verification, formal-verification, assertions, symbiyosys, functional-coverage + +
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    + + + + diff --git a/tags/yosys/index.xml b/tags/yosys/index.xml new file mode 100644 index 00000000..efb785d1 --- /dev/null +++ b/tags/yosys/index.xml @@ -0,0 +1,86 @@ + + + + yosys on VHDL News + https://vhdl.github.io/news/tags/yosys/ + Recent content in yosys on VHDL News + Hugo -- gohugo.io + Wed, 20 Oct 2021 01:13:27 +0000 + + + + + + Open Source Verification Bundle (OSVB) + https://vhdl.github.io/news/show/30/ + Wed, 20 Oct 2021 01:13:27 +0000 + + https://vhdl.github.io/news/show/30/ + OSVB gathers the most popular open source verification Frameworks and Methodologies for VHDL and System Verilog: cocotb, OSVVM, SVUnit, UVVM, VUnit. Each of them was created and is maintained by different groups of people, in different contexts and with different backgrounds. All evolved into standalonish solutions involving build and test execution helpers, along with verification components for standard interfaces. However, each project prioritised certain features, while others didn’t receive so much care. + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Mixed HDL on Fomu, with GHDL and Yosys + https://vhdl.github.io/news/articles/26/ + Wed, 02 Dec 2020 05:34:29 +0000 + + https://vhdl.github.io/news/articles/26/ + Section Mixed HDL on Fomu of the FPGA Tomu Workshop contains Makefile based examples for synthesising mixed language (VHDL and Verilog) designs using open source tooling. Find sources at im-tomu/fomu-workshop: mixed-hdl/blink. +NOTE: The workshop uses im-tomu/fomu-toolchain, which is based on open-tool-forge/fpga-toolchain. Hence, makefiles expect ghdl-yosys-plugin to be built into Yosys. Other packaging solutions can be used too, but using ghdl-yosys-plugin as a module requires adding -m ghdl to the yosys call in the Makefile. + + + + VHDL/Verilog Cryptography cores incl. co-simulation with openSSL through GHDLs VHPIdirect + https://vhdl.github.io/news/cores/24/ + Mon, 30 Nov 2020 19:50:15 +0000 + + https://vhdl.github.io/news/cores/24/ + Cryptography IP-cores &amp; tests written in VHDL / Verilog. +The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes. +The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + How to convert vhdl to other formats + https://vhdl.github.io/news/past/17/ + Mon, 28 Sep 2020 15:23:01 +0000 + + https://vhdl.github.io/news/past/17/ + I made a list of &ldquo;How to convert vhdl to &hellip;&rdquo; in hopes it gets indexed by the search engines. All commands are similar, they are listed so common search phrases get indexed. +The format translation can be done with the yosys&rsquo;s write_*commands. Therefore, in order to them to work, ghdl, yosys and ghdl-yosys-plugin have to be installed (make sure they are updated). +In the following examples, ghdl is being used, in what I believe, is the most straightforward way. + + + + Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys) + https://vhdl.github.io/news/show/5/ + Tue, 18 Aug 2020 16:31:26 +0000 + + https://vhdl.github.io/news/show/5/ + A collection of examples of using PSL (Property Specification Language) for functional and formal verification of VHDL designs with GHDL (and Yosys / SymbiYosys). +This is a project with the purpose to get a current state of PSL implementation in GHDL. It probably will find unsupported PSL features, incorrect implemented features or simple bugs like GHDL crashs. It is also intended for experiments with PSL when learning the language. You can play around with the examples, as they are pretty simple. + + + + \ No newline at end of file diff --git a/tags/youtube/index.html b/tags/youtube/index.html new file mode 100644 index 00000000..60b3503e --- /dev/null +++ b/tags/youtube/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + youtube + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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    + + + SusanaCanel - Proyectos VHDL + + @umarcor +
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    + + #15 + 1 + 0 + + · + 2020/09/18 + + + + + susanacanel/proyectos-vhdl + + + + · + tags: learning, teaching, exercises, videos, youtube, modelsim, ghdl, altera + +
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    + + + + diff --git a/tags/youtube/index.xml b/tags/youtube/index.xml new file mode 100644 index 00000000..34ae9d01 --- /dev/null +++ b/tags/youtube/index.xml @@ -0,0 +1,23 @@ + + + + youtube on VHDL News + https://vhdl.github.io/news/tags/youtube/ + Recent content in youtube on VHDL News + Hugo -- gohugo.io + Fri, 18 Sep 2020 03:59:05 +0000 + + + + + + SusanaCanel - Proyectos VHDL + https://vhdl.github.io/news/articles/15/ + Fri, 18 Sep 2020 03:59:05 +0000 + + https://vhdl.github.io/news/articles/15/ + Youtube channel SusanaCanel contains 100+ videos (in spanish) about learning VHDL. The GitHub repository contains the sources used in the videos. + + + + \ No newline at end of file diff --git a/tags/z3/index.html b/tags/z3/index.html new file mode 100644 index 00000000..ef429fec --- /dev/null +++ b/tags/z3/index.html @@ -0,0 +1,193 @@ + + + + + + + + + + + + VHDL News + + | + + z3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
    + +
    + + + + +
    +
    + + + + diff --git a/tags/z3/index.xml b/tags/z3/index.xml new file mode 100644 index 00000000..18efde14 --- /dev/null +++ b/tags/z3/index.xml @@ -0,0 +1,26 @@ + + + + z3 on VHDL News + https://vhdl.github.io/news/tags/z3/ + Recent content in z3 on VHDL News + Hugo -- gohugo.io + Mon, 23 Nov 2020 09:09:05 +0000 + + + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + \ No newline at end of file diff --git a/tools/18/index.html b/tools/18/index.html new file mode 100644 index 00000000..9a7c04b1 --- /dev/null +++ b/tools/18/index.html @@ -0,0 +1,198 @@ + + + + + + + + + + + + VHDL News + + | + + Docker dashboard (on Windows and Mac OS) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
    + +
    + + + +
    + +
    +
    + + + + + + + diff --git a/tools/20/index.html b/tools/20/index.html new file mode 100644 index 00000000..6448bbff --- /dev/null +++ b/tools/20/index.html @@ -0,0 +1,201 @@ + + + + + + + + + + + + VHDL News + + | + + Structured constraint files for HDL designs targeting FPGA boards + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + +
    +
    +

    Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources.

    +
    + +
    +
    + + + + + + + diff --git a/tools/21/index.html b/tools/21/index.html new file mode 100644 index 00000000..c6642322 --- /dev/null +++ b/tools/21/index.html @@ -0,0 +1,211 @@ + + + + + + + + + + + + VHDL News + + | + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + +
    +
    +

    Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools

    +

    Speakers: Anton Blanchard, IBM & Tristan Gingold, CERN

    +

    Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux.

    +

    From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs.

    +

    This presentation will give an overview of the Microwatt core. It will also include an overview of GHDL and how it can be used for both simulation and synthesis of a medium complexity VHDL project.

    +
    + +
    +
    + + + + + + + diff --git a/tools/23/index.html b/tools/23/index.html new file mode 100644 index 00000000..a7721831 --- /dev/null +++ b/tools/23/index.html @@ -0,0 +1,212 @@ + + + + + + + + + + + + VHDL News + + | + + Building and deploying container images for open source EDA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
    + +
    + + + +
    +
    +

    hdl/containers: README.md

    +

    This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines.

    +
    +
    +

    ghdl/docker: DEPRECATED.md

    +

    Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository.

    +
    + +
    +
    + + + + + + + diff --git a/tools/27/index.html b/tools/27/index.html new file mode 100644 index 00000000..ed2b8a5c --- /dev/null +++ b/tools/27/index.html @@ -0,0 +1,201 @@ + + + + + + + + + + + + VHDL News + + | + + MINGW-packages for Electronic Design Automation (EDA) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + +
    +
    +

    This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl.github.io/MINGW-packages.

    +
    + +
    +
    + + + + + + + diff --git a/tools/index.html b/tools/index.html new file mode 100644 index 00000000..53b04335 --- /dev/null +++ b/tools/index.html @@ -0,0 +1,364 @@ + + + + + + + + + + + + VHDL News + + | + + Tools + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    + +

    References to projects that provide tooling around VHDL or which are otherwise useful in the context of open source VHDL design and documentation.

    +
    + + + +
    + +
    + + #27 + 1 + 0 + + · + 2021/01/19 + + + + + hdl/MINGW-packages + + + + · + tags: MSYS2, Windows, package, EDA, fritzing, ghdl, ghdl-yosys-plugin, Graphviz, gtkwave, icestorm, iverilog, KiCad, nextpnr, ngspice, prjtrellis, verilator, yices2, yosys, dfu-util, eccprog, icesprog, openFPGALoader, OpenOCD + +
    + +
    + + + + +
    + +
    + + #23 + 2 + 0 + + · + 2020/11/23 + + + + + hdl/containers + + + + · + tags: debian, docker, podman, ghdl, yosys, nextpnr, gtkwave, icestorm, prjtrellis, symbiyosys, z3 + +
    + +
    + + + + +
    + +
    + + #21 + 3 + 0 + + · + 2020/10/27 + + + + + antonblanchard/microwatt + + + + · + tags: microwatt, ghdl, simulation, synthesis, power, openisa + +
    + +
    + + + + +
    + +
    + + #20 + 1 + 0 + + · + 2020/10/22 + + + + + hdl/constraints + + + + · + tags: fpga, synthesis, xdc, lpf, pcf, ucf, sdc + +
    + +
    + + + + +
    + +
    + + #18 + 1 + 0 + + · + 2020/10/09 + + + + + ghdl/docker + + + + · + tags: docker, container, simulation, synthesis, programming + +
    + +
    + + + + +
    +
    + + + + diff --git a/tools/index.xml b/tools/index.xml new file mode 100644 index 00000000..0b2d5d85 --- /dev/null +++ b/tools/index.xml @@ -0,0 +1,65 @@ + + + + Tools on VHDL News + https://vhdl.github.io/news/tools/ + Recent content in Tools on VHDL News + Hugo -- gohugo.io + Tue, 19 Jan 2021 06:41:45 +0000 + + + + + + MINGW-packages for Electronic Design Automation (EDA) + https://vhdl.github.io/news/tools/27/ + Tue, 19 Jan 2021 06:41:45 +0000 + + https://vhdl.github.io/news/tools/27/ + This repository contains references to package recipes (PKGBUILD files) for electronic design automation (EDA) tools/projects to be built as MinGW-w64 targets on MSYS2 (MINGW32 and MINGW64). The main purpose is coordination of contributions for upstreaming all tools/projects to official MSYS2 repositories, and having them updated periodically. The default package manager (pacman) allows installing multiple tools at once through group mingw-w64-*-eda (i686|x86_64) . Find further details, along with usage and contribution guidelines at hdl. + + + + Building and deploying container images for open source EDA + https://vhdl.github.io/news/tools/23/ + Mon, 23 Nov 2020 09:09:05 +0000 + + https://vhdl.github.io/news/tools/23/ + hdl/containers: README.md +This repository contains scripts and GitHub Actions (GHA) YAML workflows for building, testing and deploying OCI images (aka Docker images) including open source EDA tooling. All of them are pushed to hub.docker.com/u/hdlc. See hdl.github.io/containers for further details and contributing guidelines. + ghdl/docker: DEPRECATED.md +Some images related to synthesis and PnR were moved to hdl/containers and hub.docker.com/u/hdlc. Some of those are now mirrored to ghdl/synth:* for backwards compatibility, but are no longer built in this repository. + + + + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools + https://vhdl.github.io/news/tools/21/ + Tue, 27 Oct 2020 06:45:43 +0000 + + https://vhdl.github.io/news/tools/21/ + Microwatt and GHDL - An Open Hardware CPU written in VHDL, Synthesized with Open Source Tools +Speakers: Anton Blanchard, IBM &amp; Tristan Gingold, CERN +Microwatt is a 64 bit POWER OpenISA soft processor, written in VHDL. Over time it has grown from supporting Micropython, to Zephyr and most recently Linux. +From its original inception, Microwatt has relied heavily on GHDL, the Open Source VHDL simulator. GHDL has very recently added synthesis support and together with Yosys and Nextpnr allows for a completely open source toolchain for FPGAs. + + + + Structured constraint files for HDL designs targeting FPGA boards + https://vhdl.github.io/news/tools/20/ + Thu, 22 Oct 2020 21:52:32 +0000 + + https://vhdl.github.io/news/tools/20/ + Any HDL design targeting FPGA boards needs constraint files in a vendor/tool specific format. Constraints are typically tied to the board and the interfaces, but not to the actual design. Therefore, copying them is inefficient and increases the maintenance burden of projects including multiple designs to be tested on several boards. This repository provides constraint definitions in a standardised and distributed format, fot decoupling board details from design sources. + + + + Docker dashboard (on Windows and Mac OS) + https://vhdl.github.io/news/tools/18/ + Fri, 09 Oct 2020 08:48:50 +0000 + + https://vhdl.github.io/news/tools/18/ + + + + + \ No newline at end of file diff --git a/welcome/index.html b/welcome/index.html new file mode 100644 index 00000000..9801b975 --- /dev/null +++ b/welcome/index.html @@ -0,0 +1,187 @@ + + + + + + + + + + + + VHDL News + + | + + Welcome to VHDL News + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    +
    + +
    +

    Welcome to VHDL News

    +

    Hacker News VHDL News is a bit different from other community sites, and we’d appreciate it if you’d take a minute to read the following as well as the guidelines.

    +

    The community of hardware designers is small, open source HDL is a niche compared to other technology communities, and open source VHDL is a subset of the latter. Users/developers are typically lacking time to write proper docs and/or detailed articles to let their projects be known. When they do, it is scattered in different sites/channels, so communication is diffusse although strong binds between users and projects exist. However, most of them do edit sources and/or reply to issues in GitHub almost daily.

    +

    VN is an experiment. Our hypothesis is that we can build bridges in the community by providing a hub that allows to participate with minimum overhead. Hence, VN is essentially GitHub Issues on steroids. By creating a new issue, users can share references/links to News, Articles, Tools and/or Cores, or they can Show their work in progress. Depending on the type of content, some metadata can be provided. Then, other users can react or comment in the issue, can share references to specific comments, can cross-ref discussions, etc. by using the regular GitHub features they are used to. A GitHub Actions workflow is used for retrieving the content from issues and for providing a web site with more details and alternative/additional sorting strategies.

    +

    Essentially there are two rules here: don’t post or upvote crap links, and don’t be rude or dumb in comment threads.

    +

    A crap link is one that’s only superficially interesting. Stories on HN VN don’t have to be about hacking VHDL , because good hackers hardware designers aren’t only interested in hacking VHDL , but they do have to be deeply interesting.

    +

    What does “deeply interesting” mean? It means stuff that teaches you about the world. A story about a robbery, for example, would probably not be deeply interesting. But if this robbery was a sign of some bigger, underlying trend, perhaps it could be.

    +

    The worst thing to post or upvote is something that’s intensely but shallowly interesting: gossip about famous people, funny or cute pictures or videos, partisan political articles, etc. If you let that sort of thing onto a news site, it will push aside the deeply interesting stuff, which tends to be quieter.

    +

    The most important principle on HN VN , though, is to make thoughtful comments. Thoughtful in both senses: civil and substantial.

    +

    The test for substance is a lot like it is for links. Does your comment teach us anything? There are two ways to do that: by pointing out some consideration that hadn’t previously been mentioned, and by giving more information about the topic, perhaps from personal experience. Whereas comments like “LOL!” or worse still, “That’s retarded!” teach us nothing.

    +

    Empty comments can be ok if they’re positive. There’s nothing wrong with submitting a comment saying just “Thanks.” What we especially discourage are comments that are empty and negative—comments that are mere name-calling.

    +

    Which brings us to the most important principle on HN VN : civility. Since long before the web, the anonymity of online conversation has lured people into being much ruder than they’d be in person. So the principle here is: don’t say anything you wouldn’t say face to face. This doesn’t mean you can’t disagree. But disagree without calling names. If you’re right, your argument will be more convincing without them.

    +

    Guidelines

    +

    There are five mutually exclusive categories:

    +
      +
    • News: main category for content that is not specific enough to fit in the other categories.
      • +
    • Show: equivalent to Show HN.
      • +
    • Articles: references to elaborated readings such as docs, papers, books, guides, wikis, etc.
      • +
    • Tools: references to projects that provide tooling around VHDL or which are otherwise useful in the context of open source VHDL design and documentation.
      • +
    • Cores: similar to opencores.org, freerangefactory.org/core or librecores.org, yet another attempt at building a registry of open source VHDL cores, simulation models and implementation constraints.
      • +
    +

    When creating a new issue, select the category where you want your submission to be published. All of the submissions must start with a code block, where the metadata is provided.

    +
    +

    NOTE: GitHub supports Markdown frontmatter fields in the preview of sources in the repository, but not in Issues. That’s why a code block is used.

    +
    +

    The only required field is the URL to the content you want to announce. Depending on the category, other optional fields can be provided. Those are listed in the template when a new issue is created; just remove the ones you don’t need/use.

    +

    Unlike News or Show, which are for rather ephemeral references, Articles, Tools and/or Cores are expected to be long going resources that evolve over time. Hence, both users and submitters should be aware that Articles, Tools and/or Cores might change and should change. As a result, it is ok to publish News which announce some relevant change/release/update in projects that are already listed in some other category. By the same token, the metadata in VN should be updated as the references evolve. Particularly, there is an optional field named related which allows to specify multiple submissions that are related to each other.

    +

    On top of that, users are expected to follow Hacker News Guidelines in this site too.

    +

    How to create the content

    +

    VN is not meant to host the content, but the references only, along with a short description. However, the reference is an URL that can point to any public content hosted anywhere. Hence, it is not required to format the content as a fancy website. Plain references to the preview of markup files is ok too.

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    + + + + + + +