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files.qip
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files.qip
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ttl/n9bit_counter.sv
set_global_assignment -name VERILOG_FILE rtl/joy_10btn.v
set_global_assignment -name VERILOG_FILE rtl/ttl/helper.v
set_global_assignment -name SDC_FILE "Arcade-TNKIII_MiSTer.sdc"
set_global_assignment -name VERILOG_FILE rtl/ram/SRAM_sync_noinit.v
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name VERILOG_FILE rtl/ram/SRAM_dual_sync.v
set_global_assignment -name SYSTEMVERILOG_FILE "Arcade-TNKIII_MiSTer.sv"
set_global_assignment -name VERILOG_FILE rtl/ttl/DFF_pseudoAsyncClrPre2.v
set_global_assignment -name VERILOG_FILE rtl/ttl/DFF_pseudoAsyncClrPre.v
set_global_assignment -name VHDL_FILE rtl/ram/dpram_dc.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram/rom_loader.sv
set_global_assignment -name VERILOG_FILE rtl/POR.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ttl/ttl_74374_sync.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ttl/ttl_74373.sv
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74298_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74283_nodly.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74273_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74245_2dly.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74244.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74194_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74175_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74174_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74166_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74164_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74163a_sync.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74161a.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74161.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74157.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74155.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74153.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74139_nodly.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74138_nodly.v
set_global_assignment -name VERILOG_FILE rtl/ttl/ttl_74107a_sync.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/TNKIIICore_Sound_sync.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/side/TNKIIICore_Side_sync.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/registers/TNKIIICore_Registers_sync.sv
set_global_assignment -name VERILOG_FILE rtl/ram/SRAM_dual_sync_init.v
set_global_assignment -name VERILOG_FILE rtl/ram/SRAM_sync_init.v
set_global_assignment -name VERILOG_FILE rtl/ram/ROM_sync.v
set_global_assignment -name VERILOG_FILE rtl/ram/SRAM_sync.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/front/TNKIIICore_LineBuffer_sync.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/front/TNKIIICore_Front_sync.sv
set_global_assignment -name VERILOG_FILE rtl/final_video/A5001_3.v
set_global_assignment -name SYSTEMVERILOG_FILE "rtl/final_video/module RGB4bit_LUT.sv"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/final_video/TNKIIICore_FinalVideo_sync.sv
set_global_assignment -name VERILOG_FILE rtl/cpuA_B/A5001_2.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpuA_B/TNKIIICore_CPU_A_B_sync.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/back1/TNKIIICore_Back1_sync.sv
set_global_assignment -name VERILOG_FILE rtl/clocks/A5001_1.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/clocks/TNKIIICore_Clocks_Sync.sv
set_global_assignment -name VERILOG_FILE rtl/clocks/TNKIIICore_Clocks_Cen.v
set_global_assignment -name QIP_FILE rtl/ym3526/jt26.qip
set_global_assignment -name QIP_FILE rtl/T80/T80.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TNKIIICore.sv
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name VERILOG_FILE rtl/pause.v
set_global_assignment -name VERILOG_FILE rtl/joy_db15.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ls30rot_decoder.sv