diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 4eeff04fd..f8b927f76 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -377,7 +377,10 @@ function reset_sys() -> unit = {
 
   // "If little-endian memory accesses are supported, the mstatus/mstatush field
   // MBE is reset to 0."
-  // The model doesn't support little-endian (see legalize_mstatus()).
+  // TODO: The handling of mstatush is a bit awkward currently, but the model
+  // currently only supports little endian so MBE is always 0.
+  // See https://github.com/riscv/sail-riscv/issues/639
+  // mstatus[MBE] = 0b0;
 
   // "The misa register is reset to enable the maximal set of supported extensions"
   reset_misa();