From e204f5e83598af62fb10293988a5d71d6d465f02 Mon Sep 17 00:00:00 2001 From: Tim Hutt Date: Fri, 1 Nov 2024 09:17:05 +0000 Subject: [PATCH] Update model/riscv_fdext_regs.sail Co-authored-by: Jessica Clarke Signed-off-by: Tim Hutt --- model/riscv_fdext_regs.sail | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/model/riscv_fdext_regs.sail b/model/riscv_fdext_regs.sail index 00daea98a..fc1d3e78c 100644 --- a/model/riscv_fdext_regs.sail +++ b/model/riscv_fdext_regs.sail @@ -39,7 +39,7 @@ function canonical_NaN_Q() -> bits(128) = canonical_NaN(128) val nan_box : forall 'n 'm, 'n <= 'm . (implicit('m), bits('n)) -> bits('m) function nan_box(n, x) = ones('m - 'n) @ x -// When an n-bit float is stored ina smaller m-bit register it is "unboxed" +// When an n-bit float is stored in a smaller m-bit register it is "unboxed" // - only if it is a valid boxed NaN. Otherwise a canonical NaN value is stored. // TODO: Use right-open interval when available. See https://github.com/rems-project/sail/issues/471 val nan_unbox : forall 'n 'm, 'm in {16, 32, 64, 128} & 'n >= 'm . (implicit('m), bits('n)) -> bits('m)