From bbbfead5e0f54fe46c1175941cb546f0a12b0088 Mon Sep 17 00:00:00 2001 From: Tim Hutt Date: Thu, 5 Dec 2024 15:38:40 +0000 Subject: [PATCH] Move extension scattered enum to non-scattered enum Having the enum be scattered can lead to slightly awkward dependency order issues. It also doesn't really need to be scattered, so this moves it into a single non-scattered enum in one file. --- Makefile | 2 +- model/riscv_extensions.sail | 53 +++++++++++++++++++++++++++++++++ model/riscv_fdext_control.sail | 5 ---- model/riscv_insts_aext.sail | 4 +-- model/riscv_insts_base.sail | 3 -- model/riscv_insts_dext.sail | 1 - model/riscv_insts_end.sail | 1 - model/riscv_insts_fext.sail | 2 -- model/riscv_insts_mext.sail | 2 -- model/riscv_insts_svinval.sail | 1 - model/riscv_insts_zba.sail | 3 -- model/riscv_insts_zbb.sail | 3 -- model/riscv_insts_zbc.sail | 3 -- model/riscv_insts_zbkx.sail | 1 - model/riscv_insts_zbs.sail | 1 - model/riscv_insts_zcb.sail | 1 - model/riscv_insts_zcd.sail | 1 - model/riscv_insts_zcf.sail | 1 - model/riscv_insts_zfa.sail | 1 - model/riscv_insts_zfh.sail | 1 - model/riscv_insts_zicbom.sail | 1 - model/riscv_insts_zicboz.sail | 1 - model/riscv_insts_zicond.sail | 1 - model/riscv_insts_zifencei.sail | 2 +- model/riscv_insts_zkn.sail | 4 +-- model/riscv_insts_zks.sail | 2 -- model/riscv_sys_regs.sail | 3 -- model/riscv_types.sail | 3 -- model/riscv_vext_control.sail | 1 - model/riscv_zihpm.sail | 1 - model/riscv_zkr_control.sail | 1 - 31 files changed, 57 insertions(+), 53 deletions(-) create mode 100644 model/riscv_extensions.sail diff --git a/Makefile b/Makefile index 4f3b63af5..6992d269f 100644 --- a/Makefile +++ b/Makefile @@ -106,7 +106,7 @@ SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS) SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail SAIL_ARCH_SRCS = $(PRELUDE) -SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail +SAIL_ARCH_SRCS += riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS) SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail diff --git a/model/riscv_extensions.sail b/model/riscv_extensions.sail new file mode 100644 index 000000000..51a4103d4 --- /dev/null +++ b/model/riscv_extensions.sail @@ -0,0 +1,53 @@ +/*=======================================================================================*/ +/* This Sail RISC-V architecture model, comprising all files and */ +/* directories except where otherwise noted is subject the BSD */ +/* two-clause license in the LICENSE file. */ +/* */ +/* SPDX-License-Identifier: BSD-2-Clause */ +/*=======================================================================================*/ + +/* ISA extension names as enums */ +enum extension = { + Ext_B, // Bit manipulation + Ext_C, // Compressed + Ext_D, // Double precision float + Ext_F, // Single precision float + Ext_M, // Multiply/Divide; not Machine! + Ext_S, // Supervisor + Ext_Sstc, // Supervisor time compare + Ext_Svinval, + Ext_U, // User + Ext_V, // Vector + Ext_Zaamo, + Ext_Zabha, + Ext_Zalrsc, + Ext_Zba, + Ext_Zbb, + Ext_Zbc, + Ext_Zbkb, + Ext_Zbkc, + Ext_Zbkx, + Ext_Zbs, + Ext_Zca, + Ext_Zcb, + Ext_Zcd, + Ext_Zcf, + Ext_Zdinx, + Ext_Zfa, + Ext_Zfh, + Ext_Zfhmin, + Ext_Zfinx, + Ext_Zhinx, + Ext_Zicbom, + Ext_Zicboz, + Ext_Zicond, + Ext_Zifencei, + Ext_Zihpm, + Ext_Zknd, + Ext_Zkne, + Ext_Zknh, + Ext_Zkr, + Ext_Zksed, + Ext_Zksh, + Ext_Zmmul, +} diff --git a/model/riscv_fdext_control.sail b/model/riscv_fdext_control.sail index 9338788df..857cef64c 100644 --- a/model/riscv_fdext_control.sail +++ b/model/riscv_fdext_control.sail @@ -15,13 +15,8 @@ /* **************************************************************** */ -enum clause extension = Ext_F function clause extensionEnabled(Ext_F) = (misa[F] == 0b1) & (mstatus[FS] != 0b00) - -enum clause extension = Ext_D function clause extensionEnabled(Ext_D) = (misa[D] == 0b1) & (mstatus[FS] != 0b00) & flen >= 64 - -enum clause extension = Ext_Zfinx function clause extensionEnabled(Ext_Zfinx) = sys_enable_zfinx() /* Floating Point CSRs */ diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail index 17863b820..a7887f5ad 100644 --- a/model/riscv_insts_aext.sail +++ b/model/riscv_insts_aext.sail @@ -10,7 +10,7 @@ /* This file specifies the atomic instructions in the 'A' extension. */ /* ****************************************************************** */ -enum clause extension = Ext_Zabha + function clause extensionEnabled(Ext_Zabha) = true // Some print utils for lr/sc. @@ -53,7 +53,6 @@ function amo_width_valid(size : word_width) -> bool = { } /* ****************************************************************** */ -enum clause extension = Ext_Zalrsc function clause extensionEnabled(Ext_Zalrsc) = misa[A] == 0b1 union clause ast = LOADRES : (bool, bool, regidx, word_width, regidx) @@ -168,7 +167,6 @@ mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" /* ****************************************************************** */ -enum clause extension = Ext_Zaamo function clause extensionEnabled(Ext_Zaamo) = misa[A] == 0b1 union clause ast = AMO : (amoop, bool, bool, regidx, regidx, word_width, regidx) diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index 1510dd425..505f82b41 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -9,10 +9,7 @@ /* ****************************************************************** */ /* This file specifies the instructions in the base integer set. */ -enum clause extension = Ext_C function clause extensionEnabled(Ext_C) = misa[C] == 0b1 - -enum clause extension = Ext_Zca function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C) /* ****************************************************************** */ diff --git a/model/riscv_insts_dext.sail b/model/riscv_insts_dext.sail index 2cb453fbc..40a16e148 100644 --- a/model/riscv_insts_dext.sail +++ b/model/riscv_insts_dext.sail @@ -224,7 +224,6 @@ function fle_D (v1, v2, is_quiet) = { /* **************************************************************** */ /* Helper functions for 'encdec()' */ -enum clause extension = Ext_Zdinx function clause extensionEnabled(Ext_Zdinx) = sys_enable_zfinx() & flen >= 64 function haveDoubleFPU() -> bool = extensionEnabled(Ext_D) | extensionEnabled(Ext_Zdinx) diff --git a/model/riscv_insts_end.sail b/model/riscv_insts_end.sail index 728c21e43..f8419a355 100644 --- a/model/riscv_insts_end.sail +++ b/model/riscv_insts_end.sail @@ -27,7 +27,6 @@ mapping clause assembly = C_ILLEGAL(s) <-> "c.illegal" ^ spc() ^ hex_bits_16(s) /* ****************************************************************** */ /* End definitions */ -end extension end extensionEnabled end ast end execute diff --git a/model/riscv_insts_fext.sail b/model/riscv_insts_fext.sail index 966338db8..0f6550ec9 100644 --- a/model/riscv_insts_fext.sail +++ b/model/riscv_insts_fext.sail @@ -26,10 +26,8 @@ /* **************************************************************** */ // TODO: Add config flags to control Zfh and Zfhmin -enum clause extension = Ext_Zfh function clause extensionEnabled(Ext_Zfh) = (misa[F] == 0b1) & (mstatus[FS] != 0b00) -enum clause extension = Ext_Zfhmin // Zfhmin is a subset of Zfh. This can be changed to extensionEnabled(Ext_Zfh) | sys_enable_zfhmin() when more configuration is implemented. function clause extensionEnabled(Ext_Zfhmin) = extensionEnabled(Ext_Zfh) diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail index 069ad20de..20a928119 100644 --- a/model/riscv_insts_mext.sail +++ b/model/riscv_insts_mext.sail @@ -11,9 +11,7 @@ /* ****************************************************************** */ -enum clause extension = Ext_M function clause extensionEnabled(Ext_M) = misa[M] == 0b1 -enum clause extension = Ext_Zmmul function clause extensionEnabled(Ext_Zmmul) = true diff --git a/model/riscv_insts_svinval.sail b/model/riscv_insts_svinval.sail index 2816fdc14..34c2a753f 100644 --- a/model/riscv_insts_svinval.sail +++ b/model/riscv_insts_svinval.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Svinval function clause extensionEnabled(Ext_Svinval) = sys_enable_svinval() union clause ast = SINVAL_VMA : (regidx, regidx) diff --git a/model/riscv_insts_zba.sail b/model/riscv_insts_zba.sail index bef115cc4..acd70518b 100644 --- a/model/riscv_insts_zba.sail +++ b/model/riscv_insts_zba.sail @@ -6,10 +6,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_B function clause extensionEnabled(Ext_B) = misa[B] == 0b1 - -enum clause extension = Ext_Zba function clause extensionEnabled(Ext_Zba) = true | extensionEnabled(Ext_B) /* ****************************************************************** */ diff --git a/model/riscv_insts_zbb.sail b/model/riscv_insts_zbb.sail index 5a62ba2dd..0a1b39af0 100644 --- a/model/riscv_insts_zbb.sail +++ b/model/riscv_insts_zbb.sail @@ -6,10 +6,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zbb function clause extensionEnabled(Ext_Zbb) = true | extensionEnabled(Ext_B) - -enum clause extension = Ext_Zbkb function clause extensionEnabled(Ext_Zbkb) = true /* ****************************************************************** */ diff --git a/model/riscv_insts_zbc.sail b/model/riscv_insts_zbc.sail index 54755f584..8e8f14517 100644 --- a/model/riscv_insts_zbc.sail +++ b/model/riscv_insts_zbc.sail @@ -6,10 +6,7 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zbc function clause extensionEnabled(Ext_Zbc) = true - -enum clause extension = Ext_Zbkc function clause extensionEnabled(Ext_Zbkc) = true /* ****************************************************************** */ diff --git a/model/riscv_insts_zbkx.sail b/model/riscv_insts_zbkx.sail index 226938477..c10f52de6 100644 --- a/model/riscv_insts_zbkx.sail +++ b/model/riscv_insts_zbkx.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zbkx function clause extensionEnabled(Ext_Zbkx) = true /* ****************************************************************** */ diff --git a/model/riscv_insts_zbs.sail b/model/riscv_insts_zbs.sail index a016612c9..b8fa77207 100644 --- a/model/riscv_insts_zbs.sail +++ b/model/riscv_insts_zbs.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zbs function clause extensionEnabled(Ext_Zbs) = true | extensionEnabled(Ext_B) /* ****************************************************************** */ diff --git a/model/riscv_insts_zcb.sail b/model/riscv_insts_zcb.sail index 3bef3464c..cd04be411 100644 --- a/model/riscv_insts_zcb.sail +++ b/model/riscv_insts_zcb.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zcb function clause extensionEnabled(Ext_Zcb) = sys_enable_zcb() & extensionEnabled(Ext_Zca) union clause ast = C_LBU : (bits(2), cregidx, cregidx) diff --git a/model/riscv_insts_zcd.sail b/model/riscv_insts_zcd.sail index 2d5f7c032..cbe8f449c 100644 --- a/model/riscv_insts_zcd.sail +++ b/model/riscv_insts_zcd.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zcd function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (xlen == 32 | xlen == 64) union clause ast = C_FLDSP : (bits(6), regidx) diff --git a/model/riscv_insts_zcf.sail b/model/riscv_insts_zcf.sail index d061c1b93..a8206e80c 100644 --- a/model/riscv_insts_zcf.sail +++ b/model/riscv_insts_zcf.sail @@ -15,7 +15,6 @@ /* ****************************************************************** */ -enum clause extension = Ext_Zcf function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & xlen == 32 union clause ast = C_FLWSP : (bits(6), regidx) diff --git a/model/riscv_insts_zfa.sail b/model/riscv_insts_zfa.sail index 2b1f7c50f..5b1cca6fb 100644 --- a/model/riscv_insts_zfa.sail +++ b/model/riscv_insts_zfa.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zfa function clause extensionEnabled(Ext_Zfa) = true /* FLI.H */ diff --git a/model/riscv_insts_zfh.sail b/model/riscv_insts_zfh.sail index c9a84e05f..a8c8aff53 100644 --- a/model/riscv_insts_zfh.sail +++ b/model/riscv_insts_zfh.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zhinx function clause extensionEnabled(Ext_Zhinx) = sys_enable_zfinx() /* **************************************************************** */ diff --git a/model/riscv_insts_zicbom.sail b/model/riscv_insts_zicbom.sail index a8fdd8bcb..e9e1a9b93 100644 --- a/model/riscv_insts_zicbom.sail +++ b/model/riscv_insts_zicbom.sail @@ -8,7 +8,6 @@ // Cache Block Operations - Management -enum clause extension = Ext_Zicbom function clause extensionEnabled(Ext_Zicbom) = sys_enable_zicbom() function cbo_clean_flush_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBCFE][0], senvcfg[CBCFE][0]) diff --git a/model/riscv_insts_zicboz.sail b/model/riscv_insts_zicboz.sail index abf18dc82..270ac71a8 100644 --- a/model/riscv_insts_zicboz.sail +++ b/model/riscv_insts_zicboz.sail @@ -8,7 +8,6 @@ // Cache Block Operations - Zero -enum clause extension = Ext_Zicboz function clause extensionEnabled(Ext_Zicboz) = sys_enable_zicboz() function cbo_zero_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBZE][0], senvcfg[CBZE][0]) diff --git a/model/riscv_insts_zicond.sail b/model/riscv_insts_zicond.sail index 9491fe950..2a71f2d99 100644 --- a/model/riscv_insts_zicond.sail +++ b/model/riscv_insts_zicond.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_Zicond function clause extensionEnabled(Ext_Zicond) = true union clause ast = ZICOND_RTYPE : (regidx, regidx, regidx, zicondop) diff --git a/model/riscv_insts_zifencei.sail b/model/riscv_insts_zifencei.sail index 7e7e60742..80f718d29 100644 --- a/model/riscv_insts_zifencei.sail +++ b/model/riscv_insts_zifencei.sail @@ -10,7 +10,7 @@ /* This file specifies the instructions in the 'Zifencei' extension. */ /* ****************************************************************** */ -enum clause extension = Ext_Zifencei + function clause extensionEnabled(Ext_Zifencei) = true union clause ast = FENCEI : unit diff --git a/model/riscv_insts_zkn.sail b/model/riscv_insts_zkn.sail index d4a3c9107..8626f65c4 100644 --- a/model/riscv_insts_zkn.sail +++ b/model/riscv_insts_zkn.sail @@ -10,7 +10,7 @@ * Scalar Cryptography Extension - Scalar SHA256 instructions (RV32/RV64) * ---------------------------------------------------------------------- */ -enum clause extension = Ext_Zknh + function clause extensionEnabled(Ext_Zknh) = true union clause ast = SHA256SIG0 : (regidx, regidx) @@ -75,7 +75,6 @@ function clause execute (SHA256SUM1(rs1, rd)) = { * ---------------------------------------------------------------------- */ -enum clause extension = Ext_Zkne function clause extensionEnabled(Ext_Zkne) = true union clause ast = AES32ESMI : (bits(2), regidx, regidx, regidx) @@ -118,7 +117,6 @@ function clause execute (AES32ESI (bs, rs2, rs1, rd)) = { * ---------------------------------------------------------------------- */ -enum clause extension = Ext_Zknd function clause extensionEnabled(Ext_Zknd) = true union clause ast = AES32DSMI : (bits(2), regidx, regidx, regidx) diff --git a/model/riscv_insts_zks.sail b/model/riscv_insts_zks.sail index ba4a86853..6e61bf83a 100644 --- a/model/riscv_insts_zks.sail +++ b/model/riscv_insts_zks.sail @@ -11,7 +11,6 @@ * ---------------------------------------------------------------------- */ -enum clause extension = Ext_Zksh function clause extensionEnabled(Ext_Zksh) = true union clause ast = SM3P0 : (regidx, regidx) @@ -48,7 +47,6 @@ function clause execute (SM3P1(rs1, rd)) = { * ---------------------------------------------------------------------- */ -enum clause extension = Ext_Zksed function clause extensionEnabled(Ext_Zksed) = true union clause ast = SM4ED : (bits(2), regidx, regidx, regidx) diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index b4fadd26b..c9a81ddc6 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -118,7 +118,6 @@ val sys_enable_zicboz = pure "sys_enable_zicboz" : unit -> bool val sys_enable_sstc = pure "sys_enable_sstc" : unit -> bool // Supervisor timecmp -enum clause extension = Ext_Sstc function clause extensionEnabled(Ext_Sstc) = sys_enable_sstc() /* This function allows an extension to veto a write to Misa @@ -146,10 +145,8 @@ function clause is_CSR_defined(0x301) = true // misa function clause read_CSR(0x301) = misa.bits function clause write_CSR(0x301, value) = { misa = legalize_misa(misa, value); misa.bits } -enum clause extension = Ext_U function clause extensionEnabled(Ext_U) = misa[U] == 0b1 -enum clause extension = Ext_S function clause extensionEnabled(Ext_S) = misa[S] == 0b1 /* diff --git a/model/riscv_types.sail b/model/riscv_types.sail index 4a4de0772..c4d2d0d81 100644 --- a/model/riscv_types.sail +++ b/model/riscv_types.sail @@ -8,9 +8,6 @@ /* Basic type and function definitions used pervasively in the model. */ -/* ISA extension names as enums */ -scattered enum extension - // Function used to determine if an extension is enabled in the current configuration. // This means an extension is implemented & supported, *and* any necessary bits // are set in the relevant CSRs (misa, mstatus, etc.) to enable its use. It is possible diff --git a/model/riscv_vext_control.sail b/model/riscv_vext_control.sail index 9bd1467e5..fa9b311ed 100755 --- a/model/riscv_vext_control.sail +++ b/model/riscv_vext_control.sail @@ -6,7 +6,6 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -enum clause extension = Ext_V function clause extensionEnabled(Ext_V) = (misa[V] == 0b1) & (mstatus[VS] != 0b00) mapping clause csr_name_map = 0x008 <-> "vstart" diff --git a/model/riscv_zihpm.sail b/model/riscv_zihpm.sail index 1fba75267..ee6057556 100644 --- a/model/riscv_zihpm.sail +++ b/model/riscv_zihpm.sail @@ -7,7 +7,6 @@ /*=======================================================================================*/ /* Hardware Performance Monitoring counters */ -enum clause extension = Ext_Zihpm function clause extensionEnabled(Ext_Zihpm) = true /* Hardware performance monitoring counters */ diff --git a/model/riscv_zkr_control.sail b/model/riscv_zkr_control.sail index 4284cce43..5da31b330 100644 --- a/model/riscv_zkr_control.sail +++ b/model/riscv_zkr_control.sail @@ -7,7 +7,6 @@ /*=======================================================================================*/ /* Zkr entropy seed source */ -enum clause extension = Ext_Zkr function clause extensionEnabled(Ext_Zkr) = true /* Valid return states for reading the seed CSR. */