From a0d99dc9c99b7a0181b299e9b5b6824ccd81c961 Mon Sep 17 00:00:00 2001
From: guan jian <148229859+rez5427@users.noreply.github.com>
Date: Fri, 29 Nov 2024 19:30:41 +0800
Subject: [PATCH] Make mstatus[VS] dirty when vstart is written

Set `mstatus[VS]` to dirty when `vstart` is written. There are still some writes to vector CSRs that are missing calls to `dirty_v_context()` but these will be fixed in a future.

This also removes `dirty_v_context_if_present()` because the vector extension is always supported when this function is called.

Co-authored-by: Yui5427 <785369607@qq.com>
---
 model/riscv_vext_control.sail | 2 +-
 model/riscv_vext_regs.sail    | 6 +-----
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/model/riscv_vext_control.sail b/model/riscv_vext_control.sail
index d2d2c184b..9bd1467e5 100755
--- a/model/riscv_vext_control.sail
+++ b/model/riscv_vext_control.sail
@@ -33,7 +33,7 @@ function clause read_CSR(0xC20) = vl
 function clause read_CSR(0xC21) = vtype.bits
 function clause read_CSR(0xC22) = get_vlenb()
 
-function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
+function clause write_CSR(0x008, value) = { dirty_v_context(); let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
 function clause write_CSR(0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); zero_extend(vcsr[vxsat]) }
 function clause write_CSR(0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); zero_extend(vcsr[vxrm]) }
 function clause write_CSR(0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); zero_extend(vcsr.bits) }
diff --git a/model/riscv_vext_regs.sail b/model/riscv_vext_regs.sail
index 6b1b98dd4..14947e77c 100644
--- a/model/riscv_vext_regs.sail
+++ b/model/riscv_vext_regs.sail
@@ -82,10 +82,6 @@ function dirty_v_context() -> unit = {
   mstatus[SD] = 0b1
 }
 
-function dirty_v_context_if_present() -> unit = {
-  if sys_enable_vext() then dirty_v_context()
-}
-
 function rV (r : regno) -> vregtype = {
   match r {
     0 => vr0,
@@ -222,7 +218,7 @@ val ext_write_vcsr : (bits(2), bits(1)) -> unit
 function ext_write_vcsr (vxrm_val, vxsat_val) = {
   vcsr[vxrm]  = vxrm_val; /* Note: frm can be an illegal value, 101, 110, 111 */
   vcsr[vxsat] = vxsat_val;
-  dirty_v_context_if_present()
+  dirty_v_context()
 }
 
 /* num_elem means max(VLMAX,VLEN/SEW)) according to Section 5.4 of RVV spec */